An admittance matrix processing module and a power flow streaming parallel computing device

Abstract

The present application relates to a kind of admittance matrix processing module and power flow stream parallel computing device, wherein, admittance matrix processing module includes: admittance matrix stream computing module, for receiving branch data, whether the branch contains transformer is judged according to the value of non-standard transformer ratio, and the equivalent circuit of branch is calculated, and the mutual admittance calculation of current node from_bus to target node to_bus is completed in the interval of receiving two branch data, and the calculation result is written into admittance matrix queue simultaneously;Admittance matrix access module is used to receive the mutual admittance value in the form of upper triangular of the admittance matrix queue, and when reaching the memory write burst length, the mutual admittance value in the form of upper triangular is written into memory.The present application completes the dynamic stream computing admittance matrix value, and the parallel pipeline computation of power flow.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power flow calculation, in particular to a conductance matrix processing module and a power flow stream parallel computing device. BACKGROUND

[0002] Power flow calculation is a very important analysis and calculation of power systems, which calculates electrical quantities in the steady-state operation state of power systems, including active power, reactive power and voltage distribution in the power grid, according to the wiring mode, parameters and operating conditions of the power system. Power flow calculation is also the basis for system safety, stability and reliability analysis, and is used to study various problems raised in system planning and operation. For the planned power system, through power flow calculation, it can be verified whether the proposed power system planning scheme can meet the requirements of various operating modes; for the running power system, through power flow calculation, it can be predicted whether various load changes and network structure changes will endanger the safety of the system, whether the voltage of all buses in the system is within the allowed range, whether various components (lines, transformers, etc.) in the system will appear overload, and what preventive measures should be taken in advance when overload may occur, etc.

[0003] The existing document (Nwankpa C, Johnson J, Nagvajara P, et al. FPGA hardware results for power system computation [C] / / 2009 IEEE / PES Power Systems Conference and Exposition. 0 [2023-09-26]. DOI: 10.1109 / PSCE.2009.4839953.) proposes a power flow calculation FPGA system based on the Newton-Raphson method by collecting real-time SCADA system network and telemetry data.

[0004] This scheme is based on the traditional Newton-Raphson method, and when the matrix dimension is relatively large, the solution time is long, and even it does not converge, and it cannot give the solution of the equation set. At the same time, in the face of massive data dynamic changes of the power grid, the power flow calculation of this scheme has the shortcomings of high storage resource consumption and slow calculation speed, and does not effectively play the speed advantage of FPGA in data pipeline calculation and matrix parallel operation. SUMMARY

[0005] The technical problem to be solved by the present application is to provide a conductance matrix processing module and a power flow stream parallel computing device, which can realize parallel pipeline calculation of power flow.

[0006] The technical scheme adopted by the present application to solve the technical problem is: a conductance matrix processing module is provided, which comprises:

[0007] An admittance matrix streaming calculation module is configured to receive branch data, determine whether a branch contains a transformer according to a value of a non-standard transformer ratio, calculate an equivalent circuit of the branch, and complete mutual admittance calculation of a current node from_bus to a target node to_bus within an interval of receiving two pieces of branch data, and write the calculation result into an admittance matrix queue synchronously;

[0008] An admittance matrix access module is configured to receive mutual admittance values in an upper triangular form in the admittance matrix queue, and write the mutual admittance values in the upper triangular form into a memory when a memory write burst length is reached.

[0009] When the mutual admittance calculation is performed, the admittance matrix streaming calculation module maps mutual admittance values in an upper triangular form of the current node from_bus to the target node to_bus to contribution values of the admittance matrix lower triangular target node to_bus, and accumulates the mutual admittance values of the target node to_bus to a self-admittance matrix register of a corresponding target node to_bus label, the self-admittance of the node is synchronously calculated when all rows of the current node from_bus are read, and the self-admittance register of each node is synchronously accumulated and updated when all branch data are read.

[0010] When the current branch does not contain a transformer, the admittance matrix streaming calculation module performs the following calculation process:

[0011] Calculate impedance square sum, branch admittance real part and branch admittance imaginary part, and mutual admittance of the current node from_bus to the target node to_bus, pull up a write admittance matrix queue write valid signal, write conductance data in the mutual admittance of the current node from_bus to the target node to_bus into the admittance matrix queue, write susceptance data in the mutual admittance of the current node from_bus to the target node to_bus into the admittance matrix queue, write a column label value of the target node to_bus into the admittance matrix queue, clear the write admittance matrix queue write valid signal, and add 1 to a row data number counter of the current node from_bus when the mutual admittance of the current node from_bus to the target node to_bus and the writing are completed once.

[0012] Calculate self-admittance to the target node to_bus, the self-admittance is the branch admittance real part and imaginary part plus half of the branch end-to-ground susceptance, update and accumulate conductance values of the target node to_bus into high bits of the self-admittance register of the target node to_bus, and update and accumulate susceptance values of the target node to_bus into low bits of the self-admittance register of the target node to_bus.

[0013] The self-inductance value of the current node from_bus is calculated and accumulated, and the accumulated conductance value of the current node from_bus is updated into the high bit of the self-inductance register of the current node from_bus, and the accumulated electric capacity value of the current node from_bus is updated into the low bit of the self-inductance register of the current node from_bus.

[0014] When the admittance matrix streaming calculation module contains a transformer, the calculation process is as follows:

[0015] The ratio square sum, the impedance square sum, the branch admittance real part and the branch admittance imaginary part without a transformer, and the mutual inductance of the transformer conversion part of the current node from_bus to the target node to_bus are calculated, the write enable signal of the write admittance matrix queue is pulled high, the conductance data in the mutual inductance of the transformer conversion part of the current node from_bus to the target node to_bus is written into the admittance matrix queue, the electric capacity data in the mutual inductance of the transformer conversion part of the current node from_bus to the target node to_bus is written into the admittance matrix queue, and the column label value of the target node to_bus is written into the admittance matrix queue; the write enable signal of the write admittance matrix queue is cleared; after completing the mutual inductance calculation and writing of the transformer conversion part of the current node from_bus to the target node to_bus once, the row data counter of the current node from_bus is incremented by 1;

[0016] The self-inductance of the current node from_bus containing transformer conversion and the self-inductance of the target node to_bus containing transformer conversion are calculated.

[0017] The self-inductance of the target node to_bus is calculated, and the self-inductance of the target node to_bus containing transformer conversion is added to half of the electric capacity of the branch to ground; the accumulated conductance value of the target node to_bus is updated into the high bit of the self-inductance register of the target node to_bus, and the accumulated electric capacity value of the current node to_bus is updated into the low bit of the self-inductance register of the target node to_bus.

[0018] The self-inductance value of the current node from_bus is calculated and accumulated, and the accumulated conductance value of the current node from_bus is updated into the high bit of the self-inductance register of the current node from_bus; the accumulated electric capacity value of the current node from_bus is updated into the low bit of the self-inductance register of the current node from_bus.

[0019] When the admittance matrix access module writes the mutual inductance value in the upper triangular form into the memory, if the preset multiple of the non-zero element of the current row in the admittance matrix is less than or equal to the maximum burst length, the following writing process is performed:

[0020] The preset multiple of the current row non-zero element in the admittance matrix is set as the read-write burst length of the memory; when the data in one row of the admittance matrix is taken and the read-write burst length of the memory is not reached, the data in the next row is continuously taken, the accumulated value of the non-zero element in the next row is judged, the GB_row_num_FIFO queue is set to store the number of non-zero elements in each row of the admittance matrix, and the number of non-zero elements in the current row of the admittance matrix is written into the GB_row_num_FIFO queue.

[0021] The number of non-zero elements in the next row of the admittance matrix is calculated, the row address of the next row is obtained, the address of the current row is obtained, and the number of non-zero elements in the current row is calculated; the value of the row accumulated counter pointed to by the row address pointer register of the admittance matrix is updated.

[0022] The number of bytes in the current accumulated admittance matrix that need to be transmitted is updated.

[0023] The above steps are repeatedly executed, when the number of bytes in the current accumulated admittance matrix that need to be transmitted is greater than the maximum burst length, the read-write burst length of the memory is set as the maximum burst length, and the non-zero element part in the row pointed to by the row address pointer register of the admittance matrix is taken out; the remaining element number register is updated; if the value in the remaining element number register is greater than the maximum burst length, the data read out from the memory is directly written into the admittance matrix queue, and the value of the remaining element number register is updated.

[0024] The above data reading operation is repeatedly executed until the value in the remaining element number register is less than the maximum burst length; the number of non-zero elements in the next row is taken out from the GB_row_num_FIFO queue, the row address pointer register of the admittance matrix is updated, the row address of the next row is obtained, the address of the current row is obtained, and the number of non-zero elements in the current row is calculated; the value of the row accumulated non-zero element counter is updated; and the number of elements to be taken in the next row is accumulated in the byte number register.

[0025] When the admittance matrix access module writes the mutual admittance values in the upper triangular form into the memory, if the preset multiple of the current row non-zero element in the admittance matrix is greater than the maximum burst length, the value in the remaining element number register is updated as the sum of the preset multiple of the current row non-zero element in the admittance matrix and the maximum burst length, and the writing process is executed.

[0026] The technical solution adopted by the present application to solve the technical problems is to provide an admittance matrix processing method, comprising:

[0027] Receiving branch data, judging whether the branch contains a transformer according to the value of the non-standard transformer ratio, calculating the equivalent circuit of the branch, and completing the mutual admittance calculation from the current node from_bus to the target node to_bus within the interval of receiving two branch data, and synchronously writing the calculation result into the admittance matrix queue;

[0028] Receiving the mutual admittance value in the upper triangular form in the admittance matrix queue, and writing the mutual admittance value in the upper triangular form into the memory when the memory write burst length is reached.

[0029] The technical scheme adopted by the present application to solve its technical problems is to provide a power flow streaming parallel computing device, comprising the above admittance matrix processing module.

[0030] The power flow streaming parallel computing device further comprises:

[0031] The data receiving module is used for receiving the data sequence of the power grid binary, performing branch data format analysis, shifting the effective byte data obtained by analysis, and assembling the branch data;

[0032] The power imbalance dynamic increment calculation module is used for calculating the dynamic increment of the power imbalance of the node according to the node type;

[0033] The Jacobian matrix dynamic increment calculation module is used for calculating the partial derivative of the power and voltage of the i-th node to the voltage of the j-th node to the voltage of the j-th node according to the node type;

[0034] The mixed compression storage module of the Jacobian matrix is used for storing the row elements of the Jacobian matrix in the row compression format, and establishing a column data element chain table to realize the read-write operation of the rows and columns in the Jacobian matrix;

[0035] The Jacobian matrix block division calculation module is used for performing block division calculation on the Jacobian matrix;

[0036] The Jacobian matrix node sorting module is used for sorting the Jacobian submatrix structure calculated by the Jacobian matrix block division calculation module;

[0037] The tree topology calculation module of the matrix node is used for dynamically calculating the column data element chain table to obtain the Jacobian parallel level elimination tree;

[0038] The matrix sub-node resource allocation module is used for allocating computing resources to each node in the Jacobian parallel level elimination tree;

[0039] The Jacobian matrix parallel elimination tree calculation module is used for optimizing the node sorting of the Jacobian matrix;

[0040] The node merging assembly tree calculation module is configured to merge and combine nodes with the same non-zero element structure in the Jacobian parallel level elimination tree into super nodes, and calculate a parallel level assembly tree of the Jacobian matrix based on the super nodes.

[0041] The iterative parallel calculation module is configured to perform sub-matrix decomposition calculation on the parallel level assembly tree of the Jacobian matrix from lower layers to upper layers, and then perform parallel calculation on a sub-tree formed by all descendant nodes of a root node in the tree based on an optimal number of calculation resources allocated to each node.

[0042] The technical solution adopted by the present application to solve the technical problem is to provide a computer readable storage medium having a computer program stored thereon, the computer program being executed by a processor to implement the steps of the admittance matrix processing method.

[0043] Advantages

[0044] Compared with the prior art, the present application has the following advantages and positive effects: the present application is targeted at the data flow characteristics of the power grid, and realizes the completion of mutual admittance calculation using the symmetry of line impedance data without storing original line data, thereby realizing the calculation of the lower triangular part of the admittance matrix, completing the parallel pipeline calculation of the dynamic flow calculation admittance matrix value and power flow, improving the calculation efficiency of the power flow calculation mode, reducing resource consumption, and accelerating the power flow calculation time. BRIEF DESCRIPTION OF DRAWINGS

[0045] Figure 1 is a timing diagram of the flow calculation of the admittance matrix in the first embodiment of the present application;

[0046] Figure 2 is a storage timing logic diagram of the power flow branch data sequence in the first embodiment of the present application;

[0047] Figure 3 is a schematic diagram of the admittance matrix queue storage structure in the first embodiment of the present application;

[0048] Figure 4 is a flow chart of the flow calculation of the admittance matrix in the first embodiment of the present application;

[0049] Figure 5 is a timing diagram of the SDRAM reading of the admittance matrix in the first embodiment of the present application;

[0050] Figure 6 is a structural diagram of the power flow flow calculation device in the second embodiment of the present application. DETAILED DESCRIPTION

[0051] The application will be further described in connection with the following specific embodiments. It should be understood that these embodiments are only used to illustrate the application and not used to limit the scope of the application. Furthermore, it should be understood that after reading the content of the application, those skilled in the art can make various modifications or changes to the application, and these equivalent forms also fall within the scope defined by the appended claims.

[0052] The first embodiment of the application relates to a kind of admittance matrix processing module, comprising:

[0053] Admittance matrix streaming calculation module, for receiving branch data, according to the value of non-standard transformer ratio judgment branch whether containing transformer, and calculate branch equivalent circuit, and complete the mutual admittance calculation of current node from_bus to target node to_bus in the interval of receiving two branch data, and synchronously write the calculation result in admittance matrix queue;

[0054] Admittance matrix access module, for receiving the mutual admittance value of upper triangular form in the admittance matrix queue, and when reaching the memory write burst length, the mutual admittance value of upper triangular form is written into memory.

[0055] As Figure 1 As shown in the figure, it gives the timing logic of the non-zero element binary data sequence branch_data of power flow calculation branch triplets format received by FPGA serial port, wherein branch_data={frombus[31:0],tobus[31:0],impedance_R[31:0],impedance_X[31:0],susceptance_B[31:0],tranf_ratio[31:0]}, each row of branch data unit of branch_data is 24 bytes, including six data blocks, each data block is four bytes. Wherein, frombus and tobus respectively represent 32-bit branch starting and end point number, impedance_R and impedance_X respectively represent 32-bit branch resistance and reactance, susceptance_B represents 32-bit branch admittance to ground, and tranf_ratio represents the non-standard ratio coefficient of transformer-containing branch. The data received by FPGA from serial port does not need to store the original input data as cache, and the calculation of network admittance matrix data is completed directly in the interval of two data reception, and the embodiment designs a pipeline write data mode, and the admittance matrix result is saved to synchronous dynamic random access memory (SDRAM).

[0056] Figure 2The storage timing logic of the FPGA branch data sequence. The FPGA branch data sequence. The FPGA branch card sets the clock frequency to 50MHz, the period is 20ns, and the serial port receives the baud rate of 115200Bps. First, each data block in branch is assembled by the serial port receiving module in four bytes. When the branch_sig signal is valid, the FPGA end receives a byte of data data_out every 434 clock cycles, and delays one cycle to save it in the data register. count_data is the number of received branch data rows, data_type is the received data type label, data_type is 1 to 6, and each count interval, every four clock cycles, the data data is assembled and saved to the register frombus, the register tobus, the register impedance_R, the register impedance_X, the register susceptance_B, and the register tranf_ratio. When a row of data units in branch is received, the one_row_flag signal is pulled high, and the serial port receives 1bit data every 434 clock cycles. It takes 434*8 cycles to receive a byte of data. Each data type bit is 4 bytes long, and a data unit has 6 data, so a data unit transmission requires 434*8*4*6 cycles. When data_type=6 and one_row_flag=1, data_type=1 starts to loop. In the interval of each row of data transmission into the FPGA, the mutual admittance calculation of from_bus to to_bus is started, and the self-admittance cumulative value of from_bus is saved to the corresponding register. At the same time, since the branch data only retains the upper triangular matrix data, if the self-admittance data in the admittance matrix is directly calculated, it will not be able to be directly calculated due to the lack of lower triangular data of the matrix. The embodiment proposes a dynamic incremental calculation process of the lower triangular admittance matrix. The diagonal self-admittance value of the admittance matrix is stored separately in the dig_GB[63:0][n-1:0] register, which is 64 bits long and has a depth of n cells. n is the number of network nodes. In the process of calculating the admittance value of from_bus to other nodes, the admittance value of the target to_bus is dynamically accumulated and saved to the self-admittance diagonal matrix dig_GB. When the i-th row of data is read, dig_GB[i] is also calculated synchronously. When the transmission of the binary sequence of the branch triplet data is completed, the GB matrix stream calculation in the upper triangular form is completed synchronously, and the results are saved to the SDRAM.

[0057] Figure 3For the admittance matrix queue storage structure, a data unit includes mutual admittance from the bus to the bus, and is stored in the order of {conductance G, electric capacity B, admittance value column label GB col}. The GB matrix adopts a row compression storage format, including three registers, GB_row_ptr[31:0][n:0], GB_col[31:0][max_GB-1:0] and GB_data[63:0][max_GB-1:0], wherein n and max_GB are register depths, n represents the number of nodes of power flow calculation, and max_GB is the maximum non-zero element storage capacity of the matrix set in advance. The row address of the first non-zero element of each row of the admittance matrix is stored in GB_row_ptr, GB_col represents the column label value of the non-zero element, and GB_data represents the non-zero element data value.

[0058] Figure 4The flow chart of the streaming calculation of the branch data and the GB admittance matrix. The streaming calculation of the admittance matrix is divided into three steps: Step 1, the relevant lower triangular mutual admittance values of the historical to_bus are saved in advance to the admittance matrix diagonal line register dig_GB; Step 2, the mutual admittance (i < j) of the current form_bus to to_bus is calculated; and Step 3, the mutual admittance cumulative value of the current from_bus row is written into the target node. When the FPGA receives the from_bus of the ith data, the mutual admittance value of the corresponding from_bus to to_bus is calculated every time a to_bus data is received, and the result is sent to the GB_FIFO queue. According to the read transformer ratio tranf_ratio value, it is judged whether the branch contains a transformer. If tranf_ratio = 1, it indicates that the branch does not contain a transformer, and the mutual admittance value of the branch is directly calculated by the equivalent calculation of the branch impedance value and the ground admittance of the two ends. If tranf_ratio ≠ 1, it indicates that the branch contains a non-standard transformer ratio transformer, and the equivalent circuit of the transformer needs to be calculated. When the data of the node from_bus to all to_bus nodes is read and calculated, the self-admittance of the node from_bus is also accumulated and saved to the dia_GB[from_bus] register. At the same time, in the process of calculating the mutual admittance value of from_bus to to_bus, the corresponding mutual admittance value is synchronously accumulated and saved to dia_GB, that is, dia_GB[to_bus] ← dia_GB[to_bus] + the mutual admittance value of the current from_bus to to_bus. Finally, when the entire branch reading is completed, the dia_GB register saves the final correct self-admittance value of each node. The GB_FIFO[31:0][255:0] queue is 32 bits per unit, with a depth of 256 unit cells, and stores the upper triangular mutual admittance part of the GB admittance matrix. According to the consecutive three unit cells, the conductance B, the susceptance B and the column label value GB_col are stored.

[0059] The admittance matrix streaming calculation module in the embodiment maps the upper triangular form mutual admittance value of the current node from_bus to the target node to_bus to the contribution value of the target node to_bus to the lower triangular admittance matrix when calculating the mutual admittance, and accumulates the mutual admittance value of the target node to_bus to the self-admittance matrix register of the corresponding target node to_bus label. When all the rows of the current node from_bus are read, the self-admittance of the node is calculated synchronously, and when all the branch data are read, the self-admittance register of each node is calculated synchronously. The specific process is as follows:

[0060] Initialize the read-in branch counter, i.e. count_branch = 0, and the total branch number is branch_num. When the FPGA data reading module receives the read branch signal read_branch_sig = 1, it starts to receive the branch binary sequence from the serial port. Initialize the data valid byte counter cnt_bit, i.e. cnt_bit = 0. The cnt_bit receives a valid bit data every 434 clock cycles and starts to count repeatedly. Initialize the read-in byte counter, i.e. cnt_byte = 0. Initialize the data type identification register data_type, i.e. data_type = 1, indicating that the data received is of the from_bus type. Initialize the data counter cnt_one_data, i.e. cnt_one_data = 0, indicating that it takes 434x8x4 cycles to read a complete 4-byte data.

[0061] When the read-in branch number count_branch is less than the total branch number branch_num, the following process is repeatedly executed to calculate the mutual admittance and self-admittance of the admittance matrix.

[0062] When the data counter cnt_one_data = 434x8x4, it means that a complete data has been read in, and the data valid signal is pulled high, i.e. data_flga = 1. When data_flga = 1, the current data type register data_type is judged. When data_type = 1, 2, 3, 4, 5, or 6, the data is written into the from_bus, to_bus, impedance_R, impedance_X, susceptance_B, and tranf_ratio registers, respectively.

[0063] Then, it is judged whether the current branch contains a transformer, and two cases are considered according to whether it contains a transformer, and different calculation processes are executed.

[0064] If the transformer ratio register tranf_ratio = 1, it means that the current branch does not contain a transformer. This calculation process includes two parts, mutual admittance and self-admittance accumulation and addition, respectively.

[0065] First, calculate the mutual admittance of the current node from_bus to the target node to_bus:

[0066] First, calculate the impedance square sum, i.e. Then, calculate the branch admittance real part and the branch admittance imaginary part, respectively, i.e. , , then calculate the mutual admittance from the current node from_bus to the target node to_bus, including conductance data from_to_G and susceptance data from_to_B, i.e. from_to_G <- real_admittance, from_to_B <- imag_admittance. Raise the write enable signal W_GB_FIFO of the admittance matrix queue GB_FIFO, i.e. W_GB_FIFO <- 1, then execute the operation of writing the conductance data from_to_G into the admittance matrix queue GB_FIFO, i.e. write_FIFO[GB_FIFO, from_to_G], then execute the operation of writing the susceptance data from_to_B into the admittance matrix queue GB_FIFO, i.e. write_FIFO[GB_FIFO, from_to_B], then execute the operation of writing the column index value of the target node to_bus into the admittance matrix queue GB_FIFO, i.e. write_FIFO[GB_FIFO, to_bus], and finally, clear the write enable signal W_GB_FIFO of the admittance matrix queue GB_FIFO, i.e. W_GB_FIFO <- 0. After completing the calculation and writing of the mutual admittance from the current node from_bus to the target node to_bus, increase the row data counter branch_row_num of the current node from_bus by 1, i.e. branch_row_num <- branch_row_num + 1.

[0067] The self-admittance value of the lower triangular part in the admittance matrix related to the target node to_bus is accumulated and stored in the diagonal self-admittance dig_GB register, that is, the lower triangular part of the flow of the target node to_bus end is written: first, the self-admittance of the target node to_bus is calculated, including the conductance part self_to_bus_G and the susceptance part self_to_bus_B, and the self-admittance is the branch admittance real part and the branch admittance imaginary part plus half of the branch-to-ground susceptance, that is, self_to_bus_G←real_admittance+susceptance / 2, self_to_bus_B←imag_admittance+susceptance / 2. Then, the conductance value and the susceptance value of the self-admittance register dig_GB of the target node to_bus are updated, respectively, the self-admittance register dig_GB of the target node to_bus is 64 bits, the high 32 bits [63:32] store the conductance value, and the low 32 bits [31:0] store the susceptance value, and the specific is: the conductance value self_to_bus_G of the target node to_bus is updated and accumulated to the high bit of the self-admittance register of the target node to_bus, that is, dig_GB[to_bus][63:32]←dig_GB[to_bus][63:32]+ self_to_bus_G, and the susceptance value self_to_bus_B of the target node to_bus is updated and accumulated to the low bit of the self-admittance register of the target node to_bus, that is, dig_GB[to_bus][31:0]←dig_GB[to_bus][31:0]+ self_to_bus_B.

[0068] The self-admittance value of the lower triangular part in the admittance matrix related to the target node to_bus is accumulated and stored in the diagonal self-admittance dig_GB register, that is, the lower triangular part of the flow of the target node to_bus end is written: first, the self-admittance of the target node to_bus is calculated, including the conductance part self_to_bus_G and the susceptance part self_to_bus_B, and the self-admittance is the branch admittance real part and the branch admittance imaginary part plus half of the branch-to-ground susceptance, that is, self_to_bus_G←real_admittance+susceptance / 2, self_to_bus_B←imag_admittance+susceptance / 2. Then, the conductance value and the susceptance value of the self-admittance register dig_GB of the target node to_bus are updated, respectively, the self-admittance register dig_GB of the target node to_bus is 64 bits, the high 32 bits [63:32] store the conductance value, and the low 32 bits [31:0] store the susceptance value, and the specific is: the conductance value self_to_bus_G of the target node to_bus is updated and accumulated to the high bit of the self-admittance register of the target node to_bus, that is, dig_GB[to_bus][63:32]←dig_GB[to_bus][63:32]+ self_to_bus_G, and the susceptance value self_to_bus_B of the target node to_bus is updated and accumulated to the low bit of the self-admittance register of the target node to_bus, that is, dig_GB[to_bus][31:0]←dig_GB[to_bus][31:0]+ self_to_bus_B.

[0069] If the transformer ratio register tranf_ratio ≠ 1, it means that the branch contains a non-standard transformer, and the value of tranf_ratio is the transformer ratio. First, calculate the transformer branch of the equivalent circuit, and then calculate the mutual admittance and self-admittance cumulative values of the current node from_bus to the target node to_bus. This process includes two parts, mutual admittance part and self-admittance cumulative sum part.

[0070] Calculate the mutual admittance part of the branch current from_bus to the target node to_bus:

[0071] Calculate the transformer ratio square, i.e. k_square← , calculate the impedance square sum term , calculate the branch admittance real part real_admittance and branch admittance imaginary part imag_admittance without transformer, i.e. , ; then calculate the mutual admittance of the current node from_bus to the target node to_bus containing the transformer conversion part, including conductance data from_to_G and susceptance data from_to_B, i.e. from_to_G←-real_admittance / tranf_ratio, from_to_B←-imag_admittance / tranf_ratio. Then pull up the write valid signal W_GB_FIFO of the admittance matrix queue GB_FIFO, i.e. W_GB_FIFO←1, execute the operation of writing conductance data from_to_G into admittance matrix queue GB_FIFO, i.e. write_FIFO[GB_FIFO, from_to_G], then execute the operation of writing susceptance data from_to_B into admittance matrix queue GB_FIFO, i.e. write_FIFO[GB_FIFO, from_to_B], then execute the operation of writing the column label value of the target node to_bus into admittance matrix queue GB_FIFO, i.e. write_FIFO[GB_FIFO, to_bus], and finally, clear the write valid signal W_GB_FIFO of the admittance matrix queue GB_FIFO, i.e. W_GB_FIFO←0. When completing the branch mutual admittance calculation and writing of the current node from_bus to the target node to_bus, the data counter branch_row_num of the current node from_bus row is incremented by 1, i.e. branch_row_num←branch_row_num+1.

[0072] The self-admittance value of the lower triangular part of the admittance matrix related to the target node to_bus is accumulated and stored in the diagonal self-admittance dig_GB register.

[0073] According to the transformer The transformer equivalent circuit of the type calculates the self-admittance value of both sides, including the current node from_bus end and the target node to_bus end, specifically: calculate the self-admittance of the current node from_bus end containing the transformer conversion, including the conductance part from_transf_G and the susceptance part from_transf_B, that is, from_transf_G←real_admittance, from_transf_B←imag_admittance. Calculate the self-admittance of the target node to_bus end containing the transformer conversion, including the conductance part to_transf_G and the susceptance part to_transf_B, that is, to_transf_G←real_admittance / k_square, to_transf_B←imag_admittance / k_square.

[0074] Next, calculate the self-admittance value of the relevant target node to_bus after the transformer ratio conversion, and add the self-admittance value to dig_GB[to_bus] and write it into the lower triangle of the target node to_bus. The process is as follows: first calculate the self-admittance of the target node to_bus, including the conductance part self_to_bus_G and the susceptance part self_to_bus_B, where the self-admittance is the susceptance value to_transf_B of the target node to_bus after the transformer ratio conversion plus half of the susceptance of the branch to the ground, that is, self _to_bus_G←to_transf_B+susceptance / 2, self_to_bus_B←to_transf_B+susceptance / 2; then update the conductance and susceptance values ​​in the self-admittance register dig_GB of the target node to_bus respectively, specifically: update and accumulate the conductance value self_to_bus_G of the current target node to_bus to the high bit of the self-admittance register of the target node to_bus, that is, dig_GB[to_bus][63:32]←dig_GB[to_bus][63:32]+ self_to_bus_G, update and accumulate the susceptance value self_to_bus_B of the current node to_bus to the low bit of the self-admittance register of the target node to_bus, that is, dig_GB[to_bus][31:0]←dig_GB[to_bus][31:0]+ self_to_bus_B.

[0075] Calculate the accumulated sum of the self-admittance values ​​of the current node from_bus and update the conductance and susceptance parts of the self-admittance register dig_GB[from_bus] of the current node from_bus. Specifically, update the accumulated conductance value self_to_bus_G of the current node from_bus to the high bit of the self-admittance register of the current node from_bus, that is, dig_GB[from_bus][63:32]←dig_GB[from_bus][63:32]+ self_to_bus_G, and update the accumulated susceptance value self_to_bus_B of the current node from_bus to the low bit of the self-admittance register of the current node from_bus, that is, dig_GB[from_bus][31:0]←dig_GB[from_bus][31:0]+ self_to_bus_B.

[0076] The upper triangular form admittance matrix in this embodiment is stored in SDRAM in row compressed format, the read-write burst length register of SDRAM is set as RW_burst_length[7:0], when the read SDRAM signal read_sdram is valid, the first data is taken after a delay of delay_out clock cycles, and the address cannot cross the current partition at each read-write data.

[0077] The GB admittance matrix is stored in row compressed format, the GB_row_ptr[31:0] internal register represents the row address of the first non-zero element of each row in the GB matrix, the GB_col[31:0] represents the column index value corresponding to each non-zero element of the row, and the GB_data[63:0] represents the admittance value of each non-zero element. The admittance value of the i-th node to the j-th node , wherein, There are 64 bits in total, and the high 32 bits represent the conductance G, and the low 32 bits represent the susceptance B. In SDRAM, the admittance matrix data GB_data and the column index value GB_col are sequentially packed and linearly stored in the GB_data_col[95:0] register, that is, GB_data_col[95:0]={GB_data[63:0],GB_col[31:0]}, and each data unit includes 12 bytes. GB_data_col[95:64] represents the conductance value , GB_data_col[63:32] represents the susceptance value , and GB_data_col[31:0] represents the column index number of the admittance value.

[0078] Figure 5 The timing diagram for SDRAM reading GB admittance values is shown in the figure, WDATA_GB[31:0] represents the 32-bit data bus of SDRAM, head_addr represents the storage starting address of the GB admittance matrix in SDRAM. The read-write burst length register RW_burst_length of SDRAM is assigned a value, RW_burst_length←4, and 4 bytes of data can be taken out at each transmission. After 3 transmissions, one unit of 12 bytes of data in the GB admittance matrix can be taken out, and the assembled GB_data_col is sent to the data bus WDATA_GB[31:0] and stored in the GB_FIFO for data buffering.

[0079] First, the number of elements in each row of the GB admittance matrix is calculated, and the current_GB_ptr pointer register points to the current address in the GB_row_ptr. When the row counter k searches the entire GB_row_ptr register address from 0 to the matrix dimension n, the data in the adjacent cells in the GB_row_ptr is obtained from the current row k, the next row address next_row_addr is obtained, the current row address current_row_addr is obtained, and the number of non-zero elements in the current row current_row_num is calculated.

[0080] The number of data taken out of the GB matrix is recorded as num_GB, and the number of data transmission times from the SDRAM is num_trans. When the SDRAM data output valid signal SDRAM_data_valid = 1, the num_trans counter is incremented by 1, num_trans <- num_trans + 1. When num_trans = 3, the num_GB counter is incremented by 1, num_GB <- num_GB + 1. When the SDRAM read signal RD_SDRAM is valid, the data is read from the SDRAM in turn and stored in the GB_FIFO queue. The above steps are executed in a loop, and when the number of data taken out of the GB matrix num_GB counter value = the number of non-zero data in the current row of the admittance matrix current_row_num, it indicates that the non-zero elements in the row pointed to by current_GB_ptr have been completely read.

[0081] For the current row in the GB matrix, there are current_row_num non-zero elements, and the byte number register current_row_byte <- current_row_num x 12. The value of the byte number register current_row_byte is compared with the size of the maximum burst length max_burst_length, and different SDRAM read-write control processes are set, which are divided into two cases, as follows:

[0082] First, record the cumulative calculation register acc_GB_num of the row data taken out of the GB matrix, acc_GB_num <- current_row_num, and the remaining data counter of the current row of the GB matrix remaining_elements_GB <- 0.

[0083] If the value of the byte number register current_row_byte is less than or equal to the maximum burst length max_burst_length, the following write procedure is performed:

[0084] The read-write burst length RW_burst_length of the SDRAM is set to the value of the byte number register current_row_byte, i.e. RW_burst_length <- current_row_byte, and the current row in the GB matrix is fetched and stored in the FIGO in current_row_byte + delay_out clock cycles, where delay_out is the data output delay of the SDRAM. When the data of a row in the GB matrix is fetched and the maximum burst length is not reached, the data of the next row is fetched, the accumulated value acc_GB_num of the non-zero elements of the next row is judged, the GB_row_num_FIFO queue is set to store the number of non-zero elements of each row in the GB matrix, and the operation of writing the number of non-zero elements current_row_num of the current row in the GB matrix into the GB_row_num_FIFO queue is performed, i.e. write_FIFO[GB_row_num_FIFO, current_row_num]. At this time, the data read from the GB_row_num_FIFO indicates the number of non-zero elements of the current row.

[0085] The current row address pointer register current_GB_ptr of the GB matrix is set to current_GB_ptr + 1. The number of non-zero elements of the next row in the GB matrix is calculated, the address of the next row is obtained, i.e. next_row_addr <- GB_row_ptr[current_GB_ptr + 1], the address of the current row is obtained, i.e. current_row_addr <- GB_row_ptr[current_GB_ptr], the number of non-zero elements of the current row is calculated, i.e. current_row_num <- (next_row_addr - current_row_addr) / 12, and the accumulated counter acc_GB_num of the row pointed to by the current_GB_ptr of the admittance matrix is updated, i.e. acc_GB_num <- acc_GB_num + current_row_num.

[0086] Then, the number of bytes current_row_byte in the GB matrix that need to be transmitted is updated, i.e. current_row_byte <- current_row_byte + current_row_num x 12.

[0087] Finally, the above steps are repeated, and the size relationship between the number of bytes current_row_byte that need to be transmitted in the current accumulated GB matrix and the maximum burst length max_burst_length is judged. Until the number of bytes current_row_byte that need to be transmitted in the current accumulated GB matrix is greater than the maximum burst length max_burst_length, the SDRAM read-write burst length RW_burst_length is set to the maximum burst length max_burst_length, i.e. RW_burst_length←max_burst_length, and the non-zero element part in the row pointed to by the admittance matrix current row address pointer register current_GB_ptr is taken out. Then, the remaining element number register remaining_elements_GB is updated, i.e. remaining_elements_GB←current_row_byte-max_burst_length. The size relationship between the value in the remaining element number register and the maximum burst length max_burst_length is judged. If the value in the remaining element number register is greater than the maximum burst length max_burst_length, the data read out from the SDRAM is directly written into the admittance matrix queue GB_FIFO, and the remaining element number register is updated, i.e. remaining_elements_GB←remaining_elements_GB-max_burst_length.

[0088] The above data reading operation is repeatedly performed until the value in the remaining element number register is less than the maximum burst length max_burst_length, and then the next row of non-zero element numbers is taken out from the GB_row_num_FIFO queue, the current row address pointer register of the GB matrix is updated, that is, current_GB_ptr <- current_GB_ptr + 1, the row address of the next row is obtained, that is, next_row_addr <- GB_row_ptr[current_GB_ptr + 1], the address of the current row is obtained, that is, current_row_addr <- GB_row_ptr[current_GB_ptr], the non-zero element number of the current row is calculated, that is, current_row_num <- (next_row_addr - current_row_addr) / 12. The row cumulative non-zero element counter acc_GB_num is updated, that is, acc_GB_num <- acc_GB_num + current_row_num. The next row of element numbers to be taken out current_row_num is accumulated in the byte number register current_row_byte, that is, current_row_byte <- remaining_elements_GB + current_row_num * 12.

[0089] If the value in the byte number register is greater than the maximum burst length, then the value in the remaining element number register is directly updated to the sum of the preset multiple of the non-zero elements in the current row of the admittance matrix and the maximum burst length, that is, remaining_elements_GB <- current_row_byte + max_burst_length, and then the above-mentioned writing process is performed.

[0090] It can be found that, according to the power grid data flow characteristics, the present application realizes the calculation of the lower triangular part data of the admittance matrix by using the symmetry of the line impedance data without storing the original line data, completes the dynamic streaming calculation of the admittance matrix value, and realizes the parallel pipeline calculation of the power flow, thereby improving the calculation efficiency of the power flow calculation mode, reducing resource consumption, and accelerating the power flow calculation time.

[0091] The second embodiment of the present application relates to a power flow streaming parallel computing device, as shown in the accompanying drawings, comprising: Figure 6

[0092] ​The data receiving module is used for receiving the data sequence of the power grid binary, and performing branch data format analysis, and shifting the effective byte data obtained by the analysis to assemble the branch data. Specifically, the data receiving module is responsible for receiving the data sequence of the power grid binary read by the serial port, analyzing the branch data format, shifting the effective byte data received by the serial port in units of four bytes according to the serial port baud rate and clock frequency, assembling the original data of 32 bits and saving the original data into a data[31:0] register, and when the data is valid, that is, when the data_flag=1, according to the value of the data type identification counter data_type, when data_type=1, 2, 3, 4, 5, or 6, the data in the data is respectively assigned to six registers of frombus, tobus, impedance_R, impedance_X, susceptance_B and tranf_ratio, and the data is sent to the admittance matrix streaming calculation module in synchronization with the clock beat.

[0093] The admittance matrix streaming calculation module in the first embodiment is responsible for receiving the 32-bit branch data assembled by the data receiving module, judging whether the branch contains a transformer calculation branch equivalent circuit according to the value of the non-standard transformer ratio tranf_ratio, completing the mutual admittance calculation of from_bus to to_bus within the interval of two branch data sent by the data receiving module, and writing the data into the GB_FIFO queue in synchronization. At the same time, when each row of branch data is calculated, the upper triangular form of the mutual admittance value of from_bus to to_bus is mapped to the contribution value of the lower triangular to_bus node of the admittance matrix, and the target node mutual admittance value of to_bus is accumulated into the self-admittance matrix register dig_GB[to_bug] corresponding to the to_bus label. When all the rows of from_bus=i are read, the self-admittance of node i is also calculated and saved into dig_GB[i] in synchronization. When all the branch row data is read, the self-admittance register dig_GB of each node is also accumulated and updated to complete the calculation of the admittance matrix in synchronization, without the need for intermediate data buffering.

[0094] Sparse compressed data access module, which includes three parts, respectively, in the first embodiment of admittance matrix access module, jacoby_FIFO queue read-write control module and SDRAM read-write control module to keep the jacoby matrix. Admittance matrix access module is responsible for receiving admittance matrix stream computing module in the form of upper triangular mutual admittance value, when reaching SDRAM write burst length, by SDRAM control module is written into SDRAM memory. Jacoby_FIFO queue read-write control module is responsible for buffering the admittance matrix values read out by SDRAM when calculating jacoby matrix; at the same time, the partial derivative of the power and voltage of each node to the node voltage when calculating jacoby matrix is cached, when reaching SDRAM write burst length, by SDRAM control module is written into SDRAM memory. SDRAM read-write control module to keep the jacoby matrix is responsible for controlling the access operation of row compressed format admittance matrix and jacoby matrix.

[0095] Power imbalance dynamic increment calculation module, for calculating the partial derivative of the power and voltage of the i th node to the node voltage of the j th node according to the node type, specifically: through GB_FIFO control module and SDRAM control module, read the admittance matrix data in SDRAM by row and cache to SDRAM, determine the read-write burst length burst_length of SDRAM according to the number of non-zero elements of each row data in admittance matrix, judge the type of PQ node and PU node, respectively calculate the dynamic increment calculation of power imbalance of each node. Because SDRAM saves the upper triangular form of admittance matrix, when calculating the power imbalance of node i, the power accumulation of the lower triangular matrix (here, j<=i) part of node i to node j is missing, therefore, this embodiment reads the admittance matrix data of the i th row when calculating the dynamic increment of power imbalance, at the same time, the power contribution value to node j is accumulated into the register corresponding to the label j of power imbalance, which can update the power imbalance of the i th node after reading each row of admittance matrix value without repeatedly addressing the upper triangular part of admittance matrix value.

[0096] The Jacobian matrix dynamic incremental calculation module is configured to calculate the partial derivative of the power and voltage of the i-th node to the voltage of the j-th node according to the node type, specifically: through the GB_FIFO control module and the SDRAM control module, the admittance matrix data in the SDRAM is read by row and cached in the SDRAM, the read-write burst length burst_length of the SDRAM is determined according to the number of non-zero elements in each row of data in the admittance matrix, the types of PQ nodes and PU nodes are judged, and the partial derivative of the power and voltage of the i-th node to the voltage of the j-th node is calculated. Since the admittance matrix read in the SDRAM is in upper triangular form, in order to calculate one row of elements in the Jacobian matrix synchronously after each row of admittance data is read, the dynamic incremental calculation process of the Jacobian matrix in the embodiment is as follows: when the i-th row of admittance matrix data is read, the upper triangular partial derivative part of the Jacobian matrix above the diagonal line, i.e., node i to j (here, j>i), is preferentially calculated, and the partial derivative calculation result is written into the active power partial derivative register derivative_P_FIFO, the column label register of the active power partial derivative derivative_P_col_FIFO, the reactive power and voltage partial derivative register derivative_QU_FIFO, and the column label register of the reactive power and voltage partial derivative derivative_QU_col_FIFO. At the same time, the upper triangular part of the power contribution value of node i to j is mapped to the lower triangular part of the Jacobian matrix, and the numerical value is accumulated in the Jacobian matrix power contribution value register acc_M and acc_N. Subsequent reading of the k-th row (k>i) does not need to readdress the lower triangular part of the admittance matrix, i.e., the data of the first to k-1 columns, directly reads the data in the power contribution value register acc_M and acc_N corresponding to the label k, and continues to accumulate the power of the k-th row in the upper triangular part to the acc_M and acc_N registers. When the k-th row of data is read, the value in the power accumulation contribution value acc_M and acc_N register is the power accumulation value of node k to all nodes in the row.

[0097] The mixed compression storage module of the Jacobian matrix is used for storing the row elements of the Jacobian matrix in a row compression format, and establishing a column data element linked list to realize the read-write operation on the rows and columns in the Jacobian matrix. In order to facilitate the read of the data by the matrix LU decomposition by row and by column during the calculation of the power flow sparse equation set, the waste of logical resources and time sequence caused by data addressing is saved. The Jacobian column data linked list can provide convenience in data search in the subsequent calculation process of the Jacobian matrix block division, node optimal sorting and node parallel elimination tree, and can quickly locate the parent node and child node of a node. During the calculation of the Jacobian matrix element of the jth node by the ith node, a local 2*2 partial derivative sub-matrix is generated, and in the process of writing into the SDRAM, in order to maintain the structural integrity of the Jacobian matrix, the local 2*2 sub-matrix is written into the active power partial derivative register derivative_P_FIFO, the column label register derivative_P_col_FIFO of the active power partial derivative, the reactive power and voltage partial derivative register derivative_QU_FIFO, and the column label register derivative_QU_col_FIFO of the reactive power and voltage partial derivative, respectively, and a FIFO read-write control module is designed to rearrange and assemble the active power partial derivative and the reactive power and voltage partial derivative data into a 12-byte data, and write the active power partial derivative and the reactive power and voltage partial derivative data into the SDRAM in the order of active power partial derivative first and then reactive power and voltage partial derivative. During the process of writing data into the SDRAM, the next row of Jacobian matrix data is read out from the FIFO and calculated in a pipeline.

[0098] The Jacobian matrix block division calculation module is used for block division calculation of the Jacobian matrix. Because the Jacobian matrix is an upper triangular matrix and is asymmetric, in order to reduce the number of non-zero elements generated in the LU decomposition process of the Jacobian matrix and reduce the utilization rate of storage resources, the multi-objective genetic annealing algorithm is used to divide the Jacobian matrix. The method constructs a graph data structure of the Jacobian matrix, and the optimal block structure of the Jacobian matrix can be calculated by the method. Under the condition of meeting the load balancing of each parallel matrix decomposition module, the least number of non-zero elements is generated in the sub-matrix decomposition process, and the data dependency between each sub-matrix is minimized, thereby improving the calculation efficiency of the sub-matrix parallel decomposition.

[0099] The Jacobian matrix node sorting module is used for node sorting of the Jacobian sub-matrix structure calculated by the Jacobian matrix block division calculation module. In the process of power flow calculation, the Jacobian matrix of the node is calculated from the admittance matrix and the imbalance of power and voltage square , and the power flow imbalance equation , the Jacobian matrix The optimal node ordering of the Jacobian matrix can improve the calculation efficiency of the decomposition of the power flow equation Jacobian matrix. Meanwhile, the parallelism of the decomposition of the Jacobian matrix is improved, and thus the power flow calculation time is accelerated.

[0100] The tree topology calculation module of the matrix node is used for dynamically calculating the column data element linked list to obtain the Jacobian parallel level elimination tree. The module adopts the hybrid storage structure of the Jacobian matrix column linked list and the row compressed format sparse matrix, realizes the fast transposition calculation of the sparse Jacobian matrix element, can improve the simultaneous extraction of all elements in a row and a column of the Jacobian matrix when solving the Jacobian matrix decomposition of the power flow sparse equation set, reduces the column data addressing time, and accelerates the equation set solving efficiency. Meanwhile, the module also adopts the child-parent hybrid storage structure of the Jacobian matrix elimination tree structure, including the parent node number of each node and the linked list of each child, can realize the effective calculation and data storage of the node level ordering sequence in the elimination tree calculation process. The module also provides the node number of the calculation resource allocation for the multi-front surface power flow power sparse equation parallel solving module, and the storage of the submatrix decomposition result. In addition, the linked list storage space is allocated for the contribution submatrix of the lower layer submatrix to the upper layer node, and the influence of the lower layer node contribution submatrix is superimposed to the corresponding node number of the upper layer for storage.

[0101] The matrix sub-node resource allocation module is used for allocating the calculation resource to each node in the Jacobian parallel level elimination tree, improving the calculation efficiency of the Jacobian matrix decomposition calculation task, and meeting the load balancing of each node and calculation branch, so that the overall power flow equation calculation time is the shortest. The resource allocation process includes two stages of forward search and reverse search. In the forward search calculation stage, the estimation value of the resource allocation number of all nodes in the Jacobian level elimination tree is completed, and in the reverse search stage, the node submatrix calculation module (sub_matrix_compute, SMC) resource number value allocation and resource number correction are performed.

[0102] The Jacobian matrix parallel elimination tree calculation module is used for optimizing the node ordering of the Jacobian matrix. The module constructs the level elimination tree structure, and all sub-tree branches under the same root node on the same branch have no data dependency between each other, each branch can be calculated synchronously and in parallel, so that the parallelism of the matrix decomposition is improved, and at the same time, the Jacobian matrix decomposition process produces the least non-zero element filling when the power flow equation is calculated, reduces the storage resource consumption, and accelerates the power flow calculation time.

[0103] The node merging assembly tree calculation module is used for merging and combining nodes with the same non-zero element structure in the Jacobian parallel level elimination tree into super nodes, and calculating a parallel level assembly tree of the Jacobian matrix based on the super nodes. The module performs data dimension reduction on the original Jacobian matrix, calculates a parallel level assembly tree of the Jacobian matrix, each node in the assembly tree is a set of original Jacobian matrix nodes, and the assembly tree can more efficiently perform parallel level division on the Jacobian matrix, synchronously performs parallel decomposition of sub-matrices of sub-branches without mutual dependence, and speeds up the efficiency of matrix decomposition of power flow calculation sparse equations.

[0104] The multi-frontal power flow sparse equation matrix hierarchical iteration parallel calculation module is used for performing sub-matrix decomposition calculation on the parallel level assembly tree of the Jacobian matrix from the lower layer to the upper layer, and then performing parallel calculation on a sub-tree formed by all descendant nodes of a root node in the tree based on the optimal number of calculation resources allocated to each node. The module allocates all descendant child branches of the same node to the same sub-matrix calculation module (sub_matrix_compute, SMC), performs matrix decomposition iteration calculation from the end node to the upper layer after the sub-matrix decomposition calculation is completed, and gradually accumulates the contribution results to the upper root node, and finally completes the decomposition of the entire Jacobian matrix, thereby speeding up the calculation speed of matrix decomposition of power flow calculation sparse equations.

[0105] The third embodiment of the present application relates to a method for processing an admittance matrix, comprising the following steps:

[0106] Receiving branch data, judging whether the branch contains a transformer according to the value of the non-standard transformer ratio, calculating the equivalent circuit of the branch, and completing the mutual admittance calculation of the current node from_bus to the target node to_bus within the interval of receiving two pieces of branch data, and synchronously writing the calculation result into the admittance matrix queue;

[0107] Receiving the mutual admittance value in the upper triangular form in the admittance matrix queue, and writing the mutual admittance value in the upper triangular form into the memory when the memory write burst length is reached.

[0108] When the mutual admittance calculation of the current node from_bus to the target node to_bus is completed within the interval of receiving two pieces of branch data, the mutual admittance value in the upper triangular form of the current node from_bus to the target node to_bus is mapped to the contribution value of the lower triangular target node to_bus of the admittance matrix, and the mutual admittance value of the target node to_bus is accumulated into the self-admittance matrix register corresponding to the label of the target node to_bus, the self-admittance synchronous calculation of the node is completed after all the row reading of the current node from_bus is completed, and the self-admittance register synchronous accumulation update calculation of each node is completed after all the branch data reading is completed.

[0109] When the current branch does not contain a transformer, the calculation process is as follows:

[0110] Calculate the impedance square sum, branch admittance real part and branch admittance imaginary part, and the mutual admittance of the current node from bus to the target node to bus; pull up the write valid signal of the write admittance matrix queue, write the conductance data in the mutual admittance of the current node from bus to the target node to bus into the admittance matrix queue, and write the susceptance data in the mutual admittance of the current node from bus to the target node to bus into the admittance matrix queue; write the column label value of the target node to bus into the admittance matrix queue; clear the write valid signal of the write admittance matrix queue; after completing the mutual admittance of the current node from bus to the target node to bus and writing, increase the row data number counter of the current node from bus by 1;

[0111] Calculate the self-admittance of the target node to bus, and the self-admittance is the sum of the branch admittance real part and imaginary part plus half of the ground susceptance at both ends of the branch; update the accumulated conductance value of the target node to bus into the high bit of the self-admittance register of the target node to bus, and update the accumulated susceptance value of the target node to bus into the low bit of the self-admittance register of the target node to bus;

[0112] Calculate the self-admittance value accumulation of the current node from bus, and update the accumulated conductance value of the current node from bus into the high bit of the self-admittance register of the current node from bus, and update the accumulated susceptance value of the current node from bus into the low bit of the self-admittance register of the current node from bus.

[0113] When the current branch contains a transformer, the calculation process is as follows:

[0114] The variable ratio square sum, impedance square sum, branch admittance real part and branch admittance imaginary part without transformer, and mutual admittance of the transformer-contained conversion part of the current node from_bus to the target node to_bus are calculated; the write enable signal of the write admittance matrix queue is pulled high, the conductance data in the mutual admittance of the transformer-contained conversion part of the current node from_bus to the target node to_bus is written into the admittance matrix queue, the susceptance data in the mutual admittance of the transformer-contained conversion part of the current node from_bus to the target node to_bus is written into the admittance matrix queue, and the column label value of the target node to_bus is written into the admittance matrix queue; the write enable signal of the write admittance matrix queue is cleared; after the mutual admittance calculation and writing of the transformer-contained conversion part of the current node from_bus to the target node to_bus are completed, the row data counter of the current node from_bus is incremented by 1.

[0115] The self-admittance of the current node from_bus end with transformer conversion and the self-admittance of the target node to_bus end with transformer conversion are calculated.

[0116] The self-admittance of the target node to_bus is calculated, which is the self-admittance of the target node to_bus end with transformer conversion plus half of the branch-to-ground susceptance; the accumulated conductance value of the target node to_bus is updated into the high bit of the self-admittance register of the target node to_bus, and the accumulated susceptance value of the current node to_bus is updated into the low bit of the self-admittance register of the target node to_bus.

[0117] The self-admittance value accumulation of the current node from_bus is calculated, and the accumulated conductance value of the current node from_bus is updated into the high bit of the self-admittance register of the current node from_bus; the accumulated susceptance value of the current node from_bus is updated into the low bit of the self-admittance register of the current node from_bus.

[0118] When writing the mutual admittance value in upper triangular form into the memory, if the preset multiple of the current row non-zero elements in the admittance matrix is less than or equal to the maximum burst length, the following writing process is performed:

[0119] The preset multiple of the current row non-zero elements in the admittance matrix is set as the read-write burst length of the memory; when the admittance matrix data is taken to the read-write burst length of the memory, the next row data is continued to be taken, the accumulated value of the next row non-zero elements is judged, the non-zero element number of each row in the admittance matrix is stored in the GB_row_num_FIFO queue, and the current row non-zero element number in the admittance matrix is written into the GB_row_num_FIFO queue.

[0120] The number of non-zero elements of the next row of the admittance matrix is calculated, the row address of the next row is obtained, the address of the current row is obtained, and the number of non-zero elements of the current row is calculated; the value of the row cumulative counter pointed to by the current row address pointer register of the admittance matrix is updated;

[0121] The number of bytes of the current accumulated admittance matrix to be transmitted is updated;

[0122] The above steps are repeatedly executed, when the number of bytes of the current accumulated admittance matrix to be transmitted is greater than the maximum burst length, the read-write burst length of the memory is set to the maximum burst length, and the non-zero element part in the row pointed to by the current row address pointer register of the admittance matrix is taken out; the remaining number of elements to be taken out register is updated; if the value in the remaining number of elements to be taken out register is greater than the maximum burst length, the data read out from the memory is directly written into the admittance matrix queue, and the value of the remaining number of elements to be taken out register is updated;

[0123] The above data reading operation is repeatedly executed until the value in the remaining number of elements to be taken out register is less than the maximum burst length; the number of non-zero elements of the next row is taken out from the GB_row_num_FIFO queue, the current row address pointer register of the admittance matrix is updated, the row address of the next row is obtained, the address of the current row is obtained, and the number of non-zero elements of the current row is calculated; the value of the row cumulative non-zero element counter is updated; and the number of elements to be taken out of the next row is added to the byte number register.

[0124] When the mutual admittance values in the upper triangular form are written into the memory, if the preset multiple of the non-zero elements of the current row in the admittance matrix is greater than the maximum burst length, the value in the remaining number of elements to be taken out register is updated to the sum of the preset multiple of the non-zero elements of the current row in the admittance matrix and the maximum burst length, and the writing process is executed.

[0125] The fourth embodiment of the present application relates to a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the steps of the admittance matrix processing method of the third embodiment.

[0126] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can adopt a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage and optical storage, etc.) containing computer usable program code.

[0127] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flow or blocks. Figure 1 one or more flow or blocks.

[0128] These computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart block or blocks. Figure 1 one or more flow or blocks. Figure 1 one or more flow or blocks.

[0129] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flow or blocks. Figure 1 one or more flow or blocks.

[0130] The above description is only specific embodiments of the application, but the protection scope of the application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the application, which should be covered by the protection scope of the application. Therefore, the protection scope of the application should be subject to the protection scope of the claims.

Claims

1. An admittance matrix processing module, characterized in that: include: The admittance matrix streaming calculation module is used to receive branch data, determine whether the branch contains a transformer based on the value of the non-standard transformer ratio, calculate the branch equivalent circuit, and use the symmetry of the line impedance data to complete the mutual admittance calculation of the current node from_bus to the target node to_bus within the interval between receiving two branch data, and synchronously write the calculation results to the admittance matrix queue; The admittance matrix access module is used to receive the upper triangular transadmittance values ​​in the admittance matrix queue and write the upper triangular transadmittance values ​​into the memory when the memory write burst length is reached.

2. The admittance matrix processing module according to claim 1, characterized in that: When performing mutual admittance calculation, the admittance matrix streaming calculation module maps the mutual admittance value of the current node from_bus to the target node to_bus in the upper triangular form to the contribution value to the target node to_bus in the lower triangular form of the admittance matrix, and accumulates the mutual admittance value of the target node to_bus into the self-admittance matrix register corresponding to the label of the target node to_bus. When all rows of the current node from_bus are read, the self-admittance of the node is synchronously calculated. When all branch data are read, the self-admittance registers of each node are synchronously accumulated and updated.

3. The admittance matrix processing module according to claim 2, characterized in that: When the current branch does not contain a transformer, the calculation process of the admittance matrix flow calculation module is as follows: Calculate the square sum of impedances, the real part of branch admittance, the imaginary part of branch admittance, and the mutual admittance of the current node from_bus to the target node to_bus; pull high the write valid signal of the write admittance matrix queue, write the conductance data in the mutual admittance of the current node from_bus to the target node to_bus into the admittance matrix queue, and write the admittance data in the mutual admittance of the current node from_bus to the target node to_bus into the admittance matrix queue; write the column label value of the target node to_bus into the admittance matrix queue; clear the write valid signal of the write admittance matrix queue; after completing the mutual admittance and write of the current node from_bus to the target node to_bus, increment the row data count counter of the current node from_bus by 1; Calculate the self-admittance of the target node to_bus, where the self-admittance is the real and imaginary parts of the branch admittance plus half of the susceptance of the branch to the ground at both ends; update the accumulated conductance value of the target node to_bus to the high bit of the self-admittance register of the target node to_bus, and update the accumulated susceptance value of the target node to_bus to the low bit of the self-admittance register of the target node to_bus; Calculate the accumulated sum of the self-admittance values ​​of the current node from_bus, and update the accumulated conductance value of the current node from_bus to the high bit of the self-admittance register of the current node from_bus, and update the accumulated susceptance value of the current node from_bus to the low bit of the self-admittance register of the current node from_bus.

4. The admittance matrix processing module according to claim 2, characterized in that: When the current branch contains a transformer, the calculation process of the admittance matrix flow calculation module is as follows: Calculate the sum of squares of the transformation ratio, the sum of squares of the impedance, the real part of the branch admittance and the imaginary part of the branch admittance when the transformer is not included, and the mutual admittance of the current node from_bus to the target node to_bus including the transformer conversion part; pull up the write valid signal of the write admittance matrix queue, write the conductance data in the mutual admittance of the current node from_bus to the target node to_bus including the transformer conversion part into the admittance matrix queue, write the admittance data in the mutual admittance of the current node from_bus to the target node to_bus including the transformer conversion part into the admittance matrix queue, and write the column label value of the target node to_bus into the admittance matrix queue; clear the write valid signal of the write admittance matrix queue; after completing the calculation and writing of the mutual admittance including the transformer conversion part of the current node from_bus to the target node to_bus, add 1 to the row data number counter of the current node from_bus; Calculate the self-admittance of the current node from_bus end including the transformer conversion, and the self-admittance of the target node to_bus end including the transformer conversion; Calculate the self-admittance of the target node to_bus, which is the self-admittance of the target node to_bus including the transformer conversion plus half of the susceptance of the branch to ground; update the accumulated conductance value of the target node to_bus to the high bit of the self-admittance register of the target node to_bus, and update the accumulated susceptance value of the current node to_bus to the low bit of the self-admittance register of the target node to_bus; Calculate the accumulated sum of the self-admittance values ​​of the current node from_bus, and update the accumulated conductance value of the current node from_bus to the high bit of the self-admittance register of the current node from_bus; update the accumulated susceptance value of the current node from_bus to the low bit of the self-admittance register of the current node from_bus.

5. The admittance matrix processing module according to claim 1, characterized in that: When the admittance matrix access module writes the upper triangular mutual admittance value into the memory, if the preset multiple of the non-zero elements in the current row of the admittance matrix is ​​less than or equal to the maximum burst length, the following writing process is performed: Setting a preset multiple of the non-zero elements in the current row of the admittance matrix as the read / write burst length of the memory; when the read / write burst length of the memory does not reach the read / write burst length of the memory after the data of one row of the admittance matrix is ​​retrieved, continuing to retrieve the data of the next row, determining the accumulated value of the non-zero elements of the next row, setting a GB_row_num_FIFO queue to store the number of non-zero elements in each row of the admittance matrix, and writing the number of non-zero elements in the current row of the admittance matrix into the GB_row_num_FIFO queue; Calculate the number of non-zero elements in the next row of the admittance matrix, obtain the row address of the next row, obtain the address of the current row, and calculate the number of non-zero elements in the current row; Update the value of the row accumulation counter pointed to by the current row address pointer register of the admittance matrix; Update the number of bytes that need to be transmitted in the current accumulated admittance matrix; Repeat the above steps. When the number of bytes to be transmitted in the currently accumulated admittance matrix is ​​greater than the maximum burst length, set the read / write burst length of the memory to the maximum burst length, extract the non-zero elements in the row pointed to by the current row address pointer register of the admittance matrix, and update the register for the number of remaining untaken elements. If the value in the register for the number of remaining untaken elements is greater than the maximum burst length, directly write the data read from the memory into the admittance matrix queue and update the value of the register for the number of remaining untaken elements. Repeat the above data reading operation until the value in the register for the number of remaining unread elements is less than the maximum burst length; take the number of non-zero elements in the next row from the GB_row_num_FIFO queue, update the current row address pointer register of the admittance matrix, obtain the row address of the next row, obtain the address of the current row, and calculate the number of non-zero elements in the current row; Update the row cumulative non-zero element counter value; accumulate the number of elements to be taken in the next row into the byte number register.

6. The admittance matrix processing module according to claim 5, characterized in that: When the admittance matrix access module writes the mutual admittance value in upper triangular form into the memory, if the preset multiple of the non-zero elements in the current row of the admittance matrix is ​​greater than the maximum burst length, the value in the register for the number of remaining untaken elements is updated to the sum of the preset multiple of the non-zero elements in the current row of the admittance matrix and the maximum burst length, and the writing process is executed.

7. A method for processing an admittance matrix, characterized in that: The following steps are involved: Receive branch data, determine whether the branch contains a transformer based on the value of the non-standard transformer ratio, calculate the branch equivalent circuit, and use the symmetry of the line impedance data to complete the mutual admittance calculation of the current node from_bus to the target node to_bus within the interval between receiving two branch data, and synchronously write the calculation results to the admittance matrix queue; The upper triangular transadmittance values ​​in the admittance matrix queue are received, and when a memory write burst length is reached, the upper triangular transadmittance values ​​are written into the memory.

8. A power flow parallel computing device, characterized in that: The method comprises the admittance matrix processing module as claimed in any one of claims 1 to 6.

9. The power flow parallel computing device according to claim 8, characterized in that: Also includes: The data receiving module is used to receive the binary data sequence of the power grid, parse the branch data format, shift the valid byte data obtained by parsing, and assemble them into branch data; A power imbalance dynamic increment calculation module is used to calculate the dynamic increment of the power imbalance of a node according to the node type; Jacobian matrix dynamic incremental calculation module, used to calculate the partial derivatives of the power and voltage of the i-th node with respect to the j-th node voltage according to the node type; A hybrid compression storage module for the Jacobian matrix, which is used to store the row elements of the Jacobian matrix in a row-compressed format and establish a column data element linked list to implement read and write operations on the rows and columns of the Jacobian matrix; Jacobian matrix block partitioning calculation module, used to divide the Jacobian matrix into blocks for calculation; A Jacobian matrix node sorting module is used to sort the nodes of the Jacobian submatrix structure calculated by the Jacobian matrix block partitioning calculation module; The tree topology calculation module of the matrix node is used to dynamically calculate the column data element linked list to obtain the Jacobi parallel hierarchical elimination tree; Matrix sub-node resource allocation module, used to allocate computing resources to each node in the Jacobi parallel hierarchical elimination tree; Jacobian matrix parallel elimination tree calculation module, used to optimize the node ordering of the Jacobian matrix; A node merging assembly tree calculation module is used to merge nodes with the same non-zero element structure in the Jacobi parallel hierarchical elimination tree into super nodes, and calculate the parallel hierarchical assembly tree of the Jacobi matrix based on the super nodes; The iterative parallel computing module is used to perform sub-matrix decomposition calculations from the lower layer to the upper layer of the parallel hierarchical assembly tree of the Jacobian matrix, and then allocate the optimal number of computing resources to each node to perform parallel calculations on the subtree composed of all descendant nodes of the root node in the tree.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the admittance matrix processing method according to claim 7 are implemented.

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