Semiconductor power module and packaging method thereof

Abstract

The invention relates to the technical field of semiconductor packaging, and discloses a semiconductor power module and a packaging method thereof. The method comprises the following steps: S1, providing a substrate and at least one power chip; s2, when the preset metallization layer does not exist on the upper surface and / or the lower surface of the power chip, a first metallization layer is preset on the upper surface of the power chip and / or a second metallization layer is preset on the lower surface of the power chip; s3, carrying out activated coating treatment and / or planarization treatment on the surface of the substrate to form an activated coating and / or a planarized surface; s4, placing the power chip on the substrate, and completing interconnection between the substrate and the power chip through a hot pressing sintering process; s5, connecting the power chip and the substrate by using a connecting key to obtain an interconnection structure; and S6, performing packaging processing and terminal forming on the interconnection structure to obtain the semiconductor power module. Through the mode, the cost can be saved, the process risk can be reduced, and the reliability of the semiconductor power module can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a semiconductor power module and a packaging method thereof. Background Art

[0002] As new energy vehicles develop toward higher power density and reliability, power devices and modules are facing increasingly stringent requirements for electrical performance and packaging. To meet these demands, silicon carbide power devices and modules are becoming increasingly popular. Regarding packaging, advanced interconnect technologies, high-performance packaging materials, low stray inductance, and high heat dissipation performance are also becoming industry trends.

[0003] At present, the power module packaging structure of related technologies generally includes a ceramic copper-clad substrate, a power chip, a metal wire, a lead frame, and a plastic shell. The packaging method is as follows: tin-based solder or sintering material (generally silver-based high-temperature slurry) is applied to the surface of the upper circuit copper layer of the ceramic copper-clad substrate at the position corresponding to the power chip; the power chips are sequentially attached to the corresponding positions, and the lower surface is subjected to reflow soldering or pressure sintering; the ceramic copper-clad substrate and the lead frame are fixed and installed by a positioning fixture, and the pre-coated solder at the connection is vacuum reflow soldered; the upper surface of the power chip is then connected to the circuit layer of the ceramic copper-clad substrate by metal wire (generally ultrasonic welding); the product with the patch wire bonded is placed in an injection mold for injection molding to form a plastic shell; the connection frame portion of the lead frame is cut off, and the pins are bent into the required shape (adaptive to PCB circuit board installation). The metal wires and lead frames are both used as circuit conductors to achieve internal and external circuit interconnection.

[0004] The above encapsulation method has the following disadvantages:

[0005] (1) The connection between the power chip and the metal frame (busbar) or copper-clad ceramic substrate often relies on silver-based sintering paste, which has high material costs;

[0006] (2) Solder and paste may experience shrinkage and overflow during drying and sintering processes, which may affect accuracy and even insulation performance;

[0007] (3) The silver-based sintering slurry process requires a pre-deposited silver layer on the surface of the metal frame (busbar) or copper-clad ceramic substrate. However, the resulting silver / copper interface and the slurry silver / pre-deposited silver interface have reliability issues such as silver migration, high-temperature oxidation, and de-wetting of the coating.

[0008] (4) The multi-layer metal interface structure has large stray inductance and high loss. Summary of the Invention

[0009] The present invention provides a semiconductor power module and a packaging method thereof, which can solve the above problems.

[0010] To solve the above technical problems, the present invention adopts a technical solution: providing a packaging method for a semiconductor power module, comprising:

[0011] Step S1: providing a substrate and at least one power chip;

[0012] Step S2: When no preset metallization layer exists on the upper surface and / or lower surface of the power chip, pre-positioning a first metallization layer on the upper surface of the power chip and / or pre-positioning a second metallization layer on the lower surface of the power chip;

[0013] Step S3: performing an activation coating treatment and / or a flattening treatment on the surface of the substrate to form an activation coating and / or a flattened surface;

[0014] Step S4: placing the power chip on the substrate, and completing the interconnection between the substrate and the power chip through a hot pressing sintering process based on the activated coating and / or the planarized surface;

[0015] Step S5: connecting the upper surface of the power chip and the substrate using a connecting key to obtain an interconnection structure;

[0016] Step S6: performing packaging processing and terminal forming on the interconnection structure to obtain the semiconductor power module.

[0017] According to one embodiment of the present invention, in step S2, the activated coating is a single layer or a composite layer, and the outermost layer of the activated coating is a single metal, an alloy or a compound.

[0018] According to one embodiment of the present invention, when no preset metallization layer exists on the upper surface and / or lower surface of the power chip, pre-positioning a first metallization layer on the upper surface of the power chip and / or pre-positioning a second metallization layer on the lower surface of the power chip includes:

[0019] When at least one metallization layer exists on the upper surface and / or lower surface of the power chip, and the outermost layer of the metallization layer is not the preset metallization layer, pre-positioning a first metallization layer on the upper surface of the power chip and / or pre-positioning a second metallization layer on the lower surface of the power chip;

[0020] When no metallization layer exists on the upper surface and / or lower surface of the power chip, at least one first metallization layer is pre-disposed on the upper surface of the power chip and / or at least one second metallization layer is pre-disposed on the lower surface of the power chip.

[0021] According to one embodiment of the present invention, the outermost layer of the first metallization layer is a single metal, alloy or compound; the outermost layer of the second metallization layer is a single metal, alloy or compound.

[0022] According to one embodiment of the present invention, the substrate of the power chip is provided with a micro-groove array structure; when a second metallization layer is pre-disposed on the lower surface of the power chip, the second metallization layer is located on the surface of the micro-groove array structure.

[0023] According to one embodiment of the present invention, the packaging method further includes:

[0024] Placing a copper foil layer on the upper surface of the power chip, and performing activation plating and / or flattening treatment on the surface of the copper foil layer;

[0025] When a first metallization layer is pre-installed on the upper surface of the power chip, the copper foil layer is connected to the first metallization layer on the upper surface of the power chip based on the hot pressing and sintering process, and the copper foil layer is used to connect the connection key.

[0026] According to one embodiment of the present invention, the packaging method further includes:

[0027] A heat sink is provided, and the back surface of the substrate and / or the surface of the heat sink are subjected to activation plating treatment and / or flattening treatment, and the heat sink is connected to the back surface of the substrate based on the hot pressing sintering process.

[0028] According to one embodiment of the present invention, before step S2, the packaging method further includes:

[0029] The substrate is subjected to a reducing gas heating treatment to remove an oxide layer on the surface of the substrate.

[0030] According to one embodiment of the present invention, the substrate includes a ceramic copper-clad substrate, a metal frame or a metal busbar.

[0031] In order to solve the above technical problems, another technical solution adopted by the present invention is: providing a semiconductor power module, which is prepared by adopting the packaging method of the semiconductor power module.

[0032] The beneficial effects of the present invention are as follows: a packaging method for a semiconductor power module includes: step S1: providing a substrate and at least one power chip; step S2: when there is no preset metallization layer on the upper surface and / or lower surface of the power chip, pre-setting a first metallization layer on the upper surface of the power chip and / or pre-setting a second metallization layer on the lower surface of the power chip; step S3: performing activation plating treatment and / or flattening treatment on the surface of the substrate to form an activated plating layer and / or a flattened surface; step S4: placing the power chip on the substrate, and completing the interconnection between the substrate and the power chip through a hot pressing sintering process based on the activated plating layer and / or the flattened surface; step S5: using a connecting key to connect the upper surface of the power chip and the substrate to obtain an interconnection structure; step S6: performing packaging treatment and terminal forming on the interconnection structure to obtain the semiconductor power module. In this packaging method, the connection between the substrate and the power chip does not rely on sintering slurry, which not only saves slurry costs and equipment investment and energy consumption related to the printing process, but also solves problems such as dimensional shrinkage, slurry overflow, and chip tilt caused by slurry drying and sintering processes, thereby improving assembly accuracy; this packaging method does not require a pre-plated silver layer on the substrate surface, which saves costs and reduces process risks, while also avoiding reliability risks such as silver migration, high-temperature oxidation, and plating dewetting between the silver / copper interface and the slurry silver / pre-plated silver interface; in addition, since the structure of the interface metallization layer has been simplified, the corresponding thermal conductivity, electrical conductivity, and anti-stray performance are also improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 1 is a flow chart of a method for packaging a semiconductor power module according to an embodiment of the present invention;

[0034] Figure 2 is a schematic structural diagram of an interconnection structure according to an embodiment of the present invention;

[0035] Figure 3 is a schematic structural diagram of an interconnection structure according to another embodiment of the present invention;

[0036] Figure 4 is a schematic structural diagram of an interconnection structure according to another embodiment of the present invention;

[0037] Figure 5 is a schematic structural diagram of an interconnection structure according to another embodiment of the present invention;

[0038] Figure 6 These are images of the products of Examples 19-22 of the present invention under an ultrasonic scanning microscope, wherein (a) corresponds to Example 19, (b) corresponds to Example 20, (c) corresponds to Example 21, and (d) corresponds to Example 22.

[0039] The meanings of the reference numerals in the accompanying drawings are:

[0040] 100-interconnect structure; 10-power chip; 20-activated plating layer and / or flattened surface; 30-substrate; 40-bonding wire; 50-second metallization layer; 60-copper foil layer; 70-heat sink; 80-first metallization layer; 31-circuit copper layer; 32-insulating layer; 33-heat dissipation copper layer; 51-microgrooves. DETAILED DESCRIPTION

[0041] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0042] The terms "first", "second" and "third" in the present invention are used only for descriptive purposes and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first", "second" and "third" may explicitly or implicitly include at least one of such features. In the description of the present invention, "multiple" means at least two, for example, two, three, etc., unless otherwise clearly and specifically defined. All directional indications in the embodiments of the present invention (such as up, down, left, right, front, back...) are only used to explain the relative positional relationship, movement, etc. between the components under a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units inherent to these processes, methods, products or devices.

[0043] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present invention. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute a separate or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0044] The packaging method of the power module in the related art requires coating tin-based solder or sintering material (generally silver-based high-temperature paste) on the substrate surface corresponding to the power chip position when connecting the substrate and the power chip. The power chips are then sequentially attached to the corresponding positions and their lower surfaces are reflow soldered or pressure sintered. This results in high material costs, and the solder and paste are subject to problems such as dimensional shrinkage and overflow during the drying and sintering processes, thereby affecting accuracy and even insulation performance. The packaging method of the embodiment of the present invention does not rely on sintering paste for the connection between the substrate and the power chip, which not only saves paste costs and equipment investment and energy consumption related to the printing process, but also solves problems such as dimensional shrinkage, paste overflow, and chip tilt caused by the paste drying and sintering processes, thereby improving assembly accuracy.

[0045] Figure 1 FIG1 is a flow chart of a method for packaging a semiconductor power module according to an embodiment of the present invention. It should be noted that the method of the present invention is not limited to the method of packaging a semiconductor power module according to an embodiment of the present invention. Figure 1 The process sequence shown is limited. Figure 1 As shown, the method includes the steps of:

[0046] Step S1: providing a substrate and at least one power chip.

[0047] In step S1, see Figure 2 The substrate 30 includes a ceramic copper-clad substrate, a metal frame, or a metal busbar. The ceramic copper-clad substrate includes, from top to bottom, a circuit copper layer 31, an insulation layer 32, and a heat dissipation copper layer 33. One or more power chips 10 may be provided. The top and / or bottom surfaces of the power chip 10 may or may not be provided with a metallization layer.

[0048] As an embodiment, in this step, the substrate 30 may also be subjected to a reducing gas heating treatment, such as hydrogen or formic acid reflux, to remove the oxide layer on the surface of the substrate 30 and improve the connection performance and connection quality of the substrate 30 .

[0049] Step S2: When there is no preset metallization layer on the upper surface and / or lower surface of the power chip, pre-set a first metallization layer on the upper surface of the power chip and / or pre-set a second metallization layer on the lower surface of the power chip.

[0050] In step S2, the absence of a preset metallization layer means that the metallization layer may or may not exist, and the outermost layer of the metallization layer may not be the preset metallization layer. When the preset metallization layer does not exist on the upper surface and / or lower surface of the power chip, the metallization layer needs to be fabricated according to the actual application. The metallization layer can be a single layer or multiple layers, and each layer can be made of a single metal, alloy, or compound.

[0051] As an embodiment, when at least one metallization layer exists on the upper surface and / or lower surface of the power chip 10, and the outermost layer of the metallization layer is not a preset metallization layer, a first metallization layer 80 is pre-deposited on the upper surface of the power chip 10 and / or a second metallization layer 50 is pre-deposited on the lower surface of the power chip. In this embodiment, the first metallization layer 80 and / or the second metallization layer 50 are preset metallization layers, and the materials of the first metallization layer 80 and the second metallization layer 50 can be the same or different.

[0052] As an embodiment, when no metallization layer exists on the upper surface and / or lower surface of the power chip 10, at least one first metallization layer 80 is pre-deposited on the upper surface of the power chip 10 and / or at least one second metallization layer 50 is pre-deposited on the lower surface of the power chip 10. In this embodiment, the materials of the first metallization layer 80 and the second metallization layer 50 can be the same or different.

[0053] When the number of layers of the first metallization layer 80 is one, this layer is the outermost layer. When the number of layers of the first metallization layer 80 is greater than one, the outermost layer is the outermost layer. The outermost layer of the first metallization layer 80 is a predetermined metallization layer, which may be a single metal, a metal compound, or an alloy. For example, the outermost layer of the first metallization layer 80 may be one of an Au layer, a Cu layer, an Ag layer, an Al layer, a Ni layer, a Pd layer, a Zn layer, and a Pt layer.

[0054] When the number of layers of the second metallization layer 50 is one, this layer is the outermost layer. When the number of layers of the second metallization layer 50 is greater than one, the outermost layer is the outermost layer. The outermost layer of the second metallization layer 50 is a predetermined metallization layer, which may be a single metal, an alloy, or a compound. For example, the outermost layer of the second metallization layer 50 may be one of an Au layer, a Cu layer, an Ag layer, an Al layer, a Ni layer, a Pd layer, a Zn layer, and a Pt layer.

[0055] Step S3: performing activation coating treatment and / or planarization treatment on the surface of the substrate to form an activated coating and / or a planarized surface.

[0056] In step S3, the activation coating treatment and the planarization treatment can reduce the difficulty of connection between the substrate 30 and the power chip 10. Among them, the activation coating treatment includes but is not limited to electroplating, chemical plating, physical vapor deposition, chemical vapor deposition and mechanical cold spraying. The planarization treatment includes but is not limited to electrolytic polishing, machining, mechanical grinding, mirror finishing and mechanical chemical grinding. In one feasible embodiment, only the surface of the substrate 30 is subjected to activation coating treatment. In another feasible embodiment, only the surface of the substrate 30 is subjected to planarization treatment. In another feasible embodiment, the surface of the substrate 30 is subjected to activation coating treatment and planarization treatment, which can be understood as first performing activation coating treatment on the surface of the substrate 30 to form an activated coating layer, and then performing planarization treatment on the activated coating layer to form a planarized surface.

[0057] The activated coating of this embodiment is a single layer or a composite layer, and the outermost layer of the activated coating is a single metal, alloy, or compound. For example, the outermost layer of the activated coating is one of Au coating, Cu coating, Ag coating, Al coating, Ni coating, Pd coating, Zn coating, and Pt coating.

[0058] Step S4: placing the power chip on the substrate, and completing the interconnection between the substrate and the power chip through a hot pressing and sintering process based on the activated coating and / or flattened surface.

[0059] In step S4, see Figure 2 The power chip 10 is placed on the substrate 30, with the activated coating and / or flattened surface 20 facing the power chip 10, and sintered in a hot pressing diffusion device at a temperature of 180-300°C and a pressure of 1-30 MPa for 1-60 minutes to achieve interconnection between the activated coating and / or flattened surface 20 and the second metallization layer 50, that is, to complete the interconnection between the substrate 30 and the power chip 10, and obtain the following: Figure 2 The structure shown includes, from top to bottom, a first metallization layer 80, a power chip 10, a second metallization layer 50, an activated plating layer and / or a planarized surface 20, and a substrate 30. The second metallization layer 50 is located on the lower surface of the power chip 10 and is opposite to the activated plating layer and / or the planarized surface 20. The substrate 30 is a ceramic copper-clad substrate and includes, from top to bottom, a circuit copper layer 31, an insulating layer 32, and a heat-dissipating copper layer 33.

[0060] Step S5: Use a connecting key to connect the upper surface of the power chip and the substrate to obtain an interconnection structure.

[0061] In step S5, the connection key includes a welding wire, a metal strip or a clip connection. Figure 2 As shown, the power chip 10 is connected to the substrate 30 via bonding wires 40 .

[0062] Step S6: performing packaging processing and terminal forming on the interconnect structure to obtain a semiconductor power module.

[0063] In step S6, the encapsulation process includes plastic encapsulation and potting. For example, the interconnect structure is placed in an injection mold for injection molding to form a plastic encapsulated housing. The connection frame portion of the lead frame is cut off, and the pins are bent into the required shape (adaptive PCB circuit board installation). Among them, the metal wire and lead frame can be used as circuit conductors to realize the interconnection of the internal and external circuits of the interconnect structure.

[0064] The packaging method of the semiconductor power module of an embodiment of the present invention is based on the diffusion connection between the substrate 30 and the power chip 10, and does not rely on sintering slurry. It not only saves slurry cost and equipment investment and energy consumption related to the printing process, but also solves the problems of size shrinkage, slurry overflow, chip tilting, etc. caused by the slurry drying and sintering processes, thereby improving the assembly accuracy. The packaging method does not require a pre-plated silver layer on the substrate surface, which saves costs and reduces process risks. At the same time, it also avoids the reliability risks such as silver migration, high-temperature oxidation and de-wetting of the plating layer at the silver / copper interface and the slurry silver / pre-plated silver interface. In addition, since the structure of the interface metallization layer is simplified, the corresponding thermal conductivity, electrical conductivity and anti-stray performance are also improved.

[0065] As an example, see Figure 3 The substrate of the power chip 10 is provided with a micro-groove array structure. When the second metallization layer 50 is pre-disposed on the lower surface of the power chip 10, the second metallization layer 50 is located on the surface of the micro-groove array structure.

[0066] Furthermore, the microgroove array structure includes a plurality of microgrooves 51 distributed in an array. The depth H of the microgrooves 51 is 10-2000 nm, and the ratio between the dam top width W1 and the dam bottom width W2 of the microgroove array structure is 0.1-10. The array shape of the microgrooves 51 can be rectangular, square, spiral, or concentric, etc., and is not specifically limited here.

[0067] The micro-groove array structure can improve the connection strength between the power chip 10 and the substrate 30 .

[0068] On the basis of the above embodiment, during or after step S3, the packaging method further includes: pre-depositing a copper foil layer 60 on the upper surface of the power chip 10, and performing an activation plating treatment and / or a flattening treatment on the surface of the copper foil layer 60; when a first metallization layer 80 is pre-deposited on the upper surface of the power chip 10, connecting the copper foil layer 60 to the first metallization layer 80 on the upper surface of the power chip 10 based on a hot pressing sintering process, and the copper foil layer 60 is used to connect the connection key.

[0069] In a feasible embodiment, a copper foil layer 60 is pre-deposited on the upper surface of the power chip 10, and the lower surface of the copper foil layer 60 is subjected to activation plating treatment and / or flattening treatment; when a first metallization layer 80 is pre-deposited on the upper surface of the power chip 10, the step of connecting the copper foil layer 60 with the first metallization layer 80 on the upper surface of the power chip 10 based on the hot pressing and sintering process can be completed in step S3 (it can be understood that the connection between the copper foil layer 60 and the power chip 10 and the connection between the power chip 10 and the substrate 30 are simultaneously implemented with the hot pressing and sintering process). After the power chip 10 is connected to the copper foil layer 60, the copper foil layer 60 is connected to the connection key. In another feasible embodiment, a copper foil layer 60 is pre-deposited on the upper surface of the power chip 10, and the lower surface of the copper foil layer 60 is activated and plated and / or planarized. The step of connecting the copper foil layer 60 to the power chip 10 based on the hot pressing and sintering process can be completed after step S3. After the power chip 10 is connected to the copper foil layer 60, the copper foil layer 60 is connected to the connection key.

[0070] See Figure 4 The interconnect structure 100 prepared by the above steps includes, from top to bottom, a copper foil layer 60, a first metallization layer 80, a power chip 10, a second metallization layer 50, an activated plating layer and / or a planarized surface 20, and a substrate 30. Substrate 30 is a ceramic copper-clad substrate. The surface of the copper foil layer 60 has been activated and / or planarized, enabling the lower surface of the copper foil layer 60 to be directly connected to the first metallization layer 80. No connecting material, such as a nanosilver film, is required between the lower surface of the copper foil layer 60 and the upper surface of the power chip 10. Compared to traditional on-chip copper layer processes, this simplifies the fabrication process and reduces material costs.

[0071] Based on the above embodiment, after step S3, the packaging method further includes: providing a heat sink 70, and performing activation coating treatment and / or flattening treatment on the back side of the substrate 30 and / or the surface of the heat sink 70, and connecting the heat sink 70 to the back side of the substrate 30 based on a hot pressing sintering process.

[0072] This embodiment performs an activation plating and / or flattening process on the back surface of the substrate 30 and / or the surface of the heat sink 70, enabling direct connection between the back surface of the substrate 30 and / or the surface of the heat sink 70. The heat sink 70 is then connected to the back surface of the substrate 30 via a hot pressing and sintering process, eliminating the need for tin-based solder or other connecting materials. Compared to conventional semiconductor power devices or modules, the semiconductor power module of this embodiment eliminates the need for tin-based solder or other connecting materials to connect the heat sink 70 to the substrate 30. This avoids the high material costs associated with the large connection area between the substrate 30 and the heat sink 70, which results in large amounts of solder or sintering slurry.

[0073] See Figure 5 The interconnect structure 100 prepared by the above steps includes, arranged in order from top to bottom, a copper foil layer 60, a first metallization layer 80, a power chip 10, a second metallization layer 50, an activated plating layer and / or a planarized surface 20, a substrate 30, and a heat sink 70. Substrate 30 is a ceramic copper-clad substrate. The surface of the copper foil layer 60 has been activated and / or planarized, enabling the lower surface of the copper foil layer 60 to be directly connected to the first metallization layer 80 on the upper surface of the power chip 10. No connecting material, such as a nanosilver film, is required between the lower surface of the copper foil layer 60 and the upper surface of the power chip 10. Compared to conventional copper layer-on-chip processes, this simplifies the manufacturing process and reduces material costs. The back surface of the substrate 30 and / or the surface of the heat sink 70 are subjected to activation coating treatment and / or flattening treatment, so that the back surface of the substrate 30 and / or the surface of the heat sink 70 have the ability to be directly connected. The heat sink 70 is connected to the back surface of the substrate 30 through a hot pressing sintering process, without the need to use tin-based solder or other connecting materials, thereby saving material costs.

[0074] The following describes the embodiment

[0075] Example 1

[0076] Step S1: providing a substrate and at least one power chip, wherein the substrate is a metal frame or a metal busbar;

[0077] Step S2: When no preset metallization layer exists on the upper surface and / or lower surface of the power chip, pre-positioning a first metallization layer on the upper surface of the power chip and / or pre-positioning a second metallization layer on the lower surface of the power chip;

[0078] Step S3: The substrate surface is subjected to activation plating treatment and planarization treatment, wherein the activation plating treatment is copper A electroplating and the planarization treatment is mechanical chemical grinding;

[0079] Step S4: Place the power chip on the substrate, and complete the interconnection between the substrate and the power chip through a hot pressing sintering process based on the activated coating and the flattened surface. The hot pressing sintering process has a temperature of 280°C, a pressure of 20 MPa, and a sintering time of 10 minutes.

[0080] Example 2

[0081] Step S1: providing a substrate and at least one power chip, wherein the substrate is a metal frame or a metal busbar;

[0082] Step S2: When no preset metallization layer exists on the upper surface and / or lower surface of the power chip, pre-positioning a first metallization layer on the upper surface of the power chip and / or pre-positioning a second metallization layer on the lower surface of the power chip;

[0083] Step S3: The substrate surface is subjected to activation plating treatment and planarization treatment, wherein the activation plating treatment is copper B electroplating and the planarization treatment is mechanical chemical grinding;

[0084] Step S4: Place the power chip on the substrate, and complete the interconnection between the substrate and the power chip through a hot pressing sintering process based on the activated coating and the flattened surface. The hot pressing sintering process has a temperature of 280°C, a pressure of 20 MPa, and a sintering time of 10 minutes.

[0085] Example 3

[0086] Step S1: providing a substrate and at least one power chip, wherein the substrate is a metal frame or a metal busbar;

[0087] Step S2: When no preset metallization layer exists on the upper surface and / or lower surface of the power chip, pre-positioning a first metallization layer on the upper surface of the power chip and / or pre-positioning a second metallization layer on the lower surface of the power chip;

[0088] Step S3: the substrate surface is planarized by mechanical chemical polishing;

[0089] Step S4: placing the power chip on the substrate, and completing the interconnection between the substrate and the power chip through a hot pressing sintering process based on the flattened surface. The hot pressing sintering process has a temperature of 280°C, a pressure of 20 MPa, and a sintering time of 10 minutes.

[0090] Example 4

[0091] Step S1: providing a substrate and at least one power chip, wherein the substrate is a metal frame or a metal busbar;

[0092] Step S2: When no preset metallization layer exists on the upper surface and / or lower surface of the power chip, pre-positioning a first metallization layer on the upper surface of the power chip and / or pre-positioning a second metallization layer on the lower surface of the power chip;

[0093] Step S3: The substrate surface is subjected to activation plating and planarization treatment, wherein the activation plating treatment is copper A electroplating and the planarization treatment is electrolytic polishing;

[0094] Step S4: Place the power chip on the substrate, and complete the interconnection between the substrate and the power chip through a hot pressing sintering process based on the activated coating and the flattened surface. The hot pressing sintering process has a temperature of 280°C, a pressure of 20 MPa, and a sintering time of 10 minutes.

[0095] Example 5

[0096] Step S1: providing a substrate and at least one power chip, wherein the substrate is a metal frame or a metal busbar;

[0097] Step S2: When no preset metallization layer exists on the upper surface and / or lower surface of the power chip, pre-positioning a first metallization layer on the upper surface of the power chip and / or pre-positioning a second metallization layer on the lower surface of the power chip;

[0098] Step S3: The substrate surface is subjected to activation plating treatment and flattening treatment, wherein the activation plating treatment is copper B electroplating and the flattening treatment is electrolytic polishing;

[0099] Step S4: Place the power chip on the substrate, and complete the interconnection between the substrate and the power chip through a hot pressing sintering process based on the activated coating and the flattened surface. The hot pressing sintering process has a temperature of 280°C, a pressure of 20 MPa, and a sintering time of 10 minutes.

[0100] Example 6

[0101] Step S1: providing a substrate and at least one power chip, wherein the substrate is a metal frame or a metal busbar;

[0102] Step S2: When no preset metallization layer exists on the upper surface and / or lower surface of the power chip, pre-positioning a first metallization layer on the upper surface of the power chip and / or pre-positioning a second metallization layer on the lower surface of the power chip;

[0103] Step S3: the substrate surface is planarized, and the planarization process is electrolytic polishing;

[0104] Step S4: placing the power chip on the substrate, and completing the interconnection between the substrate and the power chip through a hot pressing sintering process based on the flattened surface. The hot pressing sintering process has a temperature of 280°C, a pressure of 20 MPa, and a sintering time of 10 minutes.

[0105] The products prepared in Examples 1-6 were subjected to shear strength tests respectively, and the test results are shown in Table 1.

[0106] Shear strength: The shear strength of the interconnection structure between the power chip and the substrate is tested using push-pull force testing equipment at a test speed of 0.3 mm / s.

[0107] Table 1:

[0108]

[0109] As shown in Table 1, by combining different types of activation coatings and planarization processes, a good diffusion connection can be achieved between the power chip and the substrate. Without the activation coating, a diffusion connection can be achieved using only the planarization process, but the connection strength is relatively low. In various embodiments combining activation coatings and planarization processes, an average shear strength exceeding 40 MPa can be achieved, with the highest average shear strength approaching 60 MPa. This connection strength is fully sufficient for applications where power chips are connected to substrates.

[0110] Example 7

[0111] Step S1: providing a substrate and at least one power chip, wherein the substrate is a metal frame or a metal busbar;

[0112] Step S2: When no preset metallization layer exists on the upper surface and / or lower surface of the power chip, pre-positioning a first metallization layer on the upper surface of the power chip and / or pre-positioning a second metallization layer on the lower surface of the power chip;

[0113] Step S3: The substrate surface is subjected to activation plating and planarization treatment, wherein the activation plating treatment is copper A electroplating and the planarization treatment is electrolytic polishing;

[0114] Step S4: Place the power chip on the substrate, and complete the interconnection between the substrate and the power chip through a hot pressing sintering process based on the activated coating and the flattened surface. The hot pressing sintering process has a temperature of 280°C, a pressure of 20 MPa, and a sintering time of 10 minutes.

[0115] Example 8

[0116] Step S1: providing a substrate and at least one power chip, and performing a formic acid reflow treatment on the substrate to remove an oxide layer on the surface of the substrate, wherein the substrate is a metal frame or a metal busbar;

[0117] Step S2: When no preset metallization layer exists on the upper surface and / or lower surface of the power chip, pre-positioning a first metallization layer on the upper surface of the power chip and / or pre-positioning a second metallization layer on the lower surface of the power chip;

[0118] Step S3: The substrate surface is subjected to activation plating and planarization treatment, wherein the activation plating treatment is copper A electroplating and the planarization treatment is electrolytic polishing;

[0119] Step S4: Place the power chip on the substrate, and complete the interconnection between the substrate and the power chip through a hot pressing sintering process based on the activated coating and the flattened surface. The hot pressing sintering process has a temperature of 280°C, a pressure of 20 MPa, and a sintering time of 10 minutes.

[0120] Example 9

[0121] Step S1: providing a substrate and at least one power chip, wherein the substrate is a metal frame or a metal busbar;

[0122] Step S2: When no preset metallization layer exists on the upper surface and / or lower surface of the power chip, pre-positioning a first metallization layer on the upper surface of the power chip and / or pre-positioning a second metallization layer on the lower surface of the power chip;

[0123] Step S3: The substrate surface is subjected to activation plating treatment and flattening treatment, wherein the activation plating treatment is copper B electroplating and the flattening treatment is electrolytic polishing;

[0124] Step S4: Place the power chip on the substrate, and complete the interconnection between the substrate and the power chip through a hot pressing sintering process based on the activated coating and the flattened surface. The hot pressing sintering process has a temperature of 280°C, a pressure of 20 MPa, and a sintering time of 10 minutes.

[0125] Example 10

[0126] Step S1: providing a substrate and at least one power chip, and performing a formic acid reflow treatment on the substrate to remove an oxide layer on the surface of the substrate, wherein the substrate is a metal frame or a metal busbar;

[0127] Step S2: When no preset metallization layer exists on the upper surface and / or lower surface of the power chip, pre-positioning a first metallization layer on the upper surface of the power chip and / or pre-positioning a second metallization layer on the lower surface of the power chip;

[0128] Step S3: The substrate surface is subjected to activation plating treatment and flattening treatment, wherein the activation plating treatment is copper B electroplating and the flattening treatment is electrolytic polishing;

[0129] Step S4: Place the power chip on the substrate, and complete the interconnection between the substrate and the power chip through a hot pressing sintering process based on the activated coating and the flattened surface. The hot pressing sintering process has a temperature of 280°C, a pressure of 20 MPa, and a sintering time of 10 minutes.

[0130] Example 11

[0131] Step S1: providing a substrate and at least one power chip, and performing a formic acid reflow treatment on the substrate to remove an oxide layer on the surface of the substrate, wherein the substrate is a metal frame or a metal busbar;

[0132] Step S2: When no preset metallization layer exists on the upper surface and / or lower surface of the power chip, pre-positioning a first metallization layer on the upper surface of the power chip and / or pre-positioning a second metallization layer on the lower surface of the power chip;

[0133] Step S3: The substrate surface is subjected to activation plating treatment and flattening treatment, wherein the activation plating treatment is electroplating copper A and the flattening treatment is mirror finishing;

[0134] Step S4: Place the power chip on the substrate, and complete the interconnection between the substrate and the power chip through a hot pressing sintering process based on the activated coating and the flattened surface. The hot pressing sintering process has a temperature of 280°C, a pressure of 20 MPa, and a sintering time of 10 minutes.

[0135] Example 12

[0136] Step S1: providing a substrate and at least one power chip, and performing a formic acid reflow treatment on the substrate to remove an oxide layer on the surface of the substrate, wherein the substrate is a metal frame or a metal busbar;

[0137] Step S2: When no preset metallization layer exists on the upper surface and / or lower surface of the power chip, pre-positioning a first metallization layer on the upper surface of the power chip and / or pre-positioning a second metallization layer on the lower surface of the power chip;

[0138] Step S3: The substrate surface is subjected to activation plating treatment and flattening treatment, wherein the activation plating treatment is electroplating copper B and the flattening treatment is mirror finishing;

[0139] Step S4: Place the power chip on the substrate, and complete the interconnection between the substrate and the power chip through a hot pressing sintering process based on the activated coating and the flattened surface. The hot pressing sintering process has a temperature of 280°C, a pressure of 20 MPa, and a sintering time of 10 minutes.

[0140] Example 13

[0141] Step S1: providing a substrate and at least one power chip, and performing a formic acid reflow treatment on the substrate to remove an oxide layer on the surface of the substrate, wherein the substrate is a metal frame or a metal busbar;

[0142] Step S2: When no preset metallization layer exists on the upper surface and / or lower surface of the power chip, pre-positioning a first metallization layer on the upper surface of the power chip and / or pre-positioning a second metallization layer on the lower surface of the power chip;

[0143] Step S3: The substrate surface is subjected to activation plating and flattening treatment, wherein the activation plating treatment is copper A electroplating, and the flattening treatment is electrolytic polishing + mirror finishing;

[0144] Step S4: Place the power chip on the substrate, and complete the interconnection between the substrate and the power chip through a hot pressing sintering process based on the activated coating and the flattened surface. The hot pressing sintering process has a temperature of 280°C, a pressure of 20 MPa, and a sintering time of 10 minutes.

[0145] Example 14

[0146] Step S1: providing a substrate and at least one power chip, and performing a formic acid reflow treatment on the substrate to remove an oxide layer on the surface of the substrate, wherein the substrate is a metal frame or a metal busbar;

[0147] Step S2: When no preset metallization layer exists on the upper surface and / or lower surface of the power chip, pre-positioning a first metallization layer on the upper surface of the power chip and / or pre-positioning a second metallization layer on the lower surface of the power chip;

[0148] Step S3: The substrate surface is subjected to activation plating and flattening treatment, wherein the activation plating treatment is copper B electroplating, and the flattening treatment is electrolytic polishing + mirror finishing;

[0149] Step S4: Place the power chip on the substrate, and complete the interconnection between the substrate and the power chip through a hot pressing sintering process based on the activated coating and the flattened surface. The hot pressing sintering process has a temperature of 280°C, a pressure of 20 MPa, and a sintering time of 10 minutes.

[0150] Example 15

[0151] Step S1: providing a substrate and at least one power chip, and performing a formic acid reflow treatment on the substrate to remove an oxide layer on the surface of the substrate, wherein the substrate is a metal frame or a metal busbar;

[0152] Step S2: When no preset metallization layer exists on the upper surface and / or lower surface of the power chip, pre-positioning a first metallization layer on the upper surface of the power chip and / or pre-positioning a second metallization layer on the lower surface of the power chip;

[0153] Step S3: the substrate surface is planarized, and the planarization process is electrolytic polishing;

[0154] Step S4: placing the power chip on the substrate, and completing the interconnection between the substrate and the power chip through a hot pressing sintering process based on the flattened surface. The hot pressing sintering process has a temperature of 280°C, a pressure of 20 MPa, and a sintering time of 10 minutes.

[0155] The substrates of the power chips of the above-mentioned Examples 7-15 are provided with a micro-groove array structure. The products prepared in the above-mentioned Examples 7-15 were subjected to shear strength tests respectively. The test results are shown in Table 2.

[0156] Shear strength: The shear strength of the interconnect structure between the power chip and the substrate was tested along the directions perpendicular to the micro-grooves and parallel to the micro-grooves at a test speed of 0.3 mm / s using a push-pull test device.

[0157] Table 2:

[0158]

[0159] As shown in Table 2, by combining different types of activation coatings and planarization processes, a good diffusion bond can be achieved between the power chip and substrate. Across various combinations of activation coating, planarization, and pretreatment processes, the lowest bond strength approaches 20 MPa, which is sufficient for power chip-to-substrate connections. Furthermore, the power chip's surface features a microgroove array structure, and the shear strength in directions perpendicular to and parallel to the grooves is comparable.

[0160] Example 16

[0161] Step S1: providing a substrate and at least one power chip, and performing a formic acid reflow treatment on the substrate to remove an oxide layer on the surface of the substrate, wherein the substrate is a ceramic copper-clad substrate;

[0162] Step S2: When no preset metallization layer exists on the upper surface and / or lower surface of the power chip, pre-positioning a first metallization layer on the upper surface of the power chip and / or pre-positioning a second metallization layer on the lower surface of the power chip;

[0163] Step S3: the substrate surface is planarized by mechanical grinding.

[0164] Step S4: placing the power chip on the substrate, and completing the interconnection between the substrate and the power chip through a hot pressing sintering process based on the flattened surface. The hot pressing sintering process has a temperature of 280°C, a pressure of 25 MPa, and a sintering time of 10 minutes.

[0165] Example 17

[0166] Step S1: providing a substrate and at least one power chip, wherein the substrate is a ceramic copper-clad substrate;

[0167] Step S2: When no preset metallization layer exists on the upper surface and / or lower surface of the power chip, pre-positioning a first metallization layer on the upper surface of the power chip and / or pre-positioning a second metallization layer on the lower surface of the power chip;

[0168] Step S3: the substrate surface is planarized by mechanical grinding.

[0169] Step S4: placing the power chip on the substrate, and completing the interconnection between the substrate and the power chip through a hot pressing sintering process based on the flattened surface. The hot pressing sintering process has a temperature of 280°C, a pressure of 20 MPa, and a sintering time of 10 minutes.

[0170] Example 18

[0171] Step S1: providing a substrate and at least one power chip, and performing a formic acid reflow treatment on the substrate to remove an oxide layer on the surface of the substrate, wherein the substrate is a ceramic copper-clad substrate;

[0172] Step S2: When no preset metallization layer exists on the upper surface and / or lower surface of the power chip, pre-positioning a first metallization layer on the upper surface of the power chip and / or pre-positioning a second metallization layer on the lower surface of the power chip;

[0173] Step S3: the substrate surface is planarized by mechanical grinding.

[0174] Step S4: placing the power chip on the substrate, and completing the interconnection between the substrate and the power chip through a hot pressing sintering process based on the flattened surface. The hot pressing sintering process has a temperature of 280°C, a pressure of 20 MPa, and a sintering time of 10 minutes.

[0175] The products prepared in Examples 16-18 were subjected to shear strength tests, respectively. The test results are shown in Table 3.

[0176] Shear strength: The shear strength of the interconnection structure between the power chip and the substrate is tested using push-pull force testing equipment at a test speed of 0.3 mm / s.

[0177] Table 3:

[0178] As shown in Table 3, under different sintering conditions and pretreatment processes, even without substrate surface activation, mechanical polishing alone provides a smooth, planarized connection between the power chip and the ceramic copper-clad substrate. At a sintering temperature of 280°C, a sintering pressure of 25 MPa, and a sintering time of 10 minutes, the average bond strength reaches nearly 80 MPa, reaching the optimal level for commercial silver and copper sintering processes.

[0179] Example 19

[0180] Step S1: providing a substrate and at least one power chip, wherein the substrate is a metal frame or a metal busbar;

[0181] Step S2: When no preset metallization layer exists on the upper surface and / or lower surface of the power chip, pre-positioning a first metallization layer on the upper surface of the power chip and / or pre-positioning a second metallization layer on the lower surface of the power chip;

[0182] Step S3: The substrate surface is subjected to activation coating treatment and flattening treatment;

[0183] Step S4: placing the power chip on the substrate, pre-depositing a copper foil layer on the upper surface of the power chip, and performing activation plating treatment and flattening treatment on the surface of the copper foil layer. Based on the activation plating layer and the flattened surface, the interconnection between the substrate and the power chip, as well as between the copper foil layer and the power chip, is completed by a hot pressing sintering process. The temperature of the hot pressing sintering process is 280°C, the pressure is 20 MPa, and the sintering time is 10 minutes. The activation plating layer on the surface of the copper foil layer is electroplated copper A, and the flattening treatment on the surface of the copper foil layer is electrolytic polishing.

[0184] Example 20

[0185] Step S1: providing a substrate and at least one power chip, wherein the substrate is a metal frame or a metal busbar;

[0186] Step S2: When no preset metallization layer exists on the upper surface and / or lower surface of the power chip, pre-positioning a first metallization layer on the upper surface of the power chip and / or pre-positioning a second metallization layer on the lower surface of the power chip;

[0187] Step S3: The substrate surface is subjected to activation coating treatment and flattening treatment;

[0188] Step S4: placing the power chip on the substrate, pre-depositing a copper foil layer on the upper surface of the power chip, and flattening the surface of the copper foil layer. Based on the activated plating layer and the flattened surface, a hot pressing sintering process is used to complete the interconnection between the substrate and the power chip, as well as between the copper foil layer and the power chip. The hot pressing sintering process has a temperature of 280°C, a pressure of 20 MPa, and a sintering time of 10 minutes. The flattening treatment of the surface of the copper foil layer is electrolytic polishing.

[0189] Example 21

[0190] Step S1: providing a substrate and at least one power chip, wherein the substrate is a metal frame or a metal busbar;

[0191] Step S2: When no preset metallization layer exists on the upper surface and / or lower surface of the power chip, pre-positioning a first metallization layer on the upper surface of the power chip and / or pre-positioning a second metallization layer on the lower surface of the power chip;

[0192] Step S3: The substrate surface is subjected to activation coating treatment and flattening treatment;

[0193] Step S4: placing the power chip on the substrate, pre-depositing a copper foil layer on the upper surface of the power chip, and performing activation plating treatment on the surface of the copper foil layer. Based on the activation plating and the flattened surface, the interconnection between the substrate and the power chip, as well as between the copper foil layer and the power chip, is completed by a hot pressing sintering process. The temperature of the hot pressing sintering process is 280°C, the pressure is 20 MPa, and the sintering time is 10 minutes. The activation plating on the surface of the copper foil layer is electroplated copper A.

[0194] Example 22

[0195] Step S1: providing a substrate and at least one power chip, wherein the substrate is a metal frame or a metal busbar;

[0196] Step S2: When no preset metallization layer exists on the upper surface and / or lower surface of the power chip, pre-positioning a first metallization layer on the upper surface of the power chip and / or pre-positioning a second metallization layer on the lower surface of the power chip;

[0197] Step S3: The substrate surface is subjected to activation coating treatment and flattening treatment;

[0198] Step S4: Place the power chip on the substrate and pre-deposit a copper foil layer on the upper surface of the power chip. Based on the activated plating layer and the flattened surface, a hot pressing sintering process is used to complete the interconnection between the substrate and the power chip, as well as between the copper foil layer and the power chip. The hot pressing sintering process has a temperature of 280°C, a pressure of 20 MPa, and a sintering time of 10 minutes.

[0199] The above examples 19-22 were repeated 5 times to prepare 4 groups of products (each group has 5) and the connection status of each product was tested. The test results are shown in Table 4 and Table 4. Figure 6 shown.

[0200] Connection status: Use a scanning acoustic tomography (SAT) microscope to observe the bonding interface between the copper foil layer and the power chip, and judge the quality of the connection based on the image morphology.

[0201] Table 4:

[0202]

[0203]

[0204] As shown in Table 4, by combining different types of activation and planarization processes, a good diffusion connection can be obtained between the power chip surface and the copper foil layer. Figure 6 As shown, it can be seen from the SAT image that a good connection effect is achieved between the upper surface of the power chip and the copper foil layer of the semiconductor power modules prepared in Example 19 and Example 20.

[0205] The above are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention description and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A method for packaging a semiconductor power module, characterized in that: include: Step S1: providing a substrate and at least one power chip; Step S2: When no preset metallization layer exists on the upper surface and / or lower surface of the power chip, pre-positioning a first metallization layer on the upper surface of the power chip and / or pre-positioning a second metallization layer on the lower surface of the power chip; Step S3: performing an activation coating treatment and / or a flattening treatment on the surface of the substrate to form an activation coating and / or a flattened surface; Step S4: placing the power chip on the substrate, and completing the interconnection between the substrate and the power chip through a hot pressing sintering process based on the activated coating and / or the planarized surface; Step S5: connecting the upper surface of the power chip and the substrate using a connecting key to obtain an interconnection structure; Step S6: performing packaging processing and terminal forming on the interconnection structure to obtain the semiconductor power module.

2. The method for packaging a semiconductor power module according to claim 1, wherein: In step S2, the activated coating is a single layer or a composite layer, and the outermost layer of the activated coating is a single metal, an alloy or a compound.

3. The method for packaging a semiconductor power module according to claim 1, wherein: When no preset metallization layer exists on the upper surface and / or the lower surface of the power chip, pre-setting a first metallization layer on the upper surface of the power chip and / or pre-setting a second metallization layer on the lower surface of the power chip includes: When at least one metallization layer exists on the upper surface and / or lower surface of the power chip, and the outermost layer of the metallization layer is not the preset metallization layer, pre-positioning a first metallization layer on the upper surface of the power chip and / or pre-positioning a second metallization layer on the lower surface of the power chip; When no metallization layer exists on the upper surface and / or lower surface of the power chip, at least one first metallization layer is pre-disposed on the upper surface of the power chip and / or at least one second metallization layer is pre-disposed on the lower surface of the power chip.

4. The method for packaging a semiconductor power module according to claim 3, wherein: The outermost layer of the first metallization layer is a single metal, alloy or compound; the outermost layer of the second metallization layer is a single metal, alloy or compound.

5. The method for packaging a semiconductor power module according to claim 1, wherein: The substrate of the power chip is provided with a micro-groove array structure; when a second metallization layer is pre-disposed on the lower surface of the power chip, the second metallization layer is located on the surface of the micro-groove array structure.

6. The method for packaging a semiconductor power module according to any one of claims 1 to 5, characterized in that: The packaging method further comprises: Placing a copper foil layer on the upper surface of the power chip, and performing activation plating and / or flattening treatment on the surface of the copper foil layer in advance; When a first metallization layer is pre-installed on the upper surface of the power chip, the copper foil layer is connected to the first metallization layer on the upper surface of the power chip based on the hot pressing and sintering process, and the copper foil layer is used to connect the connection key.

7. The method for packaging a semiconductor power module according to claim 6, wherein: The packaging method further comprises: A heat sink is provided, and the back surface of the substrate and / or the surface of the heat sink are subjected to activation plating treatment and / or flattening treatment, and the heat sink is connected to the back surface of the substrate based on the hot pressing sintering process.

8. The method for packaging a semiconductor power module according to claim 1, wherein: Before step S2, the packaging method further includes: The substrate is subjected to a reducing gas heating treatment to remove an oxide layer on the surface of the substrate.

9. The method for packaging a semiconductor power module according to claim 1, wherein: The substrate includes a ceramic copper-clad substrate, a metal frame or a metal busbar.

10. A semiconductor power module, characterized in that: The semiconductor power module is prepared by the packaging method according to any one of claims 1 to 9.

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