Film stack simplification for high aspect ratio patterning and vertical scaling

Abstract

Methods for forming a patterned multilayer stack including a metal-containing layer are provided herein. Methods involve using a silicon-containing non-metallic material in a multi-layer stack including a sacrificial layer to be later removed and replaced with a metal while maintaining etch contrast to pattern the multi-layer stack and selectively remove the sacrificial layer prior to depositing the metal. Methods involve replacing silicon nitride with silicon oxycarbide and replacing a metal-containing layer with a sacrificial non-metallic material to fabricate a multi-layer stack, patterning the multi-layer stack, selectively removing the sacrificial non-metallic material to leave a space in the stack, and depositing a metal-containing material into the space. The sacrificial non-metallic material includes silicon nitride and doped polysilicon, such as boron doped silicon.

Description

This application is a divisional application of the invention patent application with application number 201980073253.2, application date September 10, 2019, and invention name “Simplified membrane stacking for high aspect ratio patterning and vertical scaling”. Incorporated by Reference

[0001] The PCT application form is filed concurrently with this specification as a part of this application. Each application to which this application claims the benefit of or priority as identified in the concurrently filed PCT application form is incorporated herein by reference in its entirety and for all purposes. Background Art

[0002] Semiconductor device manufacturing involves the fabrication of a variety of devices, such as flash memory. As devices shrink, structures for manufacturing complex, efficient, and multiple memory cells are needed to maximize the density of memory cells in memory devices. 3D NAND technology addresses the challenges associated with two-dimensional NAND technology by vertically stacking memory cells in multiple layers. Furthermore, manufacturing involves increasingly complex multilayer stacks that combine conductive and dielectric materials.

[0003] The background description provided here is for the purpose of generally presenting the context of the present disclosure. No admission is made, either explicitly or implicitly, that the work of the presently designated inventors is prior art to the present disclosure to the extent that it is described in this background section and in aspects of the specification that were not determined to be prior art at the time the application was filed. Summary of the Invention

[0004] Methods and apparatus for fabricating semiconductor devices are provided herein. One aspect relates to a method comprising: providing a semiconductor substrate; depositing a metal-free multilayer stack having at least three different materials, at least one of the three different materials being a sacrificial layer; etching a trench or a via in the metal-free multilayer stack having the at least three different materials; after etching the trench or the via, selectively etching the sacrificial layer relative to other materials of the metal-free multilayer stack to form at least one space between multiple layers of the metal-free multilayer stack; and depositing metal in the at least one space to form a metal-containing multilayer stack having the trench or the via etched therein.

[0005] In various embodiments, the metal-free multilayer stack includes three different materials.

[0006] In various embodiments, the metal-free multilayer stack includes four different materials.

[0007] The method may further include recessing a dielectric material in sidewalls of the trench or via in the metal-free multilayer stack after etching the trench or via and before selectively etching the sacrificial layer.

[0008] In various embodiments, the sacrificial layer is polysilicon or silicon nitride.

[0009] In various embodiments, the at least three different materials include one or more of silicon oxide, undoped polysilicon, doped polysilicon, silicon nitride, oxygen-doped silicon carbide, and nitrogen-doped silicon carbide.

[0010] In various embodiments, the metal is tungsten or molybdenum.

[0011] The method may further include depositing a metal-containing liner in the at least one space before depositing the metal, thereby depositing the metal on the metal-containing liner in the at least one space. In some embodiments, the metal-containing liner is selected from the group consisting of titanium nitride, aluminum oxide, and tungsten carbonitride.

[0012] In various embodiments, the metal-free multilayer stack includes alternating layers of silicon oxycarbide, nitrogen-doped silicon carbide, and silicon oxide.

[0013] In various embodiments, a metal-free multilayer stack includes a sacrificial dielectric and alternating layers of silicon oxycarbide and silicon oxide.

[0014] In various embodiments, the at least three different materials include silicon nitride, silicon oxide, nitrogen-doped silicon carbide, and oxygen-doped silicon carbide.

[0015] In various embodiments, the at least three different materials include polysilicon, silicon oxide, nitrogen-doped silicon carbide, and oxygen-doped silicon carbide.

[0016] In various embodiments, the at least three different materials include polysilicon, silicon nitride, silicon oxide, and oxygen-doped silicon carbide.

[0017] In some embodiments, the sacrificial layer is silicon nitride. In some embodiments, the sacrificial layer can be polysilicon, or doped polysilicon.

[0018] In various embodiments, the layers of the metal-free multilayer stack are deposited by atomic layer deposition.

[0019] In some embodiments, layers of the metal-free multilayer stack are deposited in different chambers of a single tool.

[0020] In various embodiments, the layers of the metal-free multilayer stack are deposited without breaking vacuum.

[0021] In some embodiments, layers of the metal-free multilayer stack are deposited in four different tools.

[0022] In various embodiments, at least two layers of the metal-free multilayer stack are deposited in a first tool, and at least two other layers of the metal-free multilayer stack are deposited in a second tool.

[0023] In some embodiments, the layers of the metal-free multilayer stack are deposited by chemical vapor deposition.

[0024] In various embodiments, the layers of the metal-free multilayer stack are deposited by plasma enhanced chemical vapor deposition.

[0025] In some embodiments, the layers of the metal-free multilayer stack are deposited by physical vapor deposition.

[0026] In various embodiments, the method further includes: recessing one of the at least three different materials after etching the trench or via to form a recessed region of the via; depositing a dielectric material or a semiconductor material into the trench or via; etching back the dielectric material or semiconductor material in the trench or via to form smooth sidewalls, thereby leaving the dielectric material or semiconductor material in the recessed region; and depositing a gate material into the trench or via before selectively etching the sacrificial silicon nitride.

[0027] Another aspect relates to a method comprising: providing a semiconductor substrate; depositing a multilayer stack of alternating sacrificial silicon nitride layers and non-oxide layers; etching trenches or vias in the multilayer stack of alternating sacrificial silicon nitride and non-oxide layers; after etching the trenches, selectively etching the sacrificial silicon nitride to form spaces between the non-oxide layers; and depositing metal in the spaces to form a substrate including trenches etched in the alternating metal and non-oxide layers and at least one dielectric barrier layer.

[0028] In various embodiments, the at least one dielectric barrier layer includes oxygen-doped silicon carbide.For example, the oxygen concentration in the oxygen-doped silicon carbide can be between about 1% and about 65% atomic.

[0029] In various embodiments, the non-oxide layer includes one or more of a second silicon nitride, silicon oxycarbide, and polysilicon having a wet etch contrast relative to the sacrificial silicon nitride.

[0030] In some embodiments, the polysilicon is doped. For example, the polysilicon can be doped with a dopant selected from the group consisting of boron, phosphorus, and arsenic.

[0031] In various embodiments, the metal includes tungsten.

[0032] In various embodiments, the metal comprises molybdenum.

[0033] In various embodiments, the sacrificial silicon nitride has a wet etch contrast ratio of at least about 10:1 in 100:1 dilute hydrofluoric or phosphoric acid relative to the non-oxide layer and the at least one dielectric barrier layer.

[0034] In various embodiments, the method further comprises: recessing a layer in the multilayer stack after etching the trench or through-hole to form a recessed region of the through-hole; depositing a dielectric material or a semiconductor material into the trench or through-hole after recessing the layer; etching back the dielectric material or semiconductor material in the trench or through-hole to form smooth sidewalls, thereby leaving the dielectric material or semiconductor material in the recessed region; and depositing a gate material into the trench or through-hole before selectively etching the sacrificial silicon nitride.

[0035] These and other aspects are further described below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a process flow diagram of operations performed according to a method of forming a 3D NAND structure.

[0037] Figure 2 、 3 , 4A, 4B, 5A, 5B, and 6-8 are schematic diagrams of exemplary cross sections of multilayer stacks during operation of various processes.

[0038] Figures 9A-9D Schematic diagrams showing exemplary cross-sections of a multilayer stack during various processing operations.

[0039] Figure 10 is a process flow diagram of operations performed in accordance with certain disclosed embodiments.

[0040] Figure 11A is a process flow diagram of operations performed in accordance with certain disclosed embodiments.

[0041] Figure 11B is a process flow diagram of exemplary operations performed in accordance with certain disclosed embodiments.

[0042] Figures 12A-12M Schematic diagrams showing exemplary cross-sections of a multilayer stack during various operations performed in accordance with certain disclosed embodiments.

[0043] Figure 13Block diagrams showing various reactor components configured for implementing the techniques are depicted according to certain disclosed embodiments.

[0044] Figure 14 Embodiments of a multi-site cluster tool are depicted in accordance with disclosed embodiments.

[0045] Figure 15 Another example of a multi-station processing tool is schematically shown according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments presented. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known processing operations are not described in detail so as not to unnecessarily obscure the disclosed embodiments. Although the disclosed embodiments will be described in conjunction with specific embodiments, it should be understood that they are not intended to limit the disclosed embodiments.

[0047] Semiconductor device processing involves the formation of multilayer stacks that can be used to manufacture a variety of three-dimensional devices, such as 3D NAND structures. Some stacks include multiple alternating layers of dielectric material and conductive material, each of which can be about 10 nm or thicker. One way to form such a stack involves depositing multiple alternating layers of oxide material and nitride material (ONON multilayer deposition), then selectively removing the nitride material and backfilling the space previously occupied by the nitride material with metal. This method can be used to manufacture 3D NAND structures.

[0048] Another approach is to directly pattern a stack of multiple alternating oxide layers and polysilicon (or "poly" as used elsewhere in this document) layers, with the polysilicon retained as a conductive layer. In some cases, the stack can include a metal, such as a tungsten material. However, using some techniques to form a stack including a dielectric, polysilicon, and a metal can be challenging. In particular, it can be difficult to etch trenches and to recess the sidewalls of the oxide material to form, for example, a floating gate. Etching the metal within the stack itself can also result in a high risk of metal residues on the resulting device and can also undesirably change the profile of the etched pattern. In some cases, the manufacture of 3-terminal devices includes a variety of different materials but cannot be manufactured using existing techniques. In some cases, manufacturing 2-terminal capacitors in 3D NAND structures is challenging because separate source / drain regions must be manufactured on each device.

[0049] Figure 1A process flow diagram of operations performed according to a method of forming a 3D NAND structure is shown. In operation 182, a substrate is provided. In various embodiments, the substrate is a semiconductor substrate. The substrate can be a silicon wafer, such as a 200 mm wafer, a 300 mm wafer, or a 450 mm wafer, which includes a wafer having one or more layers of material, such as a dielectric material, a conductive material, or a semiconductive material deposited thereon. An exemplary substrate 100 is provided as Figure 2 Schematic diagram in. Return Figure 1 In operation 184, a film stack of alternating oxide and nitride films is deposited on the substrate. In various embodiments, the deposited oxide layer is a silicon oxide layer. In various embodiments, the deposited nitride layer is a silicon nitride layer. Each oxide and nitride layer is deposited to approximately the same thickness, such as, in some embodiments, a thickness between about 10 nm and about 100 nm, or about 10 nm. The oxide layer may be deposited at a deposition temperature between about room temperature and about 600° C. It should be understood that “deposition temperature” (or “substrate temperature”) as used herein refers to the temperature set for the susceptor holding the substrate during deposition.

[0050] The oxide and nitride layers used to form the alternating oxide and nitride film stack can be deposited using any suitable technique, such as atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or sputtering. In various embodiments, the oxide and nitride layers are deposited by PECVD.

[0051] The film stack may include between 48 and 512 alternating oxide and nitride layers, whereby each oxide layer or nitride layer constitutes one layer. In some embodiments, depending on the application, the film stack may include fewer than 48 layers or greater than 512 layers of alternating oxide and nitride layers. A film stack comprising alternating oxide and nitride layers may be referred to as an ONON stack. Although the film stack described herein relates to alternating oxide and nitride layers, it should be understood that additional layers may be included in the stack, and further, other materials may be used for the alternating layers that are not oxide layers and are not nitride layers. For example, in some cases, silicon germanium layers may be used in place of nitride layers or silicon nitride layers. Other additional layers that may be located on the stack include silicon-containing layers, germanium-containing layers, or both. Exemplary silicon-containing layers include doped and undoped silicon carbide layers, doped and undoped polysilicon layers, amorphous silicon layers, doped and undoped silicon oxide layers, and doped and undoped silicon nitride layers. Dopants may include non-metallic dopants. For example, an exemplary doped silicon carbide layer is oxygen-doped silicon carbide. In another example, an exemplary doped silicon carbide layer is nitrogen-doped silicon carbide.

[0052] Figure 3 An example schematic diagram of a substrate 100 is shown, wherein alternating oxide (101) and nitride (102) films are deposited on the substrate 100. Note that although Figure 3 The illustrated structure shows oxide deposited first, then nitride, oxide, nitride, etc., but nitride may be deposited first, then oxide, nitride, oxide, etc.

[0053] After depositing the ONON stack, a channel can be etched in the substrate ( Figure 3 ). Subsequently, refer to Figure 1 , in operation 186, a staircase pattern is formed on the substrate. The "staircase pattern" referred to herein includes two or more steps, each step including an oxide and a nitride layer. It should be understood that the top layer of each set of oxide and nitride layers can be either an oxide or a nitride used to form the staircase steps. In various embodiments, the staircase pattern includes 24 to 256 steps. A variety of patterning techniques can be used to form the staircase pattern. For example, one technique can include depositing a sacrificial layer above the substrate and covering various areas of the substrate to etch each set of oxide and nitride layers to form the steps.

[0054] Figure 4A An example of a substrate 100 is provided that includes a stepped pattern of oxide (111) and nitride (112) layers with a hard mask 110 over the topmost nitride layer. Figure 4AFour steps of the staircase pattern are shown, but it should be understood that the staircase pattern can have 24 to 256 steps. Each step includes a nitride and an oxide layer, and as shown in FIG. Figure 4A The distance d shown in can be between about 150 nm and about 1000 nm, such as about 500 nm. The region of each step that extends outward from the edge of the step above it can be referred to as a "pad" having a particular distance d.

[0055] For purposes of discussion, the following discussion of the substrate and subsequent schematics will include Figure 4B Half side view 199 shown.

[0056] exist Figure 1 In operation 188, an oxide is deposited over the substrate. In various embodiments, the oxide can have the same composition as the oxide deposited in the layers of the ONON stack. In various embodiments, the oxide deposited on the substrate is deposited at a deposition temperature different from the deposition temperature used to deposit the oxide layer in the ONON stack. The deposition temperature can be between room temperature and approximately 600° C. After the oxide is deposited, vertical slits 135 can then be etched into the substrate. Figure 5A An exemplary substrate 100 is shown including an ONON step, a hard mask 110, and an oxide 122 deposited over the substrate. Figure 5B A side view of the substrate 100 is shown after etching the vertical slits 130 .

[0057] return Figure 1 In operation 190, the nitride is selectively etched relative to the oxide on the substrate. The etching can be performed using a selective dry etching process, for example, by exposing the substrate to any one or more of the following gases: chlorine (Cl2), oxygen (O2), nitrous oxide (N2O), tetrafluoromethane (CF4), sulfur tetrafluoride (SF4), carbon dioxide (CO2), fluoromethane (CH3F), nitrogen trifluoride (NF3), nitrogen (N2), hydrogen (H2), ammonia (NH3), methane (CH4), sulfur hexafluoride (SF6), argon (Ar), carbonyl sulfide (COS), carbon disulfide (CS2), hydrogen sulfide (H2S), and nitric oxide (NO). This operation removes the nitride layer from the ONON stack, allowing the etching species to flow into the vertical slits and selectively etch the nitride. It should be understood that selective etching involves etching the first material at a faster rate than etching the second material. For example, selectively etching the nitride relative to the oxide means etching the nitride at a faster rate than etching the oxide. A wet etch process is used to selectively etch the nitride, for example by exposing the substrate to phosphoric acid (H3PO4) and / or dilute hydrofluoric acid ("DHF") or a mixture of these solutions. Figure 6A side view of a cross section of the substrate is shown, wherein gaps 132 are formed by selectively etching the nitride.

[0058] return Figure 1 In operation 192, tungsten is deposited into the gaps in the substrate to form tungsten wordlines. Tungsten can be deposited by any suitable technique, such as ALD, CVD, PEALD, and / or PECVD. In some embodiments, a barrier layer and / or a tungsten nucleation layer is deposited prior to depositing the bulk tungsten. Exemplary barrier layers include titanium nitride, aluminum oxide, and tungsten carbonitride. Figure 7 A schematic diagram of a cross section of the substrate is shown from a side view, with tungsten 140 deposited in the gap where nitride previously existed. As shown, metal deposition results in deposition on the sidewalls of oxide 111. Although tungsten is described herein, other metals, such as molybdenum, can be used.

[0059] return Figure 1 In operation 194, vias are formed by vertically etching the substrate, which may include etching both oxide deposited above the steps and etching metal to remove metal from the sidewalls of the oxide in the alternating layers. The oxide may be etched by dry etching using exposure to one or more of the following gases: O2, Ar, C4F6, C4F8, SF6, CHF3, and CF4. Figure 8 An exemplary substrate 100 is shown comprising an ONON stack in a stair-step pattern with vias 135 etched into the stack.

[0060] exist Figure 1 In operation 196, tungsten may be deposited in the vias to form interconnects to the tungsten word lines. The depth of the vias varies and may have a depth between about 1 micron and about 12 microns. Shallow vias may be defined as having a depth less than 3.0 microns, such as between about 1.5 microns and 3.0 microns. Deep vias may have a depth greater than 3.0 microns. The critical dimension of the vias formed in the oxide may be between about 50 nm and about 500 nm. The vias may be etched using a dry etch process that may involve a masking operation to pattern the oxide. In various embodiments, the patterning process may include Figure 1 Further operations are not shown in FIG. For example, after depositing oxide over the substrate in operation 188, a trench may be etched to form a channel. The channel may be filled with a charge-trapping layer, and a large trench or slit may be etched before selectively etching the nitride in operation 190. Tungsten may be removed from the sidewalls before vertically etching the oxide and after depositing the tungsten wordline.

[0061] Figure 1An example is provided in which tungsten backfill is deposited by CVD for ONON gate replacement. This technique can be used to form an ONON or OPOP integrated solution for forming a memory cell stack. For example, in some embodiments where polysilicon is retained as the gate for the OPOP solution, both ONON and OPOP solutions can be etched in this way without significant risk. However, applying this technique to complex multilayer stacks presents challenges.

[0062] For example, the layers may include silicon oxide, tungsten, polysilicon, and another dielectric in the final structure. This may involve recessing the sidewalls of the dielectric, similar to the floating gate formation in the OPOP scheme. While one approach is to etch a film stack containing silicon oxide, silicon nitride, polysilicon, tungsten, and titanium nitride, and then recess the silicon oxide or silicon nitride (e.g., relative to the wet etch contrast between silicon oxide, silicon nitride, polysilicon, and tungsten) using the wet etch contrast between silicon oxide, silicon nitride, polysilicon, and tungsten, the dielectric may be recessed. Figures 9A-9D However, such processes present some challenges.

[0063] Figures 9A-9D Another set of schematics for processing different multilayer stacks is shown. Figure 9A The silicon nitride layer 902 includes a tungsten layer 940 (with an optional titanium nitride liner (not shown) between the tungsten layer 940 and the silicon nitride layer 902), a polysilicon layer 900 (with an optional titanium nitride layer (also not shown) between the tungsten layer 940 and the polysilicon layer 900), a silicon oxide layer 901, and a silicon nitride layer 902. Figure 9B In the etching process, a through hole or trench 950 is etched, which involves etching all of the above-mentioned materials in the stack, including metal, which may result in unwanted metal residues on the substrate. The silicon oxide 901 may be further recessed to form a structure for the substrate. Figure 9C In the embodiment, polysilicon 900 is filled to fill the recessed area adjacent to silicon oxide 901. Figure 9D In the embodiment, the polysilicon 900 is further etched to form a through hole again, thus including the following steps: Figure 9D The structure shown in .

[0064] However, this process involves etching tungsten and / or metals and other silicon-containing materials, which can be challenging. First, etching multilayer stacks of dielectrics and metals while maintaining vertical profiles is very difficult, partly due to varying etch rates and etching chemistries used for different materials. This can lead to feature collapse and degradation of feature profiles. Second, metal residues left in high-aspect-ratio structures are difficult to clean and can affect device integrity. Third, the deposition of tungsten films can result in a rough surface and can cause issues with device performance control.

[0065] Methods and apparatus are provided herein for forming and etching multilayer film stacks to perform high aspect ratio patterning and vertical and three-dimensional scaling. The multilayer film stack can include repeating groups of layers, wherein one layer is deposited on top of another. Each group of layers can include at least three different materials. In some embodiments, each group includes four different materials. For the same group of layers, one can be stacked on top of another multiple times, for example, about 5 times, or about 10 times, or about 20 times, or more.

[0066] High aspect ratio vias or trenches patterned using certain disclosed embodiments can have aspect ratios greater than about 5:1, or between about 5:1 and about 20:1, or between about 25:1 and about 35:1, or greater. Some embodiments involve replacing the metal in a film stack with another dielectric that has similar dry etching behavior to the other material, but exhibits a strong wet etch contrast relative to the other material. For example, in 100:1 dilute hydrofluoric acid or phosphoric acid, the wet etch contrast of the dielectric replacing the metal relative to the other material can be about 10:1. The disclosed embodiments can be performed to form structures having both metal and dielectric materials without the risk of causing metal residues on the substrate. In various embodiments, etching of the substrate having both metal and dielectric materials is avoided because the metal is deposited after the patterned structure. That is, in various embodiments, a metal-free film stack is etched and processed in the absence of metal so that a dielectric material is deposited and positioned in areas where metal will later be deposited, and after the desired structure is formed, the dielectric material is removed, and metal is subsequently deposited in its place to form the desired pattern or device. Certain disclosed embodiments relate to process integration of forming a structure comprising a dielectric material and a sacrificial layer in areas where metal will later be deposited, etching the sacrificial layer after patterning to leave a space in the structure, and depositing metal into the space. The disclosed embodiments may be advantageous for performing sidewall recessing to form specific devices such as floating gates. Certain disclosed embodiments also enable better profile control.

[0067] Certain disclosed embodiments can be used to forgo etching tungsten in a multilayer stack by using a sacrificial silicon nitride material to etch a pattern, then exploiting the etch contrast between the silicon nitride and other dielectric materials to selectively remove the silicon nitride to create a space into which metal is then deposited. Where the multilayer stack also includes other non-sacrificial silicon nitride layers, these materials can be replaced with oxygen-doped silicon carbide, which provides both etch contrast when selectively removing the silicon nitride and properties similar to silicon nitride to perform the function of the particular layer. The dielectric layers described herein (e.g., SiOC) will have wet etch contrast during SiN removal and recessing of SiO2, but will have similar dry etch behavior during high aspect ratio patterning. The dielectric can also be other materials that provide similar properties. Such materials can be polysilicon with different dopants, or SiN deposited under different process conditions that have significantly different wet etch rates than sacrificial SiN, or nitrogen-doped SiC (SiNC).

[0068] The disclosed embodiments may be used in a variety of applications, including for the fabrication of 3D-NAND devices, floating gates, etc. An example of a specific stack that may be formed using certain disclosed embodiments is described herein; it should be understood that other materials and other patterning schemes and stacks may be formed using certain disclosed embodiments, and the disclosed embodiments are not limited to this example.

[0069] In certain disclosed embodiments, a stack is deposited using silicon nitride as a sacrificial layer, over which a metal may later be deposited, such that the sacrificial layer can be removed after the etching operation to create a space for the metal material, and the metal backfilled into the space. Although tungsten is described herein as an exemplary metal, it should be understood that other metals, such as molybdenum, may be used. In another embodiment, polysilicon material or doped polysilicon may be used in place of silicon nitride as the sacrificial layer. Where other silicon nitride films are present in the stack to be manufactured (top and bottom films in the provided stack), such layers are replaced with oxygen-doped silicon carbide to avoid etching these layers when the sacrificial silicon nitride layer is removed. One advantage of oxygen-doped silicon carbide is that it provides an etch contrast relative to other materials on the substrate (including silicon nitride and polysilicon) when performing removal or recessing of SiN, polysilicon, or SiO2.

[0070] Thus, an alternating stack of oxygen-doped silicon carbide and silicon oxide can be formed, silicon nitride can be used as a sacrificial layer (tungsten will later be deposited in its place), and the silicon oxide can be recessed before depositing the polysilicon because the silicon oxide can be etched at an etch contrast relative to oxygen-doped silicon carbide and silicon nitride. In some embodiments, the silicon oxide can be recessed at an etch contrast relative to nitrogen-doped silicon carbide and silicon nitride. In some embodiments, the silicon oxide can be etched at an etch contrast relative to oxygen-doped silicon carbide and silicon germanium. In some embodiments, the silicon oxide can be recessed at an etch contrast relative to any other non-silicon oxide material on the substrate, including but not limited to nitrogen-doped silicon carbide, doped silicon, silicon nitride, and silicon germanium. After depositing the polysilicon and any other patterning processes, a wet etch process can be used to selectively remove the silicon nitride sacrificial layer. A titanium nitride liner can optionally be deposited, and tungsten can be deposited in the area previously occupied by the silicon nitride sacrificial layer. This type of process avoids patterning of the tungsten on the stack, thereby reducing tungsten redeposition on the substrate. Furthermore, the tungsten material in the stack is not subject to various process conditions that could warp and / or modify the grain structure of the tungsten material, since the tungsten is deposited after all other processes have been performed. Etching of the stack is simplified because the etching chemistry is not limited to chemistries that can etch tungsten; rather, the materials on the stack are all silicon-containing materials and can be precisely etched using a variety of existing etching processes.

[0071] Certain disclosed embodiments relate to depositing a metal-free multilayer stack comprising at least three different materials, at least one of which is a sacrificial layer. As used herein, the term "metal-free" includes silicon-containing materials; that is, metal-free primarily refers to materials that do not include transition metals or metalloids, but do include semiconducting materials. Exemplary metal-free materials include, but are not limited to, silicon nitride, silicon carbide, doped silicon carbide, silicon oxide, amorphous silicon, doped silicon, and polycrystalline silicon. In various embodiments, the metal-free stack does not include tungsten. In various embodiments, the metal-free stack is tungsten-free. Sacrificial layers are used during etching and patterning of the multilayer stack; the sacrificial layers can be used to avoid etching metal. After patterning, the sacrificial layers can then be etched and replaced with a metallic material for the final structure. For example, in some embodiments, a metal-free multilayer stack comprising at least three different materials is deposited, trenches or vias are etched in the metal-free multilayer stack, and after etching, the sacrificial layer is selectively etched relative to the other materials of the stack to form a space, and metal is deposited in the space. In various embodiments, the metal-free multilayer stack comprises four different silicon-containing materials. In some embodiments, the metal-free multilayer stack comprises four different metal-free materials. In some embodiments, "different" materials means materials having different molecular or atomic compositions, or different grain structures, or different lattice structures. When exposed to multiple etchants, including liquid etchants, selective etching of the sacrificial layer can be achieved by exploiting the etching contrast between the materials.

[0072] In various embodiments, the sacrificial layer can be polysilicon or a silicon nitride material. Etch contrast for the silicon nitride sacrificial layer can be achieved by using other materials in the multilayer stack, including but not limited to silicon oxide, oxygen-doped silicon carbide, or silicon oxycarbide, and polysilicon. Etch contrast for the polysilicon sacrificial layer can be achieved by using an etchant whereby the polysilicon etches substantially faster than the other materials on the substrate. Even if the other material on the stack includes polysilicon, etch contrast can be achieved using differences in dopant concentration in the polysilicon. The dopant concentration in the polysilicon can be about 1E19 atoms / cm 3 to about 1E20 atoms / cm 3 For example, in some embodiments, the multilayer stack may include boron-doped polysilicon, while the sacrificial layer includes undoped polysilicon, so that the undoped polysilicon can be etched with an etch contrast relative to the boron-doped polysilicon to leave space for later metal deposition. It should be understood that metal deposition can be performed by first depositing a liner layer such as, but not limited to, titanium nitride, followed by metal deposition.

[0073] Different variations of multilayer stacks may be used. For example, in some embodiments, the multilayer stack comprises silicon nitride, silicon oxide, and oxygen-doped silicon carbide. In some embodiments, the terms silicon oxycarbide and oxygen-doped silicon carbide are used interchangeably. In some embodiments, the multilayer stack comprises polycrystalline silicon, silicon oxide, and oxygen-doped silicon carbide. In some embodiments, the multilayer stack comprises polycrystalline silicon, silicon nitride, silicon oxide, and oxygen-doped silicon carbide.

[0074] In some embodiments, the multilayer stack includes alternating layers of silicon nitride and non-oxide layers, and trenches or through-holes are etched in the multilayer stack, followed by selective etching of the silicon nitride to form spaces between the non-oxide layers. Metal can then be deposited into the spaces. The non-oxide layer can be silicon oxycarbide, polysilicon, or a silicon nitride material having a wet etch contrast relative to another silicon nitride material. In some embodiments, the multilayer stack including alternating layers also includes another layer having a material different from the silicon nitride or non-oxide layer. This layer can be a dielectric barrier layer. In some embodiments, this layer is not a dielectric barrier layer. In some embodiments, this layer is not a dielectric material. In some embodiments, the other layer having a material different from the silicon nitride and non-oxide layers is an oxygen-doped silicon carbide layer. In some embodiments, this other layer is used to achieve an etch contrast when etching the silicon nitride. In some embodiments, the multilayer stack can be used to form a 3D NAND structure.

[0075] As described herein, the oxygen-doped silicon carbide or silicon oxycarbide has an oxygen concentration between about 1% and about 65% atomic%.

[0076] Figure 10 is a process flow diagram depicting operations performed according to certain disclosed embodiments. In operation 1082, a substrate is provided. The substrate can be a silicon wafer, such as a 200 mm wafer, a 300 mm wafer, or a 450 mm wafer, including a wafer having one or more layers of material, such as a dielectric, conductive, or semiconductive material, deposited on the wafer. In operation 1084, a film stack is deposited comprising an oxide, an oxygen-doped carbide, and one or more layers of sacrificial silicon nitride, wherein the sacrificial silicon nitride is deposited in spaces where metal is desired in the final structure. Although silicon oxide, silicon nitride, and oxygen-doped silicon carbide are described herein, it should be understood that in some embodiments, other oxides, nitrides, and oxygen-doped carbides may be used.

[0077] Silicon-oxygen doped carbides may be deposited by plasma enhanced chemical vapor deposition by introducing a silicon-containing precursor, an oxygen-containing reactant, and a carbon-containing reactant while igniting a plasma.

[0078] Precursor molecules for depositing silicon carbide may include silicon-containing molecules having silicon-hydrogen (Si-H) and / or silicon-silicon (Si-Si) bonds, and silicon-carbon (Si-C) bonds. In some embodiments, the precursor molecules for depositing the silicon carbide layer may be silicon- and carbon-containing precursors. Precursor molecules for depositing silicon carbide oxides include silicon-containing molecules having silicon-hydrogen (Si-H) bonds and / or silicon-silicon (Si-Si) bonds, and silicon-oxygen (Si-O) bonds and / or silicon-carbon (Si-C) bonds. Precursor molecules for depositing silicon carbon nitrides include silicon-containing molecules having silicon-hydrogen (Si-H) bonds and / or silicon-silicon (Si-Si) bonds, and silicon-nitrogen (Si-N) bonds and / or silicon-carbon (Si-C) bonds. Precursor molecules for depositing silicon oxynitride include silicon-containing molecules having silicon-hydrogen (Si-H) bonds and / or silicon-silicon (Si-Si) bonds, and silicon-nitrogen (Si-N) bonds, silicon-oxygen (Si-O) bonds, and / or silicon-carbon (Si-C) bonds. In some embodiments, the silicon-containing precursor may include a reactant having an Si-O bond and a reactant having an Si-C bond. It should be understood that any number of suitable reactants may be used within the scope of this disclosure. The silicon-containing precursor includes one or more Si-H bonds and / or one or more Si-Si bonds. During the deposition process, the Si-H bonds and / or Si-Si bonds break and act as reaction sites for forming bonds between the silicon-containing precursors in the deposited silicon carbide film. The broken bonds may also be used as sites for crosslinking during the heat treatment performed during or after deposition. The bonding and crosslinking at the reaction sites can form a main chain or matrix together in the resulting silicon carbide film. In some embodiments, silicon carbide, nitrogen-doped silicon carbide, boron- and nitrogen-doped silicon carbide, and combinations thereof, including combinations with oxygen-doped silicon carbide, may be used instead of oxygen-doped silicon carbide.

[0079] As discussed, the precursors used in forming the silicon carbide film can include silicon-containing precursors, such that at least some of the silicon-containing precursors have at least one Si-H and / or at least one Si-Si bond. In certain embodiments, the silicon-containing precursors have at most one hydrogen atom per silicon atom. Thus, for example, a precursor having one silicon atom has at most one hydrogen atom bonded to the silicon atom; a precursor having two silicon atoms has one hydrogen atom bonded to one silicon atom and optionally another hydrogen atom bonded to a second silicon atom; a precursor having three silicon atoms has at least one hydrogen atom bonded to one silicon atom and optionally one or more hydrogen atoms bonded to one or both of the remaining silicon atoms, and so on. Additionally, the silicon-containing precursors may include at least one Si-O bond, at least one Si-N bond, and / or at least one Si-C bond. While any number of suitable precursors may be used to form the silicon carbide film, at least some of the precursors will include silicon-containing precursors having at least one Si-H or Si-Si bond, and optionally at least one Si-O, Si-N, and / or Si-C bond.

[0080] In certain embodiments, at least some of the carbon provided to the silicon carbide film is provided by one or more hydrocarbon groups on the silicon-containing precursor. Such groups can be selected from alkyl, alkenyl, alkynyl, aryl, and the like. In certain embodiments, the hydrocarbon group has a single carbon atom to minimize steric hindrance to Si-H and / or Si-Si bond cleavage reactions during deposition. However, the precursor is not limited to a single carbon group; rather, a higher number of carbon atoms, such as 2, 3, 4, 5, or 6 carbon atoms, can be used. In certain embodiments, the hydrocarbon group is linear. In certain embodiments, the hydrocarbon group is cyclic.

[0081] In some embodiments, the silicon-containing precursor belongs to the chemical class It should be understood that other chemical classes of silicon-containing precursors can be employed and the silicon-containing precursors are not limited to the chemical classes discussed below.

[0082] In some embodiments, the silicon-containing precursor can be a siloxane. In some embodiments, the siloxane can be cyclic. Cyclic siloxanes can include cyclotetrasiloxanes, such as 2,4,6,8-tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (OMCTS), and heptamethylcyclotetrasiloxane (HMCTS). Other cyclic siloxanes can also include, but are not limited to, cyclotrisiloxane and cyclopentasiloxane. An embodiment using cyclic siloxanes is to introduce pores into the annular structure of the oxygen-doped silicon carbide film, the size of the pores corresponding to the radius of the ring. For example, a cyclotetrasiloxane ring can have a diameter of about 100 nm. radius.

[0083] In some embodiments, siloxanes may have a three-dimensional or cage-like structure. Cage-like siloxanes have silicon atoms bridged to each other via oxygen atoms to form a polyhedron or any 3-D structure. An example of a cage-like siloxane precursor molecule is silsesquioxane. Cage-like siloxane structures are described in more detail in U.S. Patent No. 6,576,345, co-owned by Cleemput et al., which is incorporated herein by reference in its entirety for all purposes. Like cyclic siloxanes, cage-like siloxanes can introduce pores into oxygen-doped silicon carbide films. In some embodiments, the porosity level is mesoporous.

[0084] In some embodiments, the siloxane can be linear. Examples of suitable linear siloxanes include, but are not limited to, disiloxanes, such as pentamethyldisiloxane (PMDSO) and tetramethyldisiloxane (TMDSO), and trisiloxanes, such as hexamethyltrisiloxane and heptamethyltrisiloxane.

[0085] In some embodiments, the silicon-containing precursor can be an alkylsilane or other hydrocarbon-substituted silane. The alkylsilane includes a central silicon atom, wherein one or more alkyl groups are bonded thereto and one or more hydrogen atoms are bonded thereto. In certain embodiments, any one or more of the alkyl groups contain 1-5 carbon atoms. The hydrocarbyl group can be saturated or unsaturated (e.g., olefins (e.g., vinyl), alkynyl, and aromatic groups). Examples include, but are not limited to, trimethylsilane (3MS), triethylsilane, pentamethyldisilane ((CH ) 2Si-CH 2 -Si(CH ) 3) and dimethylsilane (2MS).

[0086] In some embodiments, the silicon-containing precursor may be an alkoxysilane. Alkoxysilanes include a central silicon atom having one or more alkoxy groups bonded thereto and one or more hydrogen atoms bonded thereto. Examples include, but are not limited to, trimethoxysilane (TMOS), dimethoxysilane (DMOS), methoxysilane (MOS), methyldimethoxysilane (MDMOS), diethoxymethylsilane (DEMS), dimethylethoxysilane (DMES), and dimethylmethoxysilane (DMMOS).

[0087] In addition, disilane, trisilane, or other higher silanes can be used instead of monosilane. An example of a disilane from the alkylsilane class is hexamethyldisilane (HMDS). Another example of a disilane from the alkylsilane class can include pentamethyldisilane (PMDS). Other types of alkylsilanes can include alkylcarbosilanes, which can have a branched polymer structure with a carbon bonded to a silicon atom and an alkyl bonded to the silicon atom. Examples include dimethyltrimethylsilylmethane (DTMSM) and bisdimethylsilylethane (BDMSE). In some embodiments, one of the silicon atoms can have a carbon-containing or hydrocarbon-containing group attached thereto, and one of the silicon atoms can have a hydrogen atom attached thereto.

[0088] In some embodiments, two or more different chemical sources may be used. For example, one chemical source may include silicon, while a second chemical source includes carbon. In some embodiments, the chemical source including silicon may be TEOS or any silane as described above. In some embodiments, the chemical source including carbon may include methane, alkanes (e.g., ethane (C2H6)), alkenes (e.g., ethylene (C2H4)), and alkynes (e.g., C2H3).

[0089] In depositing silicon carbide, multiple silicon-containing precursors may be present in the process gas. For example, siloxane and alkylsilane may be used together, or siloxane and alkoxysilane may be used together. The relative proportions of the various precursors can be selected based on the chemical structure of the selected precursors and the application of the resulting silicon carbide film.

[0090] Some silicon carbide films in multilayer stacks can have high breakdown voltage and low leakage current. An example of a breakdown voltage achieved by certain disclosed embodiments is approximately 4 MV / cm. An example of a low leakage current achieved by certain disclosed embodiments is approximately 1E-8 at 2 MV / cm.

[0091] In some embodiments, the process conditions can substantially preserve Si-C bonds, and Si-O bonds and Si-N bonds (if present) in the as-deposited layer of the silicon carbide film. Thus, the reaction conditions adjacent to the substrate provide for the selective breaking of Si-H and / or Si-Si bonds, such as extracting hydrogen from the broken Si-H bonds, but the reaction conditions do not provide for the extraction of oxygen from Si-O bonds, nitrogen from Si-N bonds, or carbon from Si-C bonds. However, as described below, the introduction of a co-reactant (e.g., oxygen) can extract carbon from Si-C bonds. Typically, the reaction conditions described are present on the exposed surface of the substrate (the surface on which the silicon carbide film is deposited). They can further be present at a distance above the substrate, for example, from about 0.5 microns to about 150 mm above the substrate. In practice, the activation of the precursor can occur in the gas phase at a considerable distance above the substrate. Typically, the relevant reaction conditions will be uniform or substantially uniform over the entire exposed surface of the substrate, although some applications may allow for some variation.

[0092] The silicon-containing precursor is usually transported to an environment adjacent to the substrate together with other substances (especially carrier gas). In some embodiments, the silicon-containing precursor exists together with free radical substances and other substances (including other reactive substances and / or carrier gas). In some embodiments, the silicon-containing precursor can be imported as a mixture. Upstream of the deposition reaction surface, the silicon-containing precursor can be mixed with an inert carrier gas. Exemplary inert carrier gases include but are not limited to nitrogen (N2), argon (Ar) and helium (He). In addition, the silicon-containing precursor can be imported into a mixture with a primary and secondary substance so that the secondary substance contains some elements or structural features (e.g., ring structure, cage structure, unsaturated bond, etc.) that are present in the silicon carbide film at a relatively low concentration. As appropriate, multiple precursors can exist in equimolar or quite similar ratios to form the main chain or matrix in the resulting silicon carbide film. In other embodiments, the relative amounts of different precursors substantially deviate from equimolar amounts.

[0093] To deposit silicon oxide, one or more silicon-containing precursors may be used. Suitable silicon-containing precursors for use according to the disclosed embodiments include polysilane (H3Si-(SiH2) n -SiH3), where n >0. Examples of silanes are silane (SiH4), disilane (Si2H6), and organosilanes such as methylsilane, ethylsilane, isopropylsilane, tert-butylsilane, dimethylsilane, diethylsilane, di-tert-butylsilane, allylsilane, sec-butylsilane, tert-hexylsilane (thexylsilane), isopentylsilane, tert-butyldisilane, di-tert-butyldisilane, and the like.

[0094] Halosilanes include at least one halogen group, and may or may not include hydrogen and / or carbonyl.The example of halosilanes is iodosilane, bromosilane, chlorosilane and fluorosilane.Although halosilane (especially fluorosilane) can form reactive halide species, it can etch silicon material when plasma ignites, but in some embodiments, when plasma ignites, halogenated silane may not be imported into chamber, therefore can alleviate the reactive halide species formed by halosilane.Concrete chlorosilane is tetrachlorosilane, trichlorosilane, dichlorosilane, monochlorosilane, chloroallyl silane, chloromethylsilane, dichloromethylsilane, chlorodimethylsilane, chloroethylsilane, tert-butylchlorosilane, di-tert-butylchlorosilane, chloroisopropylsilane, chloro-sec-butylsilane, tert-butyldimethylchlorosilane, tert-hexyldimethylchlorosilane etc.

[0095] Aminosilanes include at least one nitrogen atom bonded to a silicon atom, but may also contain hydrogen, oxygen, halogens, and carbon. Examples of aminosilanes are mono-, di-, tri-, and tetra-aminosilanes (H3Si(NH2), H2Si(NH2)2, HSi(NH2)3, and Si(NH2)4, respectively) and substituted mono-, di-, tri-, and tetra-aminosilanes, such as tert-butylaminosilane, methylaminosilane, tert-butylsilylamine, bis(tert-butylamino)silane, (SiH2(NHC(CH3)3)2(BTBAS), tert-butylsilylcarbamate, SiH(CH3)-(N(CH3)2)2, SiHCl-(N(CH3)2)2, (Si(CH3)2NH)3, and the like. Another example of an aminosilane is trimethylsilylamine (N(SiH3)). In various embodiments, plasma may not be used during the deposition of any layer of the multilayer stack. In some embodiments, plasma may be used during the deposition of any layer of the multilayer stack.

[0096] Exemplary techniques for depositing some of the layers described herein are provided in US Pat. No. 8,741,394, US Pat. No. 9,028,924, and US Patent Publication No. 2011 / 0236594, which are incorporated herein by reference in their entireties.

[0097] Oxygen doping can be adjusted using certain techniques, such as adjusting the temperature, pressure, plasma power, and frequency, as well as the oxygen-containing reactive gas flow relative to other gas flows. The amount of oxygen doping affects the relative etch contrast. For example, silicon nitride may have a specific etch contrast of about 0% to about 65% relative to silicon carbide doped with oxygen, whereas the same material may have a lower etch contrast relative to silicon carbide doped with 66% oxygen under the same process conditions. In hot phosphoric acid (H3PO4), silicon nitride has an etch contrast relative to silicon oxide. Silicon carbide oxide can be used to provide wet etch contrast both relative to silicon nitride in H3PO4 wet etching and relative to silicon oxide in hydrofluoric acid (HF) wet etching.

[0098] return Figure 10 In operation 1086, any pattern can be etched on the substrate. For example, in some embodiments, trenches or through-holes are etched through the multilayer stack, which can be performed using existing dielectric etching techniques without any risk of metal residue or degradation of the etching profile. For example, this operation may involve recessing the silicon oxide material, which can be performed because oxygen-doped silicon carbide, silicon nitride, and polysilicon can provide sufficient etching contrast relative to the etching of silicon oxide. In various embodiments, the etching chemicals used to pattern the stack include one or more of tetrafluoromethane (CF4), fluoromethane (CFH3), difluoromethane (CH2F2), octafluorocyclobutane (C4F8), and nitrogen trifluoride (NF3). Patterning can be performed to etch trenches or through-holes. In some embodiments, this operation may not include a silicon oxide recessing operation.

[0099] During the patterning in operation 1086, the etch contrast can vary depending on the materials in the stack. In some embodiments, the silicon oxide is recessed after etching the trenches so that the silicon oxide is selectively removed from the sidewalls in the trenches, resulting in the trenches having a varying width at a specific depth within the stack. For example, trenches can be etched into a stack comprising silicon nitride, silicon oxide, and polysilicon (wherein the silicon oxide is between the silicon nitride and the polysilicon), and then the silicon oxide can be etched in the trenches so that the sidewalls of the trenches with the silicon oxide are recessed. The recessing of the silicon oxide can be performed using a specific etching chemistry that has an etch contrast relative to other materials on the substrate. In various embodiments, the etching of silicon oxide is between about 5 and about 1000 times faster than that of silicon nitride, polysilicon, and oxygen-doped silicon carbide.

[0100] Silicon oxide is provided as an example. In some embodiments, the dielectric material is recessed so that the dielectric material is selectively removed from the sidewalls of the trench. Exemplary dielectric materials include, but are not limited to, silicon oxide and doped silicon oxide.

[0101] In operation 1090, a sacrificial silicon nitride material is selectively etched from the substrate relative to other materials on the substrate (polysilicon, oxide, oxygen-doped silicon carbide). This operation can be performed in a wet etching process using the etch contrast of the sacrificial silicon nitride relative to these materials. For example, in some embodiments, the sacrificial silicon nitride can be etched by immersing the substrate in hot H3PO4. Etching in this manner will result in the formation of spaces on the substrate in locations previously occupied by silicon nitride. The etch selectivity of silicon nitride relative to other materials on the substrate can be between about 10 and about 1000, where the other materials are silicon oxide, oxygen-doped silicon carbide, and polysilicon.

[0102] In operation 1092, tungsten is deposited on the substrate in the spaces previously occupied by the sacrificial silicon nitride material. For example, tungsten can be deposited into the horizontal spaces between oxide layers. In some embodiments, a metal-containing liner is deposited before depositing the metal. In various embodiments, the metal-containing liner can be titanium nitride, aluminum oxide, or tungsten carbonitride. The metal deposited in operation 1092 can be deposited directly on or above the metal-containing liner. For example, tungsten can be deposited on a titanium nitride liner.

[0103] Figure 11A An exemplary process flow diagram depicting operations performed according to certain disclosed embodiments is shown. In this example, a substrate is provided in operation 1282. In operation 1284, a metal-free film stack is deposited, such as with reference to FIG. Figure 9A and the following Figure 12A As described. In operation 1285, a trench is etched in the metal-free stack. In various embodiments, the etched trench has a high aspect ratio, for example, a high aspect ratio between about 5:1 and about 20:1. In various embodiments, the width of the trench is between about 30 nm and about 200 nm. In operation 1286, the silicon oxide can be recessed. In various embodiments, the silicon oxide recessing is performed so that the etching rate of the silicon oxide is at least about 50 times faster than the etching rate of other materials in the metal-free stack. The silicon oxide recessing can be performed using any suitable etching chemistry, including but not limited to halogen-based chemistry, such as hydrofluoric acid. In operation 1290, the sacrificial silicon nitride layer is selectively removed. In various embodiments, the sacrificial silicon nitride layer is etched using a phosphorus-based chemistry for wet etching (for example, by using diluted H3PO4). In operation 1292, tungsten is deposited in the location where the sacrificial silicon nitride was removed.

[0104] Figure 11BAnother exemplary process flow diagram depicting operations performed according to certain disclosed embodiments is shown. In this example, a substrate is provided in operation 1182. In operation 1184, a film stack is deposited such that multiple groups of the following film stacks (from top to bottom) are deposited on top of one another: oxygen-doped silicon carbide, silicon nitride, doped polysilicon, silicon oxide, doped polysilicon, and silicon nitride. In operation 1186a, the silicon oxide can be recessed. In operation 1186b, polysilicon is filled into the substrate. In some embodiments, the material used to fill the substrate can be a dielectric material or a semiconductor material. In operation 1190, the sacrificial silicon nitride layer is selectively removed. In operation 1192, tungsten is deposited in the locations where the sacrificial silicon nitride was removed.

[0105] Figures 12A-12E Illustrative schematics of various substrates subjected to certain disclosed process embodiments are shown.

[0106] exist Figure 12A 9 , a substrate having oxygen-doped silicon carbide 400, a sacrificial silicon nitride layer 402, polysilicon 100, silicon oxide 101, and oxygen-doped silicon carbide 400 is provided. Figure 12B In the embodiment, a trench is formed and the silicon oxide 101 is recessed. Figure 12C In some embodiments, polysilicon 100 is deposited to fill the recessed space in silicon oxide 101. Figure 12C and 12D The polysilicon 100 is etched back in the operation between Figure 12D In the embodiment, the sacrificial silicon nitride layer 402 is selectively removed, for example, by wet etching. Figure 12E In the embodiment of the present invention, tungsten 440 is deposited into the space previously occupied by the silicon nitride layer. Because of the presence of polysilicon 100 in the structure, tungsten is not deposited on the sidewalls of previously patterned trenches or vias, thus avoiding etching of tungsten during via formation and during silicon oxide recessing.

[0107] In various embodiments, oxygen-doped silicon carbide deposited by PECVD can replace silicon nitride, and silicon nitride can replace tungsten and titanium nitride. Because the materials used can be etched using techniques developed for OPOP and ONON etch processes, high aspect ratio etching of the film stack has lower risk and no risk of metal residue. Because oxygen-doped silicon carbide, silicon nitride, and polysilicon will provide sufficient etch contrast, silicon oxide can be recessed in a similar manner. Finally, the silicon nitride can be removed and backfilled with titanium nitride and tungsten, and tungsten roughness will not be a concern because the surface will be limited by the dielectric sidewalls.

[0108] Another approach is to replace tungsten and titanium nitride with doped polysilicon. In some cases, this will simplify the etching process by reducing the number of materials to be etched with a high aspect ratio from 5 to 3. However, because doped polysilicon and undoped polysilicon have very different wet etch rates, the doped polysilicon can be removed by wet etching and then backfilled with titanium nitride and tungsten. Exemplary dopants include boron, phosphorus, and arsenic.

[0109] A variety of dopant precursors can be used during the deposition of doped polysilicon to form doped polysilicon. In some embodiments, a suitable dopant source can be elemental arsenic, or arsine (ASH3), or arsenic-doped silicate glass (ASG), or arsenic trioxide (As2O3) and / or arsenic pentoxide (As2O3). 5+ ). In other embodiments, a suitable dopant source may be elemental boron or a boron compound, such as diborane (B2H6), and a suitable dopant precursor may be a boron compound, such as an alkyl borate. For example, trimethyl borate (TMB) (shown below) is a specific alkyl borate that works well as a dopant precursor for forming the dopant source boron trioxide (BO3); however, other dopant precursors may also be suitable for forming various boron-based dopant sources. In addition, dopant sources based on elements other than boron and arsenic, such as gallium or phosphorus-based dopant sources, may also be suitable.

[0110] Trimethyl borate is a suitable dopant precursor. However, according to embodiments, other compounds can also be used as suitable dopant precursors. For example, other suitable boron-based dopant precursors can include: other alkyl borates, such as triethyl borate, triisopropyl borate, and tributyl borate, as well as trimethyl boron, triethyl boron, triphenyl boron, triisopropyl borate, tri-n-pentyl borate, B-tris(bromocycloborazane), tris(pentafluorophenyl) borane, and other similar boron-containing compounds. Additionally, dopant sources based on elements other than boron would also be suitable. Examples include dopant sources based on gallium, phosphorus, arsenic, or other elements suitable for doping semiconductor substrates, such as other group III and V elements. Arsenic-based dopant precursors can include, but are not limited to, alkyl arsines, alkoxy arsines, and amino arsine chemical families, and include, but are not limited to, the following specific compounds: arsine, triethyl arsenate, trimethyl arsine, triethyl arsine, triphenyl arsine, triphenyl arsine oxide, ethylenebis(diphenylarsine), tris(dimethylamino)arsine, and AS(OR)3, where R is -CH3 or -C2H5 or other alkyl groups (including saturated and unsaturated alkyl groups), and other similar arsenic-containing compounds. Phosphorus-based dopant precursors can include, but are not limited to, phosphine (PH3), triethoxyphosphine oxide, trimethyl phosphate, trimethyl phosphite, and other similar phosphorus-containing compounds. The choice of dopant precursor is generally determined by the ease of integration into an existing delivery system, the purity of the film, and the total cost.

[0111] Heavily boron-doped polysilicon can have a relatively high wet etch rate, thus providing an etch contrast relative to other materials on the substrate during patterning. The wet etch rate increases with increasing boron concentration, thereby providing an etch contrast that can be adjusted according to the dopant concentration.

[0112] "Silicon oxide", as referred to herein, includes any and all stoichiometric possibilities including Si x O y where x and y can be integer values as well as non-integer values, and some of the H can be bonded to Si or O. For example, "silicon oxide" includes compounds having the chemical formula SiO n where 1 < n < 2, where n can be an integer or a non-integer value. "Silicon oxide" can include sub-stoichiometric compounds, such as SiO 1.8 . "Silicon oxide" also includes silicon dioxide (SiO2) and silicon monoxide (SiO). "Silicon oxide" also includes natural and synthetic variants, and also includes any and all crystalline and molecular structures, including the tetrahedral coordination of oxygen atoms around a central silicon atom. "Silicon oxide" also includes amorphous silicon oxide and silicates.

[0113] "Silicon nitride", as referred to herein, includes Si x N yAny and all stoichiometric possibilities, including integral and non-integral values of x and y, such as x = 3 and y = 4. For example, "silicon nitride" includes compounds having the chemical formula SiN n where 1 < n < 2, where n can be an integer or a non-integral value. "Silicon nitride" can include sub-stoichiometric compounds, such as SiN 1.8 . "Silicon nitride" also includes Si3N4 and silicon nitrides with some and / or interstitial hydrogen (SiNH), and silicon nitrides with trace and / or interstitial oxygen (SiON). "Silicon nitride" also includes natural and synthetic variants, and also includes any and all lattice, crystalline, and molecular structures, including triangular α-silicon nitride, hexagonal β-silicon nitride, and cubic γ-silicon nitride. "Silicon nitride" also includes amorphous silicon nitride, and can include silicon nitride with trace impurities. Hydrogen will also be present in SiN and can be bonded to Si or N, or both. The hydrogen concentration in silicon nitride can range from about 1% to about 30%.

[0114] Figures 12F-12M Shows yet another exemplary patterning scheme, which is a schematic diagram of a variety of substrates that have undergone certain disclosed process embodiments.

[0115] In Figure 12F , a substrate is provided that has: silicon oxide 1201, doped polysilicon 1210 above and below the silicon oxide 1201; and silicon carbide doped with oxygen 1200; and a sacrificial silicon nitride layer 1202, having an etch stop layer 1230 below the sacrificial silicon nitride layer 1202. In Figure 12F , a trench 1250 is formed. In Figure 12H , the silicon oxide 1201 is recessed at 1240. In Figure 12I , polysilicon 1260 is deposited to fill the space created by the trench 1250 and the recess of the silicon oxide 1201. In Figure 12J , the doped polysilicon 1260 can be re-etched as shown. In some embodiments, the polysilicon 1260 can become a thin film transistor. In Figure 12K , a gate 1270 is deposited into the trench. In Figure 12L , the sacrificial silicon nitride layer 1202 is selectively removed, for example by wet etching, to create a feature 1225. In Figure 12M , tungsten 1240 is deposited into the feature 1225 at the position previously occupied by the silicon nitride layer. Due to the presence of polysilicon 1210 in the structure, this avoids etching tungsten during via formation and during the recess of the silicon oxide because tungsten is not deposited on the sidewalls of the previously patterned trenches or vias. Although specific materials are described with respect to Figures 12F-12M , it should be understood that Figure 12F The multilayer stack in the embodiment may include other dielectric materials having an etch contrast different from that shown and described herein. Certain disclosed embodiments may be used to form devices other than transistors, such as capacitors or other devices such as in Figure 12J Other memory cells inside the recessed area of ​​the depicted scheme. Device

[0116] Figure 13 A schematic diagram of an embodiment of an atomic layer deposition (ALD) and / or chemical vapor deposition (CVD) process station 1300 having a process chamber body 1302 for maintaining a low pressure environment is depicted. Multiple process stations 1300 may be included in a common low pressure process tool environment. For example, Figure 14 and 15 An exemplary embodiment of a multi-station processing tool is depicted. In some embodiments, one or more hardware parameters of the ALD processing station 1300, including those discussed in detail below, can be programmatically adjusted by one or more computer controllers 1350.

[0117] The processing station 1300 is in fluid communication with a reactant delivery system 1301a for delivering process gases to a distribution showerhead 1306. The reactant delivery system 1301a includes a mixing vessel 1304 for mixing and / or conditioning process gases, such as silicon precursor gases or second reactant gases (e.g., oxygen-containing reactants, carbon-containing reactants, etc.), for delivery to the showerhead 1306. One or more mixing vessel inlet valves 1320 can control the introduction of process gases into the mixing vessel 1304. Plasma can also be delivered to the showerhead 1306 or can be generated in the processing station 1300. The reactant delivery system 1301a can be configured to deliver process gases to a substrate provided in the processing station 1300.

[0118] As an example, Figure 13The embodiment includes a vaporization point 1303 for vaporizing liquid reactants to be supplied to the mixing container 1304. In some embodiments, the vaporization point 1303 can be a heated vaporizer. The saturated reactant vapor produced by such a vaporizer may condense in the downstream delivery pipeline. Incompatible gases exposed to condensed reactants may produce small particles. These small particles may clog the pipeline, hinder valve operation, contaminate the substrate, etc. Some methods to solve these problems involve cleaning and / or emptying the delivery pipeline to remove residual reactants. However, cleaning the delivery pipeline may increase the processing station cycle time and reduce the production capacity of the processing station. Therefore, in some embodiments, the delivery pipeline downstream of the vaporization point 1303 can be heated and tracked. In some examples, the mixing container 1304 can also be heated and tracked. In one non-limiting example, the pipeline downstream of the vaporization point 1303 has an increasing temperature distribution extending from approximately 100°C to approximately 150°C at the mixing container 1304.

[0119] In some embodiments, liquid precursors or liquid reactants can be vaporized at the liquid injector. For example, the liquid injector can inject a pulse of liquid reactant into the carrier gas flow upstream of the mixing container 1304. In one embodiment, the liquid injector can evaporate the reactant by flashing the liquid from a higher pressure to a lower pressure. In another example, the liquid injector can atomize the liquid into dispersed droplets, which are then evaporated in a heated delivery pipe. Smaller droplets may evaporate faster than larger droplets, thereby reducing the delay between liquid injection and complete vaporization. Faster evaporation can reduce the length of the pipeline downstream of the vaporization point 1303. In one case, the liquid injector can be directly mounted to the mixing container 1304. In another case, the liquid injector can be directly mounted on the spray head 1306.

[0120] In some embodiments, a liquid flow controller (LFC) upstream of the vaporization point 1303 may be provided to control the mass flow of the liquid to be vaporized and delivered to the processing station 1300. For example, the LFC may include a thermal mass flow meter (MFM) located downstream of the LFC. The plunger valve of the LFC may then be adjusted in response to a feedback control signal provided by a proportional-integral-differential (PID) controller in electrical communication with the MFM. However, using feedback control may require one second or longer to stabilize the liquid flow rate. This may extend the dosing time of the liquid reactant. Therefore, in some embodiments, the LFC can dynamically switch between a feedback control mode and a direct control mode. In some embodiments, this can be performed by disabling the sensing tubes of the LFC and PID controller.

[0121] The showerhead 1306 distributes the process gas toward the substrate 1319. Figure 13In the embodiment shown, substrate 1319 is positioned below showerhead 1306 and is shown resting on pedestal 1308. Showerhead 1306 can have any suitable shape and can have any suitable number and arrangement of ports for distributing process gases to substrate 1319.

[0122] In some embodiments, the pedestal 1308 can be raised or lowered to expose the substrate 1319 to the volume between the substrate 1319 and the showerhead 1306. It will be appreciated that in some embodiments, the pedestal height can be programmatically adjusted by a suitable computer controller 1350.

[0123] In another embodiment, in which a plasma is ignited, adjusting the height of the pedestal 1308 can enable the plasma density to be varied during a plasma activation cycle in a process. At the end of a process phase, the pedestal 1308 can be lowered in another substrate transfer phase to enable the substrate 1319 to be removed from the pedestal 1308.

[0124] In some embodiments, the temperature of the susceptor 1308 can be controlled via a heater 1310. In some embodiments, the susceptor 1308 can be heated to a temperature of at least about 250° C., or in some embodiments, less than about 300° C., such as about 250° C., during deposition of the silicon nitride film as described in the disclosed embodiments. In some embodiments, the susceptor is set to a temperature between about 50° C. and about 300° C., such as between about 200° C. and about 275° C. In some embodiments, the susceptor is set to a temperature between about 50° C. and about 300° C. In some embodiments, the susceptor is set to a temperature between about 200° C. and about 275° C.

[0125] Additionally, in some embodiments, pressure control of the processing station 1300 may be provided by a butterfly valve 1312. Figure 13 In the embodiment shown in FIG, butterfly valve 1312 regulates the vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, the pressure control of process station 1300 can also be adjusted by varying the flow rate of one or more gases introduced to process station 1300.

[0126] In some embodiments, the position of the showerhead 1306 can be adjusted relative to the pedestal 1308 to change the volume between the substrate 1319 and the showerhead 1306. Furthermore, it should be understood that the vertical position of the pedestal 1308 and / or showerhead 1306 can be changed by any suitable mechanism within the scope of the present disclosure. In some embodiments, the pedestal 1308 can include a rotation axis for rotating the orientation of the substrate 1319. It should be understood that in some embodiments, one or more of these example adjustments can be programmatically performed by one or more suitable computer controllers 1350.

[0127] In some embodiments in which a plasma may be used as described above, the showerhead 1306 and the base 1308 are electrically connected to a radio frequency (RF) power source 1314 and a matching network 1316 for powering the plasma. In some embodiments, the plasma energy can be controlled by controlling one or more of the process station pressure, gas concentration, RF source power, RF source frequency, and plasma power pulse timing. For example, the RF power source 1314 and the matching network 1316 can be operated at any suitable power to form a plasma having a specific composition of free radical species. Examples of suitable powers are included above. Similarly, the RF power source 1314 can provide RF power of any suitable frequency. In some embodiments, the RF power source 1314 can be configured to control high-frequency and low-frequency RF power sources independently of each other. Exemplary low-frequency RF frequencies can include, but are not limited to, frequencies between 0 kHz and 500 kHz. Exemplary high-frequency RF frequencies can include, but are not limited to, frequencies between 1.8 MHz and 2.45 GHz, or frequencies greater than approximately 13.56 MHz, or frequencies greater than 27 MHz, or frequencies greater than 180 MHz, or frequencies greater than 60 MHz. It will be appreciated that any suitable parameter may be modulated discretely or continuously to provide plasma energy for surface reactions.

[0128] In some embodiments, the plasma can be monitored in situ by one or more plasma monitors. In one case, the plasma power can be monitored by one or more voltage and current sensors (e.g., VI probes). In another case, the plasma density and / or process gas concentration can be measured by one or more optical emission spectroscopy sensors (OES). In some embodiments, one or more plasma parameters can be programmed to adjust based on the measurement results from such in situ plasma monitors. For example, an OES sensor can be used in a feedback loop to provide programmed control of the plasma power. It should be understood that in some embodiments, other monitors can be used to monitor plasma and other processing characteristics. Such monitors can include, but are not limited to, infrared (IR) monitors, sound monitors, and pressure sensors.

[0129] In some embodiments, instructions for controller 1350 can be provided via input / output control (IOC) sequencing instructions. In one example, instructions for setting the conditions of the treatment phase can be included in the corresponding recipe phase of the process recipe. In some cases, the process recipe phases may be arranged in sequence so that all instructions of the treatment phase are executed simultaneously with the treatment phase. In some embodiments, instructions for setting one or more reactor parameters can be included in the recipe phase. For example, the first recipe phase may include instructions for setting the flow rate of an inert gas and / or a reactant gas (e.g., a first precursor such as a silicon precursor), instructions for setting the flow rate of a carrier gas (e.g., argon), and a time delay instruction for the first recipe phase. The subsequent second recipe phase may include instructions for adjusting or stopping the flow rate of an inert gas and / or a reactant gas, instructions for adjusting the flow rate of a carrier gas or a purge gas, and a time delay instruction for the second recipe phase. The third recipe phase may include instructions for adjusting the flow rate of a second reactant gas, instructions for adjusting the flow rate of a carrier gas or a purge gas, and a time delay instruction for the third recipe phase. The subsequent fourth recipe stage may include instructions for adjusting or stopping the flow rates of the inert gas and / or the reactant gas, as well as instructions for adjusting the flow rates of the carrier gas or the purge gas, and time delay instructions for the fourth recipe stage. It should be understood that these recipe stages may be further subdivided and / or repeated in any suitable manner within the scope of the embodiments of the present disclosure.

[0130] As described above, one or more processing stations may be included in a multi-station processing tool. Figure 14 A schematic diagram of an embodiment of a multi-station processing tool 1400 having an inbound load lock 1402 and an outbound load lock 1404 is shown, either or both of which may include a remote plasma source. A robot 1406 at atmospheric pressure is configured to move wafers from a cassette loaded by a wafer boat 1408 into the inbound load lock 1402 via an atmospheric port 1410. The wafer is placed on a pedestal 1412 in the inbound load lock 1402 by the robot 1406, the atmospheric port 1410 is closed, and the load lock 1402 is evacuated. Where the inbound load lock 1402 includes a remote plasma source, the wafer may be exposed to a remote plasma treatment in the inbound load lock 1402 before being introduced into a processing chamber 1414. In addition, the wafer may also be heated in the inbound load lock 1402, for example, to remove moisture and adsorbed gases. Next, the chamber transfer port 1416 of the process chamber 1414 is opened and another robot (not shown) places the wafer into the reactor on a susceptor at the first station shown in the reactor for processing. Figure 14The embodiment depicted in FIG includes a load lock, but it should be understood that in some embodiments, wafers may be allowed to enter the processing station directly.

[0131] The depicted processing chamber 1414 includes four processing stations, Figure 14 The illustrated embodiment is numbered 1 through 4. Each station has a heated pedestal (shown as 1418 for station 1) and a gas line inlet. It should be understood that in some embodiments, each processing station can have a different or multiple purposes. For example, in some embodiments, a processing station can switch between ALD and plasma-enhanced ALD process modes. Additionally or alternatively, in some embodiments, the processing chamber 1414 can include one or more matched pairs of ALD processing stations and plasma-enhanced ALD processing stations. Although the depicted processing chamber 1414 includes four stations, it should be understood that a processing chamber according to the present disclosure can have any suitable number of stations. For example, in some embodiments, a processing chamber can have five or more stations, while in other embodiments, a processing chamber can have three or fewer stations.

[0132] Figure 14 One embodiment of a wafer handling system 1490 for transporting wafers within process chamber 1414 is depicted. In some embodiments, wafer handling system 1490 can transport wafers between various processing stations and / or between a processing station and a load lock. It should be understood that any suitable wafer handling system can be used. Non-limiting examples include wafer conveyors and wafer handling robots.

[0133] It should be understood that in some embodiments, a low pressure transfer chamber may be included in a multi-station processing tool to facilitate transfer between multiple processing chambers. Figure 14 Another embodiment of a multi-station processing tool 1500 is schematically shown. Figure 14 In the illustrated embodiment, a multi-station processing tool 1400 includes a plurality of processing chambers 1414, each of which includes a plurality of processing stations (numbered 1 through 4). The processing chambers 1414 interface with a low-pressure transport chamber 1404, which includes a robot 1406 configured to transport substrates between the processing chambers 1414 and a load lock 1419. An atmospheric substrate transfer module 1410, which includes an atmospheric robot 1412, is configured to facilitate transfer of substrates between the load lock 1419 and the wafer cassette 1408.

[0134] Figure 14Also depicted is an embodiment of a system controller 1450 for controlling processing conditions and hardware states of the processing tool 1400. The system controller 1450 may include one or more memory devices 1456, one or more mass storage devices 1454, and one or more processors 1452. The processor 1452 may include a CPU or computer, analog and / or digital input / output connections, a stepper motor control board, etc.

[0135] In some embodiments, the system controller 1450 controls all activities of the processing tool 1400. The system controller 1450 executes system control software 1458, which is stored in the mass storage device 1454, loaded into the memory device 1456, and executed on the processor 1452. Alternatively, the control logic can be hard-coded in the controller 1450. Application-specific integrated circuits, programmable logic devices (e.g., field-programmable gate arrays or FPGAs), etc. can be used for these purposes. In the following discussion, wherever "software" or "code" is used, functionally equivalent hard-coded logic can be used. The system control software 1458 can include instructions for controlling timing, gas mixtures, gas flow rates, chamber and / or station pressures, chamber and / or station temperatures, wafer temperature, target power levels, RF power levels, substrate pedestal, chuck and / or susceptor positions, and other parameters of the specific process performed by the processing tool 1400. The system control software 1458 can be configured in any suitable manner. For example, various process tool component subroutines or control objects may be written to control the operation of the process tool components for performing various process tool processes.The system control software 1458 may be coded in any suitable computer readable programming language.

[0136] In some embodiments, the system control software 1458 may include input / output control (IOC) sequenced instructions for controlling the various parameters described above. In some embodiments, other computer software and / or programs stored on the mass storage device 1454 and / or the memory device 1456 associated with the system controller 1450 may be employed. Examples of programs or program segments used for this purpose include substrate positioning programs, process gas control programs, pressure control programs, heater control programs, and plasma control programs.

[0137] The substrate positioning program may include program code for processing tool components to load a substrate onto the pedestal 1418 and control the spacing between the substrate and other parts of the processing tool 1400 .

[0138] The process gas control program may include code for controlling gas composition (e.g., silicon precursor gas, carbon-containing gas, carrier gas, and sweep gas as described herein) and flow rates, and optionally for flowing gases into one or more process stations to stabilize the pressure of the process station prior to deposition. The pressure control program may include code for controlling the pressure in the process station by adjusting, for example, a throttle valve in the exhaust system of the process station, gas flow into the process station, etc.

[0139] The heater control program may include code for controlling the flow of current to a heating unit for heating the substrate. Alternatively, the heater control program may control the delivery of a heat transfer gas (eg, helium) to the substrate.

[0140] According to embodiments herein, a plasma control program may include code for setting RF power levels applied to process electrodes in one or more process stations.

[0141] According to embodiments herein, a pressure control program may include code for maintaining pressure in a reaction chamber.

[0142] In some embodiments, there may be a user interface associated with the system controller 1450. The user interface may include a display screen, graphical software displays of equipment and / or process conditions, and user input devices such as a pointing device, keyboard, touch screen, microphone, etc.

[0143] In some embodiments, the parameters adjusted by the system controller 1450 may relate to process conditions. Non-limiting examples include process gas composition and flow, temperature, pressure, plasma conditions (such as RF bias power level), etc. These parameters may be provided to the user in the form of a recipe that can be entered using a user interface.

[0144] Signals for monitoring the process can be provided through analog and / or digital input connections from various process tool sensors of the system controller 1450. Signals for controlling the process can be output on analog and digital output connections of the process tool 1400. Non-limiting examples of process tool sensors that can be monitored include mass flow controllers, pressure sensors (such as manometers), thermocouples, etc. Appropriately programmed feedback and control algorithms can be used with the data from these sensors to maintain process conditions.

[0145] The system controller 1450 may provide program instructions for implementing the above-described deposition process. The program instructions may control various process parameters, such as DC power level, RF bias power level, pressure, temperature, etc. According to various embodiments described herein, the instructions may control the parameters to operate the in-situ deposition of the film stack.

[0146] The system controller 1450 will typically include one or more memory devices and one or more processors configured to execute instructions so that the device will perform methods according to the disclosed embodiments. A machine-readable medium containing instructions for controlling processing operations according to the disclosed embodiments can be coupled to the system controller 1450.

[0147] In some implementations, the system controller 1450 is part of a system, which can be part of the examples described above. Such a system can include a semiconductor processing apparatus that includes one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems can be integrated with electronics for controlling their operation before, during, and after processing of semiconductor wafers or substrates. The electronics can be referred to as a "controller" that can control various components or subcomponents of one or more systems. Depending on the processing requirements and / or the type of system, the system controller 1450 can be programmed to control any of the processes disclosed herein, including the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transport in and out of tools and other transport tools and / or load locks connected to or interfaced with a particular system.

[0148] Broadly speaking, the system controller 1450 can be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits can include chips in the form of firmware that stores program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). The program instructions can be instructions delivered to the system controller 1450 or system in the form of various separate settings (or program files) that define operating parameters for performing a particular process on or for a semiconductor wafer. In some embodiments, the operating parameters can be part of a recipe defined by a process engineer to accomplish one or more process steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0149] In some embodiments, the system controller 1450 can be part of or coupled to a computer that is integrated with the system, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the system controller 1450 can be in the "cloud" or in all or part of a wafer fab host system, which can allow remote access to wafer processing. The computer can enable remote access to the system to monitor the current progress of manufacturing operations, review the history of past manufacturing operations, study trends or performance metrics from multiple manufacturing operations, change parameters of the current process, set processing steps to follow the current process, or start a new process. In some examples, a remote computer (e.g., a server) can provide process recipes to the system via a network (which can include a local network or the Internet). The remote computer can include a user interface that enables the input or programming of parameters and / or settings, which are then transmitted from the remote computer to the system. In some examples, the system controller 1450 receives instructions in the form of data that specify parameters for each processing step to be performed during one or more operations. It should be understood that the parameters can be specific to the type of process to be performed and the type of tool that the system controller 1450 is configured to interface with or control. Thus, as described above, the system controller 1450 can be distributed, for example, by including one or more discrete system controllers 1450 networked together and working toward a common purpose, such as the processes and controls described herein. An example of a distributed controller for such a purpose would be one or more integrated circuits on a chamber communicating with one or more integrated circuits located remotely (e.g., at a platform level or as part of a remote computer), which combine to control the process on the chamber.

[0150] Example systems may include, but are not limited to, plasma etch chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etch chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, ALD chambers or modules, atomic layer etch (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing system that may be associated with or used in the manufacture and / or preparation of semiconductor wafers.

[0151] As described above, depending on one or more processing steps to be performed by the tool, the controller can communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, a host computer, another controller, or tools used in the material transport of wafer containers to and from tool locations and / or load ports in a semiconductor manufacturing facility.

[0152] Figure 15 A schematic diagram of an embodiment of a multi-station processing tool 1500 is shown having an inbound load lock 1502 and an outbound load lock 1504, either or both of which may include a remote plasma source. An example of a commercial embodiment of a suitable tool is the Strata tool available from Lam Research Corp. (Fremont, CA).

[0153] The depicted processing tool 1500 includes four processing chambers 1510a, 1510b, 1510c, and 1510d. Each processing chamber includes four processing stations, which are labeled 1, 2, 3, and 4 in processing chamber 1510a, respectively. Each station has a heated susceptor (shown as processing station 1 in processing chamber 1510a) and a gas line inlet. It should be understood that in some embodiments, each processing station can have different or multiple uses. For example, in some embodiments, a processing station can switch between PECVD, ALD, and plasma-enhanced ALD process modes. Additionally or alternatively, in some embodiments, processing chamber 1510a can include one or more pairs of matched PECVD, ALD, and plasma-enhanced ALD processing stations. Although the depicted processing chamber 1510b includes four stations 1, 2, 3, and 4, it should be understood that processing chambers according to the present disclosure can have any suitable number of stations. Each station in each processing chamber can be used to process four different materials, such that one material is deposited in each station. In some embodiments, each station can be used to deposit four different materials. In some embodiments, a single-station processing chamber can be used. In some embodiments, a four-station processing chamber can be used.

[0154] Additionally, the processing tool 1500 is shown with four processing chambers, but it should be understood that the processing tool can include more or fewer than four processing chambers, each having one or more processing stations. For example, in some embodiments, a processing chamber can have five or more stations, while in other embodiments, a processing chamber can have three or fewer stations.

[0155] Figure 15 A wafer handling system 1590 is included for transferring wafers between the processing chambers 1510a, 1510b, 1510c, and 1510d and within the processing tool 1500.

[0156] In some embodiments, wafer handling system 1590 can transfer wafers between various processing stations and / or between a processing station and a load lock. It should be understood that any suitable wafer handling system can be used. Non-limiting examples include wafer conveyors and wafer handling robots.

[0157] Figure 15Also depicted is an embodiment of a system controller 1550 for controlling processing conditions and hardware states of the processing tool 1500. The system controller 1550 may include one or more memory devices 1556, one or more mass storage devices 1554, and one or more processors 1552. The processor 1552 may include a CPU or computer, analog and / or digital input / output connections, a stepper motor control board, etc.

[0158] In some embodiments, the system controller 1550 controls all activities of the processing tool 1500. The system controller 1550 executes system control software 1558, which is stored in the mass storage device 1554, loaded into the memory device 1556, and executed on the processor 1552. Alternatively, the control logic can be hard-coded in the controller 1550. Application-specific integrated circuits, programmable logic devices (e.g., field-programmable gate arrays or FPGAs), etc. can be used for these purposes. In the following discussion, wherever "software" or "code" is used, functionally equivalent hard-coded logic can be used. The system control software 1558 can include instructions for controlling timing, gas mixtures, gas flow rates, chamber and / or station pressures, chamber and / or station temperatures, wafer temperature, target power levels, RF power levels, substrate pedestal, chuck and / or susceptor positions, and other parameters of the specific process performed by the processing tool 1500. The system control software 1558 can be configured in any suitable manner. For example, various process tool component subroutines or control objects may be written to control the operation of the process tool components for performing various process tool processes.The system control software 1558 may be coded in any suitable computer readable programming language.

[0159] Controller 1550 may have any of the features described above with reference to controller 1450 .

[0160] Suitable apparatus for performing the methods disclosed herein are further discussed and described in U.S. patent application Ser. No. 13 / 084,399, filed on April 11, 2011, entitled “PLASMA ACTIVATED CONFORMAL FILM DEPOSITION” (now U.S. Patent No. 8,728,956), and U.S. patent application Ser. No. 13 / 084,305, filed on April 11, 2011, entitled “SILICON NITRIDE FILMS AND METHODS,” the entire contents of each of which are incorporated herein.

[0161] The apparatus / processes described above may be used in conjunction with photolithographic patterning tools or processes, for example, for preparing or manufacturing semiconductor devices, displays, LEDs, photovoltaic panels, and the like. Typically, although not necessarily, such tools / processes will be performed or used in a common manufacturing facility. Photolithographic patterning of films generally includes some or all of the following operations, each of which is performed using a number of possible tools: (1) coating a workpiece (i.e., substrate) with a photoresist using a spin coating or spray coating tool; (2) curing the photoresist using a hot plate or oven or a UV curing tool; (3) exposing the photoresist to visible light or UV light or X-ray light using a tool such as a wafer stepper; (4) developing the resist to selectively remove the resist, thereby patterning it using a tool such as a wet bench; (5) transferring the resist pattern to an underlying film or workpiece using a dry etching tool or a plasma assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper. Experimental

[0162] Experiments were conducted to etch high-aspect ratio trenches in a multilayer stack comprising a set of metal-free layers between two silicon oxide layers, with an ashable hard mask layer above the top silicon oxide layer. The set of metal-free layers included silicon-containing layers. The metal-free layers did not include any tungsten. The substrate contained 4-12 sets of metal-free layers. High-aspect ratio features were etched, and the resulting features exhibited no line collapse and smooth profiles.

[0163] A second experiment was conducted to concave the sidewalls of a silicon oxide material in a patterned multilayer stack having multiple groups of metal-free layers. Each group of metal-free layers includes at least one layer of silicon oxide. Because the multilayer stack is patterned, the pillars of the multilayer stack are etched simultaneously so that the sidewalls of the silicon oxide layers of all multilayer pillars are etched simultaneously. The space between the pillars is a negative feature with an aspect ratio between about 25:1 and about 35:1. An etch selectivity of at least 50:1 is achieved for the silicon oxide relative to other silicon-containing metal-free layers on the substrate. The etching is performed using a dilute HF of 100:1. A high isotropic etch selectivity is achieved for the silicon oxide material relative to silicon nitride, polysilicon, and silicon oxycarbide materials. in conclusion

[0164] The ranges described herein are inclusive. Although the foregoing embodiments have been described in considerable detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be implemented within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and devices of the present embodiments. Therefore, the present embodiments are to be considered illustrative rather than restrictive, and the embodiments are not to be limited to the details given herein.

Claims

1. A method comprising: providing a semiconductor substrate; depositing a metal-free multilayer stack having at least three different materials, at least one of the three different materials being a sacrificial layer; etching trenches or vias in the metal-free multilayer stack having the at least three different materials; After etching the trench or via, selectively etching the sacrificial layer relative to other materials of the metal-free multilayer stack to form at least one space between layers of the metal-free multilayer stack; and Metal is deposited in the at least one space to form a metal-containing multilayer stack having trenches or vias etched therein. 2 . The method of claim 1 , wherein the metal-free multilayer stack comprises three different materials. The method of claim 1 , wherein the metal-free multilayer stack comprises four different materials.

4. The method of claim 1 , further comprising recessing a dielectric material in sidewalls of the trench or via in the metal-free multilayer stack after etching the trench or via and before selectively etching the sacrificial layer. The method of claim 1 , wherein the sacrificial layer is selected from the group consisting of polysilicon and silicon nitride.

6. The method of claim 1, wherein the at least three different materials comprise materials selected from the group consisting of silicon oxide, undoped polysilicon, doped polysilicon, silicon nitride, oxygen-doped silicon carbide, and nitrogen-doped silicon carbide.

7. The method of claim 1, wherein the layers of the metal-free multilayer stack are deposited by a technique selected from the group consisting of atomic layer deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, and physical vapor deposition.

8. The method of claim 1, wherein the layers of the metal-free multilayer stack are deposited in different chambers of a single tool.

9. The method of claim 1, wherein the layers of the metal-free multilayer stack are deposited without breaking vacuum.

10. The method of claim 1, comprising: Recessing one of the at least three different materials after etching the trench or via to form a recessed region of the via; Depositing a dielectric material or a semiconductor material into the trench or via: etching back the dielectric material or semiconductor material in the trench or via to form smooth sidewalls, thereby leaving the dielectric material in the recessed area; and Gate material is deposited into the trench or via before selectively etching the sacrificial silicon nitride.

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