A low power clock delay method, system

Abstract

The application relates to a low-power-consumption clock delay method and system in the technical field of integrated circuits, which comprises the following steps: based on a counting clock signal, the counting clock signal is phase-aligned with a clock signal to be delayed to generate a first phase clock alignment signal and a second phase clock alignment signal; the rising edge information and the falling edge information of the first phase clock alignment signal are extracted to obtain a pulse signal; the clock rising edge information and the clock falling edge information are split to obtain a first pulse filtering signal and a second pulse filtering signal; the first pulse filtering signal and the second pulse filtering signal are sequentially subjected to coarse delay, and after the coarse delay, signal synthesis processing is carried out to obtain a coarse delay clock signal; and based on a digital time converter, the coarse delay clock signal is subjected to fine delay to obtain a fine delay clock signal, thereby solving the problem that the existing delay technology cannot simultaneously realize high delay precision and a large dynamic range under low power consumption.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a low-power clock delay method and system. BACKGROUND

[0002] With the continuous development of communication technology, the market has higher and higher requirements for clocks. In the fields of communication, finance, scientific research, etc., high-resolution time synchronization technology is the cornerstone of the normal operation of the system, and high-resolution, low-power, large dynamic range clock delay technology is the basis for supporting time synchronization technology.

[0003] However, since the delay circuit used in the existing clock delay is composed of multiple delay units, in order to achieve high delay precision, it means that the delay adjustment step of the delay unit needs to be short, and then more delay units are used to achieve it, but due to the requirements of chip layout area and power consumption, the number of delay units is limited, therefore, the delay circuit used in the existing clock delay is difficult to achieve a large dynamic range under the premise of high delay precision; similarly, when the clock delay technology meets the large dynamic range, it means that a longer time delay is needed, and the time delay also depends on the delay unit, therefore, due to the limitation of chip layout area and power consumption, the number of delay units is limited, and the delay time of a single delay unit needs to be increased to achieve a large delay range, which reduces the delay resolution.

[0004] Therefore, based on the above, the existing delay technology needs to lengthen the delay link to simultaneously achieve high delay precision and large dynamic range, and lengthening the delay link leads to large power consumption and chip area. SUMMARY

[0005] The present application provides a low-power clock delay method and system to solve the problem that the existing delay technology cannot simultaneously achieve high delay precision and large dynamic range under low power consumption.

[0006] In order to solve the above technical problems, the present application solves the problems through the following technical solutions:

[0007] A low-power clock delay method, comprising the following steps:

[0008] Aligning the phase of the count clock signal and the to-be-delayed clock signal based on the count clock signal to generate a first phase clock alignment signal and a second phase clock alignment signal;

[0009] Extracting the rising edge information and falling edge information of the first phase clock alignment signal to obtain a pulse signal;

[0010] Splitting clock rising edge information and clock falling edge information of the first phase clock alignment signal, the second phase clock alignment signal and the pulse signal based on the first phase clock alignment signal, the second phase clock alignment signal and the pulse signal, to obtain a first pulse filter signal and a second pulse filter signal;

[0011] Coarsely delaying the first pulse filter signal and the second pulse filter signal in sequence, and synthesizing the coarsely delayed first pulse filter signal and the coarsely delayed second pulse filter signal to obtain a coarsely delayed clock signal;

[0012] Fine delaying the coarsely delayed clock signal based on a digital time converter to obtain a fine delayed clock signal.

[0013] Optionally, coarsely delaying the first pulse filter signal includes the following steps:

[0014] Setting a delay configuration code, and resetting and starting counting of a counting clock signal each time the first pulse filter signal sends a pulse filter signal;

[0015] The counting clock signal stops counting and outputs a set signal corresponding to the first pulse filter signal each time the counting value of the counting clock signal reaches the delay configuration code.

[0016] Optionally, coarsely delaying the second pulse filter signal includes the following steps:

[0017] Resetting and starting counting of a counting clock signal each time the second pulse filter signal sends a pulse filter signal;

[0018] The counting clock signal stops counting and outputs a reset signal corresponding to the second pulse filter signal each time the counting value of the counting clock signal reaches the delay configuration code.

[0019] Optionally, fine delaying the coarsely delayed clock signal based on a digital time converter includes the following steps:

[0020] Setting a control word of the digital time converter, and delaying the coarsely delayed clock signal based on the control word to obtain the fine delayed clock signal.

[0021] Optionally, phase aligning the counting clock signal and a clock signal to be delayed based on the counting clock signal includes the following steps:

[0022] Setting a counting clock signal, and resampling the clock signal to be delayed through the counting clock signal to obtain a first phase clock alignment signal and a second phase clock alignment signal;

[0023] The first phase clock alignment signal and the second phase clock alignment signal are inverse signals of each other, and the first phase clock alignment signal and the to-be-delayed clock signal are same-direction signals.

[0024] Optionally, rising edge information and falling edge information of the first phase clock alignment signal are extracted to obtain a pulse signal, including the following steps:

[0025] The count clock signal is reversely processed to obtain a count clock reverse signal;

[0026] The first phase clock alignment signal is resampled through the count clock reverse signal to generate a first phase clock resampled signal that is different from the first phase clock alignment signal by half a clock period of the count clock signal;

[0027] Based on the first phase clock alignment signal and the first phase clock resampled signal, a pulse signal carrying clock edge information is generated.

[0028] Optionally, the clock rising edge information and the clock falling edge information are split, including the following steps:

[0029] The first phase clock alignment signal is used to filter out falling edge pulse information in the pulse signal to obtain a first pulse filtered signal;

[0030] The second phase clock alignment signal is used to filter out rising edge pulse information in the pulse signal to obtain a second pulse filtered signal.

[0031] A low-power clock delay system, which performs the low-power clock delay method according to any one of the preceding embodiments, includes a clock synchronization circuit, a clock edge generation circuit, a clock edge separation circuit, a pulse delay circuit, an RS trigger circuit, and a digital time conversion circuit.

[0032] The clock synchronization circuit is configured to perform phase alignment between a count clock signal and a to-be-delayed clock signal based on the count clock signal to generate a first phase clock alignment signal and a second phase clock alignment signal.

[0033] The clock edge generation circuit is configured to extract rising edge information and falling edge information of the first phase clock alignment signal to obtain a pulse signal.

[0034] The clock edge separation circuit is configured to split clock rising edge information and clock falling edge information based on the first phase clock alignment signal, the second phase clock alignment signal, and the pulse signal to obtain a first pulse filtered signal and a second pulse filtered signal.

[0035] The pulse delay circuit is configured to sequentially perform coarse delay on the first pulse filtered signal and the second pulse filtered signal.

[0036] The RS trigger circuit is used to synthesize the first pulse filtered signal and the second pulse filtered signal after coarse delay to obtain a coarse delay clock signal.

[0037] The digital time conversion circuit is used to perform a fine delay on the coarse delay clock signal based on the digital time converter to obtain a fine delay clock signal.

[0038] Optionally, the pulse delay circuit includes a first pulse delay unit and a second pulse delay unit;

[0039] The first pulse delay unit receives the first pulse filtering signal, the counting clock signal, and the set delay configuration code sent by the clock edge separation circuit, and outputs a set signal;

[0040] The second pulse delay unit receives the second pulse filtering signal, the counting clock signal, and the set delay configuration code sent by the clock edge separation circuit, and outputs a reset signal.

[0041] Optionally, the clock edge generation circuit includes a D flip-flop and an XOR logic gate;

[0042] The D flip-flop receives the count clock inversion signal obtained by inverting the count clock signal and the first phase clock alignment signal sent by the clock synchronization circuit, and outputs the first phase clock resampling signal.

[0043] The XOR logic gate receives the first phase clock alignment signal and the first phase clock resampling signal, and outputs a pulse signal.

[0044] Compared with the prior art, the technical solution provided by this invention has the following advantages:

[0045] This application sets a counting clock signal and utilizes its counting function to perform coarse delay processing on the clock signal to be delayed, achieving a delay in the microsecond or even millisecond range. Simultaneously, based on this coarse delay, a digital time converter performs fine delay processing on the coarse delay clock signal, achieving a delay effect in the picosecond range. Thus, by combining coarse and fine delays, precise control of the delay is achieved. Furthermore, since this invention only requires configuring a counting clock signal and a digital time converter to achieve high delay accuracy, it eliminates the need to increase the number of delay units to improve accuracy, thereby reducing the power consumption of the delay system. Attached Figure Description

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0047] Figure 1 A low-power clock delay method is provided for the first embodiment;

[0048] Figure 2 A low-power clock delay circuit schematic diagram is provided for the first embodiment and the second embodiment;

[0049] Figure 3 A rough delay working waveform example diagram is provided for the first embodiment. DETAILED DESCRIPTION

[0050] The present application will be further described in detail below in combination with the embodiments. The following embodiments are an explanation of the present application and the present application is not limited to the following embodiments.

[0051] Embodiment one

[0052] As shown in Figure 1 and Figure 2 A low-power clock delay method, comprising the following steps: based on the count clock signal, the count clock signal and the clock signal to be delayed are phase-aligned, and the first phase clock alignment signal and the second phase clock alignment signal are generated to eliminate the phase difference between the count clock signal and the clock signal to be delayed, specifically comprising the following steps: setting the count clock signal, and resampling the clock signal to be delayed by the count clock signal to obtain the first phase clock alignment signal and the second phase clock alignment signal; wherein the first phase clock alignment signal and the second phase clock alignment signal are inverse signals, and the first phase clock alignment signal and the clock signal to be delayed are co-directional signals.

[0053] Since the phase error between the clock signal to be delayed CLK_IN and the count clock signal is uncertain, and the present application counts the rough delay based on the count clock signal CLKP, it is necessary to first align the phase of the clock signal to be delayed CLK_IN by the count clock, that is, it is necessary to first eliminate the uncertain phase difference between the count clock CLKP and the clock signal to be delayed CLK_IN, so as to avoid delay control error.

[0054] Therefore, the application realizes resampling of the clock signal to be delayed CLK IN in the clock synchronization circuit by using the counting clock signal CLK P, generates the first phase clock alignment signal CLK INP D1 and the second phase clock alignment signal CLK INN D1 which are aligned with the clock edge of the counting clock signal CLK P, so as to be processed by the subsequent circuit.

[0055] Specifically, a D flip-flop triggered based on rising edge is arranged in the clock synchronization circuit, and resampling is realized by using the edge triggering function of the D flip-flop (i.e. the output signal of the D flip-flop is updated at the clock rising edge of the triggering clock), as shown in the following figure. Figure 3 As shown in the figure, it can be seen that the clock edge change relationship of the first phase clock alignment signal CLK INP D1 and the second phase clock alignment signal CLK INN D1 is formed after the clock signal to be delayed is resampled by the D flip-flop.

[0056] After the first phase clock alignment signal CLK INP D1 and the second phase clock alignment signal CLK INN D1 are obtained, the rising edge information and the falling edge information of the first phase clock alignment signal are extracted to obtain a pulse signal, which specifically includes the following steps: the counting clock signal is reversely processed to obtain a counting clock reverse signal; the first phase clock alignment signal is resampled by the counting clock reverse signal to generate the first phase clock resampling signal which is different from the first phase clock alignment signal by half of the clock period of the counting clock signal; and the pulse signal carrying the clock edge information is generated based on the first phase clock alignment signal and the first phase clock resampling signal.

[0057] Specifically, since in clock delay, the essence of delaying a clock is to delay the clock edge position, therefore, the clock edge information needs to be extracted, and then the extracted clock edge information is delayed to realize the delay of the clock. Therefore, the application arranges a D flip-flop in the clock edge generation circuit, generates the first phase clock resampling signal CLK INP D2 which is different from the first phase clock alignment signal CLK INP D1 by half of the clock period of the counting clock signal CLK P by using the D flip-flop, and then inputs the first phase clock alignment signal CLK INP D1 and the first phase clock resampling signal CLK INP D2 to the XOR logic gate, so as to generate the pulse signal CLK INP XOR carrying the clock edge information, as shown in the following figure. Figure 3

[0058] ​It should be noted that the pulse width of the obtained pulse signal CLK_INP_XOR is half the period of the counting clock signal CLKP, because in this embodiment, coarse delay is generated based on high-frequency clock counting, and the counter uses rising edge triggering, therefore, the counter reset signals RST_S and RST_R must be released before the first counting clock edge arrives after the rising edge of the reset pulse (i.e., RST_S and RST_R need to be pulled low before the first counting edge arrives after the rising edge of the reset pulse), and therefore the width of the reset pulse signal needs to be less than 1 period of CLKP, based on this, the falling edge of the counting clock signal CLKP is used for processing in this application, so as to realize the pulse signal CLK_INP_XOR with a pulse width of half the period of the counting clock signal CLKP.

[0059] After obtaining the pulse signal CLK_INP_XOR, the clock rising edge information and the clock falling edge information of the pulse signal are split based on the first phase clock alignment signal, the second phase clock alignment signal and the pulse signal, to obtain a first pulse filter signal and a second pulse filter signal. Specifically, the falling edge pulse information in the pulse signal is filtered using the first phase clock alignment signal to obtain the first pulse filter signal; and the rising edge pulse information in the pulse signal is filtered using the second phase clock alignment signal to obtain the second pulse filter signal.

[0060] In this embodiment, the clock rising edge information and the clock falling edge information are split by a clock delay separation circuit. Specifically, two AND logic gates are provided in the clock delay separation circuit, the falling edge pulse information of the pulse signal CLK_INP_XOR is filtered using the first phase clock alignment signal CLK_INP_D1 to obtain the first pulse filter signal RST_S containing only rising edge information, and the rising edge pulse information of the pulse signal CLK_INP_XOR is filtered using the second phase clock alignment signal CLK_INN_D1 to obtain the second pulse filter signal RST_R containing only falling edge information, and their waveforms are shown in RST_S and RST_R, respectively. Figure 3

[0061] Further, the first pulse filter signal and the second pulse filter signal are sequentially subjected to coarse delay, and the first pulse filter signal and the second pulse filter signal after coarse delay are synthesized to obtain a coarse delay clock signal.

[0062] The first pulse filter signal is subjected to coarse delay, including the following steps: setting a delay configuration code, triggering the counting clock signal to reset and start counting every time the first pulse filter signal sends a pulse filter signal; and the counting value of the counting clock signal reaches the delay configuration code once, the counting clock signal stops counting, and outputs the set signal corresponding to the first pulse filter signal.

[0063] ​The second pulse filter signal is coarsely delayed by the following steps: a count clock signal is triggered to reset and start counting each time the second pulse filter signal sends a pulse filter signal; and the count clock signal stops counting and outputs a reset signal corresponding to the second pulse filter signal each time the count value of the count clock signal reaches a delay configuration code.

[0064] The embodiment realizes coarse delay by a pulse delay circuit, and specifically, a pulse delay device in the pulse delay circuit delays the first pulse filter signal RST_S containing rising edge information and the second pulse filter signal RST_R containing falling edge information, so that the output set signal SET is the signal after the first pulse filter signal RST_S is delayed, and the delay size is DELAY_CFG x T CLKP , wherein T CLKP is a CLKP clock period, and DELAY_CFG is a delay configuration code; similarly, the output reset signal RESET is the signal after the second pulse filter signal RST_R is delayed, and the delay size is DELAY_CFG x T CLKP , wherein TCLKP is a CLKP clock period.

[0065] More specifically, the input reset pulse rising edge information is delayed, and the delay size is controlled by the delay configuration code DELAY_CFG, which is realized based on a counter, the counter is reset by the RST signal, the reset pulse width is half of the CLKP period, the counter starts counting from 0 at the reset time, and the counter stops counting when the count value of the counter is equal to the delay configuration code DELAY_CFG; at this time, the pulse delay device outputs a pulse signal, the rising edge of the pulse signal is different from the rising edge of the input first pulse filter signal RST_S / second pulse filter signal RST_R by DELAY_CFG CLKP clock periods, thereby realizing a controllable delay function.

[0066] After the first pulse filter signal RST_S and the second pulse filter signal RST_R are obtained, the input set signal SET and the reset signal RESET are clocked, that is, the set signal SET generates a high level of the output clock, and the reset signal RESET generates a low level of the output clock, thereby combining the two input pulse signals into one output coarse delay clock signal, the rising edge of the coarse delay clock signal is aligned with the rising edge of the set signal SET, and the falling edge of the coarse delay clock signal is aligned with the falling edge of the reset signal RESET.

[0067] Finally, the coarse-delay clock signal is finely delayed based on the digital time converter to obtain the fine-delay clock signal. Specifically, this includes the following steps: setting the control word of the digital time converter, and delaying the coarse-delay clock signal based on the control word to obtain the final fine-delay clock signal with high resolution and a large delay range that needs to be output.

[0068] This results in a precise delay to the input clock signal, and the output clock is the input clock signal after precise delay, with a delay value of DTC_CFG×T. DTC T DTC DTC_CFG is the delay resolution of the digital time converter, and DTC_CFG is the control word of the digital time converter. The delay accuracy of the digital time converter can be within 1ps.

[0069] Based on the above scheme, this application divides the clock delay into two parts: coarse delay and fine delay. The coarse delay is based on counting the counting clock signal CLKP, and its delay control resolution is one cycle of the counting clock signal CLKP, denoted as T. CLKP This value is typically on the order of microseconds or even milliseconds; fine delay is based on a digital time converter, and its delay control resolution is the resolution of one digital time converter, denoted as T. DTC This value is typically in the picosecond range.

[0070] During the delay, use T CLKP For T DTC Normalization was performed, i.e., N T DTC The time length is equal to 1 T. CLKP (T) CLKP =N×T DTC By configuring the coarse delay control code DELAY_CFG and the fine delay control code DTC_CFG, the final achievable delay time is T. delay = DELAY_CFG×T CLKP + DTC_CFG×T DTC .

[0071] The clock frequency of the counting clock signal CLKP is 312.5MHz, i.e., T CLKP Taking 3.2ns as an example, the full range of the digital time converter is 3.2ns. If the digital time converter is selected with 8-bit control, that is, 256 delays, then the time resolution of the digital time converter is 3.2ns ÷ 256 = 12.5ps. To achieve a delay of 10.0000625us, DELAY_CFG can be configured to 3125 and DTC_CFG can be configured to 5 to achieve this delay requirement.

[0072] In traditional delay circuits, to achieve high-resolution delay, the delay step size of the delay unit is small. To achieve a larger delay range, the number of delay units needs to be increased, and each delay unit will generate power consumption. Therefore, the power consumption will increase linearly with the increase of the delay range. However, this application achieves high delay accuracy and a large delay adjustment range by using a combination of coarse and fine delay without increasing power consumption.

[0073] Example 2

[0074] like Figure 2 As shown, a low-power clock delay system includes a clock synchronization circuit, a clock edge generation circuit, a clock edge separation circuit, a pulse delay circuit, an RS trigger circuit, and a digital time conversion circuit.

[0075] A clock synchronization circuit is used to phase-align the counting clock signal with the clock signal to be delayed based on the counting clock signal, generating a first phase clock alignment signal and a second phase clock alignment signal to eliminate the phase difference between the counting clock signal and the clock signal to be delayed.

[0076] The clock edge generation circuit is used to extract the rising edge and falling edge information of the first phase clock alignment signal to obtain a pulse signal;

[0077] A clock edge separation circuit is used to separate clock rising edge information and clock falling edge information based on a first phase clock alignment signal, a second phase clock alignment signal, and a pulse signal to obtain a first pulse filtering signal and a second pulse filtering signal.

[0078] A pulse delay circuit is used to coarsely delay the first pulse filtered signal and the second pulse filtered signal sequentially.

[0079] The RS trigger circuit is used to synthesize the first pulse filtered signal and the second pulse filtered signal after coarse delay to obtain the coarse delay clock signal.

[0080] A digital time conversion circuit is used to finely delay a coarse-delayed clock signal based on a digital time converter, thereby obtaining a fine-delayed clock signal.

[0081] The pulse delay circuit includes a first pulse delay unit and a second pulse delay unit. The first pulse delay unit receives a first pulse filtering signal, a counting clock signal, and a set delay configuration code sent by the clock edge separation circuit, and outputs a set signal. The second pulse delay unit receives a second pulse filtering signal, a counting clock signal, and a set delay configuration code sent by the clock edge separation circuit, and outputs a reset signal.

[0082] The clock edge generating circuit comprises a D flip-flop and an exclusive-OR logic gate; the D flip-flop receives a count clock reverse signal obtained by reverse processing of a count clock signal, a first phase clock alignment signal sent by the clock synchronization circuit, and outputs a first phase clock resampling signal; the exclusive-OR logic gate receives the first phase clock alignment signal and the first phase clock resampling signal, and outputs a pulse signal.

[0083] Since the low-power clock delay system of the embodiment performs the low-power clock delay method as shown in the first embodiment, the description is not repeated here.

[0084] The above description is only the preferred embodiment of the present application, and is not intended to limit the present application in any form or in essence. It should be noted that those skilled in the art can make some improvements and supplements without departing from the method of the present application, and these improvements and supplements should also be considered as the protection scope of the present application. For those skilled in the art, some minor changes, modifications and equivalent changes made by using the disclosed technical content without departing from the spirit and scope of the present application are equivalent embodiments of the present application; at the same time, any equivalent changes, modifications and evolution of the above-mentioned embodiments according to the essential technology of the present application are still within the scope of the technical solutions of the present application.

Claims

1. A low power clock delay method, characterized by, Includes the following steps: The counting clock signal and the clock signal to be delayed are phase-aligned based on the counting clock signal to generate a first phase clock alignment signal and a second phase clock alignment signal. Specifically, this includes: setting a counting clock signal and resampling the clock signal to be delayed using the counting clock signal to obtain the first phase clock alignment signal and the second phase clock alignment signal; wherein the first phase clock alignment signal and the second phase clock alignment signal are opposite signals to each other, and the first phase clock alignment signal and the clock signal to be delayed are in the same direction. Extract the rising edge and falling edge information of the first phase clock alignment signal to obtain a pulse signal; Based on the first phase clock alignment signal, the second phase clock alignment signal, and the pulse signal, the rising edge information and the falling edge information of the clock are decomposed to obtain the first pulse filtering signal and the second pulse filtering signal; The first pulse filtering signal is coarsely delayed, specifically including: setting a delay configuration code; when the first pulse filtering signal sends a pulse filtering signal, triggering a counting clock signal to reset and start counting; when the count value of the counting clock signal reaches one delay configuration code, the counting clock signal stops counting and outputs a set signal corresponding to the first pulse filtering signal; The second pulse filtering signal is coarsely delayed, specifically including: when the second pulse filtering signal sends a pulse filtering signal, the counting clock signal is triggered to reset and start counting; when the count value of the counting clock signal reaches a delay configuration code, the counting clock signal stops counting and outputs a reset signal corresponding to the second pulse filtering signal; The set signal and the reset signal are combined to obtain a coarse delay clock signal, wherein the rising edge of the coarse delay clock signal is aligned with the rising edge of the set signal, and the falling edge of the coarse delay clock signal is aligned with the falling edge of the reset signal. The coarse-delay clock signal is finely delayed by a digital time converter to obtain a fine-delay clock signal.

2. The low power clock delay method of claim 1, wherein, The coarse-delay clock signal is finely delayed based on a digital time converter, including the following steps: Configure the control word of the digital time converter, and delay the coarse delay clock signal based on the control word to obtain the fine delay clock signal.

3. The low power clock delay method of claim 1, wherein, Extracting the rising edge and falling edge information of the first phase clock alignment signal to obtain a pulse signal includes the following steps: The counting clock signal is reversed to obtain the counting clock inverted signal; The first phase clock alignment signal is resampled by the inverted counting clock signal to generate a first phase clock resampled signal that differs from the first phase clock alignment signal by half a clock cycle of the counting clock signal. Based on the first phase clock alignment signal and the first phase clock resampling signal, a pulse signal carrying clock edge information is generated.

4. The low power clock delay method of claim 1, wherein, The process of separating clock rising edge information from clock falling edge information includes the following steps: The falling edge pulse information in the pulse signal is filtered out using the first phase clock alignment signal to obtain the first pulse filtering signal; The rising edge pulse information in the pulse signal is filtered out using the second phase clock alignment signal to obtain a second pulse filtered signal.

5. A low power clocked delay system, characterized by, The low-power clock delay system executes the low-power clock delay method according to any one of claims 1-4, and comprises a clock synchronization circuit, a clock edge generation circuit, a clock edge separation circuit, a pulse delay circuit, an RS trigger circuit, and a digital time conversion circuit. The clock synchronization circuit is configured to align the count clock signal with the clock signal to be delayed based on the count clock signal to generate a first phase clock alignment signal and a second phase clock alignment signal, and specifically comprises: setting the count clock signal, and resampling the clock signal to be delayed by using the count clock signal to obtain the first phase clock alignment signal and the second phase clock alignment signal; wherein the first phase clock alignment signal and the second phase clock alignment signal are inverse signals of each other, and the first phase clock alignment signal and the clock signal to be delayed are same-direction signals. The clock edge generation circuit is configured to extract rising edge information and falling edge information of the first phase clock alignment signal to obtain a pulse signal. The clock edge separation circuit is configured to separate clock rising edge information and clock falling edge information based on the first phase clock alignment signal, the second phase clock alignment signal, and the pulse signal to obtain a first pulse filtered signal and a second pulse filtered signal. The pulse delay circuit is configured to sequentially perform coarse delay on the first pulse filtered signal and the second pulse filtered signal, wherein the first pulse filtered signal is subjected to coarse delay, specifically comprising: setting a delay configuration code, and triggering the count clock signal to reset and start counting when the first pulse filtered signal sends a pulse filtered signal; when the count value of the count clock signal reaches the delay configuration code, the count clock signal stops counting and outputs a set signal corresponding to the first pulse filtered signal. The second pulse filtered signal is subjected to coarse delay, specifically comprising: triggering the count clock signal to reset and start counting when the second pulse filtered signal sends a pulse filtered signal; when the count value of the count clock signal reaches the delay configuration code, the count clock signal stops counting and outputs a reset signal corresponding to the second pulse filtered signal. The RS trigger circuit is configured to perform clock synthesis on the set signal and the reset signal to obtain a coarse delay clock signal, wherein the rising edge of the coarse delay clock signal is aligned with the rising edge of the set signal, and the falling edge of the coarse delay clock signal is aligned with the falling edge of the reset signal. The digital time conversion circuit is configured to perform fine delay on the coarse delay clock signal based on a digital time converter to obtain a fine delay clock signal.

6. A low power clocked delay system as claimed in claim 5, wherein, The pulse delay circuit comprises a first pulse delay and a second pulse delay. The first pulse delay receives the first pulse filtered signal, the count clock signal, and the set delay configuration code sent by the clock edge separation circuit, and outputs the set signal. The second pulse delay device receives a second pulse filtering signal sent by the clock edge separation circuit, a count clock signal and a set delay configuration code, and outputs a reset signal.

7. A low power clocked delay system as claimed in claim 5, wherein, The clock edge generation circuit comprises a D flip-flop and an exclusive OR logic gate. The D flip-flop receives a count clock reverse signal obtained by reverse processing of the count clock signal and a first phase clock alignment signal sent by the clock synchronization circuit, and outputs a first phase clock resampling signal. The exclusive OR logic gate receives the first phase clock alignment signal and the first phase clock resampling signal, and outputs a pulse signal.

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