Manufacturing method of shallow trench isolation structure and shallow trench isolation structure

Abstract

The invention discloses a manufacturing method of a shallow trench isolation structure and the shallow trench isolation structure. The manufacturing method of the shallow trench isolation structure comprises the following steps: forming a hard mask layer with a protection structure on a semiconductor layer; forming a groove which penetrates through the hard mask layer and extends into the semiconductor layer; forming an isolation medium in the groove, wherein the protection structure is adjacent to the isolation medium in the groove; and removing the hard mask layer to form a shallow trench isolation structure, wherein in the process of removing the hard mask layer, the side wall of the isolation medium in the groove is protected by the protection structure, so that a gap is prevented from being formed between the semiconductor layer and the side wall of the isolation medium.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a manufacturing method of a shallow trench isolation structure and the shallow trench isolation structure. Background Art

[0002] Shallow trench isolation (STI) is a key isolation technology in semiconductor manufacturing, used to isolate active devices from each other to prevent interference and crosstalk. With the continuous advancement of integrated circuit manufacturing processes, the requirements for device isolation are becoming increasingly stringent. STI is widely used due to its excellent isolation performance and suitability for submicron and nanometer-scale processes.

[0003] In a conventional semiconductor process, a hard mask layer is formed in a semiconductor layer, and the semiconductor layer is etched through the hard mask layer to form a trench in the semiconductor layer. Subsequently, an isolation dielectric is filled in the trench and the hard mask layer is removed to form an STI structure.

[0004] In the STI structure formed by traditional processes, a gap (divot) is formed between the semiconductor layer and the sidewall of the isolation dielectric. In subsequent processes, conductive material may remain in the gap, causing defects such as edge leakage, reducing the reliability of the semiconductor device. Summary of the Invention

[0005] In view of the above problems, the purpose of the present application is to provide a method for manufacturing a shallow trench isolation structure and a shallow trench isolation structure to solve the problem of gaps formed between the semiconductor layer and the sidewalls of the isolation medium in the prior art.

[0006] According to one aspect of the present invention, a method for manufacturing a shallow trench isolation structure is provided, comprising: forming a hard mask layer having a protective structure on a semiconductor layer; forming a trench penetrating the hard mask layer and extending into the interior of the semiconductor layer; forming an isolation dielectric in the trench, wherein the protective structure is adjacent to the isolation dielectric in the trench; and removing the hard mask layer to form a shallow trench isolation structure; wherein, during the process of removing the hard mask layer, the protective structure protects the sidewalls of the isolation dielectric in the trench to prevent the formation of gaps between the semiconductor layer and the sidewalls of the isolation dielectric.

[0007] Optionally, the method for forming a hard mask layer having a protective structure on a semiconductor layer includes: forming a first hard mask layer on the surface of the semiconductor layer; forming a protective area in the first hard mask layer, and the area other than the protective area in the first hard mask layer is a non-protective area.

[0008] Optionally, the method for forming a hard mask layer having a protective structure on a semiconductor layer includes: forming a second hard mask layer on the first hard mask layer, wherein the thickness of the second hard mask layer on the protective area is greater than the thickness of the second hard mask layer on the non-protective area, and the second hard mask layer on the protective area forms a protective protrusion, and the protective protrusion and the protective area constitute a protective structure; and forming a third hard mask layer on the second hard mask layer, wherein the portion of the third hard mask layer covering the protective protrusion forms a protrusion accordingly.

[0009] Optionally, the method for forming a protective area in the first hard mask layer includes: forming a patterned resist mask layer on the first hard mask layer; performing ion implantation on the first hard mask layer through the opening of the resist mask layer to form a doped area in the first hard mask layer, and the doped area is the protective area.

[0010] Optionally, a second hard mask layer is formed by SACVD process, the thickness of the second hard mask layer above the protection area is greater than the thickness of the second hard mask layer above the non-protection area, and the second hard mask layer above the protection area forms a protection protrusion.

[0011] Optionally, the method for forming an isolation medium in the trench includes: forming an isolation medium that fills the trench and covers the surface of the third hard mask layer; removing the isolation medium covering the surface of the third hard mask layer, and retaining the isolation medium filling the trench; wherein, while removing the isolation medium on the surface of the third hard mask layer, the raised portion of the third hard mask layer is removed together, and the top of the isolation medium is flush with the surface of the remaining hard mask layer.

[0012] Optionally, the first hard mask layer and the second hard mask layer are oxide layers, and the third hard mask layer is a nitride layer.

[0013] Optionally, the third hard mask layer is removed by a wet etching process; the second hard mask layer and the first hard mask layer are removed by wet etching, and during the process of removing the second hard mask layer and the first hard mask layer, the protective structure protects the sidewalls of the isolation medium.

[0014] Optionally, during the process of removing the first hard mask layer, an etching rate of the protection area is lower than an etching rate of the non-protection area.

[0015] According to another aspect of the present invention, a shallow trench isolation structure formed by using any of the above-mentioned shallow trench isolation structure manufacturing methods is provided, wherein the isolation structure includes a trench formed in a semiconductor layer and an isolation medium filled in the trench, wherein there is no gap between the semiconductor layer and the sidewalls of the isolation medium.

[0016] The unexpected technical effects of this application are:

[0017] In this embodiment, a hard mask layer having a protective structure is formed, wherein the protective structure protects the sidewalls of the isolation dielectric in the trench during the process of etching back the isolation dielectric to prevent formation of gaps between the semiconductor layer and the sidewalls of the isolation dielectric.

[0018] Furthermore, the protection structure is formed during the process of forming the hard mask layer and is removed simultaneously during the process of removing the hard mask layer, so no additional steps are required.

[0019] In a preferred embodiment, a patterned resist mask layer is formed on the surface of the first hard mask layer, and ions are implanted into the first hard mask layer through openings in the resist mask layer to form a protective region in the first hard mask layer. During the formation of the second hard mask layer, a protective protrusion is formed in the second hard mask layer above the protective region, and the protective protrusion and the protective region together constitute a protective structure. This embodiment utilizes the effect of the doped first mask layer on the subsequent deposition rate of the second mask layer to form the protective protrusion, avoiding the use of an etching process, thereby preventing damage to the semiconductor layer by the etching process, and also avoiding the introduction of excessive etching auxiliary structural layers.

[0020] In a preferred embodiment, a SACVD deposition process is used to form the second hard mask layer. The SACVD process has a high sensitivity to the doped first hard mask layer, so that in the process of forming the second hard mask layer, the deposition rate of the second hard mask layer above the protective area is higher than the deposition rate of the second hard mask layer above the non-protective area. Therefore, through the same deposition steps, the thickness of the second hard mask layer above the protective area is greater than the thickness of the second hard mask layer above the non-protective area.

[0021] In a preferred embodiment, the third hard mask layer is removed by wet etching using different etching selectivity ratios between the third hard mask layer and the second hard mask layer and between the third hard mask layer and the isolation medium. Compared with dry etching which requires a photolithography process, the process of this embodiment is simpler and at least one photolithography step is saved.

[0022] In a preferred embodiment, wet etching is used to remove the second and first hard mask layers. Because the protective protrusions cover the sidewalls of the isolation dielectric, they are removed before the isolation dielectric. Furthermore, the thickness of the protective protrusions is greater than the thickness of the remaining areas of the second hard mask layer. When the remaining areas of the second hard mask layer are removed, a portion of the protective protrusions remains, and the isolation dielectric adjacent to the protective protrusions is protected from the etchant. When the first hard mask layer is removed, the remaining protective protrusions continue to protect the sidewalls of the isolation dielectric.

[0023] Furthermore, when the protective protrusion is removed, a portion of the non-protective area of ​​the first hard mask layer has been removed, and the remaining thickness of the protected area is greater than the remaining thickness of the non-protective area. In addition, the etching rate of the doped protective area is lower than the etching rate of the non-protective area, so that the non-protected area is removed before the protected area, and the isolation medium adjacent to the protective area cannot contact the etchant and is protected. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0025] Figures 1a to 1e Schematic cross-sectional views of various stages in the process of forming an STI structure in the prior art are shown, wherein:

[0026] Figure 1a A schematic diagram showing a method of forming a hard mask layer on a semiconductor layer in the prior art is shown;

[0027] Figure 1b A schematic diagram showing a method of forming a trench in a semiconductor layer in the prior art is shown;

[0028] Figure 1c A schematic diagram showing the formation of an isolation dielectric filling the trench and covering the surface of the hard mask layer in the prior art is shown;

[0029] Figure 1d A schematic diagram of removing the second hard mask layer in the prior art is shown;

[0030] Figure 1e A schematic diagram showing the removal of the first hard mask layer to form a shallow trench isolation structure in the prior art is shown;

[0031] Figure 2 A flow chart showing a method for manufacturing a shallow trench isolation structure provided by an embodiment of the present application is shown;

[0032] Figures 3a to 3j 1 shows cross-sectional views of various stages in the manufacturing process of a semiconductor device according to an embodiment of the present application, wherein:

[0033] Figure 3a A schematic diagram showing a method of forming a first hard mask layer on the surface of a semiconductor layer according to an embodiment of the present application is shown;

[0034] Figure 3b A schematic diagram showing a protective region formed in a first hard mask layer according to an embodiment of the present application is shown;

[0035] Figure 3c A schematic diagram showing forming a second hard mask layer on a first hard mask layer according to an embodiment of the present application is shown;

[0036] Figure 3d A schematic diagram showing forming a third hard mask layer on the second hard mask layer according to an embodiment of the present application is shown;

[0037] Figure 3e A schematic diagram illustrating forming a trench penetrating a hard mask layer and a semiconductor layer according to an embodiment of the present application is shown;

[0038] Figure 3f A schematic diagram showing the formation of an isolation dielectric filling the trench and covering the surface of the hard mask layer according to the present application;

[0039] Figure 3g A schematic diagram illustrating the removal of a portion of the isolation medium located on the surface of the hard mask layer according to an embodiment of the present application is shown;

[0040] Figure 3h A schematic diagram showing the removal of the third hard mask layer according to an embodiment of the present application is shown;

[0041] Figure 3i A schematic diagram showing an embodiment of the present application in which the second hard mask layer and the non-protective area of ​​the first hard mask layer are removed while the protective area of ​​the first hard mask layer is retained;

[0042] Figure 3j A schematic diagram showing the removal of the protection area of ​​the first hard mask layer according to an embodiment of the present application is shown.

[0043] Explanation of the figure marks: 110-first semiconductor layer; 120-mask layer; 121-first mask layer; 122-second mask layer; 123-third mask layer; 130-first trench; 140-dielectric layer; 150-gap; 210-second semiconductor layer; 221-first hard mask layer; 221a-protection area; 221b-non-protection area; 222-second hard mask layer; 222a-protection protrusion; 223-third hard mask layer; 223a-protrusion; 230-second trench; 240-isolation medium. DETAILED DESCRIPTION

[0044] The present application will be described in more detail below with reference to the accompanying drawings. In each of the drawings, identical elements are represented by similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0045] When describing the structure of a device, when a layer or region is referred to as being "on" or "over" another layer or region, it may mean that the layer or region is directly above the other layer or region, or that other layers or regions are included between the layer or region and the other layer or region. Furthermore, if the device is turned over, the layer or region will be "below" or "beneath" the other layer or region.

[0046] If the purpose is to describe the situation of being directly on another layer or another area, this article will use the expression "directly on..." or "above and adjacent to...".

[0047] This application may be embodied in various forms, some examples of which are described below.

[0048] Figures 1a to 1e Schematic cross-sectional views of various stages in the process of forming an STI (Shallow Trench Isolation) structure in the prior art are shown.

[0049] like Figure 1a As shown, a mask layer 120 is formed on the first semiconductor layer 110, and a patterned resist mask layer PR1 is formed on the mask layer 120. In this embodiment, the mask layer 120 includes a stacked first mask layer 121, a second mask layer 122, and a third mask layer 123, wherein the first mask layer 121 is an oxide layer (e.g., a SiO2 layer), the second mask layer 122 is a nitride layer (e.g., a SiN layer), and the third mask layer 123 is, for example, a composite layer of a carbon layer and a nitride layer (e.g., a SION layer).

[0050] like Figure 1b As shown, the mask layer 120 and the first semiconductor layer 110 are etched through the patterned resist mask layer PR1, and the pattern of the resist mask layer PR1 is transferred to the mask layer 120 and the first semiconductor layer 110 to form a first trench 130 in the first semiconductor layer 110. After the first trench 130 is formed, the third mask layer 123 is removed.

[0051] like Figure 1c As shown, a deposition process is used, for example, to form a dielectric layer 140 that fills the first trench 130 and covers the surface of the mask layer 120. The dielectric layer 140 is, for example, an oxide layer (eg, a SiO2 layer), but is not limited thereto.

[0052] like Figure 1d As shown, for example, a CMP (Chemical Mechanical Planarization) process is used to remove the dielectric layer 140 covering the surface of the mask layer 120 , and a wet etching process is used to remove the second mask layer 122 .

[0053] like Figure 1eAs shown, a wet etching process is used to remove the first mask layer 121 to form a shallow trench isolation structure. After removing the second mask layer 122, the top sidewalls of the dielectric layer 140 are exposed. During the removal of the first mask layer 121, the etchant contacts the top surface and top sidewalls of the dielectric layer 140, and portions of the sidewalls of the dielectric layer 140 are etched away by the etchant, thereby forming a gap 150 between the first semiconductor layer 110 and the sidewalls of the dielectric layer 140. In subsequent manufacturing processes, conductive material may remain in the gap 150, resulting in defects such as edge leakage, thereby reducing the reliability of the semiconductor device.

[0054] In view of this, an embodiment of the present application provides a method for manufacturing a shallow trench isolation structure. Figure 2 A flow chart showing a method for manufacturing a shallow trench isolation structure according to an embodiment of the present application is shown. Figure 2 , the manufacturing method comprises:

[0055] S10: forming a hard mask layer having a protective structure on the semiconductor layer;

[0056] S20: forming a trench penetrating the hard mask layer and reaching the interior of the semiconductor layer;

[0057] S30: forming an isolation dielectric in the trench, wherein the protection structure is adjacent to the isolation dielectric in the trench; and

[0058] S40: removing the hard mask layer to form a shallow trench isolation structure;

[0059] In this embodiment, a hard mask layer having a protective structure is formed. The protective structure protects the sidewalls of the isolation dielectric in the trench during removal of the hard mask layer, thereby preventing the formation of gaps between the semiconductor layer and the sidewalls of the isolation dielectric. Furthermore, the protective structure is formed during the formation of the hard mask layer and is removed simultaneously during the removal of the hard mask layer, eliminating the need for additional steps.

[0060] Figures 3a to 3j The cross-sectional views of various stages in the manufacturing process of the semiconductor device according to the embodiment of the present application are shown below. Figure 2 as well as Figures 3a to 3j The manufacturing method of the semiconductor device according to the embodiment of the present application is described below.

[0061] In step S10, a hard mask layer having a protective structure is formed on the semiconductor layer, such as Figures 3a to 3d shown.

[0062] like Figure 3a As shown, a first hard mask layer 221 is formed on the surface of the second semiconductor layer 210 .

[0063] In this step, a first hard mask layer 221 is formed on the surface of the second semiconductor layer 210, for example, using a deposition process. The second semiconductor layer 210 can be composed of any of a doped semiconductor substrate, a doped well region, and a doped epitaxial semiconductor layer. Desired semiconductor devices, such as MOS transistors, diodes, and triodes, can also be formed in the second semiconductor layer 210. In this embodiment, the first hard mask layer 221 is an oxide layer, such as a silicon oxide (SiO2) layer.

[0064] like Figure 3b As shown, a protection region 221 a is formed in the first hard mask layer 221 .

[0065] In this step, a patterned resist mask layer PR21 is formed on the surface of the first hard mask layer 221. Ions are then implanted into the first hard mask layer 221 through the openings in the resist mask layer PR21 to form doped regions in the first hard mask layer 221. The doped first hard mask layer forms a protected region 221a, while the undoped first hard mask layer 221 forms an unprotected region 221b. In one embodiment, nitrogen ions are implanted into the first hard mask layer 221 to dope the first hard mask layer 221 with nitrogen (N), for example, but this is not limiting.

[0066] like Figure 3c As shown, a second hard mask layer 222 is formed on the first hard mask layer 221 .

[0067] In this embodiment, the second hard mask layer 22 is an oxide layer, such as a silicon oxide (SiO2) layer. The second hard mask layer 222 is formed, for example, using a sub-atmospheric chemical vapor deposition (SACVD) process. The SACVD process is highly sensitive to the doped first hard mask layer 221. Specifically, this high sensitivity is manifested in that, during the formation of the second hard mask layer 222, the deposition rate of the second hard mask layer 222 above the protection region 221a is higher than the deposition rate of the second hard mask layer 222 above the unprotected region 221b. Consequently, after the same deposition steps, the thickness of the second hard mask layer 222 above the protection region 221a is greater than the thickness of the second hard mask layer 222 above the unprotected region 221b. The second hard mask layer 222 above the protection region 221a forms a protective protrusion 222a, which together with the protection region 221a constitutes a protective structure.

[0068] like Figure 3d As shown, a third hard mask layer 223 is formed on the second hard mask layer 222 .

[0069] In this step, a third hard mask layer 223 is formed, for example, using a deposition process. The third hard mask layer 223 conformally covers the second hard mask layer 222 and the protective protrusion 222a. Thus, the portion of the third hard mask layer 223 covering the protective protrusion 222a forms a corresponding protrusion 223a. In this embodiment, the third hard mask layer 223 is a nitride layer, such as a silicon nitride (SiN) layer.

[0070] In step S20, a trench is formed that penetrates the hard mask layer and reaches the interior of the semiconductor layer, wherein the trench is formed between the protection structures, such as Figure 3e shown.

[0071] In this step, a patterned resist mask layer is formed on the surface of the hard mask layer (specifically, the third hard mask layer 233), and the hard mask layer and the second semiconductor layer 210 are etched through the opening of the resist mask layer to transfer the pattern of the resist mask layer to the hard mask layer and the second semiconductor layer 210 to form a second trench 230 that penetrates the hard mask layer and extends to the interior of the second semiconductor layer 210. After the second trench 230 is formed, the resist mask layer is removed.

[0072] The opening of the reagent-resistant mask layer defines the position of the second trench 230. In this embodiment, the opening of the reagent-resistant mask layer is opposite to the area between the protrusions 223, and the second trench 230 formed is located between the protrusions 223a and the protective structure. In other words, the protrusions 223 and the protective structure are respectively adjacent to the sidewalls of the second trench 230. Figure 3e As shown, the protection structure is on the first side of the second trench 230 (eg Figure 3e the left side in the figure) and the second side (e.g. Figure 3e The right side of the second groove 230 is adjacent to the protrusion 223. Accordingly, the protrusion 223 is adjacent to the first side of the second groove 230 (as shown in FIG. Figure 3e the left side in the figure) and the second side (e.g. Figure 3e The right side in the figure) is adjacent to the second trench 230.

[0073] Although Figure 3e The cross-sectional view only shows the first and second sidewalls of the second trench 230, but it should be understood that the protective structure is adjacent to any sidewall of the second trench 230. For example, when the horizontal cross-section of the second trench 230 is circular, square, or the like, the protective structure surrounds the second trench 230 and is adjacent to the sidewalls of the second trench 230. When the horizontal cross-section of the second trench 230 is annular, the protective structure is adjacent to both the outer and inner sidewalls of the second trench 230.

[0074] In step S30, an isolation dielectric 240 is formed in the second trench 230, and the protection structure is adjacent to the isolation dielectric 240 in the second trench 230, as shown in FIG. Figure 3f to Figure 3g shown.

[0075] Specifically, if Figure 3f As shown, for example, a deposition process is used to form an isolation dielectric 240, which fills the second trench 230 and covers the surface of the hard mask layer (specifically, the third hard mask layer 233). In this embodiment, the isolation dielectric 240 is, for example, an oxide layer, such as a silicon oxide (SiO2) layer. In other embodiments, the isolation dielectric 240 can be configured as other materials, such as a nitride layer, as needed.

[0076] Then, if Figure 3g As shown, a CMP (Chemical Mechanical Planarization) process or an etching process is used to remove the portion of the isolation dielectric 240 located on the surface of the hard mask layer, and the isolation dielectric 240 filling the second trench 230 is retained. In the process of removing the portion of the isolation dielectric 240 located on the surface of the hard mask layer, the raised portion 223a of the third hard mask layer 223 is also removed, so that the top of the isolation dielectric 240 is flush with the top of the third hard mask layer 223.

[0077] In step S40, the hard mask layer is removed to form a shallow trench isolation structure, such as Figures 3h to 3i shown.

[0078] Specifically, if Figure 3h As shown, the third hard mask layer 223 is removed. In this step, for example, wet etching is used to remove the third hard mask layer 223. The third hard mask layer (nitride layer) 223 and the isolation dielectric (oxide layer) 240 have different etch selectivities. By selecting an etchant for the wet etching, the third hard mask layer 223 is removed while the isolation dielectric 240 is retained. Simultaneously, the third hard mask layer (nitride layer) 223 and the second hard mask layer (oxide layer) 222 have different etch selectivities. By selecting an etchant for the wet etching, the third hard mask layer 223 is removed while the second hard mask layer 222 is retained.

[0079] Then, if Figure 3i and Figure 3j As shown, the second hard mask layer 222 and the first hard mask layer 221 are removed. During the removal of the second hard mask layer 222 and the first hard mask layer 221, the protection structure protects the sidewalls of the isolation dielectric 240 in the second trench 230 to prevent a gap from being formed between the second semiconductor layer 210 and the sidewalls of the isolation dielectric 240.

[0080] Specifically, for example, a wet etching process is used to remove the second hard mask layer 222 and the first hard mask layer 221. In this embodiment, the second hard mask layer 222, the first hard mask layer 221, and the isolation dielectric 240 are all oxide layers. During the same etching step, the wet etching etchant contacts the exposed surfaces, thereby achieving the etching process. During the removal of the second hard mask layer 222, the protective protrusion 222a adjacent to the isolation dielectric 240 protects the sidewalls of the isolation dielectric 240. Because the sidewalls of the isolation dielectric 240 are covered by the protective protrusion 222a, the protective protrusion 222a contacts the wet etching etchant and is etched before the sidewalls of the isolation dielectric 240. Furthermore, the thickness of the protective protrusion 222a is greater than the thickness of the remaining areas of the second hard mask layer 222. When the remaining areas of the second hard mask layer 222 are removed, a portion of the protective protrusion 222a remains.

[0081] Next, the first hard mask layer 221 is removed. During the removal of the first hard mask layer 221, the remaining protective protrusions 222a continue to protect the sidewalls of the isolation dielectric 240. Furthermore, when the protective protrusions 222a are completely removed, the protected regions 221a continue to protect the sidewalls of the isolation dielectric 240. Specifically, when the protective protrusions 222a are removed, a portion of the unprotected regions 221b of the first hard mask layer 221 has been removed, and the remaining thickness of the protected regions 221a is greater than the remaining thickness of the unprotected regions 221b. Furthermore, the etching rate of the doped protected regions 221a is lower than that of the unprotected regions 221b, causing the unprotected regions 221b to be etched faster than the protected regions 221a.

[0082] After the above steps, a portion of the top of the isolation dielectric 240 is removed, and a portion of the sidewall of the isolation dielectric 240 extending beyond the second semiconductor layer 210 may also be removed. However, no gap will appear between the second semiconductor layer 210 and the sidewall of the isolation dielectric 240.

[0083] Corresponding to the manufacturing method of the shallow trench isolation structure provided in the above embodiments, another embodiment of the present application further provides a shallow trench isolation structure, and the shallow trench isolation structure is manufactured by any one of the manufacturing methods provided in the above embodiments. Figure 3j The figure shows an exemplary structure of a shallow trench isolation structure provided in an embodiment of the present application. In the shallow trench isolation structure provided in an embodiment of the present application, due to the protection of the protective structure adjacent to the isolation dielectric, no gap will appear between the sidewalls of the second semiconductor layer 210 and the isolation dielectric 240. This prevents the introduction of conductive material between the sidewalls of the second semiconductor layer 210 and the isolation dielectric 240 during the subsequent deposition of the conductive layer, further preventing defects such as edge leakage in the shallow trench isolation structure, and ensuring the reliability of the semiconductor device.

[0084] The unexpected technical effects of this application are:

[0085] In this embodiment, a hard mask layer having a protective structure is formed, wherein the protective structure protects the sidewalls of the isolation dielectric in the trench during the process of etching back the isolation dielectric to prevent formation of gaps between the semiconductor layer and the sidewalls of the isolation dielectric.

[0086] Furthermore, the protection structure is formed during the process of forming the hard mask layer and is removed simultaneously during the process of removing the hard mask layer, so no additional steps are required.

[0087] In a preferred embodiment, a patterned resist mask layer is formed on the surface of the first hard mask layer, and ions are implanted into the first hard mask layer through openings in the resist mask layer to form a protective region in the first hard mask layer. During the formation of the second hard mask layer, a protective protrusion is formed in the second hard mask layer above the protective region, and the protective protrusion and the protective region together constitute a protective structure. This embodiment utilizes the effect of the doped first mask layer on the subsequent deposition rate of the second mask layer to form the protective protrusion, avoiding the use of an etching process, thereby preventing damage to the semiconductor layer by the etching process, and also avoiding the introduction of excessive etching auxiliary structural layers.

[0088] In a preferred embodiment, a SACVD deposition process is used to form the second hard mask layer. The SACVD process has a high sensitivity to the doped first hard mask layer, so that in the process of forming the second hard mask layer, the deposition rate of the second hard mask layer above the protective area is higher than the deposition rate of the second hard mask layer above the non-protective area. Therefore, through the same deposition steps, the thickness of the second hard mask layer above the protective area is greater than the thickness of the second hard mask layer above the non-protective area.

[0089] In a preferred embodiment, the third hard mask layer is removed by wet etching using different etching selectivity ratios between the third hard mask layer and the second hard mask layer and between the third hard mask layer and the isolation medium. Compared with dry etching which requires a photolithography process, the process of this embodiment is simpler and at least one photolithography step is saved.

[0090] In a preferred embodiment, wet etching is used to remove the second and first hard mask layers. Because the protective protrusions cover the sidewalls of the isolation dielectric, they are removed before the isolation dielectric. Furthermore, the thickness of the protective protrusions is greater than the thickness of the remaining areas of the second hard mask layer. When the remaining areas of the second hard mask layer are removed, a portion of the protective protrusions remains, and the isolation dielectric adjacent to the protective protrusions is protected from the etchant. When the first hard mask layer is removed, the remaining protective protrusions continue to protect the sidewalls of the isolation dielectric.

[0091] Furthermore, when the protective protrusion is removed, a portion of the non-protective area of ​​the first hard mask layer has been removed, and the remaining thickness of the protected area is greater than the remaining thickness of the non-protective area. In addition, the etching rate of the doped protective area is lower than the etching rate of the non-protective area, so that the non-protected area is removed before the protected area, and the isolation medium adjacent to the protective area cannot contact the etchant and is protected.

[0092] While the embodiments of the present application are described above, these embodiments do not exhaustively describe all details, nor do they limit the present application to the specific embodiments described. Clearly, numerous modifications and variations are possible based on the above description. These embodiments are selected and described in detail in this specification to better explain the principles and practical applications of the present application, thereby enabling those skilled in the art to better utilize the present application and its modifications. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a shallow trench isolation structure, comprising: forming a hard mask layer having a protective structure on the semiconductor layer; forming a trench penetrating the hard mask layer and extending into the interior of the semiconductor layer; forming an isolation dielectric in the trench, wherein the protection structure is adjacent to the isolation dielectric in the trench; as well as removing the hard mask layer to form a shallow trench isolation structure; In the process of removing the hard mask layer, the protection structure protects the sidewalls of the isolation dielectric in the trench to prevent a gap from being formed between the semiconductor layer and the sidewalls of the isolation dielectric.

2. The method for manufacturing a shallow trench isolation structure according to claim 1, wherein: The method of forming a hard mask layer having a protection structure on a semiconductor layer includes: forming a first hard mask layer on a surface of the semiconductor layer; A protection region is formed in the first hard mask layer, and a region other than the protection region in the first hard mask layer is a non-protection region.

3. The method for manufacturing a shallow trench isolation structure according to claim 2, wherein: The method of forming a hard mask layer having a protection structure on a semiconductor layer includes: forming a second hard mask layer on the first hard mask layer, wherein a thickness of the second hard mask layer on the protection area is greater than a thickness of the second hard mask layer on the unprotected area, and the second hard mask layer on the protection area forms a protection protrusion, and the protection protrusion and the protection area constitute a protection structure; and A third hard mask layer is formed on the second hard mask layer, wherein a portion of the third hard mask layer covering the protection protrusion forms a protrusion accordingly.

4. The method for manufacturing a shallow trench isolation structure according to claim 2, wherein: The method of forming a protection region in the first hard mask layer includes: forming a patterned resist mask layer on the first hard mask layer; Ion implantation is performed on the first hard mask layer through the opening of the resist mask layer to form a doped region in the first hard mask layer, where the doped region is a protection region.

5. The method for manufacturing a shallow trench isolation structure according to claim 3, wherein: A second hard mask layer is formed by SACVD process, the thickness of the second hard mask layer above the protection area is greater than the thickness of the second hard mask layer above the non-protection area, and the second hard mask layer above the protection area forms a protection protrusion.

6. The method for manufacturing a shallow trench isolation structure according to claim 3, wherein: The method of forming an isolation dielectric in the trench includes: forming an isolation dielectric filling the trench and covering a surface of the third hard mask layer; removing the isolation dielectric covering the surface of the third hard mask layer, and retaining the isolation dielectric filling the trench; Wherein, while removing the isolation dielectric on the surface of the third hard mask layer, the protruding portion of the third hard mask layer is also removed, and the top of the isolation dielectric is flush with the surface of the remaining hard mask layer.

7. The method for manufacturing a shallow trench isolation structure according to claim 3, wherein: The first hard mask layer and the second hard mask layer are oxide layers, and the third hard mask layer is a nitride layer.

8. The method for manufacturing a shallow trench isolation structure according to claim 7, wherein: The third hard mask layer is removed by a wet etching process; the second hard mask layer and the first hard mask layer are removed by wet etching. During the process of removing the second hard mask layer and the first hard mask layer, the protection structure protects the sidewall of the isolation medium.

9. The method for manufacturing a shallow trench isolation structure according to claim 8, wherein: During the process of removing the first hard mask layer, an etching rate of the protection area is lower than an etching rate of the non-protection area.

10. A shallow trench isolation structure formed by the method for manufacturing a shallow trench isolation structure according to any one of claims 1 to 9, the isolation structure comprising a trench formed in a semiconductor layer and an isolation dielectric filled in the trench, wherein: There is no gap between the semiconductor layer and the sidewall of the isolation medium.

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