A daisy chain configuration method for stacked chips

Abstract

The application provides a daisy chain configuration method of stacked chips, comprising a plurality of dies of stacked packages, any die in the plurality of dies is defined as a master chip, and the remaining dies are slave chips; a configuration file transmission interface and a pulse signal transmission interface are arranged between the master chip and the slave chips and adjacent slave chips and are connected with each other; after the master chip is configured, the master chip periodically sends a valid pulse signal to the slave chips and sends a configuration file of the slave chips to the slave chips during the valid pulse signal; after a slave chip connected with the master chip receives the configuration file, the slave chip is configured, and after any slave chip is configured, the pulse signal transmission interface between the configured slave chip and adjacent slave chips is connected, and the valid pulse signal sent by the master chip and the configuration file sent by the master chip are transmitted to the next slave chip.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology, and particularly relates to a daisy-chain configuration method for stacked chips. Background Technology

[0002] SSI (Stacked Silicon Interconnect) is a 2.5D integrated circuit packaging technology designed to break through the limitations of traditional single-chip size and enable the design of FPGA chips with higher integration and performance.

[0003] As a large-scale programmable device, FPGA chip solves the problem of insufficient custom circuits. Users can describe the required functions through hardware languages, and then compile the description language into a code stream file (i.e., configuration file) through software. Finally, the FPGA software can be configured. The programmable and configurable advantages of FPGA chip make it widely used in various fields.

[0004] In existing technologies, FPGA chips can be packaged using SSI packaging, which allows multiple FPGA dies to be packaged together, thus further expanding the capacity of FPGAs.

[0005] Stacking not only FPGA chips but also other chips can significantly improve the performance of a single chip. However, configuring individual chips in a stacked chip system presents a major challenge. While the packaged stacked chip appears as a single chip to the user, it is actually a combination of multiple chips. Each die needs to be powered on independently. In active mode, it actively emits a clock signal and reads the bitstream file (FPGA configuration file) from external storage. In passive mode, it passively receives the external configuration bitstream file. Connecting the configuration pins of multiple chips externally results in a large number of pins and a complex configuration method, hindering users from quickly configuring the stacked chips.

[0006] Therefore, it is necessary to design a configuration method for stacked chips that can reduce the number of configuration pins in the stacked chips and reduce the complexity of configuration. Summary of the Invention

[0007] This invention provides a daisy-chain configuration method for stacked chips, which has the advantage of simple configuration.

[0008] Other objects and advantages of the present invention can be further understood from the technical features disclosed herein.

[0009] To achieve one, some, or all of the above objectives or other objectives, the present invention provides a daisy-chain configuration method for stacked chips, comprising multiple stacked dies, defining any one of the dies as a master chip, and the remaining dies as slave chips; the master chip and slave chips, as well as adjacent slave chips, are provided with interconnected configuration file transmission interfaces and pulse signal transmission interfaces. After the master chip is powered on, it downloads and configures the configuration file according to a pre-set configuration mode. After the master chip completes the configuration, it periodically sends valid pulse signals to the slave chips and sends the slave chip's configuration file to the slave chip during the valid pulse signal period; after the slave chips are powered on, they are configured in passive parallel loading mode. After receiving the configuration file, the slave chips connected to the master chip perform configuration, and after any slave chip completes the configuration, the pulse signal transmission interface between the configured slave chip and the adjacent slave chip is connected, and the valid pulse signal sent by the master chip and the configuration file sent by the master chip are transmitted to the next slave chip.

[0010] The master chip and the slave chip are connected via read / write enable signal interfaces and clock signal interfaces, respectively. The master chip and the slave chip share the same configuration clock signal and read / write enable signal. The clock signal interface and configuration file transmission interface of the slave chip are both in passive input mode. The master chip and the slave chip are connected in a parallel daisy chain.

[0011] When the main chip is configured in active configuration mode, the main chip generates a configuration clock signal and sends it to each of the slave chips.

[0012] When the main chip is configured in passive configuration mode, the main chip and the slave chip receive configuration clock signals from the outside.

[0013] The configuration completion signal of the master chip and the configuration completion signal of the slave chip are connected together in an open-drain manner and connected to the ground terminal through a resistor. The configuration completion signals of the connected master chip and slave chip are finally used as the configuration completion signal of the packaged chip.

[0014] After the master chip and the slave chip are configured, the configuration completion signal is pulled high, and the master chip is controlled to send a valid pulse signal or the pulse signal transmission interface between the slave chips is connected, and the configuration file is sent to the next slave chip to be configured during the valid pulse signal period; when all the die configuration completion signals of the stacked chips are pulled high, the stacked chip configuration is completed.

[0015] After the final stage of configuration, the slave chip does not output a valid pulse signal or transmit the configuration file sent by the master chip.

[0016] After the master chip and slave chip are powered on, the received read / write enable signal is set low, and the master chip and slave chip are in the receiving configuration file state.

[0017] The chip is configured to passive parallel X32 loading mode after power-on.

[0018] After the master chip is configured, it periodically sends valid pulse signals to the slave chip at a set clock interval, wherein the set clock interval is the ratio of 32 to the data bit width sent by the master chip per clock cycle.

[0019] The master chip and each of the slave chips are disposed on the interconnect layer of the stacked chips, and the daisy chain connection between the master chip and the slave chips is implemented through the interconnect layer.

[0020] Compared with the prior art, the beneficial effects of the present invention mainly include: the present invention stacks multiple bare dies and packages them into a single packaged chip; the multiple bare dies are connected through a set interface on the chip to achieve cascading; the slave chips in the multiple bare dies share the clock signal of the master chip; the master chip is configured according to the required configuration mode and configuration bandwidth; the slave chips are configured according to the maximum configuration bandwidth; when the master chip completes the configuration, it sends a valid pulse signal and a valid configuration file to the next slave chip; similarly, after the slave chip completes the configuration, it sends the valid pulse signal and valid configuration file sent by the master chip to the next slave chip, thereby realizing the one-to-one configuration of the cascaded chips, while not occupying too many chip pin resources and saving chip area.

[0021] To make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of a daisy chain structure formed by stacking FPGA chips according to Embodiment 1 of the present invention.

[0024] Figure 2 This is a timing diagram for downloading a configuration file of a stacked chip in Example 1. Detailed Implementation

[0025] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front, or back, are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the present invention.

[0026] Example 1

[0027] Example 1 provides a daisy-chain configuration method for stacked chips, including multiple stacked dies. Any one of the dies is defined as a master chip, and the remaining dies are slave chips. The master chip, slave chips, and adjacent slave chips are interconnected by configuration file transmission interfaces and pulse signal transmission interfaces. After power-on, the master chip downloads and configures the configuration file according to a pre-set configuration mode. After configuration, the master chip periodically sends valid pulse signals to the slave chips and sends the slave chip's configuration file during the valid pulse signal period. After power-on, the slave chips are configured in passive parallel loading mode. Upon receiving the configuration file, the slave chips connected to the master chip perform configuration. After configuration by any slave chip, the pulse signal transmission interface between the configured slave chip and adjacent slave chips is connected, and the valid pulse signal and configuration file sent by the master chip are transmitted to the next slave chip.

[0028] In the stacked chip of this invention, a daisy-chain configuration structure (cascaded structure) is formed between the master chip and the slave chips. During configuration, each slave chip uses the configuration clock signal of the master chip (the master chip's configuration clock signal can be actively issued by the master chip or received from an external clock signal), and the master chip sends the slave chip's configuration file to the corresponding slave chip. Specifically, after the master chip completes its configuration, it periodically sends valid pulse signals to each slave chip, and during the period of the valid pulse signal, it sends the slave chip's configuration file to the slave chip for configuration. After receiving the valid pulse, each slave chip begins its configuration, and after the slave chip completes its configuration, it controls the connection of the next adjacent slave chip, so that the valid pulse signal sent by the master chip can be sent to the next slave chip and the configuration file can be sent to the next slave chip, thereby configuring the next slave chip. After the next slave chip is configured, the above steps are repeated to configure the next slave chip, until all slave chips are successfully configured.

[0029] The daisy-chain configuration structure formed within the packaged chip of this invention, during configuration, shares the same configuration clock signal and simultaneously sends the corresponding configuration file through the main chip, controlling the timing of the file transmission. Configuration of cascaded chips can be achieved solely through the interfaces of each die within the packaged chip, eliminating the need to configure pins for each die. This effectively reduces the number of configuration pins required when configuring multiple dies, improving configuration efficiency while also reducing chip area overhead and increasing chip area utilization.

[0030] The configuration method of the present invention is applicable to the rapid configuration of packaged chips such as FPGA chips, DSP chips, and MCU chips.

[0031] like Figure 1 As shown, Example 1 uses a packaged chip configuration of three FPGA chips as an example. All three FPGA chips in Example 1 are placed on the interconnect layer of a stacked chip. The interconnect layer can be used to interconnect the individual FPGA dies and form a daisy-chain configuration structure. Specifically, one FPGA die is defined as the master chip (FPGADie1 in the diagram), and the remaining two FPGA dies are slave chips (FPGA Die2 and FPGA Die3 in the diagram). The configuration clock signal interface and read / write enable signal interface of the master chip and slave chips are connected respectively. The slave chips (FPGA Die2 and FPGA Die3) share the same configuration clock signal CCLK and read / write enable signal RDWR_B with the master chip (which controls the chip to enter the data write state or data read state; during configuration, the read / write enable signal needs to be set low to 0 to control the chip to enter the data write state). By sharing the same configuration clock signal CCLK and setting the slave chip's configuration mode to passive loading mode, the configuration of different FPGA dies can be controlled by sending the configuration file from the master chip.

[0032] The main chip (FPGA Die1) is configured by selecting the corresponding configuration mode after power-on through the initial settings of the configuration pins, and all chips are configured to passively load in parallel.

[0033] The configuration mode of the main chip can be either active loading mode or passive loading mode. The main difference is whether the configuration clock signal is issued by the main chip.

[0034] When the master chip is configured to actively load, it will send a clock signal and transmit it to each slave chip through the same clock signal line shared by all chips in the daisy chain.

[0035] When the master chip is configured for passive loading, external signals are sent to the master chip and slave chips via the same clock signal shared by all chips in the daisy chain.

[0036] Whether it is active configuration or passive configuration, the configuration clock signal of the master chip is consistent with that of the master chip. In this case, the configuration of the slave chip can be carried out by the master chip sending the configuration file (without considering the adjustment of the clock signal).

[0037] The master chip and the slave chip are interconnected by a configuration file transmission interface and a pulse signal transmission interface. The pulse signal transmission interface includes an output terminal CSO_B and a receiving terminal CSI_B. The configuration file transmission interface includes an output port DOUT and a receiving port DIN. The above interfaces are respectively set on each chip, and the transmitting port and receiving port of adjacent chips correspond to each other and are interconnected. The chip above is the output terminal and the chip below is the receiving terminal.

[0038] Both the master and slave chips have configuration completion ports. Once any FPGA die is configured, the configuration completion signal (DONE) output from this interface goes high. The configuration completion signals (DONE) of different FPGA chips are connected together via an open-drain connection and a resistor to ground. The configuration completion signals from the connected master and slave chips ultimately serve as the configuration completion signal for the packaged chip. An open-drain connection means the output is connected to ground via the drain of an N-channel MOSFET (or transistor), with a pull-up resistor. When the output goes high, the external pull-up resistor pulls the signal up to the required voltage. After the configuration completion signals of all the dies in the stacked chips are connected together, the output signal serves as the configuration completion signal for the entire stack.

[0039] In Embodiment 1, the master chip and the slave chip form a configuration daisy chain through the aforementioned signal connection methods (including clock signal connection, read / write enable signal connection, pulse signal connection, data signal connection, and configuration completion signal connection). The daisy chain connection between the master chip and the slave chip is implemented through an interconnect layer.

[0040] During configuration, the main chip can download and configure the configuration file according to the preset configuration mode. The configuration download mode can be active serial, active parallel, SPI X1, SPI X2, SPI X4, SPI X8, BPI, passive serial, passive parallel and other download methods.

[0041] The slave chip uses the master chip's configuration clock signal, therefore it can only be configured in parallel configuration download mode, which is fixed during packaging. To improve configuration download efficiency, the slave chip is configured in passive parallel x32 loading mode after power-on, meaning it transmits 32 bits of data within one clock cycle (from the rising edge to the falling edge of the clock signal). The master chip's configuration speed is not limited and can be set as needed.

[0042] The chip shares the read / write enable signal RDWR_B with the main chip. When the read / write enable signal RDWR_B is low, it indicates that the chip has entered the data writing state. At this time, the external configuration file can be written into the corresponding chip for configuration.

[0043] The following text is incomplete and cannot be translated. Figure 1 Taking the configuration of stacked chips as an example, this invention explains how to implement the configuration of stacked chips. See also... Figure 2 Configuration file download sequence diagram, Figure 2 The following explanation uses the main chip (FPGA Die1) downloading the configuration file in an active SPI X8 download mode (in active mode, the configuration file is downloaded by transmitting 8 bits of data per clock cycle through the serial peripheral interface). The slave chips (FPGA Die2 and FPGA Die3) are both configured in parallel passive X32 download mode.

[0044] After the main chip downloads the configuration file according to the preset configuration mode (the main chip interface DIN[7:0] receives 8 consecutive valid data bits), it performs the configuration and pulls the DONE1 signal high after the configuration is completed (i.e., Figure 2 At time t1, the pulse signal transmission interface (CSO_B) of the master chip (FPGA Die1) emits a valid pulse signal, which is transmitted to the pulse signal transmission interface (CSI_B) of the slave chip (FPGA Die2). After configuration, the master chip emits a valid pulse signal every 4 clock cycles, that is, the signal CSI_B2 on the slave chip (FPGA Die2) is set low at time t2. Figure 2 (The CSI_B2 in the code is periodically set low; taking time t2 as an example, this explanation focuses on this). During this period of valid pulse signal, the master chip sends the configuration file to the slave chip (FPGA Die2). Figure 2 At time t2, the slave chip (FPGA Die2) receives the valid configuration file sent by the master chip via its configuration file receive port DIN[31:0]. Since the slave chip (FPGA Die2) is configured in X32 download mode, it can transmit 32 bits of valid data per clock cycle. Because the slave chip (FPGA Die2) uses the master chip's configuration clock signal, the ratio of the maximum data bit width (32 bits) during the period of sending the valid pulse signal to the data bit width sent by the master chip per clock cycle is calculated in this way in Example 1 as follows: every 4 clock cycles, the master chip will periodically send the valid pulse signal and the configuration file to the slave chip (FPGA Die2).

[0045] After receiving a valid configuration file from the chip (FPGA Die2), configuration begins, and the DONE2 signal is pulled high upon completion of configuration. Figure 2 At time t3, after the slave chip (FPGA Die2) pulls the DONE2 signal high, it connects to the pulse signal transmission interface of the next slave chip (FPGA Die3) and sends the valid pulse signal sent by the master chip to the next slave chip. Figure 2 At time t4 in the cascade, the configuration process continues until the next slave chip (FPGA Die3) is also configured. When the slave chip (FPGA Die3) is configured, as it is the last chip in the cascade, its pulse signal transmission interface and configuration file transmission interface do not send valid pulse signals or configuration files. When the slave chip (FPGA Die3) is configured, its configuration completion signal DONE3 goes high. Figure 2 At time t5, all FPGA dies in the packaged chip have their configuration complete signal DONE connected via open-drain. Once all configuration complete signals are pulled high, the pull-up resistors will be pulled up to the set voltage, indicating that the packaged stacked chip configuration is complete.

[0046] Example 1 illustrates the present invention using a three-FPGA chip package as an example. In actual implementation of the technical solution of the present invention, there are no limitations on the type and number of bare dies in the packaged chip. As long as all the bare dies in the stacked chip are set into the daisy chain structure of the present invention according to the method of the present invention, the configuration speed of the stacked chip can be greatly improved, and the configuration pins of the stacked chip can be saved, resulting in a better user experience.

[0047] The foregoing has provided a detailed description of a daisy-chain configuration method for stacked chips provided by the present invention. Specific examples have been used to illustrate the structure and working principle of the invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make various improvements and modifications to the present invention without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A daisy-chain configuration method for stacked chips, the stacked chips comprising multiple stacked and packaged dies, characterized in that, Define any one of a plurality of bare dies as the master chip, and the remaining bare dies as slave chips; The master chip, slave chips, and adjacent slave chips are interconnected by configuration file transmission interfaces and pulse signal transmission interfaces. After the main chip is powered on, it downloads the configuration file according to the preset configuration mode and performs configuration. After the main chip is configured, it periodically sends valid pulse signals to the slave chip and sends the slave chip's configuration file to the slave chip during the valid pulse signal period. After the slave chip is powered on, it is configured in passive parallel loading mode. The slave chip connected to the master chip receives the configuration file and performs configuration. After any slave chip is configured, the pulse signal transmission interface between the configured slave chip and the adjacent slave chip is connected. The valid pulse signal and the configuration file sent by the master chip are transmitted to the next slave chip. After the master chip and the slave chip are configured, the configuration completion signal is pulled high, and the master chip is controlled to send a valid pulse signal or the pulse signal transmission interface between the slave chips is connected, and the configuration file is sent to the next slave chip to be configured during the valid pulse signal period.

2. The daisy-chain configuration method for stacked chips according to claim 1, characterized in that, The read / write enable signal interface and clock signal interface between the master chip and the slave chip are respectively connected, and the master chip and the slave chip share the same configuration clock signal and read / write enable signal; Both the clock signal interface and the configuration file transmission interface of the chip are in passive input mode; The master chip and the slave chip are connected in a parallel daisy chain.

3. The daisy-chain configuration method for stacked chips according to claim 2, characterized in that, When the main chip is configured in active configuration mode, the main chip generates a configuration clock signal and sends it to each of the slave chips. When the main chip is configured in passive configuration mode, the main chip and the slave chip receive configuration clock signals from the outside.

4. The daisy-chain configuration method for stacked chips according to claim 2, characterized in that, The configuration completion signal of the master chip and the configuration completion signal of the slave chip are connected together in an open-drain manner and connected to the ground terminal through a resistor. The configuration completion signals of the connected master chip and slave chip are finally used as the configuration completion signal of the packaged chip.

5. The daisy-chain configuration method for stacked chips according to claim 4, characterized in that, When all die configuration completion signals in the stacked chip are pulled high, the stacked chip configuration is complete.

6. The daisy-chain configuration method for stacked chips according to claim 1, characterized in that, After the final stage of configuration, the slave chip does not output a valid pulse signal or transmit the configuration file sent by the master chip.

7. The daisy-chain configuration method for stacked chips according to claim 2, characterized in that, After the master chip and slave chip are powered on, the received read / write enable signal is set low, and the master chip and slave chip are in the receiving configuration file state.

8. The daisy-chain configuration method for stacked chips according to claim 1, characterized in that, The chip is configured to passive parallel X32 loading mode after power-on.

9. A daisy-chain configuration method for stacked chips according to claim 8, characterized in that, After the master chip is configured, it periodically sends valid pulse signals to the slave chip at a set clock interval, wherein the set clock interval is the ratio of 32 to the data bit width sent by the master chip per clock cycle.

10. A daisy-chain configuration method for stacked chips according to claim 2, characterized in that, The master chip and each of the slave chips are disposed on the interconnect layer of the stacked chips, and the daisy chain connection between the master chip and the slave chips is implemented through the interconnect layer.

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