Display panel

Abstract

The invention provides a display panel. The display panel comprises a circuit substrate, a plurality of joint patterns and a plurality of micro light-emitting elements, the plurality of bonding patterns are arranged on the substrate surface of the circuit substrate, and each bonding pattern is provided with a first side wall surface. The plurality of miniature light-emitting elements are respectively jointed on the circuit substrate through the jointing patterns, and each miniature light-emitting element is provided with a second side wall surface. The first side wall surface and the second side wall surface have a segment difference in any direction parallel to the surface of the substrate.

Description

Technical Field

[0001] The present invention relates to a display panel, and in particular to a display panel with micro light-emitting elements. Background Art

[0002] Mass transfer is the mainstream technology currently used to manufacture micro light emitting diode (micro-LED) display panels. Among them, a process method has been proposed in which the complete epitaxial layer is first bonded to a CMOS (Complementary Metal Oxide Semiconductor) backplane and then isolated by etching to obtain micro-crystals (i.e., micro-LEDs). This type of process first creates a metal layer (such as Au or AuSn) for bonding on the circuit substrate before separating the micro-crystals. When gas etching is used for the above separation process, part of the metal reacts with the etching gas to form a gas compound and is carried away. However, due to the limitation of saturated vapor pressure, part of the removed metal cannot be completely vaporized and remains in solid form on the sidewalls of the separated micro-crystals, causing short circuit failure of the micro-crystals or other structural defects. Summary of the Invention

[0003] The present invention is directed to a display panel having a better manufacturing process yield.

[0004] According to an embodiment of the present invention, a display panel includes a circuit substrate, a plurality of bonding patterns, and a plurality of micro-light-emitting elements. The plurality of bonding patterns are disposed on a substrate surface of the circuit substrate and each have a first sidewall surface. The plurality of micro-light-emitting elements are bonded to the circuit substrate via the bonding patterns and each have a second sidewall surface. The first sidewall surface and the second sidewall surface have a step difference in any direction parallel to the substrate surface.

[0005] Based on the above, in a display panel according to one embodiment of the present invention, a micro-light-emitting element is bonded to the substrate surface of a circuit substrate via a bonding pattern. In any direction parallel to the substrate surface, there is a step difference between the first sidewall surface of the bonding pattern and the second sidewall surface of the micro-light-emitting element. This structural feature is formed by encapsulating the micro-light-emitting element during the etching process of the bonding pattern, thereby preventing residues of the bonding pattern from affecting the micro-light-emitting element. In other words, the present invention provides protection for the micro-light-emitting element during the etching process, which can significantly reduce the risk of damage to the micro-light-emitting element and help improve the process yield of separating a complete epitaxial layer on the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic cross-sectional view of a display panel according to a first embodiment of the present invention;

[0007] Figures 2A to 2E yes Figure 1 A schematic cross-sectional view of a manufacturing process of a display panel;

[0008] Figure 3 is a schematic cross-sectional view of a display panel according to a second embodiment of the present invention;

[0009] Figures 4A to 4B yes Figure 3 A cross-sectional schematic diagram of part of the manufacturing process of a display panel;

[0010] Figure 5 is a schematic cross-sectional view of a display panel according to a third embodiment of the present invention;

[0011] Figure 6 is a schematic cross-sectional view of a display panel according to a fourth embodiment of the present invention;

[0012] Figure 7 is a schematic cross-sectional view of a display panel according to a fifth embodiment of the present invention.

[0013] Description of Reference Numerals

[0014] 10, 10A, 10B, 20, 30: display panel;

[0015] 100: circuit substrate;

[0016] 100s: substrate surface;

[0017] 110: bonding pattern;

[0018] 110M: bonding material layer;

[0019] 120, 120A: ohmic contact layer;

[0020] 120M: Ohmic contact material layer;

[0021] 120s, 200s: surface;

[0022] 130, 130", 130A, 130B: etching protection layer;

[0023] 130M: Etching protective material layer;

[0024] 130sw, SW1, SW2, SW3, SW4: side wall;

[0025] 200: micro light emitting element;

[0026] 210: first type semiconductor layer;

[0027] 220: second type semiconductor layer;

[0028] 230: active layer;

[0029] DB: metal debris;

[0030] ePL: cutoff plane;

[0031] INS1, INS1A, INS2: insulation layer;

[0032] PR: photoresist pattern;

[0033] RFL1, RFL2: light reflecting layer;

[0034] s, s1, s2: spacing;

[0035] W, W1, W2, W3, W1', W2', W3': width;

[0036] X, Z: direction. DETAILED DESCRIPTION

[0037] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0038] In the accompanying drawings, the thickness of layers, films, panels, regions, etc. is exaggerated for clarity. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it may be directly on or connected to another element, or an intermediate element may also exist. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there is no intermediate element. As used herein, "connection" may refer to physical and / or electrical connection. Furthermore, "electrical connection" may be the presence of other elements between two elements.

[0039] Figure 1 is a schematic cross-sectional view of a display panel according to a first embodiment of the present invention. Figures 2A to 2E yes Figure 1 A cross-sectional diagram of the manufacturing process of the display panel. Figure 1 The display panel 10 includes a circuit substrate 100, a plurality of bonding patterns 110, and a plurality of micro-light-emitting elements 200. The circuit substrate 100 is, for example, but not limited to, a CMOS (Complementary Metal Oxide Semiconductor) backplane. A plurality of bonding patterns 110 are provided on a substrate surface 100s of the circuit substrate 100. The plurality of micro-light-emitting elements 200 are bonded to the circuit substrate 100 via these bonding patterns 110. The bonding patterns 110 are made of, for example, but not limited to, Au or AuSn.

[0040] In this embodiment, the micro-light-emitting device 200 may include a first-type semiconductor layer 210, an active layer 230, and a second-type semiconductor layer 220 stacked in sequence along a direction away from the circuit substrate 100 (e.g., direction Z). More specifically, the micro-light-emitting device 200 of this embodiment is, for example, a vertical micro-light-emitting device, but is not limited thereto. The first-type semiconductor layer 210 and the second-type semiconductor layer 220 may be a P-type semiconductor (e.g., p-GaN) and an N-type semiconductor (e.g., n-GaN), respectively, while the active layer 230 may have a multiple quantum well (MQW) structure, but is not limited thereto.

[0041] An ohmic contact layer 120 may be provided between each micro-light-emitting element 200 and the corresponding bonding pattern 110. The material of the ohmic contact layer 120 may be a metal oxide (e.g., indium tin oxide), but is not limited thereto. In other embodiments, the material of the ohmic contact layer 120 may also include a metal or alloy (e.g., Ni / Ag). Therefore, in this embodiment, the ohmic contact layer 120 has a high reflectivity for light and can also serve as a light reflective layer for the display panel 10C.

[0042] It is particularly noteworthy that the display panel 10 may also optionally include an etching protection layer 130 covering the sidewall surface SW2 of each micro-light-emitting element 200. In this embodiment, the etching protection layer 130 may completely cover the sidewall surface SW2 of the micro-light-emitting element 200 and extend from the sidewall surface SW2 to the surface 120s of the ohmic contact layer 120 facing away from the circuit substrate 100. In other words, the sidewall surface SW2 of the micro-light-emitting element 200 only contacts the etching protection layer 130.

[0043] While the etching protection layer 130 covers the sidewall surfaces SW2 of the micro-light-emitting elements 200, it exposes the surface 200s of the micro-light-emitting elements 200 facing away from the circuit substrate 100. It should be noted that the display panel 10 may further include a common electrode layer (not shown) that covers and contacts the surfaces 200s of each of the plurality of micro-light-emitting elements 200 to electrically connect the second-type semiconductor layers 220 of each of these micro-light-emitting elements 200. To prevent the common electrode layer from further contacting the bonding pattern 110 and causing an electrical short circuit among the micro-light-emitting elements 200, the display panel 10 may further include an insulating layer INS1 that covers the etching protection layer 130, the sidewall surfaces SW3 of the ohmic contact layer 120, and the sidewall surfaces SW1 of the bonding pattern 110. Specifically, the etching protection layer 130 is positioned between the insulating layer INS1 and the sidewall surfaces SW2. It is particularly important to note that in this embodiment, the ohmic contact layer 120 contacts both the etching protection layer 130 and the insulating layer INS1.

[0044] In another embodiment (not shown), the insulating layer INS1 can also be implemented as a flat layer between the multiple micro-light-emitting elements 200, with the aforementioned common electrode layer extending over the flat layer. In other words, the flat layer fills the gaps between the micro-light-emitting elements 200, isolating the common electrode layer, the ohmic contact layer 120, and the bonding pattern 110. In this way, the common electrode layer can be implemented as a planar film layer based on the flat layer.

[0045] The following is an exemplary description of the manufacturing process of the display panel 10 .

[0046] Please refer to Figure 2A First, an epitaxial layer pre-formed on an epitaxial substrate (not shown) is bonded to a circuit substrate 100. The epitaxial substrate may include, for example, a semiconductor wafer or a sapphire substrate. After bonding, the epitaxial layer on the circuit substrate 100 is patterned to form a plurality of micro-light-emitting elements 200. The patterning process may employ, for example, but not limited to, photolithography.

[0047] Before bonding the epitaxial layer, a bonding material layer 110M and an ohmic contact material layer 120M are first formed on the substrate surface 100s of the circuit substrate 100. In the present embodiment, the ohmic contact material layer 120M is made of, for example, indium tin oxide (ITO), and the epitaxial layer is made of, for example, gallium nitride (GaN). During the patterning process of the aforementioned epitaxial layer, due to the different etching selectivities of the etching gas or etching liquid for ITO and GaN, the ohmic contact material layer 120M made of ITO can be used as an etching stop layer. The material of the bonding material layer 110M includes, for example, gold (Au), tin (Sn), indium (In), copper (Cu), silver (Ag) or alloys of the above materials. Before the aforementioned patterning process, the ohmic contact material layer 120M can also be first formed on the entire epitaxial layer of the epitaxial substrate and bonded to the bonding material layer 110M during the bonding process.

[0048] Then refer to Figure 2B , optionally forming an etching protection material layer 130M to cover the plurality of micro-light emitting elements 200 and the surface 120s of the ohmic contact material layer 120M. The material of the etching protection material layer 130M includes, for example, silicon dioxide (SiO2) or aluminum oxide (Al2O3), but is not limited thereto. Figure 2C After forming the etching protection material layer 130M, a plurality of photoresist patterns PR are formed. In the direction Z, these photoresist patterns PR overlap with the plurality of micro-light-emitting elements 200. In other embodiments, these photoresist patterns PR may be replaced by a plurality of shielding patterns made of silicon dioxide or other suitable materials, and the present invention is not limited thereto.

[0049] Specifically, in this embodiment, the orthographic projections of the plurality of micro-light-emitting elements 200 on the substrate surface 100s can be located within the orthographic projections of the plurality of photoresist patterns PR on the substrate surface 100s. In other words, the micro-light-emitting elements 200 completely overlap the photoresist patterns PR. If the alignment accuracy of the photoresist patterns PR during the manufacturing process is sufficiently high, the aforementioned etching protection material layer 130M can be omitted, and the photoresist pattern PR can instead directly cover the micro-light-emitting elements 200.

[0050] Reference Figure 2D After the photoresist pattern PR is formed, the bonding material layer 110M and the ohmic contact material layer 120M are patterned to form a plurality of etching protection layers 130", a plurality of bonding patterns 110, and a plurality of ohmic contact layers 120. During the patterning process, part of the metal in the bonding material layer 110M is vaporized and reacts with the etching gas. Since the presence of the gas is affected by the saturated vapor pressure, part of the metal removed cannot be completely vaporized and remains on the surface of the photoresist pattern PR in a solid form (e.g., metal debris DB).

[0051] From another perspective, since the micro-light-emitting device 200 is covered by the etching protection layer 130″ and the photoresist pattern PR, metal debris DB generated during the patterning process of the bonding material layer 110M and the ohmic contact material layer 120M will not adhere to the sidewall surface SW2 of the micro-light-emitting device 200. In this way, the metal debris DB generated during the formation of the bonding pattern 110 and the ohmic contact layer 120 can be prevented from adhering to the sidewall surface SW2 of the micro-light-emitting device 200, causing an electrical short circuit and failure.

[0052] The etching protection layer 130 ″, the ohmic contact layer 120 and the bonding pattern 110 formed after patterning respectively have a sidewall surface 130sw, a sidewall surface SW3 and a sidewall surface SW1. In the present embodiment, the sidewall surface 130sw of the etching protection layer 130 ″ can be aligned with the overlapping sidewall surface SW3 of the ohmic contact layer 120 and the sidewall surface SW1 of the bonding pattern 110, but is not limited thereto.

[0053] like Figure 2E As shown, the photoresist pattern PR is removed and a cleaning process is performed to remove the metal debris DB. After the metal debris DB is removed, an insulating layer INS1 is formed to cover the sidewall surface SW2 of the micro-light-emitting element 200, the sidewall surface 130sw of the etching protection layer 130, the sidewall surface SW3 of the ohmic contact layer 120, the sidewall surface SW1 of the bonding pattern 110, and a portion of the substrate surface 100s of the circuit substrate 100, as shown in FIG. Figure 1 The material of the insulating layer INS1 includes, for example, silicon dioxide (SiO2) or aluminum oxide (Al2O3).

[0054] It is particularly noted that after removing the photoresist pattern PR, a step of removing a portion of the etching protection layer 130" may be performed to form an etching protection layer 130 (eg, a portion of the etching protection layer 130) that exposes the surface 200s of the micro-light emitting element 200. Figure 2E As shown). However, the present invention is not limited thereto. In another variant embodiment, the step of removing a portion of the etching protection layer 130″ can be integrated into the patterning process of the insulating layer INS1. More specifically, the removal of a portion of the insulating layer INS1 and the removal of a portion of the etching protection layer 130″ can be completed in the same etching step.

[0055] Although not shown, after forming the insulating layer INS1, a common electrode layer may be formed to electrically contact the second-type semiconductor layer 220 of each of the plurality of micro-light-emitting elements 200. Furthermore, an encapsulation layer may be formed to encapsulate these micro-light-emitting elements 200 to improve the display panel 10's resistance to the operating environment. This completes the fabrication of the display panel 10 of this embodiment.

[0056] In particular, Figure 2C and Figure 2D During the patterning process, the width of the photoresist pattern PR in any direction parallel to the substrate surface 100s (e.g., direction X) is greater than the device width of the micro-light-emitting device 200 it covers in any direction parallel to the substrate surface 100s. Therefore, the widths W1, W2, and W3 of the bonding pattern 110, ohmic contact layer 120, and etching protection layer 130 formed after etching, respectively, in any direction parallel to the substrate surface 100s, are all greater than the device width W of the micro-light-emitting device 200.

[0057] From another perspective, in any direction parallel to the substrate surface 100s, the sidewall surface SW1 of the bonding pattern 110 and the sidewall surface SW2 of the micro-light-emitting element 200 have a distance s (i.e., a step difference). In other words, the sidewall surface SW2 of the micro-light-emitting element 200 is retracted compared to the sidewall surface SW1 of the bonding pattern 110. This structural feature is attributed to the use of the photoresist pattern PR (e.g., Figure 2C The micro-light-emitting element 200 is encapsulated by the bonding pattern 110 (shown in FIG. 1 ). Consequently, during the formation of the bonding pattern 110 and the ohmic contact layer 120, metal debris DB generated can be prevented from adhering to the sidewalls SW2 of the micro-light-emitting element 200, causing an electrical short circuit and resulting in failure. In other words, the display panel 10 having the above-described structural features can achieve a better manufacturing yield.

[0058] In this embodiment, the width W1 of the bonding pattern 110, the width W2 of the ohmic contact layer 120, and the width W3 of the etching protection layer 130 may be substantially equal, but this is not a limitation. The bonding pattern 110, the ohmic contact layer 120, and the etching protection layer 130 may coplanarly terminate at a cutoff plane ePL. That is, the sidewall surface SW1 of the bonding pattern 110, the sidewall surface SW3 of the ohmic contact layer 120, and the sidewall surface 130sw of the etching protection layer 130 may be aligned with each other and form the aforementioned cutoff plane ePL.

[0059] The following will list some other embodiments to illustrate the present disclosure in detail, wherein the same components will be marked with the same symbols, and the description of the same technical content will be omitted. For the omitted parts, please refer to the above embodiments and will not be repeated below.

[0060] Figure 3 is a schematic cross-sectional view of a display panel according to a second embodiment of the present invention. Figures 4A to 4B yes Figure 3 A cross-sectional diagram of part of the manufacturing process of the display panel. Figure 3 , compared to Figure 1 The display panel 10 of this embodiment optionally includes a light-reflecting layer RFL1. Specifically, in this embodiment, the etching protection layer 130A and the insulating layer INS1A only cover a portion of the sidewall surface SW2 of the micro-light-emitting element 200, while the other portion of the sidewall surface SW2 is covered by the light-reflecting layer RFL1. In other words, the sidewall surface SW2 of the micro-light-emitting element 200 is completely covered by the light-reflecting layer RFL1 and the etching protection layer 130A.

[0061] Of particular note, the light-reflecting layer RFL1 also extends from the sidewall surface SW2 of the micro-light-emitting element 200 to cover the sidewall surface SW3 of the ohmic contact layer 120 and the sidewall surface SW1 of the bonding pattern 110. The provision of the light-reflecting layer RFL1 effectively improves the light extraction efficiency of the micro-light-emitting element 200. To protect the light-reflecting layer RFL1, the display panel 20 may also be covered with another insulating layer INS2 on the side of the light-reflecting layer RFL1 facing away from the micro-light-emitting element 200. In other words, the light-reflecting layer RFL1 is sandwiched between the insulating layer INS1A and the insulating layer INS2.

[0062] Since the manufacturing processes of the display panel 20 of this embodiment before forming the insulating layer INS1A are similar to those of Figure 1 For detailed description of the display panel 10, please refer to the relevant paragraphs of the above embodiment, which will not be repeated here. Figure 1 The differences in the manufacturing process of the display panel 10 are described below.

[0063] Please refer to Figure 4AAfter the patterning process of the insulating layer INS1A and the etching protection layer 130A is completed, in addition to the surface 200s, part of the side wall surface SW2 of the micro-light emitting element 200 will also be exposed. Then, a light reflecting layer RFL1 is formed on the side wall surface SW2 of the micro-light emitting element 200. Figure 4B As shown. It is particularly noted that the light reflection layer RFL1 directly contacts the portion of the sidewall surface SW2 not covered by the etching protection layer 130A and extends to cover the insulating layer INS1A. The material of the light reflection layer RFL1 includes, for example, silver (Ag) or aluminum (Al), but is not limited thereto.

[0064] After the light reflecting layer RFL1 is formed, an insulating layer INS2 is formed to cover the light reflecting layer RFL1 and expose the surface 200s of the micro-light emitting element 200. Figure 3 As shown. The material of the insulating layer INS2 includes silicon dioxide (SiO2) or aluminum oxide (Al2O3). Since the manufacturing process of the display panel 20 after forming the insulating layer INS2 of this embodiment is similar to Figure 1 The manufacturing process of the display panel 10 after forming the insulating layer INS1 is described in detail in the relevant paragraphs of the aforementioned embodiment and will not be repeated here.

[0065] At this point, the display panel 20 of this embodiment is fabricated. In this embodiment, the sidewall surfaces SW2 of the micro-light-emitting element 200 are covered with a light-reflecting layer RFL1. The light-reflecting layer RFL1 extends from the sidewall surfaces SW2 to cover the sidewall surfaces SW1 of the bonding pattern 110. The light-reflecting layer RFL1 electrically contacts the second-type semiconductor layer 220 of the micro-light-emitting element 200 through the portion of the sidewall surfaces SW2 exposed by the insulating layer INS1A and the etching protection layer 130A, while being electrically insulated from the first-type semiconductor layer 210 and the active layer 230.

[0066] From another perspective, in this embodiment, the sidewall surface SW2 of the micro-light-emitting element 200 may be covered with three insulating layers, namely, the etching protection layer 130A, the insulating layer INS1A, and the insulating layer INS2, wherein the coverage area of ​​the etching protection layer 130A (extending only to cover the surface 120s of the ohmic contact layer 120) is different from the coverage areas of the insulating layer INS1A and the insulating layer INS2.

[0067] Figure 5 is a cross-sectional view of a display panel according to a third embodiment of the present invention. Figure 5 The display panel 10A of this embodiment is Figure 1The display panels 10 differ in the size relationship between the ohmic contact layer and the bonding pattern. Specifically, in this embodiment, the width W2' of the ohmic contact layer 120A in direction X (or any direction parallel to the substrate surface 100s) is equal to the width W3' of the etching protection layer 130B in direction X, and is smaller than the width W1' of the bonding pattern 110 in direction X.

[0068] The difference from the previous embodiment is that the ohmic contact layer 120A and the etching protection layer 130B terminate coplanarly at a cutoff plane ePL, but the cutoff plane ePL is not coplanar with the sidewall surface SW1 of the bonding pattern 110. Specifically, the cutoff plane ePL is located between the sidewall surface SW1 of the bonding pattern 110 and the sidewall surface SW2 of the micro-light-emitting element 200. In any direction parallel to the substrate surface 100s (e.g., direction X), the sidewall surface SW2 of the micro-light-emitting element 200 is spaced apart from the cutoff plane ePL by a distance s1, while the sidewall surface SW1 of the bonding pattern 110 is spaced apart from the cutoff plane ePL (or the sidewall surface SW3 of the ohmic contact layer 120A) by a distance s2. In other words, both the sidewall surface SW2 and the sidewall surface SW1 have a step difference from the cutoff plane ePL.

[0069] More specifically, the cutoff plane ePL of the ohmic contact layer 120A and the etching protection layer 130B is retracted compared to the sidewall surface SW1 of the bonding pattern 110. The reason for this structural feature is that in addition to the use of the photoresist pattern PR (such as Figure 2C In addition to encapsulating the micro-light emitting element 200, the etching gas or etching solution selected has a greater etching selectivity ratio for the etching protection material layer and the ohmic contact material layer than for the bonding material layer. In addition, since the thickness of the etching protection layer 130B is usually small, the difference in the time the etching protection layer 130B and the ohmic contact layer 120A are exposed to the process environment is very small. Therefore, in Figure 1 or Figure 5 In the embodiment, the etching protection layer 130B is substantially flush with the ohmic contact layer 120A.

[0070] Since the manufacturing method of the display panel 10A of this embodiment is similar to Figure 1 For detailed description of the display panel 10, please refer to the relevant paragraphs of the above embodiment, which will not be repeated here. Figure 5 In the embodiment, the width relationship between the bonding pattern 110, the ohmic contact layer 120A, and the micro-light-emitting element 200 (i.e., the width W2' and the width W3' are smaller than the width W1' and larger than the width W) allows the overall surface of these film structures to present a stepped shape, making it less likely that the insulating layer INS1 will break during the subsequent film formation process.

[0071] Figure 6is a cross-sectional view of a display panel according to a fourth embodiment of the present invention. Figure 6 , compared to Figure 5 The display panel 10A of this embodiment further includes a display panel 10B that optionally includes a light-reflecting layer RFL2 disposed between the overlapping micro-light-emitting elements 200 and the bonding pattern 110. The provision of the light-reflecting layer RFL2 effectively improves the light extraction efficiency of the micro-light-emitting elements 200. More specifically, the light-reflecting layer RFL2 is located between the ohmic contact layer 120A and the bonding pattern 110. The material of the light-reflecting layer RFL2 includes, for example, silver (Ag) or aluminum (Al).

[0072] It is particularly noteworthy that in this embodiment, since the light reflective layer RFL2 is also made of metal, during the etching process of the bonding pattern 110, the difference in etching selectivity between the etching gas or etching solution for the bonding material layer and the light reflective material layer is relatively small, and the thickness requirement for the light reflective material layer due to light reflection is not high. Therefore, the sidewall surface SW4 of the light reflective layer RFL2 formed after etching may be substantially aligned with the sidewall surface SW1 of the bonding pattern 110, but the present invention is not limited to this.

[0073] Since the remaining components and structural relationships of the display panel 10B are similar to Figure 5 For the display panel 10A, detailed description can be found in the relevant paragraphs of the aforementioned embodiment, which will not be repeated here.

[0074] Figure 7 is a cross-sectional view of a display panel according to a fifth embodiment of the present invention. Figure 7 , compared to Figure 3 The display panel 20 of this embodiment further optionally includes a light reflective layer RFL2 disposed between the ohmic contact layer 120 and the bonding pattern 110. The material of the light reflective layer RFL2 can be the same as that of the light reflective layer RFL1. In this embodiment, the additional light reflective layer RFL2 can reflect light emitted in the -Z direction from the active layer 230 or the light reflective layer RFL1, further improving the light extraction efficiency of the micro-light-emitting element 200.

[0075] It is particularly noted that the display panel 30 of this embodiment does not have Figure 3 Therefore, the sidewall surface SW2 of the micro-light emitting element 200 will be completely covered by the light reflecting layer RFL1 and the insulating layer INS1A. In other words, this embodiment will not cause Figure 1 The sidewall surface 130sw of the etching protection layer 130 is aligned with the cross section SW3 of the ohmic contact layer 120. However, according to the process conditions, this embodiment can also be implemented as Figure 3 The etching protection layer 130A covers a portion or all of the side wall surface SW2.

[0076] Since the remaining components and structural relationships of the display panel 30 are similar to Figure 3 For detailed description of the display panel 20, please refer to the relevant paragraphs of the aforementioned embodiment and will not be repeated here.

[0077] In summary, in a display panel according to one embodiment of the present invention, a micro-luminescent element is bonded to the substrate surface of a circuit substrate via a bonding pattern. In any direction parallel to the substrate surface, a step exists between the first sidewall surface of the bonding pattern and the second sidewall surface of the micro-luminescent element. This structural feature is due to the use of a photoresist pattern to encapsulate the micro-luminescent element during the etching process of the bonding pattern. The provision of the photoresist pattern also significantly reduces the risk of damage to the micro-luminescent element separated from the circuit substrate during the subsequent formation of the bonding pattern, thereby helping to improve the process yield of the display panel.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: include: Circuit board; a plurality of bonding patterns, disposed on the substrate surface of the circuit substrate and each having a first sidewall surface; as well as A plurality of micro-light emitting elements are respectively bonded to the circuit substrate via the plurality of bonding patterns. The plurality of micro-light emitting elements each have a second side wall surface, and the first side wall surface and the second side wall surface have a step difference in any direction parallel to the substrate surface.

2. The display panel according to claim 1, wherein: An ohmic contact layer is disposed between each of the plurality of micro-light-emitting elements and a corresponding one of the plurality of bonding patterns, and in any direction parallel to the substrate surface, a first width of the ohmic contact layer is less than or equal to a second width of each of the plurality of bonding patterns.

3. The display panel according to claim 2, wherein: The ohmic contact layer is terminated at a third sidewall surface, and the third sidewall surface is aligned with the first sidewall surface of the corresponding one of the plurality of bonding patterns.

4. The display panel according to claim 2, wherein: The second sidewall surface of each of the plurality of micro-light-emitting elements is covered with an etching protection layer, and the etching protection layer extends from the second sidewall surface to cover the surface of the ohmic contact layer facing away from the circuit substrate.

5. The display panel according to claim 4, wherein: In any direction parallel to the surface of the substrate, a third width of the etching protection layer is less than or equal to the second width.

6. The display panel according to claim 4, wherein: The ohmic contact layer and the etching protection layer are coplanar and terminated at a termination plane.

7. The display panel according to claim 6, wherein: In any direction parallel to the substrate surface, the cutoff plane is located between the first sidewall surface and the second sidewall surface, and there is a step difference between the first sidewall surface and the second sidewall surface and the cutoff plane.

8. The display panel according to claim 6, wherein: The cutoff plane is flush with the first sidewall surface.

9. The display panel according to claim 1, wherein: The second sidewall surface of each of the plurality of micro-light-emitting elements is covered with a first light-reflecting layer, and the first light-reflecting layer extends from the second sidewall surface to cover the first sidewall surface.

10. The display panel according to claim 9, wherein: A second light reflecting layer is further disposed between each of the plurality of micro-light emitting elements and a corresponding one of the plurality of bonding patterns.

11. The display panel according to claim 9, wherein Each of the plurality of micro-light emitting elements includes a first-type semiconductor layer, an active layer, and a second-type semiconductor layer stacked in a direction away from the circuit substrate. The first light reflecting layer electrically contacts the second-type semiconductor layer and is electrically insulated from the first-type semiconductor layer and the active layer.

12. The display panel according to claim 9, wherein: A first insulating layer and a second insulating layer are respectively disposed on opposite sides of the first light reflecting layer on each of the plurality of micro-light emitting elements.

13. The display panel according to claim 12, wherein: The first insulating layer contacts the second side wall surface, and the second side wall surface is completely covered by the first light reflecting layer and the first insulating layer.

14. The display panel according to claim 12, wherein: The second sidewall surface of each of the plurality of micro-light-emitting elements is covered with an etching protection layer. The etching protection layer is located between the first insulating layer and the second sidewall surface. The second sidewall surface is completely covered by the first light reflecting layer and the etching protection layer.

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