Integrated circuit die in-situ detection method based on wafer on-chip bus

Abstract

The invention provides an integrated circuit die in-situ detection method based on a wafer on-chip bus. The essence of the method is that a test function is converted into internal circuit integration from external mechanical intervention; in the spatial dimension, wafer-level interconnection with zero area overhead is realized by utilizing a cutting channel; according to the time dimension, microsecond-level Die switching is achieved through address addressing, and the mechanical movement limit is broken through. The information dimension is that internal nodes are directly accessed, and a chip'black box 'is perspective. On a large-size wafer, due to the fact that the number of Dies is large, random sampling detection can remarkably improve the testing efficiency and reduce the production cost, and meanwhile, by dynamically adjusting the sampling detection probability, the omission ratio can be controlled within an acceptable range.

Description

Technical Field

[0001] The present invention relates to an integrated circuit testing method, and in particular to an integrated circuit die in-situ detection method based on an on-wafer bus. Background Art

[0002] In our prior patent application CN2025104433471, we proposed an in-situ detection method for small- and medium-scale integrated circuit dies on large-size wafers. In this patent application, we adopted an in-situ detection method based on random sampling and dynamic adjustment. The core of this method is to detect some chips (dies) on the wafer through random sampling, and statistically analyze the process reliability based on the detection results of different areas. On this basis, the probability of random inspection is dynamically adjusted: the frequency of random inspections is reduced in areas with high reliability, and the frequency of random inspections is increased in areas with low reliability. At the same time, a penalty and reward mechanism is introduced. Through this optimized random inspection strategy and test process, it is possible to significantly improve detection efficiency and reduce production costs while ensuring detection accuracy. It is particularly suitable for efficient detection scenarios of large-size wafers. This technology solves the technical problem: the low efficiency of the traditional one-by-one testing method when facing large-size wafers and high-density chips has become an important bottleneck restricting semiconductor production.

[0003] However, there is still room for improvement in this patent application, as detailed below: In the above-mentioned prior patent application CN CN2025104433471, a probe card is used for in-situ testing of dies on wafers. Its core principle is to electrically connect the probe card to the dies on the wafer and test the electrical performance and functions of the dies one by one or in batches. During the test, the probes on the probe card contact the pads of the dies. The test equipment applies a test signal to the dies through the probe card and reads the response signal of the dies to determine whether the dies meet the design requirements. The test equipment connects each die in turn through the probe card to perform electrical performance tests, functional tests, etc. During the in-situ testing of integrated circuit dies on the wafer, the test equipment electrically connects to the pads of each die through the probe card and performs electrical performance tests and functional tests in turn. The electrical performance test mainly includes measuring the voltage, current, resistance and other parameters of the die to ensure that its electrical characteristics meet the design requirements. The functional test verifies whether its logical function is normal by inputting specific test signals to the die. The test equipment will automatically complete these test steps according to the preset test procedures and record the test results of each die.

[0004] Probe cards, as the core medium for wafer testing, are indispensable for screening defective dies and improving yield. However, their technical limitations and economic disadvantages are particularly significant when testing a large number of small- and medium-scale integrated circuit dies on large-sized wafers (such as 12 inches). Specific explanations are as follows: 1. High cost issue: equipment investment and customization burden 1. Expensive equipment and low localization rate High unit prices: High-end probe cards (such as MEMS probe cards) can cost tens to hundreds of thousands of yuan, particularly for advanced processes (below 7nm) or high-density die testing. 2.5D / 3D MEMS probe cards used for DRAM and HBM testing require multi-layer stacking, further increasing costs. Import dependence: The global market is dominated by overseas manufacturers such as FormFactor and Technoprobe (CR3 exceeding 56%), with domestic manufacturers accounting for less than 5%.

[0005] 2. High degree of customization drives up overall costs Individual die pinouts, spacing, and current characteristics must be individually designed, resulting in lengthy development cycles and the inability to reuse components. The supporting precision substrates (such as LTCC / MLC ceramics) must be imported from Japan and South Korea (Kyocera, NTK), further increasing costs.

[0006] 2. Vulnerability and Maintenance Challenges: Fragility of Precision Structures 1. The probe is easily worn out and its lifespan is restricted by multiple factors. Mechanical wear: Frequent contact between the probe tip and the pad can cause wear and tear, especially when testing high-current chips, where aluminum powder adheres and accelerates wear. Cantilever probes, due to their steep design angles and varying depths, are more susceptible to pad damage.

[0007] Operational sensitivity: Collision, overpressure (e.g., raising the wafer stage too quickly), and improper maintenance (excessive grinding force) can all cause the needle tip to bend or break. Typical lifespan is measured in touchdowns (TD), but actual lifespan in high-power testing scenarios is often lower than the theoretical value.

[0008] Environmental sensitivity exacerbates performance degradation Oxidation and contamination: Tungsten probes are easily oxidized when exposed to air for a long time, which increases the contact resistance; the adhesion of aluminum powder, ink or dust causes signal distortion.

[0009] Thermal deformation: During multi-temperature testing (-55°C to 150°C), substrate coefficient of thermal expansion (CTE) mismatches can cause deformation, leading to probe misalignment or poor contact. For example, at low temperatures, ceramic substrate contraction can pull the probe away, causing an open or short circuit.

[0010] 3. Testing Efficiency Bottleneck: Insufficient Parallel Capability and Adaptability 1. Limited parallel testing capabilities The number of small and medium-sized dies is enormous, but the number of sites (the number of dies tested simultaneously) on a single probe card is limited by the probe density. While MEMS probe cards support high density (probe pitch < 40 μm), they are extremely costly and complex to debug.

[0011] During wafer edge testing, the probe card can deform the PCB due to uneven force (e.g., only 1 / 3 of the sites are in contact), requiring frequent pauses for adjustments, which reduces efficiency.

[0012] 2. Time-consuming line replacement and maintenance Switching product models requires replacing the probe card, which takes several hours to several days on average. Maintenance also requires nitrogen cabinet storage, regular tip polishing, and contact resistance calibration (<0.5 Ω), which occupies production resources.

[0013] 4. Accuracy and Reliability Risks: The Challenge of Test Consistency Contact consistency is difficult to ensure When the tip height difference is greater than 30 μm, some probes may miss the pad (open circuit) or over-press the aluminum layer (short circuit), leading to misjudgment. Due to structural limitations of cantilever probes, the probe mark is large and the number of retests is limited. This reduces the yield of the same wafer after multiple tests.

[0014] Signal integrity risks During high-frequency testing (>1 GHz), changes in probe resistance / inductance cause signal attenuation or crosstalk, affecting the timing tolerance measurement accuracy of small and medium-sized dies.

[0015] 5. High supporting requirements: equipment and operation dependence 1. Dependence on precision equipment The system requires a high-precision probe station (for sub-micron positioning) and an ATE tester, costing over a million US dollars. Domestic probe stations lack sufficient positioning accuracy, leading to reliance on Japanese equipment (such as Tokyo Seimitsu).

[0016] 2. High operational complexity Professional training is required to avoid operational errors (such as not installing the needle tip protection cover or raising and lowering the Z axis too quickly). Debugging relies on experience (such as anticipating thermal shrinkage offset when soldering needles).

[0017] The shortcomings of probe cards in large-scale wafer testing are essentially the contradiction between "high precision requirements" and "large-scale application": Economical shortcomings: High customization, short lifespan, and strong reliance on imports drive up testing costs, especially for small and medium-sized dies (where testing costs per die are even higher). Technical risks: Precision structures are fragile, sensitive to temperature changes, and have low operational tolerance, threatening test stability.

[0018] The high cost and precision of probe cards remain barriers that must be overcome for industrial upgrading.

[0019] Therefore, there is an urgent need to provide an efficient detection method for small and medium-scale integrated circuit chips on large-size wafers that does not rely on or reduces reliance on probe card test equipment. Summary of the Invention

[0020] The main technical solutions for achieving the purpose of the present invention are: An in-situ detection method for integrated circuit dies based on on-wafer buses comprises the following steps: S0: Design and produce small and medium-scale integrated circuits on large-size wafers. S1: Using the random sampling method of CN2025104433471, randomly test the dies in situ before wafer dicing; complete the in-situ testing of the entire production batch of wafers piece by piece; S2: Wafer cutting and packaging are performed according to the test results. During the cutting process, the on-chip bus (including tri-state gates) set in the cutting lanes are cut and discarded.

[0021] In step S0, all dies are arranged in a determinant-column pattern on the wafer surface, covering all available areas except the edges. Cutting lanes are reserved between the dies in each row and column for later wafer cutting. At the same time, an on-chip bus with addressing function is inserted into the cutting lanes in each row and column, connecting all dies through the bus. Each lead of each die is connected to the bus. Each die on the wafer is connected to a test circuit via a bus, so that the test circuit can be located at a specific die during electrical testing. In particular, the on-chip bus within the dicing lane is cut and discarded after the test is completed.

[0022] In the present invention, the core steps of producing small- and medium-scale integrated circuits (dies) on large-size wafers are briefly summarized as follows: 1. Wafer preparation: Clean and polish silicon wafer substrates.

[0023] 2. Oxidation / deposition: Generate insulating layer or functional film.

[0024] 3. Photolithography: Apply photoresist → Expose → Develop to form circuit patterns.

[0025] 4. Etching / ion implantation: Etching the material according to the pattern or implanting ions to change the conductivity.

[0026] 5. Metallization: Deposition of interconnect wires (such as aluminum / copper), repeated photolithography + etching in multiple layers.

[0027] 6. On-chip in-situ testing: Use the on-chip bus to randomly address and locate a single chip (Die) using a randomization function to test its functionality.

[0028] 7. Dicing and packaging: Discard unqualified dies and package the remaining dies.

[0029] Circuit manufacturing is completed by repeatedly patterning (photolithography + etching) to superimpose device layers and wire layers.

[0030] In step S1, in order to solve the problem of efficient detection of small and medium-scale integrated circuit chips on large-size wafers, the present invention is based on the random sampling method of CN2025104433471. The core of this method is to detect some chips (Die) on the wafer by random sampling, and statistically analyze the process reliability based on the detection results of different areas. On this basis, the probability of random sampling is adjusted dynamically: the frequency of random sampling is reduced in areas with high reliability, and the frequency of random sampling is increased in areas with low reliability. At the same time, a penalty and reward mechanism is introduced to "punish" areas with poor reliability by increasing the frequency of random sampling, and to "reward" areas with high reliability by reducing the frequency of random sampling. Through this optimized sampling strategy and test process, the present invention can significantly improve detection efficiency and reduce production costs while ensuring detection accuracy, and is particularly suitable for efficient detection scenarios of large-size wafers.

[0031] It should be noted that the present invention does not make a specific definition or limitation on "large-scale wafers" or "small- and medium-scale integrated circuits." However, it should be noted that the technical solution of the present invention is applicable to small- and medium-scale integrated circuit testing on large-scale wafers, and is limited to: a large number of dies distributed on a wafer. The more dies there are, the more applicable the technical solution of the present invention is; conversely, the fewer dies there are, the less applicable the technical solution of the present invention is. Preferably, the number of dies distributed on a wafer reaches more than one thousand. More preferably, the number of dies distributed on a wafer reaches more than ten thousand.

[0032] The testing method of the present invention specifically comprises the following steps: 1. Random sampling test: A certain number of dies are randomly selected from large wafers for functional testing. This random selection relies on a specific controlled parameter-based randomization function. Dies are sampled and tested in situ before wafer dicing based on this controlled parameter-based randomization function.

[0033] The test contents include electrical performance, logical functions, etc. to ensure that the die meets the design requirements.

[0034] 2. Statistical Analysis Based on the test results, the process reliability of different areas on the wafer is statistically analyzed.

[0035] Divide the wafer into several areas and calculate the qualified rate and unqualified rate of each area; Or the wafer can be divided into several areas according to the pass rate.

[0036] 3. Dynamically adjust the sampling probability: For areas with high reliability (high pass rate), reduce the probability of random inspections and the frequency of testing.

[0037] For areas with low reliability (low pass rate), increase the probability of random inspections and the frequency of testing.

[0038] By setting reward and punishment functions, the sampling strategy can be dynamically adjusted: Penalty: Increase the frequency of random inspections in areas with high failure rates.

[0039] Reward: For areas with high pass rates, reduce the frequency of random inspections.

[0040] 4. After each wafer is tested, return to step 1 and complete the in-situ testing of the wafers for the entire production batch piece by piece.

[0041] 5. In-situ testing and cutting packaging: Before wafer dicing, in-situ testing is completed and unqualified dies are marked based on the test results. After dicing, unqualified dies are directly discarded and the remaining dies are packaged.

[0042] In the present invention, the technology for in-situ testing of dies on wafers adopts existing technology. For example: The core principle of on-wafer in-situ testing is to electrically connect the die on the wafer through a probe card, and test the electrical performance and function of the die one by one or in batches. During the test, the probes on the probe card contact the pads of the die. The test equipment applies a test signal to the die through the probe card and reads the response signal of the die to determine whether the die meets the design requirements. The test equipment connects to each die in turn through the probe card to perform electrical performance tests, functional tests, etc. After the test is completed, the qualified dies are marked and cut for packaging, and the unqualified dies are discarded.

[0043] During in-situ testing of integrated circuit dies on wafers, the test equipment electrically connects to each die's pads via a probe card, sequentially performing electrical performance and functional tests. Electrical performance testing primarily involves measuring die parameters such as voltage, current, and resistance to ensure their electrical characteristics meet design requirements. Functional testing verifies the proper functioning of the die's logic by inputting specific test signals. The test equipment automatically completes these test steps according to pre-set test procedures and records the test results for each die.

[0044] After the test is completed, qualified dies will be marked as "passed" and unqualified dies will be marked as "failed". The marking method is usually through laser marking or ink marking on the surface of the wafer to distinguish qualified from unqualified dies in the subsequent cutting and packaging process. After marking is completed, the wafer enters the cutting process, and precision cutting equipment is used to separate each die from the wafer. Qualified dies will be sent to the packaging process for steps such as wire bonding and plastic sealing, and eventually become usable chip products. Unqualified dies will be directly discarded to avoid entering the subsequent production links, thereby reducing resource waste and production costs.

[0045] Since this is a prior art well known to those skilled in the art, it will not be described in detail here.

[0046] A further improvement of the present invention is that: combining the characteristics of semiconductor production technology, optimizing the random sampling function, further improving the efficiency of Die detection, and better balancing the accuracy, comprehensiveness and economy of detection.

[0047] Its technical principles have been fully explained in CN2025104433471, and the relevant content is considered part of this application and will not be repeated here. The present invention has achieved significant beneficial technical effects in many aspects through innovative detection methods and strategies:

[0048] 1. Detection efficiency is significantly improved

[0049] Physical probes must contact each die's pad individually, limiting the number of probes required (typically testing <100 dies at a time), making this essentially a serial / small-batch test. Probe card testing time increases linearly with the number of dies (for example, testing thousands of dies on an 8-inch wafer takes hours). However, the on-chip bus technology of this invention allows for simultaneous activation of entire rows / columns of dies via address broadcast (e.g., testing 128 dies at once). It also allows for grouping and parallel testing: the wafer can be divided into multiple logical blocks for simultaneous testing (e.g., four-quadrant parallel testing). This reduces test time to 1 / 10-1 / 20 of that of traditional methods (e.g., testing a full wafer in just minutes).

[0050] Traditional chip testing methods rely on individual testing. A large wafer may contain tens of thousands of chips, and testing each one individually can take days or even weeks. This invention, however, employs randomized sampling testing technology, performing functional testing on only a subset of chips and inferring the process reliability of the entire wafer through statistical analysis. This approach significantly reduces the number of tests and significantly shortens testing time. Furthermore, the strategy of dynamically adjusting the probability of random inspections allows testing resources to be concentrated on areas with lower reliability, avoiding overtesting of high-reliability areas and further optimizing testing efficiency.

[0051] 2. Zero contact delay

[0052] The probe card requires mechanical positioning and pressure calibration (single-point contact takes 10-50 ms). The on-chip bus is addressed by electrical signals, and switching the die address only takes microseconds.

[0053] 3. Improved precision and reliability

[0054] Using probe cards presents the following pain points: Probe scratches can damage pads, leading to package bonding failure (copper pads are particularly susceptible to deformation). Incomplete probe cleaning can introduce contaminants (such as carbon particles), creating the risk of electrical shorts.

[0055] The on-chip bus solution of the present invention can achieve contactless testing: the signal is transmitted through metal wires without mechanical contact, completely eliminating physical damage. It can also achieve environmental isolation: the bus is covered with a passivation layer to prevent dust and oxidation.

[0056] Furthermore, the present invention optimizes signal integrity: the long leads (>5 cm) of the probe card introduce inductive / capacitive parasitic effects, resulting in high-frequency signal distortion (e.g., >1 GHz test error of 10%). However, the on-chip bus wiring is short (<20 cm at the wafer level) and can adopt differential signal design, supporting 10 GHz. + High-speed testing.

[0057] 4. Cost and scalability advantages

[0058] This invention dramatically reduces testing equipment costs. Probe cards are required for each chip, requiring a custom probe card (priced between 50,000 and 500,000 RMB per card) with a lifespan of only 100,000 to 500,000 contact cycles. The on-chip bus solution of this invention integrates the bus during wafer fabrication, eliminating additional hardware costs. The tester requires only basic probes contacting the wafer edge pads (a universal interface, eliminating the need for customization).

[0059] Adaptability to Advanced Processes: Probe card testing presents bottlenecks. The pads of heterogeneous integrated chips, such as 3D ICs and chiplets, are shrinking to the μm level, and probe positioning accuracy is approaching physical limits (the current minimum needle tip diameter is approximately 5 μm). The on-chip bus solution of this invention allows bus line width and spacing to scale with lithography processes (e.g., a 3 nm process can achieve a 24 nm line width), making it naturally adaptable to advanced processes. It also supports testing of 3D stacked wafers (the bus can vertically traverse TSVs).

[0060] 5. Test Depth and Flexibility In terms of internal node access, the probe card can only access the I / O pads of the die and cannot directly test the core logic; the on-chip bus connects to the internal scan chain of the die, which can directly inject test vectors and capture internal register states, locating faults to the transistor level.

[0061] In terms of dynamic power consumption testing, the dynamic current (IDDT) of the die is monitored in real time through the bus to accurately identify timing violations (such as path delay failures), which cannot be achieved by the probe card due to parasitic parameter interference.

[0062] 6. Yield Management Innovation

[0063] For early defect mapping analysis, the on-chip bus generates a real-time wafer defect distribution map (Wafer Map), combined with address location to identify systematic process defects (such as lithography hotspots and uneven etching). Traditional probe cards require post-process data analysis, which can be delayed by several hours.

[0064] Adaptive test flow: Dynamically adjusts subsequent test items based on real-time test results. Qualified dies skip redundant test items, shortening the process; defective dies trigger in-depth diagnostic mode, further improving test efficiency.

[0065] 7. Reduce production costs

[0066] The traditional method of testing each chip individually is not only time-consuming but also requires a large amount of testing equipment and manpower, increasing equipment depreciation, maintenance costs, and labor costs. By reducing the number of tests and optimizing the testing process, the present invention significantly reduces the use time and frequency of test equipment, reducing equipment depreciation and maintenance costs. At the same time, due to the significant reduction in testing time, labor costs are also reduced accordingly. Furthermore, the present invention completes testing before cutting and packaging, avoiding the packaging of unqualified chips and reducing waste during the packaging process.

[0067] 8. Optimize quality control

[0068] The present invention controls the missed detection rate within an acceptable range through reasonable algorithm design and process adjustments. For example, by dynamically adjusting the probability of random inspections and introducing a penalty and reward mechanism, it is possible to accurately locate areas with low reliability and increase detection efforts, thereby effectively reducing the possibility of missed detections. At the same time, combined with the characteristics of semiconductor processes, the present invention can control the missed detection rate to a very low level. In addition, the present invention can further reduce the potential risks of missed detections through business strategies. This optimized quality control strategy not only ensures product quality, but also improves the feasibility and reliability of the detection method.

[0069] 9. Enhanced process optimization feedback

[0070] By statistically analyzing the process reliability of different regions on the wafer, this invention can promptly identify problematic areas in the manufacturing process and provide feedback to the production process for adjustment and optimization. This real-time feedback mechanism helps engineers quickly locate process defects, reduce the chip rejection rate caused by process problems, and further improve overall production quality.

[0071] 10. Adapt to large-scale production needs

[0072] Through randomized sampling and dynamic adjustment strategies, this invention can efficiently process large numbers of chips on large wafers, making it particularly suitable for the high-density, large-scale production scenarios of modern semiconductor manufacturing. By optimizing the detection process and resource allocation, this invention not only improves detection efficiency but also reduces production bottlenecks caused by excessive detection time, providing a more competitive solution for semiconductor manufacturers.

[0073] 11. Environmental friendliness and sustainability

[0074] From a sustainable development perspective, this invention reduces energy consumption and equipment wear by shortening the use time and frequency of test equipment. It also reduces waste during the packaging process, further minimizing resource consumption and environmental impact during production. This environmentally friendly design not only aligns with the green development philosophy of modern manufacturing but also supports the sustainable development of enterprises.

[0075] In this invention, the essence of on-chip bus testing is to transform the test function from "external mechanical intervention" to "internal circuit integration": Spatial dimension: Using cutting paths to achieve wafer-level interconnection with zero area overhead. Temporal dimension: Address addressing enables microsecond-level die switching, breaking through the limits of mechanical motion. Information dimension: Direct access to internal nodes, looking through the chip's "black box." The on-chip bus is like implanting a sensor in every cell—real-time, accurate, and fully covered. This solution upgrades the testing process from "post-manufacturing screening" to "in-manufacturing monitoring," becoming a core technical fulcrum for improving semiconductor yield and reducing costs.

[0076] In summary, the technical solution of the present invention is mainly applicable to the testing of small and medium-scale integrated circuits on large-sized wafers. On large-sized wafers, due to the large number of dies, randomized sampling detection can significantly improve test efficiency and reduce production costs. At the same time, by dynamically adjusting the sampling probability, the missed detection rate can be controlled within an acceptable range. However, for small and medium-sized wafers and large-scale and ultra-large-scale integrated circuits, the limitations of the randomized sampling detection method are more obvious, with a high missed detection rate, limited improvement in test efficiency, and insufficient economic efficiency. Therefore, it is not suitable for these scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] Figure 1 : The on-chip bus covers the entire wafer surface to form a grid-like interconnection network.

[0078] Figure 2 : The on-chip bus is abolished after cutting. DETAILED DESCRIPTION

[0079] To facilitate understanding of the present invention, the technical solutions of the present invention are described below with reference to the accompanying drawings and specific examples.

[0080] To implement the method of the present invention, the overall steps are as follows: S0: Design and produce small and medium-scale integrated circuits on large-size wafers. S1: Using the random sampling method of CN2025104433471, randomly test the dies in situ before wafer dicing; complete the in-situ testing of the entire production batch of wafers piece by piece; S2: Wafer cutting and packaging are performed according to the test results. During the cutting process, the on-chip bus (including tri-state gates) set in the cutting lanes are cut and discarded.

[0081] In step S0, the core logic of arranging small- and medium-scale integrated circuits (DIEs) on a wafer is to maximize the use of the wafer area. The specific method is as follows: Repeated array arrangement: Dies are arranged closely and repeatedly on the wafer surface in exactly the same pattern (such as a checkerboard), covering all available areas except the edges.

[0082] Scribe line reservation: A narrow scribe line (about 50-100 μm wide) is reserved between dies for later wafer cutting and placement of test structures and alignment marks.

[0083] Edge rejection: The 3-5 mm area around the edge of the wafer is not used for effective die arrangement due to process non-uniformity (such as fluctuations in coating / etching thickness) and is only used as a buffer.

[0084] Test structure embedding: On-chip buses are inserted into the cutting lanes. The on-chip buses are used to connect the die and the test circuits to detect manufacturing defects.

[0085] Essential: Through high-density repeating units + cutting reserved area, a balance is achieved between wafer area utilization and cutting reliability. (For example, an 8-inch wafer can be arranged with thousands of small and medium-sized dies) All dies are arranged in a matrix on the wafer surface in exactly the same pattern, covering all available areas except the edges. Cutting lanes are reserved between the dies in each row and column for later wafer cutting. At the same time, an on-chip bus with addressing function is inserted into the cutting lanes in each row and column, connecting all dies through the bus. Each lead-out terminal of each die is connected to the bus. Each die on the wafer is connected to the test circuit through the bus, so that the test circuit can locate the specified die during electrical testing.

[0086] The die is connected to the test circuit via an on-chip bus. During wafer-level testing, the die implements test addressing and control via the on-chip bus (Test Bus) embedded within the dicing lanes. The specific implementation logic is as follows: 1. Bus physical structure

[0087] Wiring location: On-chip buses (usually metal lines) are embedded in the scribe lines, covering the entire wafer surface to form a grid-like interconnection network, see Figure 1 It should be pointed out that, in order to explain the technical principle of the present invention, Figure 1 Only a few dies are shown schematically in the figure, which does not mean that there are only such a small number of dies on the actual wafer.

[0088] In the on-chip bus used to test Die, the basic lines of the bus include: Power line (VDD / GND): provides test power supply.

[0089] Clock signal line (CLK): synchronizes test timing.

[0090] Data Bus: transmits test instructions and response results.

[0091] Address Bus: locates the row and column coordinates of the target Die (unique address).

[0092] Control line (Control): Enable / reset test mode.

[0093] 2.Die electrical connection

[0094] Lead-out terminal access: The test pads of each die extend into the cutting lanes through short metal wires (similar to bridges) and are physically connected to the bus.

[0095] Key connection points: Test Enable: Receives bus start command.

[0096] Address Matcher: Compares the address sent by the bus with its own coordinates (solidified by the photolithography mask).

[0097] Data interface (I / O): Bidirectional transmission of test signals.

[0098] As an example: When the bus sends the address X3-Y2, the address matcher of Die located at the 3rd column and 2nd row is activated and enters the test mode.

[0099] 3. Test circuit control flow

[0100] Test interface location: The test circuit module (PCM or TEG) is usually located at the edge of the wafer or at the intersection of the dicing lanes.

[0101] Addressing mechanism: Address broadcast: The tester sends the coordinate address of the target Die through the bus (such as binary code X=0011, Y=0010).

[0102] Die response: The address matchers of all dies monitor the bus at the same time, and only the dies with matching coordinates activate the test mode.

[0103] Instruction execution: The selected die receives test instructions (such as scan chain test, storage read and write), and the results are transmitted back to the tester through the data line.

[0104] Test Isolation: Unaddressed dies remain electrically disconnected to avoid interference.

[0105] 4. Key design optimization

[0106] Redundant design: The bus and die connection points adopt a double contact structure to prevent circuit breakage caused by cutting.

[0107] Signal repeater: Insert signal amplifiers into large wafers to avoid attenuation during long-distance transmission.

[0108] Test efficiency optimization: Parallel testing: Testing multiple dies simultaneously through group addressing (such as entire row / column activation).

[0109] Automatic Binning: Test results are directly marked with Die levels.

[0110] In the present invention, the functional test of integrated circuit dies uses an on-chip bus to replace the probe card equipment. The on-chip bus is essentially a simple communication network at the wafer level. It achieves precise test positioning through "address broadcast + target response", which not only avoids the need for separate test lines for each die (saving area), but also supports large-scale parallel testing, greatly improving wafer manufacturing and testing efficiency, while greatly reducing the cost of test equipment.

[0111] In the present invention, in the wafer design and production process, the construction of the on-chip bus (Test Bus) is a collaborative process of integrated design and manufacturing. The core goal is to "establish a wafer-level test network within the cutting lane to ensure that the bus automatically fails after cutting."

[0112] The following are the specific implementation steps: 1. Design Phase: Layout and Circuit Collaboration Cutting path space planning During the chip design (CAD) stage, a 20-100 μm wide cutting path is reserved and defined as the "test bus exclusive area."

[0113] Bus routing design: Horizontal bus: Power (VDD / GND), clock (CLK), and control signal lines are laid along the X direction of the wafer.

[0114] Vertical bus: Address lines and data lines are laid along the Y direction to form a grid structure.

[0115] Key optimization: Bus line width / spacing is compressed to the lithography limit (e.g., approximately 70nm in a 28nm process) to maximize the use of cutting path space.

[0116] Interface design between Die and bus Test pin extension: Design a micro-bump or metal probe at the edge of the die and bridge it to the bus within the cutting lane through a short lead (<5μm) (as shown in the figure).

[0117] Address solidification: Each die has an internal hardwired address decoder, and the coordinates are solidified by the photolithography mask (for example, the address of the die at position X3-Y2 is binary 0011_0010).

[0118] When the bus sends an address signal, only the Die that matches the coordinates activates the test mode.

[0119] Test circuit embedding: A test control module (TCM) is set at the intersection of the cutting lanes or the edge of the wafer, including signal drivers and result acquisition circuits.

[0120] The external probe area (Wafer Test Pads) is used to connect to the test machine.

[0121] 2. Manufacturing stage: process and structure realization Photolithography mask definition Bus-specific mask: Design bus patterns (metal traces, die connection points) in the cutting area and expose them synchronously with the chip circuit mask.

[0122] Multi-layer metallization process: Steps: Deposit an insulating layer in the cutting area → Photolithography bus pattern → Etching → Fill with copper (Damascene process) → Chemical Mechanical Polishing (CMP).

[0123] Process key: The bus must use the top layer of metal (such as Metal 10) to avoid short circuits with the underlying chip circuits.

[0124] Die bridge structure manufacturing Metal “bridge” etching: High-precision photolithography is used to create cantilevered metal leads (0.1-0.5 μm in width) between the die edge and the cutting path to achieve electrical connection.

[0125] Insulation protection layer: A silicon nitride passivation layer is deposited over the bus and bridge lines to prevent contamination and short circuits.

[0126] Step S1 is mainly implemented as follows: Step S10: After a certain batch of wafers has completed chip production, a wafer from the batch is selected and all dies are inspected one by one in situ before wafer dicing. Based on the above test results, the process reliability of different areas on the wafer is statistically analyzed. Based on the statistical analysis results, the parameters of the controlled parameter randomization function are initialized. It should be noted that when initializing the parameters, the initialization principle of the parameters is: For areas with high reliability (high pass rate), set a smaller randomization function density, that is, reduce the probability of random inspection; For areas with low reliability (low pass rate), set a larger randomization function density, that is, increase the probability of random inspection; At the same time, if the above statistical results show that there are significant differences in chip defect density in different areas, and the chip defect density in a certain area or certain areas is greater than a certain threshold, for example, the die rejection rate in a certain edge area of ​​the wafer is higher than 20%, then it means that the production process has intolerable defects. Subsequent testing can be stopped and the process flow can be returned to readjust process parameters or repair equipment. If the statistical results show that the chip defect density in each area is roughly the same, but the overall die yield is lower than a preset threshold, for example, the yield of all dies on the wafer is lower than the preset target yield of 90%, it also indicates that there are defects in the production process and it does not meet the expected process goals. Subsequent testing can also be stopped and the process flow can be returned to readjust process parameters or repair equipment. It should be pointed out that the target qualification rate here can be determined by the factory based on factors such as the semiconductor production process and the economic tolerance qualification rate. Different process technologies should have different target qualification rates, which are also closely related to market demand. The "failure rate is higher than 20%" and "preset target qualification rate is 90%" mentioned in the example above are merely examples and are not restrictions on the technical solution.

[0127] Of course, step S10 can also be implemented as follows: regularized sampling for die detection. Regularized sampling here refers to sampling and testing dies at regular intervals in both the horizontal and vertical directions. For example, every other die sampled is tested, every other die sampled is tested, or every third die sampled is tested. The specific interval selection can be determined based on the number of dies on each wafer. If the number of dies is large, such as tens of thousands of dies, the interval number can be appropriately increased.

[0128] After completing the above tests and analyses on the selected wafers, if the die pass rates in each area are within an acceptable range, the next step of testing is entered: Step S11: Setting a controlled parameter-containing randomization function, the parameters of which are initialized by step S10; sampling and detecting Die in situ according to the controlled parameter-containing randomization function before wafer dicing; For example, If all the dies on a wafer undergo routine inspection, the statistical results show that the pass rate of a certain edge area is about 96%, recorded as area A; the die pass rate of the remaining areas is higher than 99%, recorded as area B. Then a controlled parameter-containing randomization function can be set so that the random sampling probability of area A is 25%, and the random sampling probability of area B is 10%.

[0129] Of course, the random sampling probability settings for different regions are merely illustrative. Specific parameter settings can be determined based on the tolerable unqualified die miss rate and the market compensation mechanism. If the unqualified die miss rate requirement is low, the random sampling probability can be appropriately reduced; otherwise, it can be appropriately increased. If the final market value of a single integrated circuit product is low and the market compensation ratio is high, the random sampling probability can also be appropriately reduced.

[0130] In the above example, a controlled parameter-containing randomization function can also be set so that the random sampling probability of area A is 40% and the random sampling probability of area B is 15%; or, the random sampling probability of area A is set to 30% and the random sampling probability of area B is set to 5%; or, more strictly, the random sampling probability of area A is set to 60% and the random sampling probability of area B is set to 25%; These values ​​can be selected in accordance with the economic principle based on actual needs.

[0131] The controlled parameter-containing randomization function can use various randomization functions in the prior art. All existing programming languages ​​contain pseudo-random functions for generating random decimals with a uniform probability distribution between 0 and 1. In the present invention, it is entirely possible to directly borrow existing random functions and appropriately package and transform them to meet the above requirements. Its working principle / mechanism has been fully and clearly explained in our prior application CN2025104433471, so there is no need to waste space here. In this way, the predetermined Die set to be detected in the pointing area can be randomly determined.

[0132] Preferably, after setting the controlled parameter-containing randomization function and determining the predetermined Die set to be detected in the pointing area, it is verified whether the predetermined Die to be detected in the pointing area is too concentrated. If it is too concentrated, the predetermined Die to be detected in the pointing area is further randomized to enhance / improve the uniformity of the random distribution of the Die to be detected.

[0133] The present invention also provides another method for implementing a controlled parameter-containing randomization function, that is, when the Die pass / fail rate of the specified area and the random sampling probability of area A have been determined in the previous step, the predetermined number of Dies to be detected in the pointed area can be pre-calculated based on the number of Dies in the specified area and the random sampling probability of area A as the input parameter of the controlled parameter-containing randomization function, and the predetermined Die set to be detected in the pointed area can be randomly determined through the controlled parameter-containing randomization function.

[0134] Let's use the example mentioned above to explain. If the wafer is pre-divided into five areas, A, B, C, D, and E, and the die qualification rate in area A is about 95%, that is, the die rejection rate in this area is 100% - 95% = 5%, and the number of dies in area A is 400, and the random sampling probability of area A is set to 25%, then the number of dies scheduled to be inspected in area A can be calculated as 400 × 25% = 100.

[0135] The input parameters of the controlled parameter randomization function are set to 400 and 100, and the 100 predetermined Dies to be detected are randomly distributed among the 400 Dies through the controlled parameter randomization function.

[0136] There are two methods for dividing the areas on the wafer: First, divide the area approximately evenly according to its area; In the present invention, two specific segmentation methods can be provided: a. Using the wafer center as the origin, divide the wafer into equal-angle regions, i.e., use polar coordinates to divide the regions into equal-angle regions. b. Using the wafer center as the origin, divide the regions into equal intervals on the horizontal and vertical coordinates, i.e., divide the regions into equal intervals using plane rectangular coordinates; The so-called "approximately uniform" here actually means "uniform", and the "approximate" mainly takes into account the particularity of the wafer edge.

[0137] Second, the process reliability of different regions on the wafer is divided into high and low regions according to the statistical analysis in step S10; For example, according to the die qualified rate of different areas on the wafer, it can be divided into two areas of high and low; or divided into three areas of high, medium and low; or divided into five areas of high, relatively high, medium, relatively low and low. For specific implementation examples, please refer to the examples in our prior application CN2025104433471, the content of which is considered part of this application and will not be repeated here. It should be pointed out in particular that no matter which of the above implementation methods is adopted, the present invention will subsequently map the predetermined die position to be detected in the determined pointing area to the actual position of the wafer for the test device to detect the corresponding die. This is a routine skill possessed by those skilled in the art and will not be elaborated here.

[0138] After the area is divided, different reward and punishment functions are used in different areas for detection in subsequent steps.

[0139] Step S12: Based on the test results of S11, statistically analyze the process reliability of different areas on the wafer.

[0140] It should be noted that although all dies are individually tested in situ before wafer dicing in step S10, and the process reliability of different regions on the wafer is statistically analyzed based on the test results, this does not mean that the regional distribution of die reliability for all wafers of the process is completely consistent. This is because semiconductor processes have random defects and systematic defects, regional and process fluctuations, and batch-to-batch differences, which lead to inconsistency in the regional die reliability of different wafers. Because the uniformity of process steps such as lithography, etching, and deposition during the manufacturing process is difficult to fully guarantee, the process conditions in the edge area of ​​the wafer are usually more unstable than those in the center area, resulting in a higher defect density in the edge area. This phenomenon is called the "edge effect." Process fluctuations (such as temperature, gas flow, pressure, etc.) can cause parameters such as film thickness and doping concentration in certain areas of the wafer to deviate from the designed values, thereby forming local high-defect areas.

[0141] Therefore, the distribution of defective dies obtained during the randomized sampling inspection in step S11 will be continuously incorporated into statistical work, expanding the statistical sample size and continuously improving the accuracy of the statistical analysis of process reliability in different areas on the wafer. This will then be used to fine-tune the parameters of the controlled parameter-containing randomization function called during the next sampling inspection, thus proceeding to the next step S13.

[0142] Step S13: adjusting the parameters of the aforementioned randomization function according to the analysis results of step S12, dynamically adjusting the probability of random inspections in different areas, or dynamically adjusting the division of areas; For example, In step S10, after inspecting all dies on a wafer one by one, statistical analysis shows that the die pass rate in some areas is approximately 97%, which is defined as area A. The die pass rate in the remaining areas is higher than 99%, which is defined as area B. Based on this, the random sampling probability of area A is set to 30%, and the random sampling probability of area B is set to 10%. Based on the above settings, random sampling is performed on the next wafer in step S11; Step S13: The defect die distribution on the wafer is statistically analyzed again, and the test results of the previous wafer are combined and statistically analyzed to obtain the overall defect die distribution. Based on the overall defect die distribution, adjustments are made to area A and area B. After the adjustment, random sampling is continued on subsequent wafers to obtain the defect die distribution on the subsequent wafers. The results are combined with the overall results of the previous wafer test and statistically analyzed again to obtain a new overall defect die distribution. Based on the new overall defect die distribution, adjustments are made to area A and area B again. This process is continued so that the division of area A and area B is constantly updated and continues to approach the actual situation and is more accurate.

[0143] In step S13, in addition to dynamically adjusting the division of regions, the probability of random inspections in different regions may also be dynamically adjusted based on the results of the statistical analysis again.

[0144] Preferably, the division of regions and the probability of random inspections in different regions can also be dynamically adjusted simultaneously.

[0145] Preferably, if the statistical analysis results of the next wafer show that the die yield of the adjacent area of ​​area A has decreased, the scope of area A is appropriately expanded; otherwise, the scope of area A is appropriately reduced. This helps to inspect wafers more accurately and efficiently, achieving a dynamic balance between inspection efficiency and inspection accuracy.

[0146] Step S14: After each wafer is tested, return to step S11 to complete the in-situ testing of the wafers of the entire production batch piece by piece; Step S15: cutting and packaging the wafer according to the test results.

[0147] In step S15, unqualified dies are marked according to the test results; then the wafer is cut and only qualified dies are packaged, while unqualified dies are discarded.

[0148] In the present invention, different reward and penalty functions are used in the different areas mentioned above, and their specific meanings are explained as follows: For areas with high reliability (high pass rate), set a smaller randomization function density, that is, reduce the probability of random inspection; For areas with low reliability (low pass rate), set a larger randomization function density, that is, increase the probability of random inspection; After inspecting the next wafer and combining the statistical analysis of defective die distribution, if the die yield in a certain area increases, the randomization function density of that area is reduced, that is, the probability of random inspection in that area is reduced. If the Die qualified rate in a certain area decreases, then the randomization function density of the area is increased, that is, the probability of random inspection in the area is increased; Optionally, a more specific implementation method is: the randomization function density (spot check probability) can be selected to be in a negative linear proportional relationship with the Die qualified rate in a certain area, that is, the randomization function density (spot check probability) can be in a linear proportional relationship with the Die unqualified rate in a certain area.

[0149] That is, the reward and penalty function can be set as follows: randomized function density (spot check probability) = k·Die failure rate, where k is a preset constant coefficient. For a specific example, please refer to the prior application CN2025104433471.

[0150] Alternatively, a more specific implementation method is to select a nonlinear proportional relationship between the randomized function density (spot check probability) and the Die failure rate in a certain area, such as a square relationship or an exponential relationship. For example: randomized function density (spot check probability) = k'·Die failure rate 2 , where k' is also a preset constant coefficient.

[0151] Clearly, this nonlinear reward-penalty function is intended to implement more stringent spot checks in areas with increased die rejection rates. This means stricter "punishment" and monitoring of these areas, minimizing the risk of unqualified dies entering the next production process and maximizing inspection accuracy. Regions with high pass rates are then "rewarded," significantly reducing the probability of spot checks and improving die inspection efficiency on large wafers.

[0152] The exponential relationship will not be described in detail here. Those skilled in the art should be able to understand how to implement it based on the above two examples.

[0153] It is worth noting that, as can be seen from the various embodiments of the present invention, even for areas on the wafer with a high die yield, a low randomization function density (spot check probability) is still implemented. This is based on the characteristics of the semiconductor manufacturing process, namely, random defects always exist in the semiconductor process. For example, the air in the clean room still contains extremely low concentrations of evenly distributed dust, which may cause die defects on the wafer during the manufacturing process. Such defects are evenly distributed and random. In the present invention, a lower limit on the spot check probability is always maintained, which helps to deal with such random defects and reduce the possibility of missed detection.

[0154] In addition, when the die rejection rate in a certain area on the wafer is higher than a certain threshold, one of the following measures can be taken: (1) Detect all Dies in the area one by one; (2) Return to the design stage and / or production stage to check for design defects or process defects.

[0155] The specific method to be adopted can also be reasonably selected based on the actual situation.

[0156] In mature chip production processes, random defects usually appear as very few and evenly distributed tiny defects. Such defects are usually caused by factors such as particle contamination, minor equipment failures or material inhomogeneities during the manufacturing process, and their distribution is random and will not be concentrated in a specific area of ​​the wafer. Since the number of these random defects is small and the distribution is even, the randomized sampling detection method can effectively control the missed detection rate under mature process conditions without significantly affecting the overall product quality. The specific technical principles, defect distribution characteristics, rationality of sampling detection, etc. have been discussed in detail in our prior application CN2025104433471. The relevant content is considered part of this application and will not be repeated here.

[0157] In step S2, wafer dicing is the core process of separating the finished wafer into individual dies. Its core goal is to achieve efficient separation without damaging the circuits. The specific process and technical points are as follows: 1. Preparation before cutting Wafer thinning (Back Grinding) Use a grinder to grind the backside of the wafer to the target thickness (usually 100 μm - 500 μm) to improve cutting efficiency and meet packaging requirements.

[0158] Tape Mounting The front side of the wafer is covered with UV tape (blue film) to fix the die position and prevent it from shifting after cutting.

[0159] 2. Cutting process implementation method (1) Blade Dicing How it works: A high-speed rotating diamond blade (30,000-50,000 RPM) mechanically cuts the silicon.

[0160] Key parameters: Blade thickness: 20-50 μm (needs to be slightly larger than the cutting width) Cutting depth: penetrate the wafer and cut into the blue film 10-20 μm Advantages: Mature process, low cost, suitable for small and medium-sized chips. Disadvantages: Mechanical stress can easily lead to edge chipping and damage the low-k dielectric layer.

[0161] (2) Laser Dicing Principle: Stealth Dicing: Focused laser forms a modified layer (thermal stress crack) inside the wafer, and the die is separated by film expansion.

[0162] Ablation Dicing: A high-energy laser directly vaporizes the material to form the cut grooves. Advantages: No physical contact, zero edge chipping damage, and the cut width can be reduced to <15 μm. Disadvantages: High equipment cost, suitable for high-density chips.

[0163] (3) Plasma Dicing Principle: Deep reactive ion etching (DRIE) etches vertically through the wafer from the front. Advantages: Straight cuts, no mechanical or thermal stress, and the fastest cutting speed. Disadvantages: Requires an additional mask (photoresist), resulting in high cost. Suitable for ultra-thin wafers (<100 μm).

[0164] 3. Post-cutting processing Dicing Tape Expansion: Stretching the blue film increases die spacing for easier pickup. Cleaning: Silicon debris is removed using deionized water or ultrasound. Defect Detection: Optical scanning identifies edge chipping or microcracks.

[0165] In this invention, the on-chip test bus embedded within the scribe line is a key innovation in wafer-level testing. Its core value lies in "full interconnection during the test phase and physical isolation after dicing," ensuring perfect compatibility between testing and packaging requirements. The following is its implementation logic and technical essence: In the present invention, the essence of the wafer's on-chip bus is a temporary neural network. Its functional positioning is: the bus in the dicing lane is essentially a wafer-level temporary communication network, like a "neural network" covering the wafer. Its connection logic is: All die test pins extend to the dicing lanes via micron-scale metal traces, physically connecting pads or vias to the bus. The bus forms a grid of intersecting rows and columns within the dicing lanes, converging to test pads at the wafer edge. External testers access the bus via probe cards.

[0166] In this invention, the core value of the wafer's on-chip bus is that it eliminates the need for separate test lines for each die, saving wafer area (the dicing lane width is only 20-100 μm). Bus addressing enables precise test positioning of any die.

[0167] During the test phase, the wafer's on-chip bus enables full wafer linkage. Signal broadcast mechanism: The tester sends address codes (e.g., binary row and column coordinates X=000110, Y=010010) via the bus. All dies have built-in address decoders, and only the target die activates test mode.

[0168] Test execution: Test instructions (such as current / functional scan) are transmitted to the target die via the bus. Test results are transmitted back to the tester via the same bus, automatically marking defective dies.

[0169] The wafer's on-chip bus improves test efficiency: Parallel testing: Entire rows / columns of dies can be tested simultaneously via bus grouping. Fast binning: Test data is directly divided into chip performance levels (such as high-speed / low-speed bins).

[0170] Implement physical isolation bus in the cutting process "Precise destruction" of cutting: The cutting tool (blade / laser) penetrates the wafer along the center line of the cutting path and simultaneously cuts off the bus metal layer. The bus physical structure is divided into disconnected fragments (such as Figure 2 shown).

[0171] Automatic electrical isolation after cutting: After cutting, the bus is broken and the test terminals of each die are permanently disconnected from the outside world. The functional circuits of the die itself are completely unaffected - the bus is only connected to the test pins and is isolated from the core circuit.

[0172] Residue treatment: Bus fragments (length <100 μm) remaining in the dicing lanes are attached to the chip edge but have no electrical function: the fragments are broken at both ends and cannot form a circuit.

[0173] No size interference: The width of the fragments is much smaller than the chip size and is covered or cut off by the plastic packaging material during packaging.

[0174] 4. Package compatibility: clever spatial isolation Hidden Design: The dicing streets correspond to the die edge's dicing area, which is located inside the lead or plastic package during packaging. Bus residues are completely encapsulated by the packaging material, eliminating the risk of exposure.

[0175] Electrical Insulation: The UV curing properties of the dicing tape allow the chips to separate automatically after dicing, creating air insulation between the bus fragments. If laser cutting is used, the high temperature will oxidize the metal layer, further increasing the insulation.

[0176] "Self-destruction mechanism" during the cutting phase Physical removal: The cutting blade / laser penetrates the wafer along the centerline of the cutting lane, simultaneously cutting off the on-chip bus metal layer and bridge wires: Failure protection design: Redundant breaking points: The bus is designed with a neck-narrowing structure every 200μm within the cutting lane (the width is reduced by 30%) to ensure that the cutting stress breaks first at this point.

[0177] Electrical isolation: The metal fragments (<10 μm) remaining at the edge of the die after cutting have no electrical connection path and are covered by the encapsulation glue.

[0178] The technical essence of this invention lies in expendable wafer-level interconnection. The on-chip bus is a model of "spatial reuse + phased functionality": Space strategy: Occupy the cutting path area that needs to be removed and increase the test function at zero area cost.

[0179] Time strategy: It only serves the testing needs of the wafer manufacturing stage, and the interconnection is automatically disconnected through physical cutting after completion.

[0180] Design for failure: The cutting process serves as both a separation method and a triggering mechanism for bus failure, without the need for additional operations.

[0181] Analogy: It's like scaffolding in a building - it provides support during the construction phase and is removed without leaving a trace after completion.

[0182] This design achieves a perfect combination of test efficiency (full-wafer addressing) and chip independence (package purity), and is the crystallization of wisdom for resource optimization in semiconductor manufacturing.

[0183] In summary, in mature chip production processes, random defects are usually few in number, evenly distributed, and have little impact. Therefore, the randomized sampling detection method can effectively control the missed detection rate without significantly affecting the overall product quality. By randomly selecting test samples, statistically analyzing process reliability, and dynamically adjusting the sampling probability, the randomized sampling detection method significantly improves test efficiency and reduces production costs while ensuring test accuracy. This technical principle makes the randomized sampling detection method of the present invention have broad application prospects in mature semiconductor production processes.

[0184] The foregoing description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be readily conceived by a person skilled in the art within the technical scope disclosed in the present invention are intended to be covered by the scope of protection of the present invention. Any matters not described in detail in this specification constitute prior art known to those skilled in the art.

Claims

1. A method for in-situ detection of integrated circuit die based on on-wafer bus, characterized in that The steps include: S0: Design and produce small and medium-scale integrated circuit dies on large-size wafers, characterized by: All dies are arranged in a repeating matrix on the wafer surface in the same pattern, covering all available areas except the edges. Die lanes are reserved between rows and columns for later wafer dicing. An on-chip bus with addressing function is inserted into the dicing lanes in each row and column, connecting all dies through the bus. Each lead-out terminal of each die is connected to the bus. Each die on the wafer is connected to the test circuit via a bus, so that the test circuit can be located at the specified die during electrical testing; the on-chip bus within the dicing lane is cut away after the test is completed; S1: Using the random sampling method of CN2025104433471, randomly test the dies in situ before wafer dicing; complete the in-situ testing of the entire production batch of wafers piece by piece; S2: Wafer cutting and packaging are performed according to the test results. During the cutting process, the on-chip bus (including tri-state gates) set in the cutting lanes are cut off.

2. The method according to claim 1, wherein: Preferably, the production of small- and medium-scale integrated circuit dies on large-size wafers means that the number of dies distributed on a wafer reaches more than one thousand; More preferably, producing small and medium-scale integrated circuit dies on a large-size wafer means that the number of dies distributed on a wafer reaches more than 10,000.

3. The method according to claim 1, wherein: The width of the cutting line is between 20-100 μm.

4. The method according to claim 1, wherein: In S2, unqualified dies are marked according to the test results; then the wafer is cut, the unqualified dies are discarded, and the remaining dies are packaged.

5. The method according to claim 1, wherein: By setting up an on-chip bus within the dicing lanes and establishing a wafer-level test network, the bus is automatically disabled after dicing. A "self-destruct mechanism" for the on-chip bus is implemented during the dicing phase to complete phased functions. This expendable wafer-level interconnection exemplifies "spatial reuse + phased functions." Space strategy: Occupy the cutting lane area that needs to be removed, and increase the test function at zero area cost; Time strategy: Only serves the testing needs of the wafer manufacturing stage, and automatically disconnects the interconnection through physical cutting after completion; Design for failure: The cutting process serves as both a separation method and a triggering mechanism for bus failure, without the need for additional operations.

6. The method according to claim 1, wherein: Step S1 is specifically as follows:

1. Design Phase: Layout and Circuit Collaboration Cutting path space planning During the chip design (CAD) phase, a 20-100μm wide cutting lane is reserved, which is defined as the "test bus exclusive area"; Bus routing design: Horizontal bus: Power (VDD / GND), clock (CLK), and control signal lines are laid along the X direction of the wafer; Vertical bus: Address lines and data lines are laid along the Y direction to form a grid structure; Key optimization: compressing bus line width / spacing to the lithography limit (e.g., approximately 70 nm in a 28 nm process) to maximize the use of scribe line space; Interface design between Die and bus Test pin extension: Design a micro pad or metal probe at the edge of the die and bridge it to the bus within the dicing lane through a short lead (< 5 μm); Address solidification: Each die has an internal hardwired address decoder, and the coordinates are solidified by the photolithography mask (for example, the address of the die at position X3-Y2 is binary 0011_0010); When the bus sends an address signal, only the Die that matches the coordinates activates the test mode; Test circuit embedding: Setting up a test control module (TCM) at the intersection of the dicing lanes or at the edge of the wafer, including signal drivers and result acquisition circuits; 2. Manufacturing stage: process and structure realization Photolithography mask definition Bus-specific mask: Design bus patterns in the cutting lane area and expose them synchronously with the chip circuit mask; Multi-layer metallization process: Steps: Deposit an insulating layer in the cutting area → Photolithography of the bus pattern → Etching → Filling with copper (Damascene process) → Chemical Mechanical Polishing (CMP); The bus uses the top metal layer to avoid short circuits with the underlying chip circuits; Die bridge structure manufacturing Metal "bridge" etching: Use high-precision photolithography to create metal leads between the die edge and the cutting path to achieve electrical connection; Insulation protection layer: A silicon nitride passivation layer is deposited over the bus and bridge lines to prevent contamination and short circuits.

7. The method according to claim 1, wherein The on-chip bus embedded in the cutting lanes enables "full interconnection of dies during the testing phase and physical isolation of dies after cutting." 8. The method according to claim 1, wherein Step S1 is specifically as follows: S10: In-situ regular sampling test of Die before wafer dicing; or, Test all dies one by one in situ before wafer dicing; Based on the test results, the process reliability of different areas on the wafer is statistically analyzed, and the parameters of the controlled parameter-containing randomization function are initialized based on the statistical analysis results; S11: Setting a controlled parameter-containing randomization function, and sampling and testing Die in situ according to the aforementioned randomization function before wafer dicing; S12: Based on the S11 test results, statistically analyze the process reliability of different areas on the wafer; S13: adjusting the parameters of the aforementioned randomization function according to the analysis results of S12, dynamically adjusting the sampling probability of different areas, and / or dynamically adjusting the division of areas; S14: After each wafer is tested, return to step S11 to complete the in-situ testing of the wafers of the entire production batch piece by piece.

9. The method according to claim 8, wherein: The regularized sampling refers to sampling Dies at fixed intervals for testing in the horizontal and vertical directions; optionally, one Die is tested every other sample, or one Die is tested every two samples, or one Die is tested every three samples, and so on.

10. The method according to claim 8, wherein: If the statistical results in step S10 show that there are significant differences in chip defect densities in different areas, and the chip defect density in a certain area or certain areas is greater than a certain threshold, it means that there are intolerable defects in the production process. Subsequent testing is stopped, and the process flow is returned to readjust process parameters or repair equipment. If the statistical results in step S10 show that the chip defect density in each area of ​​the wafer is roughly the same, but the overall die yield is lower than a preset threshold, it means that the production process has defects and does not meet the expected process goals. In this case, subsequent testing is stopped and the process flow is returned to readjust the process parameters or repair the equipment.

11. The method according to claim 8, wherein: In step S22, the regions on the wafer are divided using one of the following two methods: (1) Divide the area approximately evenly; (2) Divide the wafer into different regions according to the process reliability obtained from the statistical analysis in step S10.

12. The method according to claim 8, wherein: Dividing the regions according to the process reliability of different areas on the wafer means dividing the die yield of different areas on the wafer into two areas of high and low; or dividing it into three areas of high, medium and low; or dividing it into five areas of high, relatively high, medium, relatively low and low.

13. The method according to claim 8, wherein: In step S13, the sampling strategy is dynamically adjusted by setting the reward and punishment function: Penalty: For areas with high reliability (high pass rate), set a smaller randomization function density, that is, reduce the probability of random inspection; Reward: For areas with low reliability (low pass rate), set a larger randomization function density, that is, increase the probability of random inspection; Optionally, the randomization function density (spot check probability) is selected to be in a negative linear proportional relationship with the Die qualified rate in a certain area, that is, the randomization function density (spot check probability) is in a linear proportional relationship with the Die unqualified rate in a certain area; that is, the reward and punishment function is set as follows: randomization function density (spot check probability) = k·Die unqualified rate 2 , where k is a preset constant coefficient; Optionally, the randomization function density (spot check probability) is selected to have a nonlinear proportional relationship with the Die failure rate in a certain area, such as a square relationship or an exponential relationship; optionally: randomization function density (spot check probability) = k'·Die failure rate, where k' is a preset constant coefficient; Preferably, in step S13, the defect die distribution on the current wafer is statistically obtained again, and the defect die distribution is combined with the test results of the previous wafer for statistical analysis to obtain the overall defect die distribution, and the regional division is adjusted or not adjusted based on the overall defect die distribution; After the adjustment, random sampling is continued on subsequent wafers to obtain the distribution of defective dies on the subsequent wafers. The distribution is combined with the overall results of the previous wafer test and statistically analyzed again to obtain a new overall distribution of defective dies. Based on the new overall distribution of defective dies, the region is adjusted or not adjusted again. This process is continued. Preferably, in step S13, the distribution of defects on the current wafer is statistically obtained again, and the probability of random inspection in different areas is dynamically adjusted; Preferably, the division of regions and the probability of random inspections in different regions are dynamically adjusted simultaneously; Preferably, when the statistical analysis result of the next slice shows that the Die qualified rate of the adjacent areas of a certain area is reduced, the area range is appropriately expanded; otherwise, the area range is appropriately reduced.

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