Preparation method of photoetching-free through hole array structure

Abstract

The invention discloses a preparation method of a photoetching-free through hole array structure, which relates to the field of integrated circuit manufacturing and comprises the following steps of: preparing a micro / nano array template comprising a plurality of array units on the front surface of a substrate; depositing a dielectric film on the front surface of the substrate with the micro / nano array template; removing the micro / nano array template to obtain a patterned dielectric film; etching the substrate by taking the patterned dielectric film as an etching mask to form a blind hole array; depositing a functional layer in the blind hole; and thinning the back surface of the substrate until the bottoms of the blind holes are exposed to obtain the through hole array structure in the substrate. The dielectric film deposited between the array templates is used as the etching mask to further prepare the array through hole, the technical process is simple, a photoetching process is avoided, the manufacturing cost is low, and the method can be used for silicon-based through hole preparation, glass through hole preparation or three-dimensional passive device integration and the like.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a method for preparing a non-photolithography through-hole array structure. Background Art

[0002] With the rapid development of microelectronics technology, chip size continues to approach physical limits. Transistor size is getting smaller and smaller, while integration is increasing. However, there is a lack of matching heat dissipation capabilities. On the one hand, this leads to tunneling effects and leakage currents; on the other hand, issues such as chip power consumption, heat dissipation, and R&D costs have become difficult to ignore. The industry generally believes that Moore's Law has reached its limit. To continue Moore's Law, the concept of "More-than-Moore" has been proposed. "More-than-Moore" aims to achieve improved integrated circuit performance and functionality through innovations in system integration, circuit design, and packaging design. Among the many aspects of "More-than-Moore", three-dimensional integration technology is currently considered a key means of achieving it.

[0003] 3D integration technology, broadly speaking, involves stacking multiple, different or identical integrated circuit chips in three dimensions to achieve heterogeneous integration. In traditional 2D integration, all chips and passive components are connected via bonding wires and flip-chip technology on a substrate. 3D integration overcomes the spatial limitations of traditional 2D integration by integrating multiple chips in the third dimension, significantly improving space utilization and effectively increasing integration. 3D integration also shortens interconnect lengths, increases signal transmission speed, reduces latency and power consumption, and effectively enhances integrated circuit system performance.

[0004] Through-hole technology is a key technology for achieving three-dimensional integration. By creating vertical through-holes in the substrate and preparing a dielectric conductive layer in the through-holes, vertical mechanical and electrical interconnections between chips, wafers, or chips in the third dimension are achieved.

[0005] Common through-hole technologies include Bosch etching, laser drilling, and wet etching, using silicon, glass, metal, ceramic, or organic materials as substrates. However, these through-hole technologies require patterning and mask formation through photolithography to ensure the accuracy and consistency of subsequent through-hole etching.

[0006] Among lithography equipment, the photolithography machine, the core of lithography technology, requires high-precision optical systems and complex mechanical structures, resulting in extremely high R&D and manufacturing costs, as well as considerable maintenance and upgrade costs. Among lithography materials, photoresist and its supporting chemicals are indispensable to the lithography process. Their production requires high-purity raw materials and complex processes, resulting in high R&D and production costs. Masks also require high-precision pattern transfer and complex manufacturing processes, resulting in extremely high manufacturing costs. Due to a number of factors, including expensive equipment, high maintenance costs, high production costs, and market monopoly, lithography has become one of the most expensive processes in semiconductor manufacturing. Therefore, developing a low-cost, lithography-free through-hole fabrication method is of great practical significance. Summary of the Invention

[0007] In view of the deficiencies in the prior art, the present invention provides a method for preparing a photolithography-free through-hole array structure, thereby providing a more competitive solution for three-dimensional integrated packaging.

[0008] In order to achieve the above objectives, the technical solution of the present invention is:

[0009] A method for preparing a non-photolithographic through-hole array structure comprises the following steps:

[0010] S1: preparing a micro / nano array template on the front side of a substrate, wherein the micro / nano array template includes a plurality of array units;

[0011] S2: depositing a dielectric film on the front side of the substrate with the micro / nano array template;

[0012] S3: removing the micro / nano array template to obtain a patterned dielectric film having the same dielectric properties as the array.

[0013] The hollow area with one-to-one correspondence between unit positions;

[0014] S4: Using the patterned dielectric film as an etching mask, the substrate is etched to form a blind hole array;

[0015] S5: depositing a functional layer in the blind hole;

[0016] S6: Thinning the back side of the substrate until the bottom of the blind hole is exposed, thereby obtaining a through hole array structure in the substrate.

[0017] Optionally, the array unit is in the shape of any one or more combinations of a sphere, a triangular pyramid, a cube, and a cuboid, and is made of any one of polystyrene, oxide, metal, and the like.

[0018] Optionally, the material of the substrate is one of single crystal silicon, polycrystalline silicon, silicon nitride, glass, metal, oxide, and ceramic.

[0019] Optionally, the micro / nano array template preparation method may adopt micro / nano template etching technology, including nanostructured material film formation and etching steps, wherein the film formation step may adopt one or more of a nanostructured self-assembly method, a physical vapor deposition method, and a chemical vapor deposition method; the etching step includes one or both of a dry etching method and a wet etching method. The etching step can realize the size of the array unit structure, thereby adjusting the unit spacing of the micro / nano array template.

[0020] Optionally, S1 specifically includes: activating the front side of the substrate to obtain a hydrophilic surface; using nanospheres as array units to form a nanosphere monolayer on the hydrophilic surface, and etching the nanosphere monolayer to control the diameter of the nanospheres; the nanospheres used can be a combination of the same diameter or different diameters.

[0021] Optionally, the dielectric film is made of one of gold, titanium, chromium, and aluminum, and is deposited by one or more of chemical vapor deposition, physical vapor deposition (sputtering, evaporation), and atomic layer deposition, with a deposition thickness of 5 nm to 50 μm. For example, 50 μm, 40 μm, 30 μm, 20 μm, 10 μm, 1000 nm, 900 nm, 800 nm, 700 nm, 600 nm, 500 nm, 400 nm, 300 nm, 200 nm, 100 nm, 90 nm, 80 nm, 70 nm, 60 nm, 50 nm, 40 nm, 30 nm, 20 nm, 10 nm, 5 nm, or any value in between.

[0022] Optionally, the micro / nano array template removal method may be one or more of dry etching and wet etching.

[0023] Optionally, between S4 and S5, a step of removing the patterned dielectric film is also included.

[0024] Optionally, the blind hole etching method may be one of laser etching, deep reactive ion etching, and wet etching.

[0025] Optionally, the blind hole etched diameter of the blind hole array is 10 nm to 50 μm. For example, 50 μm, 40 μm, 30 μm, 20 μm, 10 μm, 1000 nm, 900 nm, 800 nm, 700 nm, 600 nm, 500 nm, 400 nm, 300 nm, 200 nm, 100 nm, 90 nm, 80 nm, 70 nm, 60 nm, 50 nm, 40 nm, 30 nm, 20 nm, 10 nm, or any value in between. The blind hole diameter is defined by the size of the array unit.

[0026] Optionally, the blind hole etching depth of the blind hole array is 500 nm to 500 μm, for example, 500 μm, 400 μm, 300 μm, 200 μm, 100 μm, 1000 nm, 900 nm, 800 nm, 700 nm, 600 nm, 500 nm, or any value in between.

[0027] Optionally, in S3, one of dry or wet etching can be used to etch the boundary of the hollow area of ​​the patterned dielectric film to form a vertical sidewall, thereby facilitating the subsequent processing of the vertical blind hole; further, when the substrate is a silicon-based material, the etching process can roughen the surface of the silicon-based material exposed in the hollow area, thereby facilitating the rapid etching of the subsequent blind hole.

[0028] Optionally, the deposition of the functional layers sequentially includes deposition of an insulating layer, a barrier layer, and a conductive layer; the insulating layer is deposited to achieve electrical isolation, the barrier layer is deposited to prevent diffusion of the deposited material at high temperatures, and the conductive layer is deposited to achieve electrical interconnection. After depositing the functional layers and before thinning the back side of the substrate, the process further includes: annealing the substrate to optimize the conductive layer structure, and polishing the front side to remove excess deposited material and obtain a smooth surface. The front side polishing step can be performed using one of chemical mechanical polishing, electro-mechanical polishing, wet etching, dry etching, and laser polishing. The method used for thinning the back side of the substrate can be one of chemical mechanical polishing, electro-mechanical polishing, wet etching, dry etching, and laser polishing.

[0029] Furthermore, the insulating layer may be made of any one of silicon dioxide, silicon nitride, aluminum oxide, and parylene; the insulating layer may be deposited by thermal oxidation or chemical vapor deposition (low-pressure chemical vapor deposition or enhanced chemical vapor deposition); and the thickness of the deposited insulating layer may be 1 nm to 1 μm, for example, 1 μm, 900 nm, 800 nm, 700 nm, 600 nm, 500 nm, 400 nm, 300 nm, 200 nm, 100 nm, 90 nm, 80 nm, 70 nm, 60 nm, 50 nm, 40 nm, 30 nm, 20 nm, 10 nm, 1 nm, or any value in between.

[0030] Furthermore, the barrier layer may be made of any one of titanium, titanium nitride, titanium dioxide, tantalum, tungsten, cobalt, aluminum oxide, polysilicon, etc.; the barrier layer may be deposited by chemical vapor deposition, physical vapor deposition (sputtering, evaporation), or atomic layer deposition; and the thickness of the deposited barrier layer may be 1 nm to 100 nm, for example, 100 nm, 90 nm, 80 nm, 70 nm, 60 nm, 50 nm, 40 nm, 30 nm, 20 nm, 10 nm, 1 nm, or any value in between.

[0031] Furthermore, the conductive layer can be made of any of polysilicon, tungsten, copper, silver, nickel, carbon nanotubes, and the like; and can be deposited by chemical plating, chemical vapor deposition, sputtering, or electroplating. The conductive layer preferably fills the blind vias. During subsequent backside thinning, the bottom conductive layer is exposed.

[0032] The beneficial effects of the present invention are:

[0033] A micro / nano array template is made on a substrate, and a dielectric film deposited between the micro / nano array templates is used as an etching mask to prepare array through-holes in the substrate. This replaces the graphic process that relies on photoresist as an etching template. The process flow is simple and it is a photolithography-free array through-hole manufacturing technology. The pattern production and control are flexible and suitable for actual production applications.

[0034] Other features and advantages of the present invention will be set forth in the following description, and in part will be obvious from the description, or may be learned by practicing the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 FIG. 4 is a flow chart of a preparation process of a method for preparing a non-photolithography through-hole array structure according to an embodiment.

[0036] Figure 2 Schematic diagram of preparing a micro / nano array template on a silicon substrate in step (2) of Example 1.

[0037] Figure 3 Schematic diagram of depositing dielectric film in step (3) of Example 1.

[0038] Figure 4 Schematic diagram of patterning the dielectric film in step (4) of Example 1.

[0039] Figure 5 Schematic diagram of array blind hole etching in step (5) of Example 1.

[0040] Figure 6 Schematic diagram of removing the dielectric film in step (6) of Example 1.

[0041] Figure 7 Schematic diagram of depositing the functional layer in step (7) of Example 1.

[0042] Figure 8 This is a schematic diagram of the front surface after polishing in step (8) of Example 1.

[0043] Figure 9 Schematic diagram of the array through holes after backside thinning in step (9) of Example 1.

[0044] Figure 10 for Figure 9 A top view of the array through holes.

[0045] Figure 11 Schematic diagram of preparing a micro / nano array template on a silicon substrate in step (2) of Example 2. DETAILED DESCRIPTION

[0046] The present invention is further explained below with reference to the accompanying drawings and specific embodiments. The drawings are provided for illustrative purposes only to facilitate understanding of the present invention, and their specific proportions may be adjusted according to design requirements. Those skilled in the art will understand that the vertical relationships between components and the definitions of front and back in the figures described herein refer to the relative positions of components. Therefore, they can be flipped to present the same components, and all such representations are within the scope of this specification.

[0047] Example 1

[0048] This embodiment provides a method for preparing a non-photolithographic through-hole array structure. Figure 1 , and its preparation method comprises the following steps:

[0049] (1) The substrate is a silicon substrate with a thickness of 200 μm. The silicon substrate is subjected to an RCA standard cleaning process to obtain a clean and flat surface; it is activated in a reactive ion etching system and the surface of the silicon substrate is bombarded with oxygen plasma to obtain a hydrophilic surface.

[0050] (2) Then, the silicon substrate was quickly transferred to a spin coater and coated with polystyrene nanospheres with a diameter of 300 nm. The concentration of the polystyrene nanosphere solution was 5-10%, 0.1 μL, and the solution was first rotated at 200 rpm for 30 seconds to uniformly cover the polystyrene nanospheres on the entire silicon substrate. Then, the solution was rotated at 2000 rpm for 30 seconds to remove the excess polystyrene nanospheres by centrifugal force to obtain a single layer of polystyrene nanospheres 2a uniformly covering the surface of the silicon substrate 1 to form a micro / nano array template 2; the silicon substrate with the micro / nano array template was then placed in an inductively coupled plasma etching system for dry etching. The RIE power was adjusted to 80 W and the etching time was 50 seconds. Finally, the diameter of the array unit polystyrene nanospheres 2b of the micro / nano array template 2 was adjusted to 250 nm and the spacing was 300 nm. Figure 2 shown.

[0051] (3) The silicon substrate 1 with the micro / nano array template 2 is placed in the vacuum chamber of the magnetron sputtering device, and a layer of titanium as a dielectric film 3 is deposited on the surface of the substrate by sputtering. The film thickness is 1 μm. Figure 3 As shown, for a more intuitive presentation, Figure 3 Take three polystyrene nanospheres 2b as an example.

[0052] (4) The silicon substrate is sequentially subjected to ultrasonic treatment using organic solvents such as tetrahydrofuran, acetone, and alcohol to remove byproducts of the etching process and the micro / nano array template by wet etching, and then the surface is dried with nitrogen to obtain a patterned dielectric film. After the polystyrene nanospheres 2b are removed, corresponding hollow areas 3a are formed. The boundaries of the hollow areas 3a of the patterned dielectric film are then etched by wet etching to form vertical side walls, and at the same time, the surface of the silicon substrate 1 exposed in the hollow areas 3a is roughened, thereby obtaining a patterned dielectric film 3 having hollow areas 3a with vertical side walls, as shown in FIG. Figure 4 The roughening of the surface of the silicon substrate 1 will facilitate the rapid etching of the subsequent blind holes.

[0053] (5) Place the silicon substrate 1 with the patterned dielectric film 3 into the deep silicon plasma etching system, and evacuate the reaction chamber to a background vacuum of ≤3×10 -6 Torr, alternately introduce etching gas SF6 and passivation gas C4F8, use the patterned dielectric film 3 as an etching mask, and etch the silicon substrate 1 in each hollow area 3a, finally forming an array blind hole 11 with a depth of 25μm. Figure 5 shown.

[0054] (6) Prepare a mixed solution of hydrofluoric acid (HF) and ammonium hydroxide (NH4OH), immerse the silicon substrate 1 with the array blind holes 11 in the etching solution to remove the dielectric film 3, as shown in FIG. Figure 6 As shown, the substrate was then thoroughly rinsed with deionized water and the surface was blown dry with nitrogen.

[0055] (7) Depositing functional layers in the array blind holes 11, in order: depositing a 50 nm thick silicon dioxide layer in the array blind holes 11 by enhanced chemical vapor deposition as an insulating layer 4; then depositing a 10 nm thick Ti film by atomic layer deposition as a barrier layer 5; finally, filling the blind holes with copper by electroplating as a dielectric conductive layer 6, as shown in FIG. Figure 7 shown.

[0056] (8) Annealing the array blind holes of the deposited functional layer to refine the copper grains of the dielectric conductive layer 6 and grow uniformly; then use chemical mechanical polishing equipment, and use an alkaline polishing liquid containing silicon dioxide nanoparticles to remove excess material on the surface of the silicon substrate 1 to obtain a flat surface, such as Figure 8 shown.

[0057] (9) Using chemical mechanical polishing equipment, an alkaline polishing liquid containing silicon dioxide nanoparticles is selected as the polishing liquid to polish the back of the silicon substrate 1, so that the back of the silicon substrate 1 has high flatness and low roughness, while exposing the dielectric conductive layer 6 on the back of the blind hole 11, and finally obtaining an array of through holes with a diameter of 250 nm and an aspect ratio of 100:1, forming a conductive through hole array structure in the substrate, such as Figure 9 As shown, its top view is as Figure 10 shown.

[0058] Example 2

[0059] This embodiment provides a method for preparing a non-photolithographic through-hole array structure. Figure 1 , including the following steps:

[0060] (1) A 300 μm thick silicon substrate was cleaned using an RCA standard cleaning process to obtain a clean and flat surface; the silicon substrate was activated in a reactive ion etching system and the surface was bombarded with oxygen plasma to obtain a hydrophilic surface.

[0061] (2) Then, the silicon substrate substrate was quickly transferred to a spin coater and coated with silica balls 2c and 2d with diameters of 5 μm and 15 μm, respectively. The concentration of the silica ball solution was 25-40%, 0.1 μL, and the solution was first rotated at 500 rpm for 30 seconds to uniformly cover the entire silicon substrate substrate with silica balls. Then, the solution was rotated at 2500 rpm for 40 seconds to remove excess silica balls by centrifugal force, and a single layer of 5 μm silica balls 2c and 15 μm silica balls 2d was obtained to uniformly cover the surface of the silicon substrate substrate 1 to form a micro / nano array template 2. The silicon substrate substrate with the micro / nano array template was then placed in an inductively coupled plasma etching system for dry etching. The RIE control power was 120 W and the etching time was 50 seconds. Finally, the diameter of the array unit silica balls 2e of the micro / nano array template 2 was adjusted to 10 μm and the spacing was 17 μm. Figure 11 shown.

[0062] The structures formed in the following steps may correspond to those in Reference Example 1. Figures 3 to 9 .

[0063] (3) The silicon substrate with the micro / nano array template is placed in the vacuum chamber of the magnetron sputtering equipment, and a layer of titanium as a dielectric film is deposited on the surface of the substrate by sputtering. The film thickness is 15 μm.

[0064] (4) Dry etching is performed on the silicon substrate to remove the byproducts of the etching process and the micro / nano array template to obtain a patterned dielectric layer; then, the boundaries of the hollow area of ​​the patterned dielectric film are etched by wet etching to form vertical side walls, and at the same time, the surface of the silicon material exposed in the hollow area is roughened to obtain a patterned dielectric film with a hollow area with vertical side walls.

[0065] (5) Place the silicon substrate with the patterned dielectric film into the deep silicon plasma etching system and evacuate the reaction chamber to a background vacuum of ≤3×10 -6 Torr, alternately introduce etching gas SF6 and passivation gas C4F8, use the patterned dielectric film as a mask, and finally form an array of blind holes with a depth of 100μm.

[0066] (6) Prepare a mixed solution of hydrofluoric acid (HF) and ammonium hydroxide (NH4OH), immerse the silicon substrate with the array blind holes in the etching solution to remove the patterned dielectric film, then rinse the substrate thoroughly with deionized water and blow dry the surface with nitrogen.

[0067] (7) Depositing functional layers in the array blind holes 11, in order: depositing a 700 nm thick silicon dioxide layer in the array blind holes by enhanced chemical vapor deposition as an insulating layer; then depositing a 100 nm thick Ti film by atomic layer deposition as a barrier layer; and finally, filling the blind holes with copper by electroplating as a dielectric conductive layer.

[0068] (8) Annealing treatment is performed on the array blind holes of the deposited functional layer to refine the copper grains of the dielectric conductive layer and grow uniformly; then, chemical mechanical polishing equipment is used, and the polishing liquid is an alkaline polishing liquid containing silicon dioxide nanoparticles to remove excess material on the surface of the silicon substrate to obtain a smooth surface.

[0069] (9) Chemical mechanical polishing equipment was used, and an alkaline polishing liquid containing silicon dioxide nanoparticles was selected as the polishing liquid to polish the back of the silicon substrate. This made the back of the silicon substrate have high flatness and low roughness while exposing the dielectric conductive layer on the back of the blind hole. Finally, an array through hole with a diameter of 10 μm and an aspect ratio of 10:1 was obtained.

[0070] Example 3

[0071] This embodiment provides a method for preparing a non-photolithographic through-hole array structure. Figure 1 The preparation method comprises the following steps, and the structure obtained in each step corresponds to that in reference example 1. Figures 2 to 9 :

[0072] (1) A 200 μm thick silicon substrate was cleaned using the RCA standard cleaning process to obtain a clean and flat surface; activation was performed in a reactive ion etching system, and the surface of the silicon substrate was bombarded with oxygen plasma to obtain a hydrophilic surface.

[0073] (2) The silicon substrate was then quickly transferred to a spin coater and coated with polystyrene nanospheres with a diameter of 300 nm. The concentration of the polystyrene nanosphere solution was 5-10%, 0.1 μL, and the solution was first rotated at 200 rpm for 30 seconds to uniformly cover the polystyrene nanospheres on the entire silicon substrate. The solution was then rotated at 2000 rpm for 30 seconds to remove the excess polystyrene nanospheres by centrifugal force to obtain a micro / nano array template with a single layer of polystyrene nanospheres uniformly covering the surface of the silicon substrate. The silicon substrate with the micro / nano array template was then placed in an inductively coupled plasma etching system for dry etching. The RIE power was adjusted to 80 W and the etching time was 50 seconds. Finally, the diameter of the polystyrene nanospheres in the micro / nano array template was adjusted to 250 nm and the spacing was 300 nm.

[0074] (3) The silicon substrate with the micro / nano array template is fixed on the substrate holder of the evaporation equipment, and a high-purity chromium target is installed in the evaporation source. A layer of chromium as a dielectric film is deposited on the surface of the substrate by evaporation, and the film thickness is 500 nm.

[0075] (4) The silicon substrate is sequentially subjected to ultrasonic treatment using organic solvents such as tetrahydrofuran, acetone, and alcohol to remove byproducts of the etching process and the micro / nano array template by wet etching, and then the surface is blown dry with nitrogen to obtain a patterned dielectric film; the boundaries of the hollow area of ​​the patterned dielectric film are then etched by wet etching to form vertical side walls, and at the same time, the surface of the silicon material exposed in the hollow area is roughened to obtain a patterned dielectric film having a hollow area with vertical side walls.

[0076] (5) Place the silicon substrate with the patterned dielectric film into the deep silicon plasma etching system and evacuate the reaction chamber to a background vacuum of ≤3×10 -6 Torr, etching gas SF6 and passivation gas C4F8 are alternately introduced to finally form an array blind hole with a depth of 25μm.

[0077] (6) Place the silicon substrate into the RIE equipment and remove the patterned dielectric film by dry etching.

[0078] (7) Depositing functional layers in the array blind holes 11, in order: depositing a 50 nm thick silicon dioxide layer in the array blind holes by enhanced chemical vapor deposition as an insulating layer; then depositing a 10 nm thick Ti film by atomic layer deposition as a barrier layer; and finally, filling the blind holes with copper by electroplating as a dielectric conductive layer.

[0079] (8) Annealing treatment is performed on the array blind holes of the deposited functional layer to refine the copper grains of the dielectric conductive layer and grow uniformly; then, chemical mechanical polishing equipment is used, and the polishing liquid is an alkaline polishing liquid containing silicon dioxide nanoparticles to remove excess material on the surface of the silicon substrate to obtain a smooth surface.

[0080] (9) Chemical mechanical polishing equipment was used, and an alkaline polishing liquid containing silicon dioxide nanoparticles was selected as the polishing liquid to polish the back of the silicon substrate, so that the back of the silicon substrate had high flatness and low roughness, while the dielectric conductive layer on the back of the blind hole was exposed, and finally an array through hole with a diameter of 250 nm and an aspect ratio of 100:1 was obtained.

[0081] The above embodiments are only used to further illustrate a method for preparing a non-photolithography through-hole array structure of the present invention, but the present invention is not limited to the embodiments. Any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for preparing a non-photolithography through-hole array structure, characterized in that: The following steps are involved: S1: preparing a micro / nano array template on the front side of a substrate, wherein the micro / nano array template includes a plurality of array units; S2: depositing a dielectric film on the front side of the substrate with the micro / nano array template; S3: removing the micro / nano array template to obtain a patterned dielectric film, wherein the patterned dielectric film has hollow areas corresponding to array unit positions; S4: Using the patterned dielectric film as an etching mask, the substrate is etched to form a blind hole array; S5: depositing a functional layer in the blind hole; S6: Thinning the back side of the substrate until the bottom of the blind hole is exposed, thereby obtaining a through hole array structure in the substrate.

2. The method for preparing a non-photolithography through-hole array structure according to claim 1, wherein: The array unit is in the shape of any one or more combinations of a sphere, a triangular pyramid, a cube, and a cuboid, and is made of any one of polystyrene, oxide, and metal.

3. The method for preparing a non-photolithography through-hole array structure according to claim 1, wherein: The material of the substrate is one of single crystal silicon, polycrystalline silicon, silicon nitride, glass, metal, oxide, and ceramic.

4. The method for preparing a non-photolithography through-hole array structure according to claim 1, wherein: S1 specifically includes: Activating the front side of the substrate to obtain a hydrophilic surface; Nanospheres are used as array units to form a nanosphere monolayer on a hydrophilic surface, and the nanosphere monolayer is etched to control the diameter of the nanospheres. The nanospheres used have the same diameter or a combination of different diameters.

5. The method for preparing a non-photolithography through-hole array structure according to claim 1, wherein: The material of the dielectric film is one of gold, titanium, chromium and aluminum, and the deposition thickness is 5nm to 50μm.

6. The method for preparing a non-photolithography through-hole array structure according to claim 1, wherein: Between S4 and S5, the process also includes a step of removing the patterned dielectric film.

7. The method for preparing a non-photolithography through-hole array structure according to claim 1, wherein: The blind hole array has a diameter of 10 nm to 50 μm and a depth of 500 nm to 500 μm, wherein the blind hole diameter is defined by the size of the array unit.

8. The method for preparing a non-photolithography through-hole array structure according to claim 1, wherein: S3 further includes a step of etching the boundary of the hollow area to form vertical sidewalls.

9. The method for preparing a non-photolithography through-hole array structure according to claim 1, wherein: The deposition of the functional layer includes, in sequence, the deposition of an insulating layer, the deposition of a barrier layer, and the deposition of a conductive layer; between S5 and S6, the substrate is also annealed and polished on the front side.

10. The method for preparing a non-photolithography through-hole array structure according to claim 9, wherein: The material of the insulating layer is any one of silicon dioxide, silicon nitride, aluminum oxide, and polyparaxylene, with a thickness of 1nm-1μm; the material of the barrier layer is any one of titanium, titanium nitride, titanium dioxide, tantalum, tungsten, cobalt, aluminum oxide, and polycrystalline silicon, with a thickness of 1nm-100nm; the material of the conductive layer is any one of polycrystalline silicon, tungsten, copper, silver, nickel, and carbon nanotubes.

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