Zero-voltage switch buck converter and control system thereof

Abstract

The invention discloses a zero-voltage switching Buck converter and a control system thereof, and the innovation of the zero-voltage switching Buck converter is that the zero-voltage switching of a high-side switch is realized by introducing a clamping switch. The control system comprises a control circuit and a driving circuit, wherein the driving circuit comprises a clamping switch driving circuit, a low-side switch driving circuit and a high-side switch driving circuit; the control circuit comprises an inductive current sampling module, an output voltage sampling module, a PI compensator, a comparator, two timers, three dead time modules and three triggers. According to the invention, the problems of a traditional hard-switch Buck converter can be effectively solved, and a feasible solution is provided for meeting the requirements of a VRM in a high-power-density and high-frequency application scene by realizing zero-voltage switching of a high-side switch, effectively reducing the switching loss, improving the switching frequency and conversion efficiency of the converter and reducing electromagnetic interference.

Description

Technical Field

[0001] The present invention belongs to the technical field of high power density power converters and power management, and in particular relates to a zero voltage switching buck converter and a control system thereof. Background Art

[0002] With the continuous development of technologies such as electric vehicles, big data, and artificial intelligence, voltage regulator modules (VRM) have been widely used in many fields. For example, in a computer motherboard, VRM provides precise power to the CPU to ensure its stable operation. Another example is that VRM provides reliable power support for various core components in a server, ensuring the reliability and stability of data processing and storage. As electronic devices continue to move towards miniaturization and high performance, the power density requirements for VRM are increasing, which means that the requirements for power converters are constantly moving towards high power density. Improving power density can not only improve the overall performance of the equipment, but also effectively reduce the size and weight of the equipment, meeting the dual needs of portability and high efficiency of modern electronic equipment.

[0003] To improve power density, power switching frequencies are continuously increasing. Increasing switching frequencies significantly reduces the size of magnetic components in converters, such as inductors, playing a key role in boosting power density. By increasing switching frequencies, more energy can be processed per unit time, resulting in faster transient response. Currently, the switching frequency of mainstream high-frequency power converters has reached the 1MHz level, and the trend is towards even higher switching frequencies. Furthermore, the demand for high power density and high conversion efficiency in today's electronic systems has driven the development of non-isolated point-of-load regulators (niPOLs). This allows niPOLs to operate at higher input voltages and conversion ratios than ever before, while also aiming to reduce the overall size of the power supply while maintaining high conversion efficiency. To address this challenge, the power electronics industry has implemented numerous technological upgrades to niPOLs. Simultaneously, significant advances in MOSFET technology have provided numerous solutions for increasing power density. These solutions work well over a narrow input voltage range, but their conversion efficiency and output power drop slightly at step-down ratios of 10:1 or 12:1, and they can drop dramatically at wider input ranges, such as when the step-down ratio approaches 36:1.

[0004] like Figure 1As shown in (a), the traditional hard-switching Buck converter itself greatly limits improvements in power density and conversion efficiency over a wide input voltage range. During the hard-switching process, the overlap between voltage and current at the moment the high-side switch turns on and off generates significant switching losses, which not only reduces converter efficiency but also causes severe switch heating. Hard switching at high switching frequencies also generates strong electromagnetic interference (EMI), affecting the normal operation of surrounding circuits. These problems limit further increases in switching frequency, necessitating the exploration of new circuit topologies to address the current challenges of traditional hard-switching Buck converters. Summary of the Invention

[0005] In response to the problems existing in the prior art, the present invention provides a zero-voltage switching buck converter and control system, which can effectively solve the difficulties faced by traditional hard-switching buck converters. By achieving zero-voltage turn-on of the high-side switch, it can effectively reduce switching losses, improve the switching frequency and conversion efficiency of the converter, and reduce electromagnetic interference. It provides a practical solution to meet the needs of VRM in high-power density and high-frequency application scenarios.

[0006] To solve the above technical problems, the present invention provides the following technical solutions: a control system based on a zero voltage switching Buck (hereinafter referred to as ZVS-Buck) converter, comprising: a ZVS-Buck converter, a switch drive circuit, and a control circuit; the switch drive circuit is connected to the ZVS-Buck converter, the control circuit is connected to the switch drive circuit, and the ZVS-Buck is connected to the control circuit;

[0007] The driving circuit includes: a clamp switch driving circuit, a low-side switch driving circuit, and a high-side switch driving circuit;

[0008] The control circuit includes: an inductor current sampling module, an output voltage sampling module, a compensation network module, a comparison module, a timer Timer1, a timer Timer2, a dead time module 1, an RS trigger RS_a, a dead time module 2, an RS trigger RS_b, a dead time module 3, and an RS trigger RS_c;

[0009] The input of the first input terminal of the ZVS-Buck converter is the input voltage ZVS_V IN The second input terminal input is the clamp switch drive signal S 33 The input of the third input terminal is the low-side switch drive signal S 22 The input of the fourth input terminal is the high-side switch drive signal S 11 The output of the first output terminal of the ZVS-Buck converter is the output voltage ZVS_V OUTThe output of the second output terminal is the inductor current I L ;

[0010] The input of the inductor current sampling module is the inductor current I L , the output is the inductor current sampling signal I SEN2 ;The input of the output voltage sampling module is the output voltage ZVS_V OUT , the output is the output voltage feedback signal V FB ; The input of the compensation network module is the output voltage feedback signal V FB , the output is the control signal V err ; The input of the comparison module is the inductor current sampling signal I SEN2 With the control signal V err , the output is the reset signal RESET1; the output of timer Timer1 is the clock signal CLK and the reset signal RESET3;

[0011] The input of dead time module 1 is clock signal CLK, and the output is set signal SET1; the input of reset terminal of RS flip-flop RS_a is reset signal RESET1, and the input of set terminal is set signal SET1; the output of RS flip-flop RS_a is control signal S1 and S 1B The input of the high-side switch driving circuit is the control signal S1, and the output is the high-side switch driving signal S 11 ;

[0012] The input of dead time module 2 is control signal S 1B , the output is the set signal SET2; the input of timer Timer2 is the input voltage ZVS_V IN , the output is the reset signal RESET2; the input of the reset terminal of the RS flip-flop RS_b is the reset signal RESET2, and the input of the set terminal is the set signal SET2; the output of the RS flip-flop RS_b is the control signal S2 and S 2B The input of the low-side switch driving circuit is the control signal S2, and the output is the low-side switch driving signal S 22 ;

[0013] The input of dead time module 3 is control signal S 2B , the output is the set signal SET3; the input of the reset terminal of the RS flip-flop RS_c is the reset signal RESET3, and the input of the set terminal is the set signal SET3; the output of the RS flip-flop RS_c is the control signal S3 and S 3B The input of the clamp switch driving circuit is the control signal S3, and the output is the clamp switch driving signal S 33 ;

[0014] The present invention also provides a ZVS-Buck converter, which includes: an input voltage ZVS_V IN , high-side switch ZVS_SW1, low-side switch ZVS_SW2, clamp switch ZVS_SW3, output inductor ZVS_L OUT , high-side switch output capacitor ZVS_C1, low-side switch output capacitor ZVS_C2, output capacitor ZVS_C OUT 、Input capacitance ZVS_C IN 、Output voltage ZVS_V OUT , resistor ZVS_R OUT , diode ZVS_D1, diode ZVS_D2;

[0015] Input voltage ZVS_V IN Positive electrode and input capacitor ZVS_C IN The upper end of the high-side switch ZVS_SW1, the cathode of the diode ZVS_D1, and the upper end of the high-side switch output capacitor ZVS_C1 are connected;

[0016] Input voltage ZVS_V IN Negative electrode and input capacitor ZVS_C IN The lower end of the low-side switch ZVS_SW2, the anode of the diode ZVS_D2, the lower end of the low-side switch output capacitor ZVS_C2, the output capacitor ZVS_C OUT The lower end of the output resistor ZVS_R OUT The lower end is connected to the output voltage ZVS_V OUT The negative electrode;

[0017] The lower end of the high-side switch ZVS_SW1 is connected to the anode of the diode ZVS_D1, the cathode of the diode ZVS_D2, the upper end of the low-side switch ZVS_SW2, the left end of the clamp switch ZVS_SW3, and the output inductor ZVS_L OUT The left end is connected;

[0018] The right end of the clamp switch ZVS_SW3 and the output inductor ZVS_L OUT The right end of the output capacitor ZVS_C OUT The upper end of the output resistor ZVS_R OUT The upper end is connected to the output voltage ZVS_V OUT positive electrode.

[0019] Furthermore, the aforementioned driving circuit includes: a clamp switch driving circuit, a low-side switch driving circuit, and a high-side switch driving circuit;

[0020] The control circuit includes: an inductor current sampling module, an output voltage sampling module, a PI compensator, a comparator COMP_1, a timer Timer1, a timer Timer2, a dead time module 1, an RS trigger SAMP_RS_a, a dead time module 2, an RS trigger SAMP_RS_b, a dead time module 3, and an RS trigger SAMP_RS_c;

[0021] The input of the first input terminal of the ZVS-Buck converter is the input voltage SAMP_V IN The second input terminal, the third input terminal, and the fourth input terminal respectively input the output signals from the clamp switch driving circuit, the low-side switch driving circuit, and the high-side switch driving circuit; the first output terminal of the ZVS-Buck converter outputs the output voltage SAMP_V OUT The second output terminal outputs the inductor current SAMP_I L ;

[0022] The input of the inductor current sampling module is the inductor current SAMP_ L I, the output is the inductor current sampling signal SAMP_I SEN2 ;The input of the output voltage sampling module is the output voltage SAMP_V OUT , the output is the output voltage feedback signal SAMP_V FB ;

[0023] The input of the PI compensator is the output voltage feedback signal SAMP_V FB With the reference voltage V REF1 , the output is the control signal SAMP_V err The input of the non-inverting terminal of the comparator COMP_1 is the inductor current sampling signal SAMP_I SEN2 , the input of the inverting terminal is the control signal SAMP_V err The output of comparator COMP_1 is reset signal SAMP_RESET1; the input of timer Timer1 is reference voltage V REF3 With the reference voltage V REF4 , the output is the clock signal SAMP_CLK and the reset signal SAMP_RESET3;

[0024] The input of dead time module 1 is clock signal SAMP_CLK, and the output is set signal SAMP_SET1; the input of reset terminal of RS flip-flop SAMP_RS_a is reset signal SAMP_RESET1, and the input of set terminal is set signal SAMP_SET1; the output of RS flip-flop SAMP_RS_a is control signal SAMP_S1 and SAMP_S 1B ;The input of the high-side switch driver circuit is the control signal SAMP_S1;

[0025] The input of dead time module 2 is the control signal SAMP_S 1B , the output is the set signal SAMP_SET2; the input of timer Timer2 is the input voltage SAMP_V IN , output voltage SAMP_V OUT , inductor current sampling signal SAMP_I SEN2 And the reference voltage V REF2 , the output is the reset signal SAMP_RESET2; the input of the reset terminal of the RS flip-flop SAMP_RS_b is the reset signal SAMP_RESET2, and the input of the set terminal is the set signal SAMP_SET2; the output of the RS flip-flop SAMP_RS_b is the control signal SAMP_S2 and SAMP_S 2B ;The input of the low-side switch driver circuit is the control signal SAMP_S2;

[0026] The input of dead time module 3 is the control signal SAMP_S 2B , the output is the set signal SAMP_SET3; the input of the reset terminal of the RS flip-flop SAMP_RS_c is the reset signal SAMP_RESET3, and the input of the set terminal is the set signal SAMP_SET3; the output of the RS flip-flop SAMP_RS_c is the control signal SAMP_S3 and SAMP_S 3B The input of the clamp switch driver circuit is the control signal SAMP_S3;

[0027] Furthermore, the aforementioned timer Timer1 includes: an operational amplifier OPA_b, a comparator COMP_b1, a transistor M9, a transistor M 10 , transistor M 11 , capacitor Timer1_C1, resistor R 10 ;

[0028] The input of timer Timer1 is the reference voltage V REF3 With V REF4 The inverting input of the amplifier OPA_b is input as the reference voltage V REF3 The inverting input of comparator COMP_b1 is input as reference voltage V REF4 ; The non-inverting input of amplifier OPA_b and resistor R 10 The upper end of and the drain of transistor M9 are connected;

[0029] The output terminal of the amplifier OPA_b is connected to the gate of the transistor M9 and the transistor M 10 The gate of transistor M9 is connected; the source of transistor M 10 The source access input voltage SAMP_VIN , transistor M 10 The drain of transistor M 11 The drain of , the upper end of capacitor Timer1_C1, and the non-inverting input terminal of comparator COMP_b1 are connected;

[0030] Transistor M 11 The source of transistor M is connected to the lower end of capacitor Timer1_C1 and grounded; 11 The gate of is connected to the output end of the comparator COMP_b1 through a buffer, the output end of the comparator COMP_b1 is connected to a two-input AND gate, and outputs a clock signal SAMP_CLK and a reset signal SAMP_RESET3.

[0031] Furthermore, the aforementioned timer Timer2 includes: a transconductance amplifier OTA_a, a comparator COMP_b2, a comparator COMP_a, a current mirror module, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, and a One_shot circuit;

[0032] The input of the non-inverting input terminal of the transconductance amplifier OTA_a is the inductor current sampling signal SAMP_I SEN2 , the inverting input is grounded, the output of the transconductance amplifier OTA_a is connected to the upper end of the resistor R3 and the left end of the current mirror module, the right end of the current mirror module is connected to the upper end of the resistor R4 and the inverting input of the comparator COMP_a, the non-inverting input of the comparator COMP_a is connected to the output of the comparator COMP_b2 and the left end of the resistor R9; the current mirror module is connected by the input voltage SAMP_V IN Provide power supply;

[0033] The right end of resistor R5 is connected to the input voltage SAMP_V IN The left end is connected to the right end of resistor R7, the left end of resistor R6, and the non-inverting input of comparator COMP_b2. The input of the right end of resistor R6 is the reference voltage V REF2 The inverting input of the comparator COMP_b2 is connected to the right end of the resistor R9 and the left end of the resistor R8. The input of the right end of the resistor R8 is the output voltage SAMP_V OUT , the left end of resistor R7 is grounded.

[0034] An output terminal of the comparator COMP_a is connected to an input terminal of the One_shot circuit, and an output terminal of the One_shot circuit outputs a reset signal SAMP_RESET2.

[0035] Furthermore, the aforementioned current mirror module includes: a transistor M5, a transistor M6, a transistor M7, and a transistor M8;

[0036] The transistor M5 is connected to the gate of the transistor M6 and to the upper end of the resistor R3. The drain of the transistor M5 is connected to the lower end of the resistor R3. The drain of the transistor M6 is connected to the drain of the transistor M7, the gate of the transistor M7, and the gate of the transistor M8. The source of the transistor M7 and the source of the transistor M8 are connected to the input voltage SAMP_V IN The drain of the transistor M8 is connected to the upper end of the resistor R4 and the inverting input terminal of the comparator COMP_a; the sources of the transistors M5 and M6 and the lower end of the resistor R4 are grounded.

[0037] Compared with the prior art, the beneficial technical effects of the present invention using the above technical solution are as follows:

[0038] Based on the traditional hard-switching Buck converter, this paper proposes a ZVS-Buck converter and control system. The core content of the proposed ZVS-Buck converter and control system is to enable the high-side switch of the Buck converter to be turned on at zero voltage. The high-side switch of the traditional hard-switching Buck converter has very high loss when the switch is turned on, and low loss when it is turned off (such as Figure 4 In order to reduce the size of the power supply and improve its conversion efficiency, it is necessary to solve the switching loss, thereby achieving a higher switching frequency and improving the power density of the power supply.

[0039] Aiming at the high switching loss problem of traditional hard-switching Buck converter, this paper proposes a new control method, which effectively reduces the switching loss of high-side switch and improves the system operating frequency and efficiency (such as Figure 4 (shown by the red line). BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 These are two Buck converter circuit diagrams. (a) is the traditional hard-switching Buck converter circuit, and (b) is the ZVS-Buck converter circuit diagram.

[0041] Figure 2 This is the operating modal analysis diagram of the ZVS-Buck converter circuit.

[0042] Figure 3 It is a functional block diagram of the control method of the present invention.

[0043] Figure 4 This is a comparison chart of the high-side switching losses of the hard-switching Buck converter and the ZVS-Buck converter.

[0044] Figure 5This is a circuit diagram of an implementation method of the invention. In the figure, (a) is the ZVS-Buck converter and switch drive circuit diagram, (b) is the control circuit diagram, (c) is the timer Timer2 circuit diagram, and (d) is the timer Timer1 circuit diagram. DETAILED DESCRIPTION

[0045] In order to better understand the technical content of the present invention, specific embodiments are given and described below with reference to the accompanying drawings.

[0046] Various aspects of the present invention are described herein with reference to the accompanying drawings, which show a number of illustrative embodiments. The embodiments of the present invention are not limited to those described in the accompanying drawings. It should be understood that the present invention can be implemented by any of the various concepts and embodiments described above, as well as the concepts and implementations described in detail below, because the concepts and embodiments disclosed herein are not limited to any particular implementation. In addition, some aspects disclosed herein may be used alone or in any appropriate combination with other aspects disclosed herein.

[0047] like Figure 3 As shown, the present invention proposes a control system based on a zero voltage switching Buck (ZVS-Buck) converter, comprising: a ZVS-Buck converter, a switch drive circuit, and a control circuit; the switch drive circuit is connected to the ZVS-Buck converter, the control circuit is connected to the switch drive circuit, and the ZVS-Buck is connected to the control circuit;

[0048] The driving circuit includes: a clamp switch driving circuit, a low-side switch driving circuit, and a high-side switch driving circuit;

[0049] The control circuit includes: an inductor current sampling module, an output voltage sampling module, a compensation network module, a comparison module, a timer Timer1, a timer Timer2, a dead time module 1, an RS trigger RS_a, a dead time module 2, an RS trigger RS_b, a dead time module 3, and an RS trigger RS_c;

[0050] The input of the first input terminal of the ZVS-Buck converter is the input voltage ZVS_V IN The second input terminal input is the clamp switch drive signal S 33 The input of the third input terminal is the low-side switch drive signal S 22 The input of the fourth input terminal is the high-side switch drive signal S 11 The output of the first output terminal of the ZVS-Buck converter is the output voltage ZVS_V OUT The output of the second output terminal is the inductor current I L ;

[0051] The input of the inductor current sampling module is the inductor current I L , the output is the inductor current sampling signal I SEN2 ;The input of the output voltage sampling module is the output voltage ZVS_V OUT , the output is the output voltage feedback signal V FB ; The input of the compensation network module is the output voltage feedback signal V FB , the output is the control signal V err ; The input of the comparison module is the inductor current sampling signal I SEN2 With the control signal V err , the output is the reset signal RESET1; the output of timer Timer1 is the clock signal CLK and the reset signal RESET3;

[0052] The input of dead time module 1 is clock signal CLK, and the output is set signal SET1; the input of reset terminal of RS flip-flop RS_a is reset signal RESET1, and the input of set terminal is set signal SET1; the output of RS flip-flop RS_a is control signal S1 and S 1B The input of the high-side switch driving circuit is the control signal S1, and the output is the high-side switch driving signal S 11 ;

[0053] The input of dead time module 2 is control signal S 1B , the output is the set signal SET2; the input of timer Timer2 is the input voltage ZVS_V IN , the output is the reset signal RESET2; the input of the reset terminal of the RS flip-flop RS_b is the reset signal RESET2, and the input of the set terminal is the set signal SET2; the output of the RS flip-flop RS_b is the control signal S2 and S 2B The input of the low-side switch driving circuit is the control signal S2, and the output is the low-side switch driving signal S 22 ;

[0054] The input of dead time module 3 is control signal S 2B , the output is the set signal SET3; the input of the reset terminal of the RS flip-flop RS_c is the reset signal RESET3, and the input of the set terminal is the set signal SET3; the output of the RS flip-flop RS_c is the control signal S3 and S 3B The input of the clamp switch driving circuit is the control signal S3, and the output is the clamp switch driving signal S 33 ;

[0055] The working principle of the control system is as follows: the inductor current sampling module and the output voltage sampling module sample and generate the inductor current sampling signal I after the ZVS-Buck converter starts working. SEN2 and the output voltage feedback signal V FB, output voltage feedback signal V FB After frequency compensation is performed by the compensation network module, a control signal V is generated. err . Inductor current sampling signal I SEN2 With the control signal V err After entering the comparison module, the reset signal RESET1 is generated and connected to the reset terminal of RS_a. When the reset signal RESET1 is low, the timer Timer1 generates the clock signal CLK and enters the dead time module 1. After a time T delay1 Then the generated signal SET1 is transmitted to the RS_a set terminal, T delay1 The dead time generated by the dead time module 1; the control signal S1 changes from low level to high level and is transmitted to the high-side switch drive circuit, and then the high-side switch control signal S generated by the high-side switch drive circuit 11 From low level to high level, the high-side switch ZVS_SW1 is controlled to turn on; when the inductor current sampling signal I SEN2 Ratio control signal V err When high, the reset signal RESET1 changes from low level to high level, the control signal S1 changes from high level to low level, S 1B From low level to high level; the control signal S1 is transmitted to the high-side switch driving circuit, and then the high-side switch control signal S generated by the high-side switch driving circuit 11 From high level to low level, the high-side switch ZVS_SW1 is turned off; the control signal S 1B Entering the dead time module 2, after time T delay2 Then the generated signal SET2 is transmitted to the RS_b set terminal, T delay2 The dead time generated by the dead time module 2; the control signal S2 changes from low level to high level, S 2B From high level to low level; the control signal S2 is transmitted to the low-side switch driving circuit, and then the low-side switch control signal S generated by the low-side switch driving circuit 22 From low level to high level, the low-side switch ZVS_SW2 is turned on; the timer Timer2 is controlled by ZVS_V IN Controlled, after time T delay3 After that, the timer Timer2 generates the signal RESET2 and transmits it to the reset terminal RS_b. delay3 The timing time generated by the timer Timer2; the control signal S2 changes from high level to low level, S 2B From low level to high level; the control signal S2 is transmitted to the low-side switch driving circuit, and then the low-side switch control signal S generated by the low-side switch driving circuit 22 From high level to low level, the low-side switch ZVS_SW2 is turned off; the control signal S 2B Entering the dead time module 3, after time Tdelay4 Then the generated signal SET3 is transmitted to the RS_c set terminal, T delay4 The dead time generated by the dead time module 3; the control signal S3 changes from low level to high level, S 3B From high level to low level; the control signal S3 is transmitted to the clamp switch driving circuit, and then the clamp switch driving circuit generates the clamp switch control signal S 33 From low level to high level, the clamp switch ZVS_SW3 is turned on; timer Timer1 passes time T delay5 After that, the signal RESET3 is generated and transmitted to the reset terminal RS_c, T delay5 The timing time generated by the timer Timer1; the control signal S3 changes from high level to low level, S 3B From low level to high level; the control signal S3 is transmitted to the clamp switch driving circuit, and then the clamp switch driving circuit generates the clamp switch control signal S 33 Changes from high level to low level, controlling the clamp switch ZVS_SW3 to turn off.

[0056] like Figure 1 As shown in (b), the present invention provides a ZVS-Buck converter, including: an input voltage ZVS_V IN , high-side switch ZVS_SW1, low-side switch ZVS_SW2, clamp switch ZVS_SW3, output inductor ZVS_L OUT , high-side switch output capacitor ZVS_C1, low-side switch output capacitor ZVS_C2, output capacitor ZVS_C OUT 、Input capacitance ZVS_C IN 、Output voltage ZVS_V OUT , resistor ZVS_R OUT , diode ZVS_D1, diode ZVS_D2;

[0057] Input voltage ZVS_V IN Positive electrode and input capacitor ZVS_C IN The upper end of the high-side switch ZVS_SW1, the cathode of the diode ZVS_D1, and the upper end of the high-side switch output capacitor ZVS_C1 are connected;

[0058] Input voltage ZVS_V IN Negative electrode and input capacitor ZVS_C IN The lower end of the low-side switch ZVS_SW2, the anode of the diode ZVS_D2, the lower end of the low-side switch output capacitor ZVS_C2, the output capacitor ZVS_C OUT The lower end of the output resistor ZVS_R OUT The lower end is connected to the output voltage ZVS_VOUT The negative electrode;

[0059] The lower end of the high-side switch ZVS_SW1 is connected to the anode of the diode ZVS_D1, the cathode of the diode ZVS_D2, the upper end of the low-side switch ZVS_SW2, the left end of the clamp switch ZVS_SW3, and the output inductor ZVS_L OUT The left end is connected;

[0060] The right end of the clamp switch ZVS_SW3 and the output inductor ZVS_L OUT The right end of the output capacitor ZVS_C OUT The upper end of the output resistor ZVS_R OUT The upper end is connected to the output voltage ZVS_V OUT positive electrode.

[0061] The working process of the ZVS-Buck converter is as follows Figure 2 As shown, the specific process is as follows: at time t0, when the clock signal CLK changes from low level to high level, the high-side switch control signal S_SW1 changes from low level to high level, and the high-side switch ZVS_SW1 is turned on; at this time, ZVS_V IN Add directly to the output inductor ZVS_L OUT The inductor is charged, and the inductor current I L Continue to increase; after charging for time T1, at time t1, the inductor current I L Reach peak I max At this time, the high-side switch control signal S_SW1 changes from high level to low level, and the high-side switch ZVS_SW1 is turned off; the inductor current I L During the dead time T dead2 Discharge the parasitic capacitance at node B. At time t2, the node voltage is ZVS_V SW drops to 0V, the low-side switch control signal S_SW2 changes from low level to high level, and the low-side switch ZVS_SW2 is turned on; at this time, the inductor current I L The low-side switch ZVS_SW2 is used for freewheeling, and the inductor current I L The amplitude of the inductor current I L The current value drops to 0 at t3; at this time, the output capacitor ZVS_C OUT is the output inductor ZVS_L OUT is charged, so the inductor current I L From positive to negative; after charging for time T3, the output inductance ZVS_L is detected OUT After storing enough energy, the low-side switch control signal S_SW2 changes from high level to low level at time t4, and the low-side switch ZVS_SW2 is turned off; at this time, the output inductor ZVS_L OUTResonates with the parallel combination of the high-side switch output capacitor ZVS_C1 and the low-side switch output capacitor ZVS_C2, and the node voltage ZVS_V SW To ZVS_V OUT Close to, at the same time the inductor current I L Slightly rising; after the dead time T dead3 After charging, at time t5, the node voltage ZVS_V SW Charge to ZVS_V OUT ; The clamp switch control signal S_SW3 changes from low level to high level, the clamp switch ZVS_SW3 is turned on, and the node voltage ZVS_V SW is clamped to ZVS_V OUT , inductor current I L The current circulates through the clamp switch ZVS_SW3 in an almost lossless manner. After time T4, the clamp phase ends. At time t6, the clamp switch control signal S_SW3 changes from high to low, and the clamp switch ZVS_SW3 is turned off. At this time, the output inductor ZVS_L OUT Resonates with the parallel combination of the high-side switch output capacitor ZVS_C1 and the low-side switch output capacitor ZVS_C2, and the node voltage ZVS_V SW To ZVS_V IN Close to, at the same time the inductor current I L Rising; after dead time T dead1 , at time t7 the node voltage ZVS_V SW Charge to ZVS_V IN , inductor current I L It rises to 0A, meeting the zero voltage turn-on condition. At this time, the clock signal CLK changes from low level to high level again, the high-side switch control signal S_SW1 changes from low level to high level, the high-side switch ZVS_SW1 turns on, and a cycle ends.

[0062] Specific implementation cases of the present invention are as follows Figure 5 As shown, the ZVS-Buck converter and switch drive circuit are as follows Figure 5 As shown in (a), Figure 5 The ZVS-Buck converter part in (a) is Figure 3 The specific scheme of the ZVS-Buck converter, the number of ports and their names are Figure 3 The ZVS-Buck converter in the Figure 5 In (a), the inductor current sampling module and the output current sampling module belong to the control circuit part; the input of the ZVS-Buck converter and the switch drive circuit is SAMP_V IN, high-side switch drive circuit control signal SAMP_S1, low-side switch drive circuit control signal SAMP_S2 and clamp switch drive circuit control signal SAMP_S3, the output is SAMP_V OUT , output voltage feedback signal SAMP_V FB and the inductor current sampling signal SAMP_I SEN2 SAMP_V IN Through capacitor SAMP_C IN After filtering, the output inductor SAMP_L is connected to the high-side switch tube M1, the low-side switch tube M2, and the energy storage element. OUT and output capacitor SAMP_C OUT When the high-side switch M1 of the ZVS-Buck converter is turned on, SAMP_V IN Directly applied to the inductor SAMP_L through M1 OUT At the same time, the output capacitor SAMP_C OUT charging, providing a smooth SAMP_V for the output load OUT , the low-side switch tube M2 is in the off state at this time; when the high-side switch tube M1 is disconnected, because the inductor current SAMP_I L It cannot change suddenly, so it is necessary to form a loop through the low-side switch tube M2 to release the energy stored in the output inductor. The high-side switching loss of the traditional hard-switched Buck converter is mainly caused by the loss during the turn-off to turn-on process. Therefore, the present invention introduces the switch tubes M3 and M4 to form a clamp switch, by making the node voltage SAMP_V SW Before the high-side switch M1 is turned on, SAMP_V is reached. IN To meet the zero voltage turn-on condition and reduce the switching loss of the high-side switch tube of the traditional hard-switching Buck converter. The high-side switch drive circuit, low-side switch drive circuit, and clamp switch drive circuit are existing technologies and will not be described here in detail.

[0063] Control circuit such as Figure 5 As shown in (b), the input of the control circuit is SAMP_V IN , SAMP_V OUT , output voltage feedback signal SAMP_V FB , inductor current sampling signal SAMP_I SEN2 , reference voltage V REF1 , Timer2 input reference voltage V REF2 The reference voltage V REF3 With V REF4 , the output is the control signal SAMP_S1 and SAMP_S 1B , control signal SAMP_S2 and SAMP_S 2Band control signals SAMP_S3 and SAMP_S 3B ; Output voltage feedback signal SAMP_V FB With the reference voltage V REF1 After frequency compensation by PI compensator, control signal SAMP_V is generated err Inductor current sampling signal SAMP_I SEN2 With the control signal SAMP_V err After the comparison by comparator COMP_1, reset signal SAMP_RESET1 is generated and connected to the reset terminal of SAMP_RS_a. When the reset signal SAMP_RESET1 is low, timer Timer1 generates clock signal SAMP_CLK and enters dead time module 1. After time T SAMP_delay1 Then the signal SAMP_SET1 is generated and transmitted to the SAMP_RS_a set terminal, T SAMP_delay1 The dead time generated by the dead time module 1; the control signal SAMP_S1 changes from low level to high level, SAMP_S 1B From high level to low level; the control signal SAMP_S1 is transmitted to the high-side switch drive circuit; when the inductor current sampling signal SAMP_I SEN2 than the control signal SAMP_V err When high, the reset signal SAMP_RESET1 changes from low level to high level, the control signal SAMP_S1 changes from high level to low level, and SAMP_S 1B From low level to high level; control signal SAMP_S 1B Entering the dead time module 2, after time T SAMP_delay2 The generated signal SAMP_SE2 is then transmitted to the SAMP_RS_b set terminal, T SAMP_delay2 The dead time generated by the dead zone module 2; the control signal SAMP_S2 changes from low level to high level, SAMP_S 2B From high level to low level, the control signal SAMP_S2 is transmitted to the low-side switch driving circuit; the timer Timer2 is set by the inductor current sampling signal SAMP_I SEN2 , SAMP_V IN With SAMP_V OUT Controlled, after time T SAMP_delay3 After that, the timer Timer2 generates the signal SAMP_RESE2T and transmits it to the reset terminal SAMP_RS_b. SAMP_delay3 The timing time generated by the timer Timer2; the control signal SAMP_S2 changes from high level to low level, SAMP_S 2B From low level to high level; control signal SAMP_S 2B Entering the dead time module 3, after time TSAMP_delay4 The generated signal SAMP_SET3 is then transmitted to the SAMP_RS_c set terminal, T SAMP_delay4 The dead time generated by the dead zone module 3; the control signal SAMP_S3 changes from low level to high level, SAMP_S 3B From high level to low level, the control signal SAMP_S3 is transmitted to the clamp switch drive circuit; timer Timer1 passes time T SAMP_delay1 After that, the signal SAMP_RESET3 is generated and transmitted to the reset terminal of RS_c, and the control signal SAMP_S3 changes from high level to low level. 3B From low level to high level. Figure 5 (b) The control mechanism of the control circuit.

[0064] like Figure 5 As shown in (d), the timer Timer1 includes: operational amplifier OPA_b, comparator COMP_b1, transistor M9, transistor M 10 , transistor M 11 , capacitor Timer1_C1, resistor R 10 ;

[0065] The input of timer Timer1 is the reference voltage V REF3 With V REF4 The inverting input of the amplifier OPA_b is input as the reference voltage V REF3 The inverting input of comparator COMP_b1 is input as reference voltage V REF4 ; The non-inverting input of amplifier OPA_b and resistor R 10 The upper end of and the drain of transistor M9 are connected;

[0066] The output terminal of the amplifier OPA_b is connected to the gate of the transistor M9 and the transistor M 10 The gate of transistor M9 is connected; the source of transistor M 10 The source access input voltage SAMP_V IN , transistor M 10 The drain of transistor M 11 The drain of , the upper end of capacitor Timer1_C1, and the non-inverting input terminal of comparator COMP_b1 are connected;

[0067] Transistor M 11 The source of transistor M is connected to the lower end of capacitor Timer1_C1 and grounded; 11The gate of is connected to the output end of the comparator COMP_b1 through a buffer, the output end of the comparator COMP_b1 is connected to a two-input AND gate, and outputs a clock signal SAMP_CLK and a reset signal SAMP_RESET3.

[0068] The input of the timer Timer1 is the reference voltage V REF3 With V REF4 , the output is the clock signal SAMP_CLK and the reset signal SAMP_RESET3; assuming that in the initial stage M9 and M 10 are both in the off state, the node voltage V D9 is 0, the reference voltage V REF3 Ratio node voltage V D9 High, amplifier OPA_b outputs low level, transistors M9, M 10 Turn on; amplifier OPA_b and transistor M9 form a voltage series negative feedback, and the node voltage V can be obtained by the virtual short of the amplifier. D9 Finally equal to the reference voltage V REF3 ; Node voltage V G9 Ratio node voltage V D9 The intrinsic gain of the small transistor M9 is times that of the transistor M9. By adjusting the size of the transistor M9, the transistor M9 and M 10 Normally open; transistor M 10 Branch current I DS10 Charge the capacitor Timer1_C1, the node voltage V D10 Rising; when the reference voltage V REF4 Ratio node voltage V D10 When the comparator COMP_b1 is low, the clock signal SAMP_CLK and the reset signal SAMP_RESET3 output by the comparator COMP_b1 are both high level; the transistor M 11 Turn on, discharge the charge stored in capacitor Timer1_C1, node voltage V D10 Decrease; when the node voltage V D10 drops below the reference voltage V REF4 When the comparator COMP_b outputs the clock signal SAMP_CLK and the reset signal SAMP_RESET3, both change from high level to low level; the transistor M 11 Shutdown, branch current I DS10 The capacitor Timer1_C1 is recharged, and a timing cycle ends. The above is the generation mechanism of the clock signal SAMP_CLK and the reset signal SAMP_RESET3.

[0069] like Figure 5As shown in (c), timer Timer2 includes: a transconductance amplifier OTA_a, a comparator COMP_b2, a comparator COMP_a, a current mirror module, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, and a one-shot circuit;

[0070] The input of the non-inverting input terminal of the transconductance amplifier OTA_a is the inductor current sampling signal SAMP_I SEN2 , the inverting input is grounded, the output of the transconductance amplifier OTA_a is connected to the upper end of the resistor R3 and the left end of the current mirror module, the right end of the current mirror module is connected to the upper end of the resistor R4 and the inverting input of the comparator COMP_a, the non-inverting input of the comparator COMP_a is connected to the output of the comparator COMP_b2 and the left end of the resistor R9; the current mirror module is connected by the input voltage SAMP_V IN Provide power supply;

[0071] The current mirror module includes: a transistor M5, a transistor M6, a transistor M7, and a transistor M8;

[0072] The transistor M5 is connected to the gate of the transistor M6 and to the upper end of the resistor R3. The drain of the transistor M5 is connected to the lower end of the resistor R3. The drain of the transistor M6 is connected to the drain of the transistor M7, the gate of the transistor M7, and the gate of the transistor M8. The source of the transistor M7 and the source of the transistor M8 are connected to the input voltage SAMP_V IN The drain of the transistor M8 is connected to the upper end of the resistor R4 and the inverting input terminal of the comparator COMP_a; the sources of the transistors M5 and M6 and the lower end of the resistor R4 are grounded.

[0073] The right end of resistor R5 is connected to the input voltage SAMP_V IN The left end is connected to the right end of resistor R7, the left end of resistor R6, and the non-inverting input of comparator COMP_b2. The input of the right end of resistor R6 is the reference voltage V REF2 The inverting input of the comparator COMP_b2 is connected to the right end of the resistor R9 and the left end of the resistor R8. The input of the right end of the resistor R8 is the output voltage SAMP_V OUT , the left end of resistor R7 is grounded.

[0074] An output terminal of the comparator COMP_a is connected to an input terminal of the One_shot circuit, and an output terminal of the One_shot circuit outputs a reset signal SAMP_RESET2.

[0075] The input of the timer Timer2 is the inductor current sampling signal SAMP_I SEN2 , SAMP_VIN With SAMP_V OUT , the output is the reset signal SAMP_RESET2; the inductor current sampling signal SAMP_I SEN2 Generate current I through transconductance amplifier DS5 , after passing through the current mirror module composed of M5, M6, M7 and M8, the current I is generated DS8 , current I DS8 The value of the inductor current SAMP_I L Multiply by the proportional coefficient K and add the DC bias value; I DS8 Flowing through resistor R4 generates voltage V D8 Connect to the inverting terminal of comparator COMP_a, and the non-inverting terminal of COMP_a is connected to the reference voltage V REF2 , SAMP_V IN With SAMP_V OUT After addition, subtraction and proportional operation, it is connected; when the output inductance SAMP_L is detected OUT Store enough energy, that is, V D8 When the voltage is less than the non-inverting input voltage of comparator COMP_a, the output of comparator COMP_a changes from low to high. After passing through the one-shot circuit, the output reset signal SAMP_RESET2 changes from low to high, thus completing one timing cycle. The above is the generation mechanism of the reset signal SAMP_RESET2.

[0076] The inductor current sampling module, output voltage sampling module, compensation network module, comparison module, dead time module 1, RS trigger SAMP_RS_a, dead time module 2, RS trigger SAMP_RS_b, dead time module 3, and RS trigger SAMP_RS_c in the present invention are prior arts and will not be described in detail here.

[0077] The core content of the zero voltage switching Buck converter and control system proposed in this invention is to enable the high-side switch of the Buck converter to be turned on at zero voltage. The high-side switch of the traditional hard-switched Buck converter has very high loss when the switch is turned on, and low loss when it is turned off, such as Figure 4 In order to reduce the size of the power supply and improve its conversion efficiency, it is necessary to solve the switching loss, thereby achieving a higher switching frequency and improving the power density of the power supply.

[0078] Aiming at the high switching loss problem of traditional hard-switching Buck converter, this paper proposes a new control method, which effectively reduces the switching loss of high-side switch and improves the system operating frequency and efficiency. Figure 4 The red line part is shown.

[0079] While the present invention has been described above with reference to preferred embodiments, this is not intended to limit the present invention. Persons skilled in the art will readily appreciate that various modifications and variations can be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A control system based on a zero voltage switching Buck (hereinafter referred to as ZVS-Buck) converter, characterized in that: include: A ZVS-Buck converter, a switch drive circuit, and a control circuit; the switch drive circuit is connected to the ZVS-Buck converter, the control circuit is connected to the switch drive circuit, and the ZVS-Buck is connected to the control circuit; The driving circuit includes: a clamp switch driving circuit, a low-side switch driving circuit, and a high-side switch driving circuit; The control circuit includes: an inductor current sampling module, an output voltage sampling module, a compensation network module, a comparison module, a timer Timer1, a timer Timer2, a dead time module 1, an RS trigger RS_a, a dead time module 2, an RS trigger RS_b, a dead time module 3, and an RS trigger RS_c; The input of the first input terminal of the ZVS-Buck converter is the input voltage ZVS_V IN The second input terminal input is the clamp switch drive signal S 33 The input of the third input terminal is the low-side switch drive signal S 22 The input of the fourth input terminal is the high-side switch drive signal S 11 The output of the first output terminal of the ZVS-Buck converter is the output voltage ZVS_V OUT The output of the second output terminal is the inductor current I L ; The input of the inductor current sampling module is the inductor current I L , the output is the inductor current sampling signal I SEN2 ;The input of the output voltage sampling module is the output voltage ZVS_V OUT , the output is the output voltage feedback signal V FB ; The input of the compensation network module is the output voltage feedback signal V FB , the output is the control signal V err ; The input of the comparison module is the inductor current sampling signal I SEN2 With the control signal V err , the output is the reset signal RESET1; the output of timer Timer1 is the clock signal CLK and the reset signal RESET3; The input of dead time module 1 is clock signal CLK, and the output is set signal SET1; the input of reset terminal of RS flip-flop RS_a is reset signal RESET1, and the input of set terminal is set signal SET1; the output of RS flip-flop RS_a is control signal S1 and S 1B The input of the high-side switch driving circuit is the control signal S1, and the output is the high-side switch driving signal S 11 ; The input of dead time module 2 is control signal S 1B , the output is the set signal SET2; the input of timer Timer2 is the input voltage ZVS_V IN , the output is the reset signal RESET2; the input of the reset terminal of the RS flip-flop RS_b is the reset signal RESET2, and the input of the set terminal is the set signal SET2; the output of the RS flip-flop RS_b is the control signal S2 and S 2B The input of the low-side switch driving circuit is the control signal S2, and the output is the low-side switch driving signal S 22 ; The input of dead time module 3 is control signal S 2B , the output is the set signal SET3; the input of the reset terminal of the RS flip-flop RS_c is the reset signal RESET3, and the input of the set terminal is the set signal SET3; the output of the RS flip-flop RS_c is the control signal S3 and S 3B The input of the clamp switch driving circuit is the control signal S3, and the output is the clamp switch driving signal S 33。 2. A ZVS-Buck converter, characterized in that: The ZVS-Buck converter includes: input voltage ZVS_V IN , high-side switch ZVS_SW1, low-side switch ZVS_SW2, clamp switch ZVS_SW3, output inductor ZVS_L OUT , high-side switch output capacitor ZVS_C1, low-side switch output capacitor ZVS_C2, output capacitor ZVS_C OUT 、Input capacitance ZVS_C IN 、Output voltage ZVS_V OUT , resistor ZVS_R OUT , diode ZVS_D1, diode ZVS_D2; Input voltage ZVS_V IN Positive electrode and input capacitor ZVS_C IN The upper end of the high-side switch ZVS_SW1, the cathode of the diode ZVS_D1, and the upper end of the high-side switch output capacitor ZVS_C1 are connected; Input voltage ZVS_V IN Negative electrode and input capacitor ZVS_C IN The lower end of the low-side switch ZVS_SW2, the anode of the diode ZVS_D2, the lower end of the low-side switch output capacitor ZVS_C2, the output capacitor ZVS_C OUT The lower end of the output resistor ZVS_R OUT The lower end is connected to the output voltage ZVS_V OUT The negative electrode; The lower end of the high-side switch ZVS_SW1 is connected to the anode of the diode ZVS_D1, the cathode of the diode ZVS_D2, the upper end of the low-side switch ZVS_SW2, the left end of the clamp switch ZVS_SW3, and the output inductor ZVS_L OUT The left end is connected; The right end of the clamp switch ZVS_SW3 and the output inductor ZVS_L OUT The right end of the output capacitor ZVS_C OUT The upper end of the output resistor ZVS_R OUT The upper end is connected to the output voltage ZVS_V OUT positive electrode.

3. A control system based on a ZVS-Buck converter according to claim 1, characterized in that: The driving circuit includes: a clamp switch driving circuit, a low-side switch driving circuit, and a high-side switch driving circuit; The control circuit includes: an inductor current sampling module, an output voltage sampling module, a PI compensator, a comparator COMP_1, a timer Timer1, a timer Timer2, a dead time module 1, an RS trigger SAMP_RS_a, a dead time module 2, an RS trigger SAMP_RS_b, a dead time module 3, and an RS trigger SAMP_RS_c; The input of the first input terminal of the ZVS-Buck converter is the input voltage SAMP_V IN The second input terminal, the third input terminal, and the fourth input terminal respectively input the output signals from the clamp switch driving circuit, the low-side switch driving circuit, and the high-side switch driving circuit; the first output terminal of the ZVS-Buck converter outputs the output voltage SAMP_V OUT The second output terminal outputs the inductor current SAMP_I L ; The input of the inductor current sampling module is the inductor current SAMP_I L , the output is the inductor current sampling signal SAMP_I SEN2 ;The input of the output voltage sampling module is the output voltage SAMP_V OUT , the output is the output voltage feedback signal SAMP_V FB ; The input of the PI compensator is the output voltage feedback signal SAMP_V FB With the reference voltage V REF1 , the output is the control signal SAMP_V err The input of the non-inverting terminal of the comparator COMP_1 is the inductor current sampling signal SAMP_I SEN2 , the input of the inverting terminal is the control signal SAMP_V err The output of comparator COMP_1 is reset signal SAMP_RESET1; the input of timer Timer1 is reference voltage V REF3 With the reference voltage V REF4 , the output is the clock signal SAMP_CLK and the reset signal SAMP_RESET3; The input of dead time module 1 is clock signal SAMP_CLK, and the output is set signal SAMP_SET1; the input of reset terminal of RS flip-flop SAMP_RS_a is reset signal SAMP_RESET1, and the input of set terminal is set signal SAMP_SET1; the output of RS flip-flop SAMP_RS_a is control signal SAMP_S1 and SAMP_S 1B ;The input of the high-side switch driver circuit is the control signal SAMP_S1; The input of dead time module 2 is the control signal SAMP_S 1B , the output is the set signal SAMP_SET2; the input of timer Timer2 is the input voltage SAMP_V IN , output voltage SAMP_V OUT , inductor current sampling signal SAMP_I SEN2 And the reference voltage V REF2 , the output is the reset signal SAMP_RESET2; the input of the reset terminal of the RS flip-flop SAMP_RS_b is the reset signal SAMP_RESET2, and the input of the set terminal is the set signal SAMP_SET2; the output of the RS flip-flop SAMP_RS_b is the control signal SAMP_S2 and SAMP_S 2B ;The input of the low-side switch driver circuit is the control signal SAMP_S2; The input of dead time module 3 is the control signal SAMP_S 2B , the output is the set signal SAMP_SET3; the input of the reset terminal of the RS flip-flop SAMP_RS_c is the reset signal SAMP_RESET3, and the input of the set terminal is the set signal SAMP_SET3; the output of the RS flip-flop SAMP_RS_c is the control signal SAMP_S3 and SAMP_S 3B ; The input of the clamp switch driving circuit is the control signal SAMP_S 3。 4. A control system based on a ZVS-Buck converter according to claim 3, characterized in that: Timer Timer1 includes: operational amplifier OPA_b, comparator COMP_b1, transistor M9, transistor M 10 , transistor M 11 , capacitor Timer1_C1, resistor R 10 ; The input of timer Timer1 is the reference voltage V REF3 With V REF4 The inverting input of the amplifier OPA_b is input as the reference voltage V REF3 The inverting input of comparator COMP_b1 is input as reference voltage V REF4 ; The non-inverting input of amplifier OPA_b and resistor R 10 The upper end of and the drain of transistor M9 are connected; The output terminal of the amplifier OPA_b is connected to the gate of the transistor M9 and the transistor M 10 The gate of transistor M9 is connected; the source of transistor M 10 The source access input voltage SAMP_V IN , transistor M 10 The drain of transistor M 11 The drain of , the upper end of capacitor Timer1_C1, and the non-inverting input terminal of comparator COMP_b1 are connected; Transistor M 11 The source of transistor M is connected to the lower end of capacitor Timer1_C1 and grounded; 11 The gate of is connected to the output end of the comparator COMP_b1 through a buffer, the output end of the comparator COMP_b1 is connected to a two-input AND gate, and outputs a clock signal SAMP_CLK and a reset signal SAMP_RESET3.

5. A ZVS-Buck converter control system according to claim 3 or 4, characterized in that: Timer Timer2 includes: a transconductance amplifier OTA_a, a comparator COMP_b2, a comparator COMP_a, a current mirror module, resistors R3, R4, R5, R6, R7, R8, R9, and a one-shot circuit; The input of the non-inverting input terminal of the transconductance amplifier OTA_a is the inductor current sampling signal SAMP_I SEN2 , the inverting input is grounded, the output of the transconductance amplifier OTA_a is connected to the upper end of the resistor R3 and the left end of the current mirror module, the right end of the current mirror module is connected to the upper end of the resistor R4 and the inverting input of the comparator COMP_a, the non-inverting input of the comparator COMP_a is connected to the output of the comparator COMP_b2 and the left end of the resistor R9; the current mirror module is connected by the input voltage SAMP_V IN Provide power supply; The right end of resistor R5 is connected to the input voltage SAMP_V IN The left end is connected to the right end of resistor R7, the left end of resistor R6, and the non-inverting input of comparator COMP_b2. The input of the right end of resistor R6 is the reference voltage V REF2 The inverting input of the comparator COMP_b2 is connected to the right end of the resistor R9 and the left end of the resistor R8. The input of the right end of the resistor R8 is the output voltage SAMP_V OUT , the left end of resistor R7 is grounded. An output terminal of the comparator COMP_a is connected to an input terminal of the One_shot circuit, and an output terminal of the One_shot circuit outputs a reset signal SAMP_RESET2.

6. The control system of a ZVS-Buck converter according to claim 5, characterized in that: The current mirror module includes: a transistor M5, a transistor M6, a transistor M7, and a transistor M8; The transistor M5 is connected to the gate of the transistor M6 and to the upper end of the resistor R3. The drain of the transistor M5 is connected to the lower end of the resistor R3. The drain of the transistor M6 is connected to the drain of the transistor M7, the gate of the transistor M7, and the gate of the transistor M8. The source of the transistor M7 and the source of the transistor M8 are connected to the input voltage SAMP_V IN The drain of the transistor M8 is connected to the upper end of the resistor R4 and the inverting input terminal of the comparator COMP_a; the sources of the transistors M5 and M6 and the lower end of the resistor R4 are grounded.

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