Etching method and plasma processing apparatus

Abstract

The etching method provided by the present invention comprises: (a) a step of providing a substrate including a first layer and a second layer having a pattern on the first layer; (b) a step for forming a silicon-containing layer on the surface of the second layer more preferentially than the surface of the first layer; (c) a step for forming a metal-containing layer on the surface of the silicon-containing layer; and (d) etching the exposed first layer using the second layer, the silicon-containing layer, and the metal-containing layer as masks.

Description

Technical Field

[0001] Embodiments of the present invention relate to an etching method and a plasma processing apparatus. Background Art

[0002] Patent Document 1 below discloses a method for manufacturing a semiconductor device, wherein a substrate having a patterned layer deposited thereon by a photolithography process is exposed to plasma, thereby depositing a layer containing silicon on the patterned layer. The plasma is generated from a mixed gas containing SiCl4 and one or more of argon, helium, nitrogen, and hydrogen.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent document 1: U.S. Patent Application Publication No. 2021-0183656. Summary of the Invention

[0006] Problems to be solved by the invention

[0007] The present invention provides an etching method and a plasma processing device capable of improving an etching selectivity ratio.

[0008] Technical means to solve the problem

[0009] In an exemplary embodiment, an etching method is provided. The etching method includes: (a) providing a substrate, wherein the substrate includes a first layer and a second layer having a pattern on the first layer; (b) forming a silicon-containing layer on a surface of the second layer, preferentially over a surface of the first layer; (c) forming a metal-containing layer on the surface of the silicon-containing layer; and (d) etching the exposed first layer using the second layer, the silicon-containing layer, and the metal-containing layer as masks.

[0010] Effects of the Invention

[0011] According to an exemplary embodiment, a technique capable of improving an etching selectivity ratio is provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a diagram for explaining a configuration example of a plasma processing system.

[0013] Figure 2 This is a diagram for explaining a configuration example of a capacitively coupled plasma processing apparatus.

[0014] Figure 3 is a flow chart of an etching method according to an exemplary embodiment.

[0015] Figure 4 (a) to Figure 4 (d) are used to illustrate Figure 3 Schematic cross-sectional view of the etching method.

[0016] Figure 5 (a) and (b) are schematic cross-sectional views for explaining a method for forming a resist layer according to an exemplary embodiment.

[0017] Figure 6 This is a flowchart of a method for forming a resist layer.

[0018] Figure 7 (a) is a schematic cross-sectional view for explaining the surface treatment of the silicon-containing layer, Figure 7 (b) is a schematic cross-sectional view for explaining trim etching of the silicon-containing layer.

[0019] Figure 8 is a flow chart of a method for forming a silicon-containing layer.

[0020] Figure 9 (a) is a schematic cross-sectional view for explaining the surface treatment of the metal-containing layer, Figure 9 (b) is a schematic cross-sectional view for explaining trim etching of the metal-containing layer.

[0021] Figure 10 is a flow chart of a method for forming a metal-containing layer.

[0022] Figure 11 (a) is a schematic cross-sectional view for explaining a method for forming a deposited layer according to a first modification example. Figure 11 (b) is a schematic cross-sectional view for explaining etching according to the first modification.

[0023] Figure 12 (a) is a schematic cross-sectional view for explaining etching of the second modification example, Figure 12 (b) is a schematic cross-sectional view for explaining a method for generating a deposited layer according to a second modification example. Figure 12 (c) is a schematic cross-sectional view for explaining etching according to the second modification.

[0024] Figure 13 (a) and (b) are schematic cross-sectional views for explaining a method for forming a metal-containing layer according to a third modification. DETAILED DESCRIPTION

[0025] Various exemplary embodiments will be described below.

[0026] In an exemplary embodiment, an etching method is provided. The etching method includes: (a) providing a substrate, wherein the substrate includes a first layer and a second layer having a pattern on the first layer; (b) forming a silicon-containing layer on a surface of the second layer, preferentially over a surface of the first layer; (c) forming a metal-containing layer on the surface of the silicon-containing layer; and (d) etching the exposed first layer using the second layer, the silicon-containing layer, and the metal-containing layer as masks.

[0027] In another exemplary embodiment, a plasma processing apparatus is provided. The plasma processing apparatus includes: a chamber; a substrate support disposed within the chamber and having a temperature control module; a gas supply configured to supply a processing gas into the chamber; a plasma generation unit configured to generate plasma from the processing gas within the chamber; and a control unit. The control unit is configured to control the temperature control module, the gas supply unit, and the plasma generation unit so that, when a substrate including a first layer and a second layer having a pattern on the first layer is supported by the substrate support, a silicon-containing layer is formed preferentially on the surface of the second layer relative to the surface of the first layer, a metal-containing layer is formed on the surface of the silicon-containing layer, and the exposed first layer is etched using the second layer, the silicon-containing layer, and the metal-containing layer as masks.

[0028] Hereinafter, various exemplary embodiments will be described in detail with reference to the accompanying drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals.

[0029] Figure 1 : is a diagram for illustrating a structural example of a plasma processing system. In one embodiment, the plasma processing system includes a plasma processing device 1 and a control unit 2. The plasma processing system is an example of a substrate processing system, and the plasma processing device 1 is an example of a substrate processing device. The plasma processing device 1 includes a plasma processing chamber 10, a substrate support portion 11, and a plasma generating portion 12. The plasma processing chamber 10 has a plasma processing space. In addition, the plasma processing chamber 10 has: at least one gas supply port for supplying at least one processing gas to the plasma processing space; and at least one gas exhaust port for exhausting gas from the plasma processing space. The gas supply port is connected to the gas supply portion 20 described later, and the gas exhaust port is connected to the exhaust system 40 described later. The substrate support portion 11 is arranged in the plasma processing space and has a substrate supporting surface for supporting a substrate.

[0030] The plasma generating section 12 is configured to generate plasma from at least one processing gas supplied into the plasma processing space. The plasma formed in the plasma processing space may be capacitively coupled plasma (CCP: Capacitively Coupled Plasma), inductively coupled plasma (ICP: Inductively Coupled Plasma), ECR plasma (Electron-Cyclotron-resonance plasma), helicon wave plasma (HWP: Helicon Wave Plasma) or surface wave plasma (SWP: Surface Wave Plasma), etc. In addition, various types of plasma generating sections including AC (Alternating Current: Alternating Current) plasma generating sections and DC (Direct Current: Direct Current) plasma generating sections may also be used. In one embodiment, the AC signal (AC power) used in the AC plasma generating section has a frequency in the range of 100kHz to 10GHz. Therefore, the AC signal includes an RF (Radio Frequency: high frequency) signal and a microwave signal. In one embodiment, the RF signal has a frequency in the range of 100kHz to 150MHz.

[0031] The control unit 2 processes computer-executable commands that cause the plasma processing apparatus 1 to perform the various processes described in the present invention. The control unit 2 can be configured to control the various elements of the plasma processing apparatus 1 to perform the various processes described herein. In one embodiment, a portion or all of the control unit 2 can be included in the plasma processing apparatus 1. The control unit 2 can include a processing unit 2a1, a storage unit 2a2, and a communication interface 2a3. The control unit 2 is implemented, for example, by a computer 2a. The processing unit 2a1 can be configured to perform various control operations by reading a program from the storage unit 2a2 and executing the read program. The program can be pre-stored in the storage unit 2a2 or obtained via a medium when necessary. The obtained program is stored in the storage unit 2a2 and read and executed from the storage unit 2a2 by the processing unit 2a1. The medium can be various storage media readable by the computer 2a, or a communication line connected to the communication interface 2a3. The processing unit 2a1 can be a CPU (Central Processing Unit). The storage unit 2a2 may include RAM (Random Access Memory), ROM (Read Only Memory), HDD (Hard Disk Drive), SSD (Solid State Drive), or a combination thereof. The communication interface 2a3 may also communicate with the plasma processing apparatus 1 via a communication line such as a LAN (Local Area Network).

[0032] Hereinafter, a configuration example of a capacitive coupling type plasma processing apparatus will be described as an example of the plasma processing apparatus 1 . Figure 2 This is a diagram for explaining a configuration example of a capacitively coupled plasma processing apparatus.

[0033] A capacitively coupled plasma processing apparatus 1 includes a plasma processing chamber 10, a gas supply unit 20, a power supply 30, and an exhaust system 40. In addition, the plasma processing apparatus 1 includes a substrate support unit 11 and a gas inlet unit. The gas inlet unit is configured to introduce at least one processing gas into the plasma processing chamber 10. The gas inlet unit includes a shower head 13. The substrate support unit 11 is disposed in the plasma processing chamber 10. The shower head 13 is disposed above the substrate support unit 11. In one embodiment, the shower head 13 constitutes at least a portion of the ceiling of the plasma processing chamber 10. The plasma processing chamber 10 has a plasma processing space 10s defined by the shower head 13, the sidewall 10a of the plasma processing chamber 10, and the substrate support unit 11. The plasma processing chamber 10 is grounded. The shower head 13 and the substrate support unit 11 are electrically insulated from the housing of the plasma processing chamber 10. In addition, in the plasma processing space 10s, processing that does not utilize plasma can be performed. In other words, the steps performed in the plasma processing space 10s may include steps that do not utilize plasma.

[0034] The substrate support portion 11 includes a main body 111 and a ring assembly 112. The main body 111 has a central region 111a for supporting a substrate W and an annular region 111b for supporting the ring assembly 112. A wafer is an example of a substrate W. The annular region 111b of the main body 111 surrounds the central region 111a of the main body 111 when viewed from above. The substrate W is arranged on the central region 111a of the main body 111, and the ring assembly 112 is arranged on the annular region 111b of the main body 111 so as to surround the substrate W on the central region 111a of the main body 111. Therefore, the central region 111a is also referred to as a substrate supporting surface for supporting the substrate W, and the annular region 111b is also referred to as a ring supporting surface for supporting the ring assembly 112. Depending on the processing to be performed, the ring assembly 112 can be made of an inorganic material or an organic material.

[0035] In one embodiment, the main body 111 includes a base 1110 and an electrostatic chuck 1111. The base 1110 includes a conductive component. The conductive component of the base 1110 can function as a lower electrode. The electrostatic chuck 1111 is arranged on the base 1110. The electrostatic chuck 1111 includes a ceramic component 1111a and an electrostatic electrode 1111b arranged in the ceramic component 1111a. The ceramic component 1111a has a central area 111a. In one embodiment, the ceramic component 1111a also has an annular area 111b. In addition, other components surrounding the electrostatic chuck 1111, such as an annular electrostatic chuck and an annular insulating component, may also have an annular area 111b. In this case, the ring assembly 112 can be arranged on the annular electrostatic chuck or the annular insulating component, or on both the electrostatic chuck 1111 and the annular insulating component. In addition, at least one RF / DC electrode coupled to the RF power supply 31 and / or DC power supply 32 described later may also be arranged in the ceramic component 1111a. In this case, the at least one RF / DC electrode functions as a lower electrode. In the case where the bias RF signal and / or DC signal described later is supplied to the at least one RF / DC electrode, the RF / DC electrode is also referred to as a bias electrode. In addition, the conductive component of the base 1110 and the at least one RF / DC electrode may also function as multiple lower electrodes. In addition, the electrostatic electrode 1111b may also function as a lower electrode. Therefore, the substrate support portion 11 includes at least one lower electrode.

[0036] The ring assembly 112 includes one or more ring components. In one embodiment, the one or more ring components include one or more edge rings and at least one cover ring. The edge ring is formed of a conductive material or an insulating material, and the cover ring is formed of an insulating material.

[0037] The substrate support portion 11 may also include a temperature regulating module configured to regulate at least one of the electrostatic chuck 1111, the ring assembly 112, and the substrate to a target temperature. The temperature regulating module may include a heater, a heat-conducting medium, a flow path 1110a, or a combination thereof. A heat-conducting fluid such as brine or gas flows in the flow path 1110a. In one embodiment, the flow path 1110a is formed in the base 1110, and one or more heaters are arranged in the ceramic component 1111a of the electrostatic chuck 1111. In addition, the substrate support portion 11 may also include a heat-conducting gas supply portion configured to supply heat-conducting gas to the gap between the back surface of the substrate W and the central area 111a. In one example, the target temperature is above -80°C and below 50°C.

[0038] The shower head 13 is configured to introduce at least one processing gas from the gas supply unit 20 into the plasma processing space 10s. The shower head 13 has at least one gas supply port 13a, at least one gas diffusion chamber 13b, and a plurality of gas inlet ports 13c. The processing gas supplied to the gas supply port 13a is introduced into the plasma processing space 10s from the plurality of gas inlet ports 13c through the gas diffusion chamber 13b. In addition, the shower head 13 includes at least one upper electrode. In addition, the gas inlet portion may further include, in addition to the shower head 13, one or more side gas injection portions (SGI: Side Gas Injector) installed in one or more openings formed in the side wall 10a.

[0039] The gas supply unit 20 is a component that supplies the aforementioned process gas into the plasma processing chamber 10 and may include at least one gas source 21 and at least one flow controller 22. In one embodiment, the gas supply unit 20 is configured to supply at least one process gas from a corresponding gas source 21 to the showerhead 13 via a corresponding flow controller 22. Each flow controller 22 may, for example, comprise a mass flow controller or a pressure-controlled flow controller. Furthermore, the gas supply unit 20 may also include at least one flow modulation device for modulating or pulsing the flow of at least one process gas.

[0040] The power supply 30 includes an RF power supply 31 coupled to the plasma processing chamber 10 via at least one impedance matching circuit. The RF power supply 31 is configured to supply at least one RF signal (RF power) to at least one lower electrode and / or at least one upper electrode. This generates a plasma from at least one process gas supplied to the plasma processing space 10s. Therefore, the RF power supply 31 can function as at least a portion of the plasma generating unit 12. Furthermore, by supplying a bias RF signal to the at least one lower electrode, a bias potential can be generated on the substrate W, thereby introducing ions from the generated plasma into the substrate W.

[0041] In one embodiment, the RF power supply 31 includes a first RF generator 31a and a second RF generator 31b. The first RF generator 31a is configured to generate a source RF signal (source RF power) for plasma generation. The first RF generator 31a is coupled to at least one lower electrode and / or at least one upper electrode via at least one impedance matching circuit. In one example, when the first RF generator 31a is coupled to the upper electrode, the upper electrode may include a top plate such as a silicon top plate. In one embodiment, the source RF signal has a frequency in the range of 10 MHz to 150 MHz. In one embodiment, the first RF generator 31a may also be configured to generate multiple source RF signals having different frequencies. The generated one or more source RF signals are supplied to at least one lower electrode and / or at least one upper electrode.

[0042] The second RF generating unit 31b is configured to couple with at least one lower electrode via at least one impedance matching circuit to generate a bias RF signal (bias RF power). The frequency of the bias RF signal may be the same as or different from the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency lower than that of the source RF signal. In one embodiment, the bias RF signal has a frequency in the range of 100 kHz to 60 MHz. In one embodiment, the second RF generating unit 31b may also be configured to generate a plurality of bias RF signals having different frequencies. The generated one or more bias RF signals are supplied to at least one lower electrode. In addition, in various embodiments, at least one of the source RF signal and the bias RF signal may be pulsed.

[0043] The power supply 30 may also include a DC power supply 32 coupled to the plasma processing chamber 10. The DC power supply 32 includes a first DC generator 32a and a second DC generator 32b. In one embodiment, the first DC generator 32a is connected to at least one lower electrode and generates a first DC signal. The generated first DC signal is applied to the at least one lower electrode. In one embodiment, the second DC generator 32b is connected to at least one upper electrode and generates a second DC signal. The generated second DC signal is applied to the at least one upper electrode.

[0044] In various embodiments, the first and second DC signals can also be pulsed. In this case, a sequence of voltage pulses is applied to at least one lower electrode and / or at least one upper electrode. The voltage pulses can have rectangular, trapezoidal, triangular, or a combination thereof pulse waveforms. In one embodiment, a waveform generator for generating the sequence of voltage pulses based on the DC signal is connected between the first DC generator 32a and the at least one lower electrode. Thus, the first DC generator 32a and the waveform generator constitute the voltage pulse generator. If the second DC generator 32b and the waveform generator constitute the voltage pulse generator, the voltage pulse generator is connected to the at least one upper electrode. The voltage pulses can have either positive or negative polarity. Alternatively, the sequence of voltage pulses can include one or more positive voltage pulses and one or more negative voltage pulses within a cycle. Furthermore, the first and second DC generators 32a and 32b can be provided in addition to the RF power supply 31, or the first DC generator 32a can be provided in place of the second RF generator 31b.

[0045] The exhaust system 40 can be connected to a gas outlet 10e provided at the bottom of the plasma processing chamber 10, for example. The exhaust system 40 can also include a pressure regulating valve and a vacuum pump. The pressure regulating valve is used to regulate the pressure within the plasma processing space 10s. The vacuum pump can include a turbomolecular pump, a dry pump, or a combination thereof.

[0046] Figure 3 is a flow chart of an etching method according to an exemplary embodiment. Figure 4 (a) to Figure 4 (d) are used to illustrate Figure 3 Schematic cross-sectional view of the etching method. Figure 3 The etching method MT1 shown (hereinafter referred to as "method MT1") can be performed by the plasma processing apparatus 1 of the above embodiment. The method MT1 can be applied to Figure 4 The substrate W shown in (a).

[0047] Figure 4 (a) is able to apply Figure 3 A schematic cross-sectional view of a substrate as an example of an etching method. Figure 4As shown in (a), in one embodiment, the substrate W can be a component for the manufacture of semiconductor devices. Semiconductor devices include, for example, semiconductor memory devices such as DRAM and 3D-NAND flash memories. The substrate W includes a base layer BL, a base layer UML (first layer), and a resist layer RL (second layer) having a pattern on the base layer UML. The base layer BL can be, for example, an organic film, a dielectric film, a metal film, a semiconductor film, or a stacked film thereof formed on a silicon wafer. As an example, the base layer BL can include silicon oxide, carbon-doped oxide, porous oxide, silicon nitride, silicon oxynitride, silicon, titanium nitride, titanium, tantalum nitride, tantalum, etc. The base layer UML can be a film that is etched using the resist layer RL as a mask. The base layer UML can be used as a mask for the base layer BL. The base layer UML is, for example, a spin-on-glass (SOG) film, a SiON film, a Si-containing anti-reflective film (SiARC), or an organic film.

[0048] The resist layer RL is a layer that functions as part of an etching mask for the underlying layer UML and can be a metal-containing resist film containing a metal. In one example, the metal can include at least one metal selected from Sn, Hf, and Ti. In one example, the resist layer RL contains Sn and can include tin oxide (SnO). The resist layer RL can also contain an organic substance.

[0049] Below, refer to Figure 5 (a) An example of a method for forming a resist layer RL (resist forming process) is described. First, a photoresist film containing metal is formed on an underlying layer UML that has been subjected to an adhesion treatment, etc. The photoresist film can be formed by a dry process, a wet process, or both a dry process and a wet process. After the photoresist film is formed, a heat treatment such as pre-baking is performed on the photoresist film. After the heat treatment, the photoresist film is irradiated with EUV (extreme ultraviolet light) using an exposure device and an exposure mask (reticle). Thus, as Figure 5 As shown in (a), an exposed first region RM1 and an unexposed second region RM2 are formed. The first region RM1 is an EUV exposed region corresponding to the opening provided in the exposure mask. The second region RM2 is an EUV unexposed region corresponding to the pattern provided in the exposure mask. EUV has a wavelength in the range of 10 to 20 nm, for example. EUV can have a wavelength in the range of 11 to 14 nm, and in one example has a wavelength of 13.5 nm.

[0050] Next, the second region RM2 is selectively removed by a development process. As a result, a resist layer RL having a pattern from the first region RM1 is formed on the substrate layer UML. During the development process, a portion of the first region RM1 may also be removed. In this case, the second region RM2 is removed at a first selectivity ratio relative to the first region RM1. The "selectivity ratio" in this development process is also called development contrast, which is equivalent to the ratio of the development speed of the second region RM2 to the development speed of the first region RM1. The development process can be a dry process, a wet process, or both a dry process and a wet process.

[0051] In one embodiment, in the development process, a first processing gas such as a halogen-containing gas is used. The halogen-containing gas may be a gas containing a halogen-containing inorganic acid, or a gas containing an inorganic acid such as Br, Cl, etc. An example of a gas containing a halogen-containing inorganic acid is at least one selected from HBr gas, BCl3 gas, HCl, and HF. In one embodiment, the first processing gas may be a gas containing an organic acid. The gas containing an organic acid may be, for example, a gas containing at least one selected from carboxylic acid, β-dicarbonyl compound, and alcohol. An example of a carboxylic acid may be formic acid (HCOOH), acetic acid (CH3COOH), trichloroacetic acid (CCl3COOH), monofluoroacetic acid (CFH2COOH), difluoroacetic acid (CF2HCOOH), trifluoroacetic acid (CF3COOH), chloro-difluoroacetic acid (CClF2COOH), sulfur-containing acetic acid, thioacetic acid (CH3COSH), mercaptoacetic acid (HSCH2COOH), trifluoroacetic anhydride ((CF3CO)2O), acetic anhydride ((CH3CO)2O). An example of a β-dicarbonyl compound may be acetylacetone (CH3C(O)CH2C(O)CH3), trichloroacetylacetone (CCl3C(O)CH2C(O)CH3), hexachloroacetylacetone (CCl3C(O)CH2C(O)CCl3), trifluoroacetylacetone (CF3C(O)CH2C(O)CH3), hexafluoroacetylacetone (HFAc, CF3C(O)CH2C(O)CF3). An example of an alcohol may be nonafluoro-tert-butanol ((CF3)3COH). In one embodiment, the first process gas comprises trifluoroacetic acid. In one embodiment, the first process gas comprises halogenated organic acid vapor. An example of the first process gas comprises at least one selected from trifluoroacetic anhydride, acetic anhydride, trichloroacetic acid, CFH2COOH, CF2HCOOH, chloro-difluoroacetic acid, sulfur-containing acetic acid, thioacetic acid, and thioglycolic acid. In one embodiment, the first process gas is a mixture of a carboxylic acid and a hydrogen halide or a mixture of acetic acid and formic acid.

[0052] Figure 5 (b) is a schematic cross-sectional view showing an example after development processing. Figure 5 As shown in (b), after the development process, scum (residue) S1 to S3 that are not completely removed are generated on the substrate W. The residue is the resist or by-product that is attached to the resist layer RL due to the scum S1 flying from the second region RM2. The scum S2 and S3 are respectively the portions that are not removed and remain in the second region RM2. The scum S2 and S3 can be convex portions on the surface of the resist layer RL and / or the substrate layer UML, respectively. The scum S1 to S3 can have various shapes and sizes. In addition, after the development process, at least one of the scum S1 to S3 may be generated.

[0053] like Figure 5 As shown in (b), when scum S1 to S3 is generated after the development process, the scum can be removed in the following descumming process. For example, the scum S1 to S3 on the substrate W can be removed by using the plasma generated from the second processing gas. In one example, first, the second processing gas is supplied from the gas supply unit 20 to the plasma processing space 10s. Then, a source RF signal is supplied to the upper electrode or the lower electrode. Thus, a high-frequency electric field is generated in the plasma processing space 10s, and plasma is generated from the second processing gas. At this time, a bias signal can be supplied to the lower electrode of the substrate support unit 11. Then, the scum S1 to S3 are removed by using the plasma generated from the second processing gas. In addition, the descumming process can be implemented when at least one of the scum S1 to S3 is generated.

[0054] During the slag removal process, the second process gas may include at least one selected from the group consisting of a helium-containing gas, a hydrogen-containing gas, a bromine-containing gas, and a chlorine-containing gas. In one example, the second process gas may include at least one selected from the group consisting of helium, hydrogen, hydrogen bromide, and boron trichloride. The second process gas may also include a rare gas such as Ar gas or an inert gas such as N2 gas.

[0055] (Step ST11: Providing a Substrate)

[0056] like Figure 3 As shown, first, a substrate W including a substrate layer UML and a resist layer RL having a pattern on the substrate layer UML is provided into the plasma processing chamber 10 (step ST11). In step ST11, the substrate W is provided on the substrate support portion 11. Thus, the substrate W is supported by the substrate support portion 11. Here, referring to Figure 6 An example of a forming method when forming the resist layer RL in step ST11 will be described. Figure 6 FIG. 1 is a flow chart of a method for forming a resist layer. Figure 6 As shown, first, a resist layer RL having a pattern is formed on the base layer UML (step ST11A). In step ST11A, for example, a resist layer RL having a pattern is formed by photolithography or the like (see Figure 5(a)). Next, remove the scum S1 to S3 attached to the resist layer RL and the base layer UML (see Figure 5 (b)) (process ST11B, scum removal process). When the prescribed conditions are satisfied after step ST11B (step ST11C: Yes), the following step ST12 is implemented. On the other hand, when the prescribed conditions are not satisfied after step ST11B (step ST11C: No), steps ST11A and ST11B are implemented again. The above-mentioned prescribed conditions include at least one of the pattern shape of the resist layer RL, the thickness of the resist layer RL, the number of scum, etc. In addition, after the second process, neither process ST11A nor process ST11B may be implemented.

[0057] (Step ST12: Formation of Silicon-Containing Layer)

[0058] Then, if Figure 4 As shown in (b), a silicon-containing layer SL is formed on the surface of the resist layer RL preferentially over the surface of the substrate layer UML (process ST12). In step ST12, the silicon-containing layer SL is formed using plasma generated from a third process gas supplied to the plasma processing chamber 10. In one example, first, a third process gas is supplied from the gas supply unit 20 to the plasma processing space 10s. Then, a source RF signal is supplied to the upper electrode or the lower electrode. As a result, a high-frequency electric field is generated in the plasma processing space 10s, and plasma is generated from the third process gas. Free radicals containing silicon contained in the plasma are deposited on the surface of the resist layer RL. In process ST12, the temperature of the substrate W (target temperature) can be adjusted using a temperature adjustment module of the substrate support unit 11.

[0059] The silicon-containing layer SL is preferentially formed on the surface of the resist layer RL compared to the surface of the underlayer UML, which can also be equivalent to selectively forming the silicon-containing layer SL on the surface of the resist layer RL. In step ST12, the silicon-containing layer SL can be formed only on the surface of the resist layer RL, or it can be formed on both the surface of the resist layer RL and the surface of the underlayer UML. In the latter case, the thickness of the portion provided on the surface of the resist layer RL can be significantly greater than the thickness of the portion provided on the surface of the underlayer UML.

[0060] The silicon-containing layer SL is a layer that can function as part of an etching mask for the substrate layer UML. In one embodiment, the silicon-containing layer SL is a deposit of an amorphous material containing silicon. The silicon-containing layer SL has a first portion P1 located on the top surface TF of the resist layer RL and a second portion P2 located on the side surface SF of the resist layer RL. In one embodiment, the thickness T1 of the first portion P1 is greater than the thickness T2 of the second portion P2. In one example, the thickness T1 may be greater than 1 times and less than 10 times the thickness T2. The thickness T1 is, for example, greater than 5 nm and less than 20 nm. In one example, the silicon-containing layer SL may have a first portion P1 instead of a second portion P2. In other words, the silicon-containing layer SL may have only the first portion P1.

[0061] The third process gas includes a source gas containing silicon and a diluent gas such as argon, helium, and nitrogen. In addition, the third process gas may also include a halogen-containing gas such as Cl2, H2, CH4, CH X F 4-X At least one of the hydrogen-containing gases may be added. The silicon-containing gas may be silicon tetrafluoride (SiF4), silicon tetrachloride (SiCl4), Si2Cl6, SiH4, Si2H6, or the like.

[0062] In one embodiment, the frequency of the source RF signal in step ST12 may be within a high frequency band (e.g., 10 MHz to 1 GHz) or a low frequency band (e.g., 100 Hz to 100 kHz). The RF power may be, for example, 100 W to 1.5 kW. The flow rate of the source gas included in the third process gas may be, for example, 2 sccm to 250 sccm. The pressure within the plasma processing chamber 10 may be, for example, 5 mTorr to 250 mTorr, and the temperature of the substrate W may be 0° C. to 120° C.

[0063] In one example, in step ST12, the surface of the resist layer RL is first activated, and then silane is bonded to the surface. Silicon bonds are then bonded to each other, forming a silicon-containing layer SL preferentially on the surface of the resist layer RL compared to the surface of the substrate layer UML. For a detailed description of this example, reference can be made to the information disclosed in, for example, U.S. patent application Ser. No. 17 / 658,538.

[0064] In step ST12, the silicon-containing layer SL may be formed in the plasma processing chamber 10 without generating plasma. In this case, the silicon-containing layer SL is formed by supplying a silicon-containing gas into the plasma processing chamber 10. In this case, the silicon-containing layer SL is formed by, for example, chemical vapor deposition (CVD). When forming the silicon-containing layer SL without generating plasma, at least one of the aforementioned dilution gas and the aforementioned additive gas may be supplied to the plasma processing chamber 10 in addition to the silicon-containing gas.

[0065] like Figure 7 As shown in (a), after forming the silicon-containing layer SL in step ST12, before performing the next step ST13, the silicon-containing layer SL can be exposed to a plasma PL generated from a gas containing hydrogen. Thus, the silicon-containing layer SL is surface treated. Specifically, Si-H bonds are generated on the surface of the silicon-containing layer SL. In this case, in the subsequent step ST13, metal is easily deposited on the surface of the silicon-containing layer SL. Examples of hydrogen-containing gases include hydrocarbons such as CH4 and C2H6, hydrofluorocarbons such as CH2F2 and CHF3, nitrogen-containing gases such as NH3, halogen-containing gases such as HF, HCl, HBr, and HI, and hydrogen.

[0066] like Figure 7 As shown in (b), the silicon-containing layer SL sometimes has a first deposition portion SL1 deposited on the surface of the resist layer RL and a second deposition portion SL2 deposited on the surface of the underlayer UML. In this case, Figure 8 As shown, after forming the silicon-containing layer SL by step ST12 and before performing the next step ST13, a portion of the silicon-containing layer SL may be removed. For example, a trimming etching is performed to remove the second deposition portion SL2 deposited on the surface of the substrate layer UML. Figure 8 An example of a method for forming the silicon-containing layer SL in the case of performing trim etching in step ST12 will be described. Figure 8 FIG. 1 is a flow chart of a method for forming a silicon-containing layer. Figure 8As shown, first, a silicon-containing layer SL is formed on the surface of the resist layer RL (step ST12A). Next, the second deposited portion SL2 of the silicon-containing layer SL is removed (step ST12B). In step ST12B, a portion of the first deposited portion SL1 may be removed. The trim etching is, for example, plasma etching using a fluorocarbon, fluorine, chlorine, or hydrogen bromide as an etchant. If the specified conditions are met after step ST12B (step ST12C: Yes), step ST13 described below is performed. On the other hand, if the specified conditions are not met after step ST12B (step ST12C: No), steps ST12A and ST12B are performed again. The specified conditions are at least one of the thickness and shape of the first deposited portion SL1 of the silicon-containing layer SL. Furthermore, neither step ST11B nor step ST12B may be performed after the second etching. By performing the trim etching of the silicon-containing layer SL as described above, a portion of the underlying layer UML can be reliably exposed at the end of step ST12.

[0067] (Step ST13: Formation of Metal-Containing Layer)

[0068] Then, if Figure 4 As shown in (c), a metal-containing layer ML is formed on the surface of the silicon-containing layer SL (step ST13 ). In step ST13 , the metal-containing layer ML is formed from the fourth process gas supplied into the plasma processing chamber 10 .

[0069] The metal-containing layer ML is a layer that can function as an etching mask for the substrate layer UML and contains at least a metal. The metal may contain at least one of tungsten and molybdenum. For example, the metal-containing layer ML contains W, WSi X 、Mo、MoSi X F Y (X and Y are positive numbers respectively). The metal-containing layer ML may contain at least one of F and Cl as a trace element. In one embodiment, the trace element in the metal-containing layer ML only needs to be an element with a content (mass ratio) smaller than the content (mass ratio) of the metal in the metal-containing layer ML. The thickness of the metal-containing layer ML may be uniform or uneven. The metal-containing layer ML may be a layer formed by metal silicide of a part of the silicon-containing layer SL, or it may be a new layer formed on the silicon-containing layer SL. In the former case, the boundary between the metal-containing layer ML and the silicon-containing layer SL may be clear or unclear. In the latter case, the metal-containing layer ML is a layered deposit containing metal.

[0070] The metal-containing layer ML can be provided only on the surface of the silicon-containing layer SL, or on both the surface of the silicon-containing layer SL and the surface of the substrate layer UML. In the latter case, the metal-containing layer ML can be formed preferentially on the surface of the silicon-containing layer SL compared to the surface of the substrate layer UML. In this case, the thickness of the portion provided on the surface of the silicon-containing layer SL can also be significantly greater than the thickness of the portion provided on the surface of the substrate layer UML. Forming the metal-containing layer ML preferentially on the surface of the silicon-containing layer SL compared to the surface of the substrate layer UML can also be equivalent to selectively forming the metal-containing layer ML on the surface of the silicon-containing layer SL.

[0071] The fourth process gas includes a source gas containing a metal and a diluent gas such as argon, helium, or nitrogen. The source gas may also contain fluorine. For example, the source gas may include at least one of tungsten hexafluoride (WF6) gas, tungsten hexachloride (WCl6) gas, and molybdenum pentafluoride (MoF5) gas. In this case, the metal compound contained in the source gas may also include at least one of tungsten hexafluoride (WF6), tungsten hexachloride (WCl6), and molybdenum pentafluoride (MoF5). When plasma is used in step ST13, the fourth process gas may include H2 or the like.

[0072] In one example of step ST13, a metal-containing layer ML is formed by chemical vapor deposition (CVD) without generating plasma. First, a fourth process gas is supplied from the gas supply unit 20 into the plasma processing space 10s. At this time, the substrate W is heated to above 60°C by the temperature adjustment module of the substrate support unit 11. As a result, the silicon located on the surface of the silicon-containing layer SL undergoes a thermochemical reaction with the metal contained in the fourth process gas. As a result, the silicon and the metal are combined to form a silicide. Thus, a metal-containing layer ML is formed from the silicide. In the above example, the source RF signal in step ST13 may not be input. In this case, the RF power may be 0. Similarly, the DC voltage may be 0V. The flow rate of the source gas contained in the fourth process gas is, for example, greater than 2 sccm and less than 250 sccm. The pressure in the plasma processing chamber 10 is, for example, greater than 10 mTorr and less than 250 mTorr, and the temperature of the substrate W is greater than 60°C and less than 130°C.

[0073] In another example of step ST13, the metal-containing layer ML is formed by atomic layer deposition (ALD). In this case, the metal-containing layer ML can be formed conformally or sub-conformally. For example, the ALD method is implemented by repeatedly performing a cycle including the following first to fourth steps. In the first step, a precursor gas is supplied to the substrate W. In the second step, the plasma processing chamber 10 containing the substrate W is purged. In the third step, a reactive gas is supplied to the substrate W. In the third step, plasma can be generated by the reactive gas. In the fourth step, the plasma processing chamber 10 is purged. For example, the above cycle is, for example, more than 60 cycles and less than 100 cycles. The above precursor gas can be a source gas containing a metal, or it can be the same as the above fourth process gas. The above reactive gas can contain at least an oxygen-containing gas (e.g., oxygen free radicals). The above reactive gas can contain a diluent gas. In the above another example, the source RF signal in step ST13 can also be omitted. In this case, the RF power can be 0. Similarly, the DC voltage can be 0 V. The flow rates of the precursor gas and the reactive gas are, for example, 2 sccm to 250 sccm. The pressure within the plasma processing chamber 10 is, for example, 100 mTorr to 400 mTorr, and the temperature of the substrate W is 60°C to 130°C.

[0074] In another example of step ST13, the metal-containing layer ML is formed by plasma CVD. First, a fourth process gas is supplied from the gas supply unit 20 into the plasma processing space 10s. Next, a source RF signal is supplied to the upper electrode or the lower electrode. This generates a high-frequency electric field within the plasma processing space 10s, generating plasma from the fourth process gas. Radicals containing the metal contained in the plasma are then deposited on the surface of the silicon-containing layer SL. The flow rate of the source gas contained in the fourth process gas is, for example, not less than 2 sccm and not more than 250 sccm.

[0075] like Figure 9 As shown in (a), after forming the metal-containing layer ML in step ST13, before performing step ST15 described later, the metal-containing layer ML can be exposed to plasma PL generated from a gas containing hydrogen. This allows the surface of the metal-containing layer ML to be treated. In one example, the surface of the metal-containing layer ML is subjected to a reduction treatment. This also allows halogens on the surface of the metal-containing layer ML to be removed.

[0076] like Figure 9As shown in (b), the metal-containing layer ML sometimes has a first deposition portion ML1 deposited on the surface of the silicon-containing layer SL and a second deposition portion ML2 deposited on the surface of the base layer UML. In particular, in the above-mentioned other example and the above-mentioned still another example, there is a tendency to form the second deposition portion SL2. In this case, as Figure 10 As shown, after forming the metal-containing layer ML in step ST13, a portion of the metal-containing layer ML may be removed before performing step ST15 described later. For example, a trim etching process is performed to remove the second deposition portion ML2 deposited on the surface of the base layer UML. Figure 10 An example of a method for forming the metal-containing layer ML in the case of performing trim etching in step ST13 will be described. Figure 10 Flowchart of the method for forming a metal-containing layer. Figure 10 As shown, first, a metal-containing layer ML is formed on the surface of the silicon-containing layer SL (step ST13A). Next, the second deposited portion SL2 of the metal-containing layer ML is removed (step ST13B). A portion of the first deposited portion ML1 may also be removed. Trim etching is plasma etching using, for example, fluorocarbons, fluorine, chlorine, or hydrogen bromide as an etchant. If the specified conditions are met after step ST13B (step ST13C: Yes), step ST15, described later, is performed. On the other hand, if the specified conditions are not met after step ST13B (step ST13C: No), steps ST13A and ST13B are performed again. The specified conditions are at least one of the thickness and shape of the first deposited portion ML1 of the metal-containing layer ML. Furthermore, neither step ST13A nor step ST13B may be performed after the second etching. By performing trim etching on the metal-containing layer ML as described above, a portion of the underlying layer UML can be reliably exposed at the end of step ST13.

[0077] If the specified conditions are met after step ST13 (step ST14: Yes), step ST15 described below is performed. On the other hand, if the specified conditions are not met after step ST14 (step ST14: No), steps ST12 and ST13 are performed again. This allows for good etching of the underlayer UML in step ST15, described below. The specified conditions are at least one of the thickness, shape, and other factors of the structure comprising the resist layer RL, the silicon-containing layer SL, and the metal-containing layer ML.

[0078] (Step ST15: Etching of Underlying Layer UML)

[0079] Then, if Figure 4As shown in (d), the resist layer RL, the silicon-containing layer SL and the metal-containing layer ML are used as masks to etch the substrate layer UML (process ST15). In step ST15, plasma is generated from the fifth processing gas supplied to the plasma processing chamber 10. Then, the portion of the substrate layer UML exposed from the resist layer RL, the silicon-containing layer SL and the metal-containing layer ML is exposed to plasma. Thus, a substrate layer UML with a pattern is formed, exposing a portion of the substrate BL. After step ST15, the portion of the substrate BL exposed from the substrate layer UML can be etched in the plasma processing chamber 10, or can be etched in an etching device different from the plasma processing device 1. In process ST15, not only the substrate layer UML but also the metal-containing layer ML can be etched. In process ST15, the temperature of the substrate W (target temperature) can be adjusted by the temperature adjustment module of the substrate support part 11.

[0080] When the substrate layer UML is a spin-on-glass (SOG) film, a SiON film, a Si-containing anti-reflective coating (SiARC) film, etc., the fifth process gas includes, for example, a fluorine-based etchant, a chlorine-based etchant, etc. When the substrate layer UML is an organic film, the fifth process gas includes, for example, a fluorocarbon gas, hydrogen bromide gas, oxygen gas, carbon dioxide gas, carbon monoxide gas, etc. Etching using plasma generated from the fifth process gas (plasma etching) can also be anisotropic etching.

[0081] In step ST12, the control unit 2 controls at least one of the temperature control module, gas supply unit 20, and plasma generation unit 12 of the substrate support unit 11 to preferentially form the silicon-containing layer SL on the surface of the resist layer RL over the surface of the underlayer UML. In step ST13, the control unit 2 controls the temperature control module and gas supply unit 20 of the substrate support unit 11 to form the metal-containing layer ML on the surface of the silicon-containing layer SL. In step ST15, the control unit 2 controls at least one of the temperature control module, gas supply unit 20, and plasma generation unit 12 of the substrate support unit 11 to etch the exposed underlayer UML using the resist layer RL, silicon-containing layer SL, and metal-containing layer ML as masks.

[0082] According to the above-described method MT1, the etching selectivity can be improved. More specifically, the etching selectivity of the substrate layer UML relative to the mask including the resist layer RL, the silicon-containing layer SL, and the metal-containing layer ML can be improved. For example, when the outermost surface of the mask is the metal-containing layer ML, the etching resistance of the mask to the fifth process gas can be improved compared to when the outermost surface of the mask is the silicon-containing layer SL.

[0083] In one embodiment, the metal-containing layer ML can be formed by chemical vapor deposition (CVD) without generating plasma. In this case, the metal-containing layer ML can be selectively formed on the silicon-containing layer SL. Therefore, the step of removing unnecessary metal-containing layer ML can be omitted. Furthermore, in one embodiment, by controlling the substrate temperature to above 60°C in step ST13, the thermochemical reaction can be facilitated.

[0084] In one embodiment, the metal-containing layer ML can be formed by atomic layer deposition (ALD) without generating plasma. In this case, the thickness of the metal-containing layer ML can be controlled on an atomic layer basis. Therefore, the pattern of the underlayer UML can be formed with high precision. Furthermore, in one embodiment, the metal-containing layer ML can be easily formed by controlling the substrate temperature to above 60°C in step ST13.

[0085] In one embodiment, before step ST11, a resist layer RL is formed on the underlayer UML. If at least one of scum S1 to S3 is present on the substrate W after the resist layer RL is formed, the scum S1 to S3 on the substrate W can be removed. In this case, the occurrence of process defects caused by the scum can be suppressed.

[0086] In one embodiment, the silicon-containing layer SL may be exposed to plasma PL generated from a gas containing hydrogen after step ST12 and before step ST13. In this case, the metal-containing layer ML is easily formed on the surface of the silicon-containing layer SL.

[0087] In one embodiment, a portion of the silicon-containing layer SL may be removed after step ST12 and before step ST13. In this case, the portion of the base layer UML not covered by the resist layer RL can be reliably exposed before step ST13.

[0088] In one embodiment, the metal-containing layer ML may be exposed to plasma PL generated from a gas containing hydrogen after step ST13 and before step ST15 . In this case, the etching resistance of the metal-containing layer ML can be improved.

[0089] In one embodiment, a portion of the metal-containing layer ML may be removed after step ST13 and before step ST15. In this case, the portion of the underlayer UML not covered by the resist layer RL and the silicon-containing layer SL can be reliably exposed before step S14.

[0090] Below, refer to Figures 11 to 13The etching method of a modified example of the above-described embodiment will be described. In the description of each modified example, overlapping descriptions with the above-described embodiment will be omitted, and only the differences from the above-described embodiment will be described. That is, the description of the above-described embodiment may be appropriately incorporated into each modified example to the extent technically possible.

[0091] (First Modification)

[0092] In the first modification, a further film formation is performed between step ST13 and step ST15, which is different from the above-described embodiment. Figure 11 As shown in (a), after step ST13 and before step ST15, a deposition layer DL is formed on the surface of the metal-containing layer ML. The deposition layer DL is, for example, a deposit of an amorphous material containing silicon, similarly to the silicon-containing layer SL. In one example, similarly to step ST12, the deposition layer DL is formed using plasma generated by a third processing gas supplied into the plasma processing chamber 10. In this case, the silicon-containing layer SL may be formed on the surface of the metal-containing layer ML in preference to the surface of the substrate layer UML. The deposition layer DL may be formed only on the surface of the metal-containing layer ML, or may be formed on both the surface of the metal-containing layer ML and the surface of the substrate layer UML. In the latter case, a portion of the deposition layer DL may be removed until the substrate layer UML is exposed. In other words, in the latter case, trim etching may also be performed.

[0093] After the deposition layer DL is formed, step ST15 is performed. Figure 11 As shown in (b), the resist layer RL, the silicon-containing layer SL, the metal-containing layer ML, and the deposited layer DL are used as masks to etch the base layer UML. At this time, the deposited layer DL is also etched. Alternatively, the entire deposited layer DL may be etched.

[0094] The first modified example described above also achieves the same effects as those of the embodiment described above. In addition, in step ST15 , the mask function can be reliably exerted, so etching defects are less likely to occur.

[0095] In the first modified example, a metal-containing layer may be formed on the surface of the deposited layer DL after the deposited layer DL is formed and before step ST15. In one example, the metal-containing layer is formed using the same method as step ST13. After the metal-containing layer is formed and before step ST15, a further deposited layer may be formed. In one example, a cycle of steps ST12 and ST13 may be repeated before step ST15. The number of such cycles may be, for example, 60 or more and 100 or less.

[0096] (Second Modification)

[0097] In the second modification, in step ST15, a process other than etching of the base layer UML is performed, which is different from the above-described embodiment. Figure 12 As shown in (a), before the etching of the base layer UML is completed in step ST15, the metal-containing layer ML is sometimes almost completely removed. Figure 12 As shown in (b), the step ST15 is interrupted and a deposition layer DL is formed on the surface of the metal-containing layer ML. In one example, the deposition layer DL is formed by the same method as the first modification. After the deposition layer DL is formed, the step ST15 is started again. Figure 12 As shown in (c), the substrate layer UML can also be etched.

[0098] The second modified example described above also achieves the same effects as those of the embodiment described above, and can suppress the occurrence of pattern formation defects after step ST15.

[0099] The second and first variations can also be combined. In this case, the deposition layer DL and the metal-containing layer ML can be formed after step ST15 is interrupted. In other words, after step ST15 is interrupted, a cycle of steps ST12 and ST13 can be performed. In this case, the above cycle can be repeated multiple times.

[0100] (Third Modification)

[0101] In the third modification, the sputtering method is used in step ST13, which is different from the above-described embodiment. In the third modification, after step ST12, the surface of the Si top plate TP included in the upper electrode is cleaned (see Figure 13 (a)). In one example, the surface of the Si top plate TP is cleaned by performing ion sputtering. In another example, the surface of the Si top plate TP is cleaned by introducing a reducing gas such as hydrogen fluoride into the plasma processing space 10s. Thus, an oxide film (not shown) that can be provided on the surface of the Si top plate TP is removed, and the surface is cleaned. In the above cleaning, a signal can be input to the first RF generating unit 31a, and a voltage can be applied to the second DC generating unit 32b. In addition, the cleaning of the surface of the Si top plate TP can also be performed instead of step ST12, and can also be used for the formation of the silicon-containing layer in step ST12.

[0102] Then, if Figure 13As shown in (a), a metal layer MAL is formed on the Si top plate TP. In one example, a source gas containing a metal is introduced into the plasma processing space 10s. Thus, through a thermochemical reaction, a metal layer MAL, an atomic layer of the metal, is formed on the surface of the Si top plate TP. At this time, no signal is input to the first RF generator 31a, and no voltage is applied to the second DC generator 32b.

[0103] Then, if Figure 13 As shown in (b), a metal-containing layer ML is formed on the substrate W by ion sputtering the metal layer MAL. In one example, by inputting a signal to the first RF generating unit 31a or applying a voltage to the second DC generating unit 32b, ions are caused to collide with the metal layer MAL in the plasma processing space 10s. As a result, a metal-containing layer ML is formed on the surface of the silicon-containing layer SL included in the substrate W. In the third variant, the cycle of the process of forming the metal layer MAL and the process of forming the metal-containing layer ML can also be repeatedly performed. In this way, the thickness of the metal-containing layer ML can be adjusted. The above-mentioned cycle is, for example, more than 60 cycles and less than 100 cycles. In addition, when the metal-containing layer ML is also formed on the surface of the substrate layer UML, the above-mentioned trimming etching can be performed. After the above process, process S14 is performed.

[0104] The third modification described above also achieves the same effects as the aforementioned exemplary embodiment. Furthermore, the metal content of the metal-containing layer ML can be increased, thereby improving the etching resistance of the metal-containing layer ML. Furthermore, the thickness of the metal-containing layer ML can be precisely adjusted.

[0105] While various exemplary embodiments have been described above, the present invention is not limited to these exemplary embodiments. Various additions, omissions, substitutions, and modifications may be made. Furthermore, elements from different exemplary embodiments may be combined to form other exemplary embodiments. For example, method MT may be performed using a plasma processing apparatus different from plasma processing apparatus 1.

[0106] Here, various exemplary embodiments included in the present invention are described in the following [E1] to [E14].

[0107] [E1]

[0108] An etching method comprising:

[0109] (a) providing a substrate, wherein the substrate comprises a first layer and a second layer having a pattern on the first layer;

[0110] (b) forming a silicon-containing layer on the surface of the second layer preferentially over the surface of the first layer;

[0111] (c) forming a metal-containing layer on the surface of the silicon-containing layer; and

[0112] (d) A step of etching the exposed first layer using the second layer, the silicon-containing layer, and the metal-containing layer as masks.

[0113] [E2]

[0114] The etching method according to [E1], wherein in (c), the metal-containing layer is formed without generating plasma.

[0115] [E3]

[0116] The etching method according to [E2], wherein in (c), the metal-containing layer is formed by chemical vapor deposition or atomic layer deposition.

[0117] [E4]

[0118] The etching method according to any one of [E1] to [E3], wherein in (c), the temperature of the substrate is 60° C. or higher.

[0119] [E5]

[0120] The etching method according to any one of [E1] to [E4], comprising, before the step (a), a second layer forming step of forming the second layer on the first layer.

[0121] In the second layer forming step, after the second layer is formed, scum on the substrate is removed.

[0122] [E6]

[0123] The etching method according to any one of [E1] to [E5], wherein in (b), the silicon-containing layer is formed without generating plasma.

[0124] [E7]

[0125] The etching method according to any one of [E1] to [E6], further comprising, after (b) and before (c), exposing the silicon-containing layer to plasma generated from a gas containing hydrogen.

[0126] [E8]

[0127] The etching method according to any one of [E1] to [E7], further comprising, after (b) and before (c), a step of removing a portion of the silicon-containing layer.

[0128] [E9]

[0129] The etching method according to any one of [E1] to [E8], further comprising, after (c) and before (d), exposing the metal-containing layer to plasma generated from a gas containing hydrogen.

[0130] [E10]

[0131] The etching method according to any one of [E1] to [E9], further comprising, after (c) and before (d), a step of removing a portion of the metal-containing layer.

[0132] [E11]

[0133] The etching method according to any one of [E1] to [E10], further comprising, after (c) and before (d), forming a deposition layer on the surface of the metal-containing layer.

[0134] [E12]

[0135] The etching method according to any one of [E1] to [E11], wherein the silicon-containing layer has a first portion located on a top surface of the second layer and a second portion located on a side surface of the second layer,

[0136] The thickness of the first portion is greater than the thickness of the second portion.

[0137] [E13]

[0138] The etching method according to any one of [E1] to [E12], wherein the metal-containing layer comprises W, WSi X 、Mo、MoSi X F Y At least one of them, X and Y are positive numbers.

[0139] [E14]

[0140] A plasma processing apparatus comprising:

[0141] chamber;

[0142] a substrate supporting portion, which is disposed in the chamber and has a temperature regulating module;

[0143] a gas supply unit configured to supply a processing gas into the chamber;

[0144] a plasma generating unit configured to generate plasma from the processing gas in the chamber; and

[0145] Control Department,

[0146] The control unit is configured to control the temperature regulating module, the gas supply unit, and the plasma generating unit so that when a substrate comprising a first layer and a second layer having a pattern on the first layer is supported by the substrate supporting unit, a silicon-containing layer is formed on the surface of the second layer preferentially over the surface of the first layer, and a metal-containing layer is formed on the surface of the silicon-containing layer; and the exposed first layer is etched using the second layer, the silicon-containing layer, and the metal-containing layer as masks.

[0147] Based on the above description, it should be understood that the various embodiments of the present invention are described in this specification for illustrative purposes and that various modifications can be made without departing from the scope and spirit of the present invention. Therefore, the various embodiments disclosed in this specification are not intended to be limiting.

[0148] Description of Reference Numerals

[0149] 1…plasma processing apparatus, 2…control unit, 10…plasma processing chamber, 11…substrate support unit, 12…plasma generation unit, 20…gas supply unit, DL…deposition layer, ML…metal-containing layer, P1…first portion, P2…second portion, RL…resist layer, SF…side surface, SL…silicon-containing layer, TF…top surface, UML…underlying layer.

Claims

1. An etching method, characterized in that: include: (a) providing a substrate, wherein the substrate comprises a first layer and a second layer having a pattern on the first layer; (b) forming a silicon-containing layer on the surface of the second layer preferentially over the surface of the first layer; (c) forming a metal-containing layer on the surface of the silicon-containing layer; and (d) A step of etching the exposed first layer using the second layer, the silicon-containing layer, and the metal-containing layer as masks.

2. The etching method according to claim 1, wherein: In the above (c), the metal-containing layer is formed without generating plasma.

3. The etching method according to claim 2, wherein: In the above (c), the metal-containing layer is formed by chemical vapor deposition or atomic layer deposition.

4. The etching method according to claim 3, wherein: In the above-mentioned (c), the temperature of the substrate is 60° C. or higher.

5. The etching method according to any one of claims 1 to 4, characterized in that: Before the step (a), a second layer forming step is included in which the second layer is formed on the first layer. In the second layer forming step, after the second layer is formed, scum on the substrate is removed.

6. The etching method according to any one of claims 1 to 4, characterized in that: In the above (b), the silicon-containing layer is formed without generating plasma.

7. The etching method according to any one of claims 1 to 4, characterized in that: After (b) and before (c), the method further includes exposing the silicon-containing layer to plasma generated from a gas containing hydrogen.

8. The etching method according to any one of claims 1 to 4, characterized in that: After (b) and before (c), a step of removing a portion of the silicon-containing layer is included.

9. The etching method according to any one of claims 1 to 4, wherein: After (c) and before (d), the method further includes exposing the metal-containing layer to plasma generated from a gas containing hydrogen.

10. The etching method according to any one of claims 1 to 4, characterized in that: After (c) and before (d), a step of removing a portion of the metal-containing layer is included.

11. The etching method according to any one of claims 1 to 4, wherein: After the step (c) and before the step (d), a process of forming a deposition layer on the surface of the metal-containing layer is included.

12. The etching method according to any one of claims 1 to 4, characterized in that: The silicon-containing layer has a first portion located on a top surface of the second layer and a second portion located on a side surface of the second layer, The thickness of the first portion is greater than the thickness of the second portion.

13. The etching method according to any one of claims 1 to 4, characterized in that: The metal-containing layer comprises W, WSi X 、Mo、MoSi X F Y At least one of X and Y are positive numbers.

14. A plasma processing device, characterized in that: include: chamber; a substrate supporting portion, which is disposed in the chamber and has a temperature regulating module; a gas supply unit configured to supply a processing gas into the chamber; a plasma generating unit configured to generate plasma from the processing gas in the chamber; and Control Department, The control unit is configured to control the temperature regulating module, the gas supply unit, and the plasma generating unit so that when a substrate comprising a first layer and a second layer having a pattern on the first layer is supported by the substrate supporting unit, a silicon-containing layer is formed on the surface of the second layer preferentially over the surface of the first layer, and a metal-containing layer is formed on the surface of the silicon-containing layer; and the exposed first layer is etched using the second layer, the silicon-containing layer, and the metal-containing layer as masks.

Images