Deposition mask, method for manufacturing deposition mask, and electronic device

Abstract

A deposition mask, a method for manufacturing the deposition mask, and an electronic device are provided. The deposition mask includes: a mask substrate including a plurality of cell regions and a cell peripheral region surrounding the plurality of cell regions; a mask film overlapping the plurality of cell regions of the mask substrate; and a mask frame overlapping a cell peripheral region of the mask substrate, in which the mask film includes a mask shadow defining a pixel opening, in which the mask frame includes a first mask inorganic layer on the mask substrate and a second mask inorganic layer on the first mask inorganic layer, and in which the first mask inorganic layer and the second mask inorganic layer overlap each other. The first mask inorganic layer and the second mask inorganic layer are formed in a specific pattern up to an edge of the mask substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from and all benefits arising from Korean Patent Application No. 10-2024-0037537 filed in the Korean Intellectual Property Office on March 19, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a deposition mask and a method for manufacturing the deposition mask. Background Art

[0004] Wearable devices in the form of glasses or helmets that focus near the user's eyes are being developed. For example, the wearable device may be a head-mounted display (HMD) or AR glasses. Such wearable devices provide users with augmented reality (hereinafter referred to as "AR") or virtual reality (hereinafter referred to as "VR") images.

[0005] Wearable devices such as HMDs and AR glasses require display specifications of at least 2000 PPI (pixels per inch) to allow users to use them for a long time without feeling dizzy. To this end, organic light-emitting diode on silicon (OLEDoS) technology has emerged. It is a small, high-resolution organic light-emitting display device. OLEDoS is a technology for disposing organic light-emitting diodes (OLEDs) on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is disposed. Summary of the Invention

[0006] Aspects of the present disclosure provide a silicon deposition mask capable of manufacturing a high-resolution display panel and a method for manufacturing the silicon deposition mask.

[0007] Aspects of the present disclosure provide a deposition mask that improves adhesion between a high-resolution display panel and a deposition mask by solving a problem of warping of a mask inorganic layer included in a mask frame.

[0008] It should be noted that the objects of the present disclosure are not limited to the above objects, and other objects of the present disclosure will be apparent to those skilled in the art through the following description.

[0009] The details of one or more embodiments of the subject matter described in this specification are set forth in the accompanying drawings and the description below.

[0010] In an embodiment of the present disclosure, a deposition mask includes: a mask substrate including a plurality of unit areas and a unit peripheral area surrounding the plurality of unit areas; a mask film overlapping the plurality of unit areas of the mask substrate; and a mask frame overlapping the unit peripheral area of ​​the mask substrate, wherein the mask film includes a mask shadow defining a pixel opening, wherein the mask frame includes a first mask inorganic layer on the mask substrate and a second mask inorganic layer on the first mask inorganic layer, and wherein the first mask inorganic layer and the second mask inorganic layer are formed in a specific pattern up to an edge of the mask substrate.

[0011] In an embodiment, the first mask inorganic layer and the second mask inorganic layer may not overlap with the plurality of cell regions, and wherein the second mask inorganic layer may include the same material as that of the mask shadow.

[0012] In an embodiment, the pixel opening may be a through-hole, and wherein the second mask inorganic layer may be spaced apart from the mask shadow, with the pixel opening being located between the second mask inorganic layer and the mask shadow.

[0013] In an embodiment, the mask substrate may include silicon, and wherein the mask substrate has a circular shape when viewed from the top.

[0014] In an embodiment, the first mask inorganic layer and the second mask inorganic layer may include an inorganic insulating material, and wherein the first mask inorganic layer and the second mask inorganic layer include different materials.

[0015] In an embodiment, the first mask inorganic layer may include silicon oxide, and the second mask inorganic layer may include silicon nitride.

[0016] In an embodiment, the mask frame may include a third mask inorganic layer positioned on the mask substrate on an opposite side of the first mask inorganic layer, and a fourth mask inorganic layer positioned on the third mask inorganic layer.

[0017] In embodiments, the third mask inorganic layer may be made of the same material as that of the first mask inorganic layer, and the fourth mask inorganic layer may be made of the same material as that of the second mask inorganic layer.

[0018] In an embodiment, a height of the first mask inorganic layer may be equal to a height of the third mask inorganic layer, and a height of the second mask inorganic layer is equal to a height of the fourth mask inorganic layer.

[0019] In embodiments, the mask substrate may include a first side surface facing the cell region, wherein the first mask inorganic layer may include a second side surface facing the cell region, and wherein the first side surface and the second side surface may be positioned on the same line.

[0020] In embodiments, the second mask inorganic layer may include a third side surface facing the cell region, and the third side surface may be positioned on the same line as the first and second side surfaces.

[0021] In an embodiment, the third side surface may be spaced apart from the mask shadow, and the pixel opening is located between the third side surface and the mask shadow.

[0022] In an embodiment, the second side surface may be positioned between the first side surface and the third side surface.

[0023] In embodiments, the mask frame may define a mask opening when viewed from the top, wherein the mask film may overlap the mask opening when viewed from the top, and wherein the mask frame may completely surround the mask film when viewed from the top.

[0024] A method for manufacturing a deposition mask, the method comprising: forming a first inorganic material layer on a mask substrate including a plurality of unit areas and a unit peripheral area surrounding the plurality of unit areas; forming a second inorganic material layer on the first inorganic material layer; forming a mask film by patterning the second inorganic material layer positioned on the upper surface of the mask substrate; forming a mask opening by etching the first inorganic material layer and the second inorganic material layer positioned on the lower surface of the mask substrate; and removing a portion of the mask substrate overlapping with the mask opening and a portion of the first inorganic material layer positioned on the upper surface of the mask substrate overlapping with the mask opening.

[0025] In an embodiment, forming the first inorganic material layer may include simultaneously forming the first inorganic material layer on the upper and lower surfaces of the mask substrate.

[0026] In an embodiment, forming the second inorganic material layer may include simultaneously forming the second inorganic material layer on the upper and lower surfaces of the mask substrate.

[0027] In an embodiment, the first inorganic material layer and the second inorganic material layer may include different materials.

[0028] In embodiments, a side surface of the first inorganic material layer and a side surface of the second inorganic material layer may be positioned on the same line extending from a side surface of the patterned mask substrate.

[0029] In embodiments, the first inorganic material layer and the second inorganic material layer may be patterned up to an edge of the mask substrate.

[0030] In an embodiment of the present disclosure, an electronic device includes: a display device including a display panel formed using a deposition mask, wherein the deposition mask includes: a mask substrate including a plurality of unit areas and a unit peripheral area surrounding the plurality of unit areas; a mask film overlapping with the plurality of unit areas of the mask substrate; and a mask frame overlapping with the unit peripheral area of ​​the mask substrate, wherein the mask film includes a mask shadow defining a pixel opening, wherein the mask frame includes a first mask inorganic layer on the mask substrate and a second mask inorganic layer on the first mask inorganic layer, and wherein the first mask inorganic layer and the second mask inorganic layer are formed in a specific pattern up to an edge of the mask substrate.

[0031] According to embodiments of the present disclosure, a deposition mask for manufacturing a high-resolution display panel can be provided by forming a mask inorganic layer and a mask film on a mask substrate. Furthermore, according to embodiments of the present disclosure, the deposition mask can address the warping problem of the mask inorganic layer by patterning the mask inorganic layer to be aligned with the edge of the mask substrate, thereby enhancing the adhesion between the high-resolution display panel and the deposition mask.

[0032] It should be noted that the effects of the present disclosure are not limited to those described above, and other effects of the present disclosure will be apparent to those skilled in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings.

[0034] Figure 1 is a perspective view illustrating a head mounted electronic device according to an embodiment of the present disclosure.

[0035] Figure 2 It shows Figure 1 An exploded perspective view of an example of a head-mounted electronic device.

[0036] Figure 3 is a perspective view illustrating a head mounted electronic device according to an embodiment of the present disclosure.

[0037] Figure 4 is an exploded perspective view illustrating a display device according to an embodiment of the present disclosure.

[0038] Figure 5 is a cross-sectional view illustrating an example of a portion of a display panel according to an embodiment of the present disclosure.

[0039] Figure 6 is a plan view of a mask according to an embodiment of the present disclosure.

[0040] Figure 7 yes Figure 6An enlarged plan view of area A.

[0041] Figure 8 It is along Figure 7 A cross-sectional view taken along line X1-X1'.

[0042] Figure 9 yes Figure 8 An enlarged cross-sectional view of a mask frame and structures surrounding the mask frame.

[0043] Figure 10 is a flowchart for illustrating a method for manufacturing a mask according to an embodiment of the present disclosure.

[0044] Figures 11 to 20 2 is a cross-sectional view illustrating process steps of a method for manufacturing a mask according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. However, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout.

[0046] It will be understood that when an element is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present between the element and the other element. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0047] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, the "first element," "first component," "first region," "first layer," or "first section" discussed below may be referred to as the "second element," "second component," "second region," "second layer," or "second section" without departing from the teachings herein.

[0048] The terms used herein are only for the purpose of describing specific embodiments, rather than being intended to limit. As used herein, unless the context clearly indicates otherwise, the singular "one", "one (kind / person)" and "said (the)" are intended to include plural forms. Therefore, after the reference to "one" element in the claim, the reference to "said" element includes one element and multiple elements. For example, unless the context clearly indicates otherwise, "one element" has the same meaning as the meaning of "at least one element". "At least one (kind / person)" should not be interpreted as being limited to "one" or "one (kind / person)". "Or" means "and / or". As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. It will also be understood that when the term "include" and variations thereof are used in this specification, the description indicates the presence of stated features, regions, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components and / or their groups.

[0049] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the accompanying drawings. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the accompanying drawings. For example, if the device in a figure is turned over, then the element described as being on the "lower" side of the other elements will then be positioned on the "upper" side of the other elements. Thus, depending on the particular orientation of the drawing, the term "lower" can encompass both "lower" and "upper" orientations. Similarly, if the device in a figure is turned over, then the element described as being "below" or "beneath" other elements will then be positioned "above" the other elements. Thus, the terms "below" or "under" can encompass both "upper" and "lower" orientations.

[0050] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, a term such as "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0051] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless expressly defined as such herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense.

[0052] The embodiments are described herein with reference to cross-sectional views which are schematic diagrams of idealized embodiments. As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but should include deviations in shape due to, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. In addition, the sharp angles shown may be rounded. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the present claims.

[0053] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0054] Figure 1 is a perspective view showing the head-mounted electronic device 1 according to the embodiment. Figure 2 yes Figure 1 1 is an exploded perspective view of an example of a head mounted electronic device 1.

[0055] Reference Figure 1 and Figure 2 According to an embodiment, the head-mounted electronic device 1 includes a display device housing 110, a housing cover 120, a first eyepiece 131, a second eyepiece 132, a headband 140, a first display device 10_1, a second display device 10_2, an intermediate frame 160, a first optical member 151, a second optical member 152, a control circuit board 170 and a connector.

[0056] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Each of the first display device 10_1 and the second display device 10_2 is connected to the reference Figure 4 and Figure 5 The display devices 10 described are substantially the same. Therefore, the description of the first display device 10_1 and the second display device 10_2 will be referred to. Figure 4 and Figure 5 Description instead.

[0057] The first optical member 151 may be disposed between the first display device 10_1 and the first eyepiece 131. The second optical member 152 may be disposed between the second display device 10_2 and the second eyepiece 132. Each of the first optical member 151 and the second optical member 152 may include at least one convex lens.

[0058] The middle frame 160 may be disposed between the first display device 10_1 and the control circuit board 170 and between the second display device 10_2 and the control circuit board 170. The middle frame 160 is used to support and fix the first and second display devices 10_1 and 10_2 and the control circuit board 170.

[0059] The control circuit board 170 may be disposed between the middle frame 160 and the display device housing 110. The control circuit board 170 may be connected to the first display device 10_1 and the second display device 10_2 via a connector. The control circuit board 170 may convert an image source input from the outside into digital video data (DATA) and transmit the digital video data (DATA) to the first display device 10_1 and the second display device 10_2 via the connector.

[0060] The control circuit board 170 may transmit digital video data (DATA) associated with a left-eye image optimized for the user's left eye to the first display device 10_1, and may transmit digital video data (DATA) associated with a right-eye image optimized for the user's right eye to the second display device 10_2. Alternatively, the control circuit board 170 may transmit the same digital video data (DATA) to both the first display device 10_1 and the second display device 10_2.

[0061] The display device housing 110 houses the first display device 10_1, the second display device 10_2, the middle frame 160, the first optical member 151, the second optical member 152, the control circuit board 170, and the connector. The housing cover 120 is provided to cover the opening surface of the display device housing 110. The housing cover 120 may include a first eyepiece 131 for placing the user's left eye and a second eyepiece 132 for placing the user's right eye. Figure 1 and Figure 2 In the example shown in FIG, the first eyepiece 131 and the second eyepiece 132 are separately provided, but the embodiments of the present disclosure are not limited thereto. The first eyepiece 131 and the second eyepiece 132 may be combined into a single element.

[0062] The first eyepiece 131 may be aligned with the first display device 10_1 and the first optical member 151, and the second eyepiece 132 may be aligned with the second display device 10_2 and the second optical member 152. Thus, the user may see a virtual image of the image magnified by the first optical member 151 in the first display device 10_1 through the first eyepiece 131, and see a virtual image of the image magnified by the second optical member 152 in the second display device 10_2 through the second eyepiece 132.

[0063] The headband 140 fixes the display device housing 110 to the user's head so that the first eyepiece 131 and the second eyepiece 132 of the housing cover 120 are respectively aligned with the user's left eye and right eye. By realizing a light and small display device housing 110, the head-mounted electronic device 1 can include Figure 3 The eyeglass frame shown in FIG. 1 is used instead of the headband 140 .

[0064] In addition, the head-mounted electronic device 1 may further include a battery for supplying power, an external memory slot for inserting an external memory, an external connection port for receiving an image source, and a wireless communication module. The external connection port may be a USB (Universal Serial Bus) terminal, a display port, or an HDMI (High-Definition Multimedia Interface) terminal. The wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0065] Figure 3 1 is a perspective view showing a head mounted electronic device 1_1 according to the embodiment.

[0066] Reference Figure 3 The head-mounted electronic device 1_1 according to an embodiment may be a glasses-type display device having a light and small display device housing 120_1. The head-mounted electronic device 1_1 according to an embodiment may include a display device 10_3, a left-eye lens 311, a right-eye lens 312, a support frame 350, temples 341 and 342, an optical member 320, an optical path conversion member 330, and a display device housing 120_1.

[0067] Figure 3 The display device 10_3 shown in FIG. Figure 4 and Figure 5 The display device 10 described is substantially the same. Therefore, the description of the display device 10_3 will be referred to. Figure 4 and Figure 5 Description instead.

[0068] The display device housing 120_1 may include a display device 10_3, an optical member 320, and an optical path conversion member 330. The image displayed on the display device 10_3 may be magnified by the optical member 320, and the optical path of the image may be converted by the optical path conversion member 330 to be provided to the right eye of the user through the right-eye lens 312. As a result, the user may view an augmented reality image with his right eye, which is a combination of a virtual image displayed on the display device 10_3 and a real-world image viewed through the right-eye lens 312.

[0069] Despite Figure 3 In the example shown in , the display device housing 120_1 is disposed at the right end of the support frame 350, but embodiments of the present disclosure are not limited thereto. For example, the display device housing 120_1 may be disposed at the left end of the support frame 350. In this case, the image displayed on the display device 10_3 may be provided to the user's left eye. Alternatively, the display device housing 120_1 may be disposed at the left and right ends of the support frame 350, respectively. In this case, the user can view the image displayed on the display device 10_3 through both the left eye and the right eye.

[0070] Figure 4 is an exploded perspective view illustrating the display device 10 according to an embodiment of the present disclosure.

[0071] Reference Figure 4 The display device 10 according to the embodiment displays a moving image or a still image. The display device 10 according to the embodiment can be used by portable electronic devices such as mobile phones, smart phones, tablet PCs, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). For example, the display device 10 can be used as a display unit for a television, a laptop computer, a monitor, an electronic billboard, or an Internet of Things (IoT) device. Alternatively, the display device 10 can be applied to a smart watch, a watch phone, or a head-mounted display (HMD) device for realizing virtual reality and augmented reality.

[0072] According to an embodiment, the display device 10 includes a display panel 410 , a heat dissipation layer 420 , a circuit board 430 , a driving circuit 440 , and a power supply circuit 450 .

[0073] When viewed from the top, the display panel 410 may have a shape similar to a rectangular shape. For example, when viewed from the top, the display panel 410 may have a shape similar to a rectangle having a short side in a first direction (X-axis direction) and a long side in a second direction (Y-axis direction) intersecting the first direction (X-axis direction). In the display panel 410, each of the corners where the short side in the first direction (X-axis direction) intersects the long side in the second direction (Y-axis direction) may be a rounded corner with a predetermined curvature, or may be a right angle. When viewed from the top, the shape of the display panel 410 is not limited to a rectangular shape, but may be formed into a shape similar to other polygonal shapes, a circular shape, or an elliptical shape. When viewed from the top, the shape of the display device 10 may follow the shape of the display panel 410, but embodiments of the present disclosure are not limited thereto.

[0074] The display panel 410 includes a display area where an image is displayed and a non-display area where no image is displayed.

[0075] The display area includes a plurality of pixels, and each of the plurality of pixels includes a plurality of sub-pixels SP1, SP2, and SP3 (see FIG. Figure 5 ). The sub-pixels SP1, SP2 and SP3 include a plurality of pixel transistors PTR (see Figure 5 ). The pixel transistor is formed by a semiconductor process and can be disposed on a semiconductor substrate SSUB (see Figure 5 For example, the pixel transistors may be implemented as complementary metal oxide semiconductors (CMOS).

[0076] The heat dissipation layer 420 may overlap the display panel 410 in a third direction (Z-axis direction), which is the thickness direction of the display panel 410. The heat dissipation layer 420 may be provided on one surface of the display panel 410, for example, on the rear surface of the display panel 410. The heat dissipation layer 420 is used to release heat generated in the display panel 410. The heat dissipation layer 420 may include a layer containing graphite or a metal having high thermal conductivity, such as silver (Ag), copper (Cu), and aluminum (Al).

[0077] The circuit board 430 may be electrically connected to the plurality of pads in the pad region of the display panel 410 using a conductive adhesive member such as an anisotropic conductive film. The circuit board 430 may be a flexible printed circuit board made of a flexible material, or a flexible film. Figure 4 Although the circuit board 430 is unfolded, it can be bent. When bent, one end of the circuit board 430 can be disposed on the rear surface of the display panel 410. The one end of the circuit board 430 can be opposite to the opposite end of the circuit board 430, which is connected to the pads in the pad area of ​​the display panel 410 using a conductive adhesive member.

[0078] The driving circuit 440 may receive digital video data and a timing signal from the outside and may generate a scan timing control signal, an emission timing control signal, and a data timing control signal for controlling the display panel 410 in response to the timing signal.

[0079] The power supply circuit 450 may generate a plurality of panel driving voltages in response to a supply voltage from the outside.

[0080] Each of the driving circuit 440 and the power supply circuit 450 may be implemented as an integrated circuit (IC) and attached to a surface of the circuit board 430 .

[0081] Figure 5 is a cross-sectional view showing an example of a portion of the display panel 410 according to an embodiment of the present disclosure. For example, Figure 5 A cross-sectional structure of a portion of a display area including a plurality of sub-pixels SP1 , SP2 , and SP3 is shown.

[0082] Reference Figure 5 The display panel 410 includes a semiconductor backplane SBP, an emission material backplane EBP, an emission material layer EML, an encapsulation layer TFE, an optical layer OPL and a cover layer CVL.

[0083] The semiconductor backplane SBP includes a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating films covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR, respectively.

[0084] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB may be a substrate doped with first-type impurities. A plurality of well regions WA may be positioned in the upper surface of the semiconductor substrate SSUB. The well regions WA may be doped with second-type impurities. The second-type impurities may be different from the first-type impurities. For example, when the first-type impurities are p-type impurities, the second-type impurities may be n-type impurities. Alternatively, when the first-type impurities are n-type impurities, the second-type impurities may be p-type impurities.

[0085] The semiconductor substrate SSUB can be replaced with a glass substrate or a polymer resin substrate such as polyimide. In this case, the thin film transistor (e.g., pixel transistor PTR) can be provided in the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that cannot be bent, while the polymer resin substrate can be a flexible substrate that can be bent or curved.

[0086] Each of the well regions WA includes a source region SA associated with a source electrode of the pixel transistor PTR, a drain region DA associated with a drain electrode of the pixel transistor PTR, and a channel region CH between the source region SA and the drain region DA.

[0087] Each of the source region SA and the drain region DA may be doped with first type impurities. The gate electrode GE of the pixel transistor PTR may overlap with the well region WA in the third direction (Z-axis direction). The channel region CH may overlap with the gate electrode GE in the third direction (Z-axis direction). The source region SA may be positioned on one side of the gate electrode GE, and the drain region DA may be positioned on the opposite side of the gate electrode GE.

[0088] The first semiconductor insulating film SINS1 may be provided on the semiconductor substrate SSUB. The first semiconductor insulating film SINS1 may be made of silicon carbonitride (SiCN) or silicon oxide (SiO x )-based inorganic film formation, but not limited to this.

[0089] The second semiconductor insulating film SINS2 may be provided on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 may be made of silicon oxide (SiO x )-based inorganic film is formed, but the embodiments of the present disclosure are not limited thereto.

[0090] A plurality of contact terminals CTE may be provided on the second semiconductor insulating film SINS2. Each of the plurality of contact terminals CTE may be connected to one of the gate electrode GE, the source area SA, and the drain area DA of each of the plurality of pixel transistors PTR via a hole penetrating the first semiconductor insulating film SINS1 and the second semiconductor insulating film SINS2. The contact terminal CTE may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of these.

[0091] The third semiconductor insulating film SINS3 may be provided on the side surface of each of the plurality of contact terminals CTE. The upper surface of each of the plurality of contact terminals CTE may not be covered by the third semiconductor insulating film SINS3 but may be exposed. The third semiconductor insulating film SINS3 may be made of silicon oxide (SiO x )-based inorganic film is formed, but the embodiments of the present disclosure are not limited thereto.

[0092] The emitter material base plate (EBP) includes first to eighth metal layers ML1 to ML8, reflective electrode layers RL1 to RL4, multiple vias VA1 to VA10, and a step layer STPL. Furthermore, the emitter material base plate (EBP) includes multiple interlayer insulating films INS1 to INS8, as well as interlayer insulating films INS9 and INS10, disposed between the first to eighth metal layers ML1 to ML8.

[0093] The first to eighth metal layers ML1 to ML8 are used to realize the circuit of the sub-pixel SP by connecting a plurality of contact terminals CTE exposed from the semiconductor base plate SBP.

[0094] A first interlayer insulating film INS1 may be provided on the semiconductor substrate SBP. Each of a plurality of first via holes VA1 may penetrate the first interlayer insulating film INS1 and may be connected to the contact terminal CTE exposed from the semiconductor substrate SBP. Each of a plurality of first metal layers ML1 may be provided on the first interlayer insulating film INS1 and may be connected to the first via holes VA1.

[0095] The second interlayer insulating film INS2 may be disposed on the first interlayer insulating film INS1 and the first metal layer ML1. Each of the plurality of second via holes VA2 may pass through the second interlayer insulating film INS2 to be connected to the exposed first metal layer ML1. Each of the plurality of second metal layers ML2 may be disposed on the second interlayer insulating film INS2 and may be connected to the second via holes VA2.

[0096] A third interlayer insulating film INS3 may be provided on the second interlayer insulating film INS2 and the second metal layer ML2. Each of a plurality of third via holes VA3 may pass through the third interlayer insulating film INS3 to be connected to the exposed second metal layer ML2. Each of a plurality of third metal layers ML3 may be provided on the third interlayer insulating film INS3 and may be connected to the third via hole VA3.

[0097] A fourth interlayer insulating film INS4 may be disposed on the third interlayer insulating film INS3 and the third metal layer ML3. Each of a plurality of fourth via holes VA4 may pass through the fourth interlayer insulating film INS4 to be connected to the exposed third metal layer ML3. Each of a plurality of fourth metal layers ML4 may be disposed on the fourth interlayer insulating film INS4 and may be connected to the fourth via hole VA4.

[0098] A fifth interlayer insulating film INS5 may be disposed on the fourth interlayer insulating film INS4 and the fourth metal layer ML4. Each of a plurality of fifth via holes VA5 may pass through the fifth interlayer insulating film INS5 to be connected to the exposed fourth metal layer ML4. Each of a plurality of fifth metal layers ML5 may be disposed on the fifth interlayer insulating film INS5 and may be connected to the fifth via hole VA5.

[0099] A sixth interlayer insulating film INS6 may be provided on the fifth interlayer insulating film INS5 and the fifth metal layer ML5. Each of a plurality of sixth via holes VA6 may pass through the sixth interlayer insulating film INS6 to be connected to the exposed fifth metal layer ML5. Each of a plurality of sixth metal layers ML6 may be provided on the sixth interlayer insulating film INS6 and may be connected to the sixth via hole VA6.

[0100] The seventh interlayer insulating film INS7 may be disposed on the sixth interlayer insulating film INS6 and the sixth metal layer ML6. Each of the plurality of seventh via holes VA7 may pass through the seventh interlayer insulating film INS7 to be connected to the exposed sixth metal layer ML6. Each of the plurality of seventh metal layers ML7 may be disposed on the seventh interlayer insulating film INS7 and may be connected to the seventh via hole VA7.

[0101] An eighth interlayer insulating film INS8 may be disposed on the seventh interlayer insulating film INS7 and the seventh metal layer ML7. Each of a plurality of eighth via holes VA8 may pass through the eighth interlayer insulating film INS8 to be connected to the exposed seventh metal layer ML7. Each of a plurality of eighth metal layers ML8 may be disposed on the eighth interlayer insulating film INS8 and may be connected to the eighth via hole VA8.

[0102] The first to eighth metal layers ML1 to ML8 and the first to eighth vias VA1 to VA8 may be made of substantially the same material. The first to eighth metal layers ML1 to ML8 and the first to eighth vias VA1 to VA8 may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of these. The first to eighth interlayer insulating films INS1 to INS8 may be made of substantially the same material. The first to eighth interlayer insulating films INS1 to INS8 may be made of silicon oxide (SiO x )-based inorganic film is formed, but the embodiments of this specification are not limited thereto.

[0103] The thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 can be greater than the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. The thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 can be greater than the thickness of the first metal layer ML1. The thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 can be substantially equal.

[0104] The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be greater than the thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6. The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be greater than the thickness of the seventh via VA7 and the thickness of the eighth via VA8. The thickness of the seventh via VA7 and the thickness of the eighth via VA8 may be greater than the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. The thickness of the seventh metal layer ML7 may be substantially equal to the thickness of the eighth metal layer ML8.

[0105] The ninth interlayer insulating film INS9 may be provided on the eighth interlayer insulating film INS8 and the eighth metal layer ML8. The ninth interlayer insulating film INS9 may be made of silicon oxide (SiO x )-based inorganic film is formed, but the embodiments of the present disclosure are not limited thereto.

[0106] Each of the ninth via holes VA9 may pass through the ninth interlayer insulating film INS9 to be connected to the exposed eighth metal layer ML8. The ninth via hole VA9 may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of these.

[0107] The first reflective electrode RL1 may be disposed on the ninth interlayer insulating film INS9 and may be connected to the ninth via hole VA9. The first reflective electrode RL1 may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of these.

[0108] The second reflective electrode RL2 may be disposed on the first reflective electrode RL1. The second reflective electrode RL2 may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of these. Alternatively, the second reflective electrode RL2 may be titanium nitride (TiN).

[0109] In the first sub-pixel SP1, the step layer STPL may be provided on the second reflective electrode RL2. The step layer STPL may not be provided in each of the second sub-pixel SP2 and the third sub-pixel SP3. The thickness of the step layer STPL may be determined based on the wavelength of the light of the first color and the distance from the first emission layer EML1 to the fourth reflective electrode RL4, so that the light of the first color emitted from the first emission layer EML1 is favorably reflected. The step layer STPL may be made of silicon carbon nitride (SiCN) or silicon oxide (SiO x )-based inorganic film formation, but not limited to this.

[0110] In the first subpixel SP1, the third reflective electrode RL3 may be disposed on the second reflective electrode RL2 and the stepped layer STPL. In the second and third subpixels SP2 and SP3, the third reflective electrode RL3 may be disposed on the second reflective electrode RL2. The third reflective electrode RL3 may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of these.

[0111] At least one of the first reflective electrode RL1 , the second reflective electrode RL2 , and the third reflective electrode RL3 may be removed.

[0112] The fourth reflective electrode RL4 may be disposed on the third reflective electrode RL3. The fourth reflective electrode RL4 may reflect light from the first emission layer EML1, the second emission layer EML2, and the third emission layer EML3. The fourth reflective electrode RL4 may include a metal having a high reflectivity to facilitate light reflection. The fourth reflective electrode RL4 may be composed of, but is not limited to, aluminum (Al), a stack of aluminum and titanium (Ti / Al / Ti), a stack of aluminum and ITO (ITO / Al / ITO), silver (Ag), palladium (Pd), an APC alloy (which is an alloy of copper (Cu)), and a stack of an APC alloy and ITO (ITO / APC / ITO).

[0113] The tenth interlayer insulating film INS10 may be provided on the ninth interlayer insulating film INS9 and the fourth reflective electrode RL4. The tenth interlayer insulating film INS10 may be made of silicon oxide (SiO x )-based inorganic film is formed, but the embodiments of the present disclosure are not limited thereto.

[0114] Each of the tenth via holes VA10 may pass through the tenth interlayer insulating film INS10 to be connected to the exposed fourth reflective electrode RL4. The tenth via hole VA10 may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of these. Due to the stepped layer STPL, the thickness of the tenth via hole VA10 in the first sub-pixel SP1 may be smaller than the thickness of the tenth via hole VA10 in each of the second sub-pixel SP2 and the third sub-pixel SP3.

[0115] The emission material layer EML may be disposed on the emission material backplane EBP. The emission material layer EML may include light emitting elements LE and a pixel defining layer PDL, each of the light emitting elements LE including a first electrode AND, an intermediate layer IL, and a second electrode CAT.

[0116] The first electrode AND may be disposed on the tenth interlayer insulating film INS10 and may be connected to the tenth via VA10. The first electrode AND may be connected to the drain area DA or the source area SA of the pixel transistor PTR through the tenth via VA10, the first to fourth reflective electrodes RL1 to RL4, the first to ninth vias VA1 to VA9, the first to eighth metal layers ML1 to ML8, and the contact terminal CTE. The first electrode AND may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of these. Alternatively, the first electrode AND may be titanium nitride (TiN).

[0117] The pixel defining layer PDL may be partially disposed on the first electrode AND. The pixel defining layer PDL may be disposed on an edge of the first electrode AND. The pixel defining layer PDL is used to separate the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0118] The first emission area EA1 may be defined as an area where the first electrode AND, the intermediate layer IL, and the second electrode CAT in the first sub-pixel SP1 are sequentially stacked to emit light. The second emission area EA2 may be defined as an area where the first electrode AND, the intermediate layer IL, and the second electrode CAT in the second sub-pixel SP2 are sequentially stacked to emit light. The third emission area EA3 may be defined as an area where the first electrode AND, the intermediate layer IL, and the second electrode CAT in the third sub-pixel SP3 are sequentially stacked to emit light.

[0119] The pixel defining layer PDL may include a first pixel defining layer PDL1, a second pixel defining layer PDL2, and a third pixel defining layer PDL3. The first pixel defining layer PDL1 may be disposed on an edge of the first electrode AND, the second pixel defining layer PDL2 may be disposed on the first pixel defining layer PDL1, and the third pixel defining layer PDL3 may be disposed on the second pixel defining layer PDL2. The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may be made of silicon oxide (SiO x )-based inorganic film is formed, but the embodiments of the present disclosure are not limited thereto.

[0120] The intermediate layer IL may include a first intermediate layer IL1 , a second intermediate layer IL2 , and a third intermediate layer IL3 .

[0121] The intermediate layer IL may have a series structure including a plurality of intermediate layers IL1, IL2, and IL3 that emit light of different colors. For example, the intermediate layer IL may include a first intermediate layer IL1 that emits light of a first color, a second intermediate layer IL2 that emits light of a third color, and a third intermediate layer IL3 that emits light of a second color. The first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 may be sequentially stacked on top of each other.

[0122] The first intermediate layer IL1 may have a structure in which a first hole transport layer, a first organic emission layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The second intermediate layer IL2 may have a structure in which a second hole transport layer, a second organic emission layer emitting light of a third color, and a second electron transport layer are sequentially stacked. The third intermediate layer IL3 may have a structure in which a third hole transport layer, a third organic emission layer emitting light of a second color, and a third electron transport layer are sequentially stacked.

[0123] In the first direction ( Figure 4 A plurality of intermediate layers IL arranged adjacent to each other in the X-axis direction (in the X-axis direction) may be disconnected by the pixel defining layer PDL. In the display panel 410 according to the embodiment, by disconnecting the intermediate layer IL of the adjacent sub-pixels SP1, SP2 and SP3, leakage current between the adjacent sub-pixels SP1, SP2 and SP3 can be prevented, and color crosstalk can be prevented. Color crosstalk refers to a phenomenon in which, for example, a red sub-pixel adjacent to a blue sub-pixel is unintentionally turned on when the blue sub-pixel emits blue light. Since color crosstalk occurs due to leakage current, color crosstalk may occur if a blue sub-pixel and a red sub-pixel having a large difference in the voltage used to drive the sub-pixels are adjacent to each other. For example, when a driving current is supplied to the light-emitting element LE of the blue sub-pixel to turn on the blue sub-pixel, a portion of the driving current (which is leakage current) may be transmitted to the red sub-pixel through at least some conductive layers of the intermediate layer IL. If leakage current is generated, the red sub-pixel may be unintentionally turned on when the blue sub-pixel is turned on.

[0124] The number of intermediate layers IL1, IL2, and IL3 emitting light of different colors is not limited to Figure 5 . For example, the intermediate layer IL may include two intermediate layers. In this case, one of the two intermediate layers is substantially the same as the first intermediate layer IL1, and the other of the two intermediate layers may include a second hole transport layer, a second intermediate layer IL2, a third intermediate layer IL3, and a second electron transport layer. In this case, a charge generation layer may be provided between the two intermediate layers to supply electrons to one intermediate layer and holes to the other intermediate layer.

[0125] Despite Figure 5 The first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 are all arranged in the first emission area EA1, the second emission area EA2, and the third emission area EA3, but the embodiments of the present disclosure are not limited thereto. For example, the first intermediate layer IL1 may be arranged in the first emission area EA1, but not in the second emission area EA2 and the third emission area EA3. In addition, the second intermediate layer IL2 may be arranged in the second emission area EA2, but not in the first emission area EA1 and the third emission area EA3. In addition, the third intermediate layer IL3 may be arranged in the third emission area EA3, but not in the first emission area EA1 and the second emission area EA2. In this case, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer OPL may be removed.

[0126] The second electrode CAT may be provided on the third intermediate layer IL3. The second electrode CAT may be formed of a transparent conductive material (TCP) such as ITO and IZO that can transmit light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), and an alloy of magnesium (Mg) and silver (Ag). When the second electrode CAT is formed of a semi-transmissive conductive material, light extraction efficiency may be increased by using a microcavity in each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3.

[0127] The encapsulation layer TFE may be disposed on the emission material layer EML. The encapsulation layer TFE may include one or more inorganic films TFE1 and TFE2 to prevent oxygen or moisture from penetrating into the emission material layer EML. Furthermore, the encapsulation layer TFE may include at least one organic film to protect the emission material layer EML from particles such as dust. For example, the encapsulation layer TFE may include a first inorganic encapsulation film TFE1, an organic encapsulation film TFE2, and a second inorganic encapsulation film TFE3.

[0128] The first inorganic encapsulation film TFE1 may be disposed on the second electrode CAT, the organic encapsulation film TFE2 may be disposed on the first inorganic encapsulation film TFE1, and the second inorganic encapsulation film TFE3 may be disposed on the organic encapsulation film TFE2. The first inorganic encapsulation film TFE1 and the second inorganic encapsulation film TFE3 may be made of silicon nitride (SiN x ) layer, silicon oxynitride (SiON) layer, silicon oxide (SiO x ) layer, titanium oxide (TiO x ) layer and aluminum oxide (AlO x The organic encapsulation film TFE2 may be an organic film formed of a monomer. For example, the organic encapsulation film TFE2 may be an organic film including an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0129] The adhesive layer ADL may bond the encapsulation layer TFE to the optical layer OPL. The adhesive layer ADL may be a double-sided adhesive member. In addition, the adhesive layer ADL may be a transparent adhesive member such as a transparent adhesive member and a transparent adhesive resin member.

[0130] The optical layer OPL includes a plurality of color filters CF1, CF2, and CF3, a plurality of lenses LNS, and a filling layer FIL. The plurality of color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be disposed on the adhesive layer ADL.

[0131] The first color filter CF1 may be aligned with the first emission area EA1 of the first subpixel SP1. The first color filter CF1 may transmit light of the first color, that is, light within a blue wavelength range. The blue wavelength range may be approximately 370 nm to approximately 460 nm. Therefore, the first color filter CF1 may transmit light of the first color among the light emitted from the first emission area EA1.

[0132] The second color filter CF2 can be aligned with the second emission area EA2 of the second subpixel SP2. The second color filter CF2 can transmit light of the second color, that is, light within the green wavelength range. The green wavelength range can be approximately 480 nm to approximately 560 nm. Therefore, the second color filter CF2 can transmit light of the second color among the light emitted from the second emission area EA2.

[0133] The third color filter CF3 may be aligned with the third emission area EA3 of the third subpixel SP3. The third color filter CF3 may transmit light of a third color, i.e., light within a red wavelength range. The red wavelength range may be approximately 600 nm to approximately 750 nm. Therefore, the third color filter CF3 may transmit light of the third color among the light emitted from the third emission area EA3.

[0134] The lenses LNS may be disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. Each of the lenses LNS may be for increasing the color transmitted to the display device 10 (see FIG. Figure 4 Each of the lenses LNS may have a cross-sectional shape that is convex upward.

[0135] A filling layer FIL may be provided on the plurality of lenses LNS. The filling layer FIL may have a predetermined refractive index such that light travels in a third direction (the Z-axis direction) at the interface between the plurality of lenses LNS and the filling layer FIL. Furthermore, the filling layer FIL may be a planarization layer. The filling layer FIL may be an organic film including, for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0136] The cover layer CVL can be disposed on the filling layer FIL. The cover layer CVL can be a glass substrate or a polymer resin substrate. If the cover layer CVL is a glass substrate, the cover layer CVL can be attached to the filling layer FIL. In this case, the filling layer FIL can be bonded to the cover layer CVL. If the cover layer CVL is a glass substrate, the cover layer CVL can serve as an encapsulation substrate. If the cover layer CVL is a polymer resin substrate, the cover layer CVL can be directly coated on the filling layer FIL.

[0137] Figure 6 is a plan view of the mask MK according to the embodiment. Figure 7 yes Figure 6An enlarged plan view of area A. Figure 6 The mask MK of the embodiment shown in FIG. 1 can be deposited with reference to FIG. Figure 5 The process of at least a portion of the intermediate layer IL of the display panel 410 is described as being used.

[0138] Reference Figure 6 and Figure 7 The mask MK according to the embodiment may be a mask for manufacturing an ultra-high-resolution display (display panel). For example, the mask MK may be a mask for manufacturing a display included in an extended reality device (XR device) such as a VR device, an AR device, and a MR device.

[0139] The mask MK according to the embodiment can be used to perform sub-pixel ( Figure 5 For the display included in the extended reality device, the screen is positioned directly in front of the user's eyes, and therefore the display can have a small screen rather than a large screen. In addition, because the screen is positioned close to the user's eyes, ultra-high resolution may be required. For example, the required resolution of the display included in the extended reality device may be about 1000PPI or greater, and preferably, an ultra-high resolution of 2000PPI or greater. Therefore, the mask (deposition mask) MK according to the embodiment may be a mask for manufacturing such an ultra-high resolution display.

[0140] The mask MK according to an embodiment may include a mask base MSUB.

[0141] The mask substrate MSUB according to an embodiment may include a silicon wafer. Silicon wafers can be used as substrates for ultra-high-resolution displays because, compared to large-area substrates, silicon wafers allow for finer and more precise processing by utilizing technologies developed in semiconductor processing. The mask MK according to an embodiment can be used in the same manner as a silicon wafer to form pixels on the silicon wafer for such ultra-high-resolution displays.

[0142] The shape of the mask substrate MSUB according to an embodiment can conform to the silicon wafer of the ultra-high-resolution display. For example, the mask substrate MSUB can have the same size or shape as the silicon wafer of the ultra-high-resolution display. However, it should be understood that the embodiments of the present disclosure are not limited thereto. The mask substrate MSUB can include a large-area substrate. For example, the mask substrate MSUB can include materials such as glass, quartz, and polymer resin.

[0143] The mask substrate MSUB according to embodiments may include a plurality of cell areas CA and a cell peripheral area CRA.

[0144] According to an embodiment, the cell peripheral area CRA may surround a plurality of cell areas CA. The cell peripheral area CRA may be aligned with the mask frame MF. When viewed from the top, the mask frame MF may define the mask opening COP and may surround the mask opening COP. The mask frame MF may be a region supporting the mask MK. The structure of the mask frame MF will be described later.

[0145] According to an embodiment of the present disclosure, a plurality of unit areas CA may be formed, and the unit areas CA may be spaced apart from each other. The unit area CA may be positioned to align with the mask opening COP. In other words, the unit area CA may not overlap with the mask frame MF. According to an embodiment, the unit area CA may overlap with the mask film MM. When viewed from the top, the mask film MM may include a plurality of patterns and a pixel opening SOP. When viewed from the top, the plurality of patterns included in the mask film MM may be formed as one, surrounding the pixel opening SOP. When viewed from the top, the plurality of patterns included in the mask film MM may completely surround the pixel opening SOP, and when viewed from the top, the mask frame MF may completely surround the plurality of patterns included in the mask film MM. The plurality of patterns included in the mask film MM will be described later.

[0146] Figure 8 It is along Figure 7 A cross-sectional view taken along line X1-X1'.

[0147] Reference Figure 8 The mask frame MF according to an embodiment may include a mask substrate MSUB and a first mask inorganic layer IO1, a second mask inorganic layer IO2, a third mask inorganic layer IO3, and a fourth mask inorganic layer IO4. The first mask inorganic layer IO1 and the second mask inorganic layer IO2 may be positioned on the upper surface s1 of the mask substrate MSUB, and the third mask inorganic layer IO3 and the fourth mask inorganic layer IO4 may be positioned on the lower surface s2 of the mask substrate MSUB. The mask substrate MSUB has been described above, and therefore, redundant description will be omitted.

[0148] According to an embodiment of the present disclosure, the first inorganic mask layer IO1 may be positioned on and in contact with the upper surface s1 of the mask substrate MSUB. The first inorganic mask layer IO1 may include an inorganic insulating material. For example, the first inorganic mask layer IO1 may include one of silicon nitride, silicon oxide, and silicon oxynitride.

[0149] According to an embodiment of the present disclosure, the second mask inorganic layer IO2 may be positioned on the first mask inorganic layer IO1 and may be in contact with the first mask inorganic layer IO1. According to an embodiment of the present disclosure, the second mask inorganic layer IO2 may include the same material as the mask shadow / mask shadow portion (mask shadow) MS of the mask film MM, which will be described later. In the process of manufacturing the mask MK according to an embodiment of the present disclosure, the mask shadow MS and the second mask inorganic layer IO2 may be formed as one body and then formed into the shape shown via an etching process. The manufacturing process will be described later.

[0150] According to an embodiment, the second mask inorganic layer 102 may include an inorganic insulating material. For example, the second mask inorganic layer 102 may include one of silicon nitride, silicon oxide, and silicon oxynitride. According to an embodiment of the present disclosure, the first mask inorganic layer 101 and the second mask inorganic layer 102 may include different materials. For example, when the first mask inorganic layer 101 is silicon oxide, the second mask inorganic layer 102 may include silicon nitride or silicon oxynitride without silicon oxide.

[0151] The mask MK according to the embodiment is formed by stacking a first mask inorganic layer IO1 and a second mask inorganic layer IO2 comprising different inorganic materials, so that the stress properties of each of the first mask inorganic layer IO1 and the second mask inorganic layer IO2 can be reduced. For example, the stacking structure can be designed so that if the first mask inorganic layer IO1 is formed of silicon oxide having compressive stress, the second mask inorganic layer IO2 is formed of silicon nitride having tensile stress. Therefore, the mask frame MF according to the embodiment can prevent delamination between the first mask inorganic layer IO1 and the second mask inorganic layer IO2.

[0152] According to an embodiment of the present disclosure, the third mask inorganic layer 103 can be positioned on the lower surface s2 of the mask substrate MSUB and can be in contact with the lower surface s2 of the mask substrate MSUB. The third mask inorganic layer 103 can be formed using the same process as the first mask inorganic layer 101. Therefore, the third mask inorganic layer 103 can include the same material as the first mask inorganic layer 101. The manufacturing process will be described later.

[0153] According to an embodiment of the present disclosure, the fourth mask inorganic layer 104 may be positioned on the third mask inorganic layer 103 and may be in contact with the third mask inorganic layer 103. The fourth mask inorganic layer 104 may be formed via the same process as the second mask inorganic layer 102, and therefore, the fourth mask inorganic layer 104 may include the same material as the second mask inorganic layer 102. The manufacturing process will be described later.

[0154] According to an embodiment, the mask frame MF may define mask openings COP. A plurality of mask openings COP may be generated by etching portions of the mask substrate MSUB from the lower surface s2 of the mask substrate MSUB.

[0155] According to an embodiment, the mask film MM may be positioned to be aligned with the cell area CA. The cell area CA may be defined by the mask opening COP.

[0156] According to an embodiment, the mask film MM may include a plurality of mask shadows MS, and adjacent mask shadows MS among the plurality of mask shadows MS may define a pixel opening SOP. That is, the mask film MM may include a plurality of mask shadows MS and a plurality of pixel openings SOP.

[0157] The pixel opening SOP of the mask film MM can be referred to as a hole or a mask hole. A plurality of pixel opening SOPs can penetrate the mask frame MF along the thickness direction (e.g., the third direction (Z-axis direction)) of the mask MK. In other words, the pixel opening SOP can be a through hole. A plurality of pixel opening SOPs can be produced by etching a portion of the mask substrate MSUB from the lower surface s2 of the mask substrate MSUB.

[0158] When the deposition material evaporates from the deposition source inside the deposition device, the mask shadow MS may be used to cover the substrate (eg, the display panel 410 (see FIG. 4 )) on which the deposition is to be performed. Figure 5 ) or a blocking unit of a backplane substrate). Therefore, the deposition material generated from the deposition source can be deposited on the surface of the substrate for deposition (eg, the display panel 410 or the backplane substrate) through the pixel opening SOP of the mask film MM.

[0159] Figure 9 yes Figure 8 FIG. 1 is an enlarged cross-sectional view of the mask frame MF and structures around the mask frame MF.

[0160] Reference Figure 9 The mask substrate MSUB according to the embodiment may include a side surface s3 facing the cell area CA. The side surface s3 of the mask substrate MSUB may face the pixel opening SOP and may connect the upper surface s1 and the lower surface s2.

[0161] In some embodiments, the first mask inorganic layer IO1 may include a side surface a3 facing the cell area CA. The side surface a3 of the first mask inorganic layer IO1 may face the pixel opening SOP. According to an embodiment of the present disclosure, the side surface a3 of the first mask inorganic layer IO1 may extend from the side surface s3 of the mask substrate MSUB. In other words, the side surface a3 of the first mask inorganic layer IO1 does not protrude from the side surface s3 of the mask substrate MSUB and may be positioned on the same line extending from the side surface s3 of the mask substrate MSUB. It should be noted that due to process errors, there may be errors in the range of 1 micron or less.

[0162] In some embodiments, the second mask inorganic layer 102 may include a side surface b3 facing the cell area CA. The side surface b3 of the second mask inorganic layer 102 may face the pixel opening SOP. The side surface b3 of the second mask inorganic layer 102 may be spaced apart from the mask shadow MS, and the pixel opening SOP is located between the side surface b3 of the second mask inorganic layer 102 and the mask shadow MS. In other words, the second mask inorganic layer 102 may be spaced apart from the mask shadow MS, and there is a space between the second mask inorganic layer 102 and the mask shadow MS.

[0163] In some embodiments, the side surface b3 of the second mask inorganic layer 102 may extend from the side surface a3 of the first mask inorganic layer 101. In other words, the side surface b3 of the second mask inorganic layer 102 may not protrude from the side surface a3 of the first mask inorganic layer 101 and may be positioned on the same line extending from the side surface a3 of the first mask inorganic layer 101. The expression "on the same line" means not being separated but extending and connecting.

[0164] In other words, the side surface b3 of the second mask inorganic layer 102 according to the embodiment can be positioned on the same line extending from the side surface s3 of the mask substrate MSUB. The side surface b3 of the second mask inorganic layer 102 does not protrude from the side surface s3 of the mask substrate MSUB and can be patterned so that the side surface b3 of the second mask inorganic layer 102 is aligned with the line extending from the edge of the mask substrate MSUB. It should be noted that due to process errors, there may be errors in the range of 1 micron or less.

[0165] The first mask inorganic layer IO1 and the second mask inorganic layer IO2 can be formed in a specific pattern until the edge of the mask substrate MSUB. According to an embodiment of the present disclosure, the first mask inorganic layer IO1 and the second mask inorganic layer IO2 are patterned so that they are aligned with the line extending from the edge of the mask substrate MSUB of the mask MK, and the first mask inorganic layer IO1 and the second mask inorganic layer IO2 can be formed to be in full contact with the mask substrate MSUB without any protrusions. Therefore, the mask MK according to the embodiment can solve the problem of warping of the mask inorganic layer, and as a result, the mask MK according to the embodiment can increase the ultra-high resolution display panel 410 (see Figure 5 ) and the adhesion between the mask MK.

[0166] In some embodiments, the height H1 of the first mask inorganic layer 101 may be equal to the height H3 of the third mask inorganic layer 103. This may be because the first mask inorganic layer 101 and the third mask inorganic layer 103 are formed through the same process.

[0167] Furthermore, the height H2 of the second mask inorganic layer 102 may be equal to the height H4 of the fourth mask inorganic layer 104. This may be because the second mask inorganic layer 102 and the fourth mask inorganic layer 104 are formed through the same process. Furthermore, the height H2 of the second mask inorganic layer 102 may be equal to the height Hms1 of the mask shadow MS. This may be because the second mask inorganic layer 102 and the mask shadow MS are formed through the same process. The manufacturing process will be described later.

[0168] Figure 10 is a flowchart for illustrating a method for manufacturing the mask MK according to the embodiment. Figures 11 to 20 2 are cross-sectional views for illustrating process steps of a method for manufacturing the mask MK according to an embodiment of the present disclosure.

[0169] In the following, reference will be made to Figures 10 to 20 A method for manufacturing a mask MK (see FIG. Figure 8 ) method. It should be noted that only some of the manufacturing processes of the mask MK will be described. Other processes for forming the elements described herein may be performed before or after the manufacturing processes described below. In addition, manufacturing processes of the mask MK known in the art may be performed before or after the manufacturing processes described below.

[0170] First, refer to Figure 10 Step 1001 of forming a first inorganic film (first inorganic material layer) on the upper and lower surfaces of a mask substrate will be described.

[0171] Reference Figure 11, preparing a mother mask substrate MMSUB including a plurality of cell regions CA and a cell peripheral region CRA. The cell peripheral region CRA may be a remaining region other than the plurality of cell regions CA. The mother mask substrate MMSUB may include a silicon wafer.

[0172] Subsequently, a first inorganic material layer 10A is deposited on the upper surface S1 and lower surface S2 of the master mask substrate MMSUB. In this process, the master mask substrate MMSUB is placed in a deposition chamber performing a film formation process to form the first inorganic material layer 10A. Therefore, the first inorganic material layer 10A can be simultaneously formed on the upper surface S1 and lower surface S2 of the master mask substrate MMSUB. The first inorganic material layer 10A can be formed to completely cover the upper surface S1 and lower surface S2 of the master mask substrate MMSUB.

[0173] In the following description, the first inorganic material layer 10A deposited on the upper surface S1 of the mask master substrate MMSUB is referred to as the first upper surface material layer 10A1, and the first inorganic material layer 10A deposited on the lower surface S2 of the mask master substrate MMSUB is referred to as the first lower surface material layer 10A2. As described above, the first inorganic material layer 10A may include an inorganic insulating material. Redundant descriptions will be omitted.

[0174] Then, refer to Figure 10 Step 1003 of forming a second inorganic film (second inorganic material layer) on the first inorganic film will be described.

[0175] Reference Figure 12 , a second inorganic material layer 10B is deposited on the first inorganic material layer 10A. In this process, similar to the formation of the first inorganic material layer 10A, the second inorganic material layer 10B can be formed by placing the mask master substrate MMSUB into a deposition chamber that performs a film formation process. Therefore, the second inorganic material layer 10B can be formed on the first upper surface material layer 10A1 and the first lower surface material layer 10A2 at the same time. The second inorganic material layer 10B can completely cover the first upper surface material layer 10A1 and the first lower surface material layer 10A2. In the following description, the second inorganic material layer 10B deposited on the first upper surface material layer 10A1 is referred to as the second upper surface material layer 10B1, and the second inorganic material layer 10B deposited on the first lower surface material layer 10A2 is referred to as the second lower surface material layer 10B2.

[0176] As described above, the second inorganic material layer 10B may include an inorganic insulating material and may include a material different from that of the first inorganic material layer 10A. Redundant descriptions will be omitted.

[0177] Then, refer to Figure 10Step 1005 of forming a mask film by patterning the second inorganic film positioned on the upper surface of the mask substrate will be described.

[0178] Reference Figure 13 and Figure 14 A plurality of photoresists PR are formed on the second inorganic material layer 10B (e.g., the second upper surface material layer 10B1) positioned on the upper surface S1 of the mask master substrate MMSUB. In this process, the photoresists PR may be positioned in the cell area CA and the cell peripheral area CRA. The photoresists PR positioned in the cell peripheral area CRA may completely cover the second upper surface material layer 10B1, while the photoresists PR positioned in the cell area CA may be spaced apart from each other.

[0179] Subsequently, a first etching process (first etching) is performed using the plurality of photoresists PR as a mask. For example, the first etching process (first etching) can be performed as a dry etching process. In this process, a portion of the second upper surface material layer 10B1 on which the photoresist PR is not formed can be removed, and the second upper surface material layer 10B1 can be formed into Figure 8 . The mask shadow MS and the second mask inorganic layer IO2 shown in . The mask shadow MS and the second mask inorganic layer IO2 can be spaced apart from each other in the first direction (X-axis direction), and the pixel opening SOP is located between the mask shadow MS and the second mask inorganic layer IO2. The mask shadow MS formed in this process can surround the pixel opening SOP and can be spaced apart from each other.

[0180] Then, refer to Figure 10 Step 1007 of forming an opening (temporary opening) by etching the first inorganic film and the second inorganic film positioned on the lower surface of the mask substrate will be described.

[0181] Reference Figure 15 and Figure 16 First, a plurality of photoresists PR are formed on the second inorganic material layer 10B (eg, the second lower surface material layer 10B2) located on the lower surface S2 of the mask mother substrate MMSUB. In this process, the photoresists PR may be located only in the cell peripheral area CRA.

[0182] Subsequently, a second etching process (second etching) is performed using the plurality of photoresists PR as a mask. The second etching process (second etching) can be performed toward the lower surface S2 of the mask master substrate MMSUB, that is, toward the rear surface of the mask master substrate MMSUB. For example, the second etching process (second etching) can be performed as a dry etching process.

[0183] In this process, portions of the first lower surface material layer 10A2 and the second lower surface material layer 10B2 on which the photoresist PR is not formed may be removed. In this process, a temporary opening TOP may be formed at the position where the first lower surface material layer 10A2 and the second lower surface material layer 10B2 have been removed. The temporary opening TOP may be aligned with the cell area CA. In this way, the first lower surface material layer 10A2 and the second lower surface material layer 10B2 may be formed into Figure 8 The third mask inorganic layer 103 and the fourth mask inorganic layer 104 are in the form shown in FIG. The third mask inorganic layer 103 and the fourth mask inorganic layer 104 may be positioned such that they overlap with the cell peripheral area CRA but do not overlap with the cell area CA.

[0184] Then, refer to Figure 10 Step 1009 of leaving the mask film pattern by removing the mask base and the portion of the first inorganic film aligned with the opening (temporary opening) will be described.

[0185] Reference Figure 17 and Figure 18 First, a plurality of photoresists PR are formed on the fourth mask inorganic layer IO4 positioned to be aligned with the cell peripheral area CRA. The photoresists PR may surround the temporary opening TOP.

[0186] Subsequently, a third etching process (3rd etching) is performed using the plurality of photoresists PR as a mask. The third etching process (3rd etching) can be performed toward the lower surface S2 of the mask master substrate MMSUB, that is, toward the rear surface of the mask master substrate MMSUB. For example, the third etching process (3rd etching) can be performed as a wet etching process. In this process, the portion of the mask master substrate MMSUB on which the photoresist PR is not formed can be removed. In other words, the portion of the mask master substrate MMSUB aligned with the temporary opening TOP can be removed.

[0187] In this process, the mask mother substrate MMSUB can be formed as Figure 8 The shape of the mask substrate MSUB shown in FIG. 1 may be such that the mask substrate MSUB may define a mask opening COP. The mask substrate MSUB may be positioned so that the mask substrate MSUB overlaps the cell peripheral area CRA but does not overlap the cell area CA. The mask substrate MSUB may include an upper surface s1 and a lower surface s2 aligned with the cell peripheral area CRA.

[0188] Reference Figure 19 and Figure 20 First, a plurality of photoresists PR are formed on the fourth mask inorganic layer 104 positioned to be aligned with the cell peripheral area CRA. The photoresists PR may surround the mask opening COP.

[0189] Subsequently, a fourth etching process (4th etching) is performed using the plurality of photoresists PR as a mask. The fourth etching process (4th etching) can be performed toward the lower surface s2 of the mask substrate MSUB, that is, toward the rear surface of the mask substrate MSUB. For example, the fourth etching process (4th etching) can be performed as a wet etching process. In this process, the portion of the first upper surface material layer 10A1 on which the photoresist PR is not formed can be removed. In other words, the portion of the first upper surface material layer 10A1 aligned with the mask opening COP can be removed.

[0190] In this process, the first upper surface material layer 10A1 may be formed as Figure 8 The first mask inorganic layer IO1 shown in FIG. The first mask inorganic layer IO1 can be positioned so that the first mask inorganic layer IO1 overlaps the cell peripheral area CRA but does not overlap the cell area CA. In this way, a Figure 8 The mask frame MF and the mask film MM shown in .

[0191] Reference Figures 13 to 20 , the first inorganic material layer 10A and the second inorganic material layer 10B may be patterned up to the edge of the mask substrate MSUB. In this process, as Figure 8 As shown in FIG, the pixel openings SOP may be formed so that they penetrate the mask frame MF. As described above, the pixel openings SOP included in the mask MK may be formed so that they Figure 5 Therefore, the mask MK according to the embodiment can be used to manufacture a high-resolution display panel 410 (see FIG. Figure 5 ).

[0192] The present invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present invention to those skilled in the art.

[0193] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined by the following claims.

Claims

1. A deposition mask, wherein: The deposition mask comprises: a mask substrate comprising a plurality of unit regions and a unit peripheral region surrounding the plurality of unit regions; a mask film overlapping the plurality of unit regions of the mask substrate; and a mask frame overlapping the cell peripheral region of the mask substrate, wherein the mask film includes a mask shadow defining a pixel opening, wherein the mask frame comprises a first mask inorganic layer on the mask substrate and a second mask inorganic layer on the first mask inorganic layer, and The first mask inorganic layer and the second mask inorganic layer are formed in a specific pattern up to the edge of the mask substrate.

2. The deposition mask according to claim 1, wherein The first mask inorganic layer and the second mask inorganic layer do not overlap with the plurality of unit regions, and The second mask inorganic layer includes the same material as that of the mask shadow.

3. The deposition mask according to claim 2, wherein: The pixel opening is a through hole, and The second mask inorganic layer is spaced apart from the mask shadow, and the pixel opening is located between the second mask inorganic layer and the mask shadow.

4. The deposition mask according to claim 3, wherein: The mask substrate includes silicon, and wherein the mask substrate has a circular shape when viewed from the top.

5. The deposition mask according to claim 4, wherein The first mask inorganic layer and the second mask inorganic layer include an inorganic insulating material, and The first mask inorganic layer and the second mask inorganic layer include different materials. The deposition mask according to claim 1 , wherein: The first mask inorganic layer includes silicon oxide, and the second mask inorganic layer includes silicon nitride.

7. The deposition mask according to claim 1, wherein The mask frame includes: a third mask inorganic layer positioned on the mask substrate on an opposite side of the first mask inorganic layer; and A fourth mask inorganic layer is positioned on the third mask inorganic layer.

8. The deposition mask according to claim 7, wherein The third mask inorganic layer is made of the same material as that of the first mask inorganic layer, and the fourth mask inorganic layer is made of the same material as that of the second mask inorganic layer.

9. The deposition mask according to claim 8, wherein A height of the first mask inorganic layer is equal to a height of the third mask inorganic layer, and a height of the second mask inorganic layer is equal to a height of the fourth mask inorganic layer.

10. The deposition mask according to claim 1, wherein The mask substrate includes a first side surface facing the cell area, Wherein, the first mask inorganic layer includes a second side surface facing the unit area, and Wherein, the first side surface and the second side surface are positioned on the same line.

11. The deposition mask according to claim 10, wherein The second mask inorganic layer includes a third side surface facing the cell region, and the third side surface is positioned on the same line as the first side surface and the second side surface.

12. The deposition mask according to claim 11, wherein The third side surface is spaced apart from the mask shadow, and the pixel opening is located between the third side surface and the mask shadow.

13. The deposition mask according to claim 11, wherein The second side surface is positioned between the first side surface and the third side surface.

14. The deposition mask according to claim 1, wherein When viewed from the top, the mask frame defines a mask opening, wherein the mask film overlaps the mask opening when viewed from the top, and Wherein, when viewed from the top, the mask frame completely surrounds the mask film.

15. A method for manufacturing a deposition mask, wherein: The method comprises: forming a first inorganic material layer on a mask substrate including a plurality of cell regions and a cell peripheral region surrounding the plurality of cell regions; forming a second inorganic material layer on the first inorganic material layer; forming a mask film by patterning the second inorganic material layer positioned on the upper surface of the mask substrate; forming a mask opening by etching the first inorganic material layer and the second inorganic material layer positioned on the lower surface of the mask substrate; and A portion of the mask substrate overlapping the mask opening and a portion of the first inorganic material layer positioned on the upper surface of the mask substrate overlapping the mask opening are removed.

16. The method according to claim 15, wherein The forming of the first inorganic material layer includes: simultaneously forming the first inorganic material layer on the upper surface and the lower surface of the mask substrate.

17. The method according to claim 16, wherein The forming of the second inorganic material layer includes: simultaneously forming the second inorganic material layer on the upper surface and the lower surface of the mask substrate.

18. The method according to claim 17, wherein The first inorganic material layer and the second inorganic material layer include different materials.

19. The method according to claim 15, wherein A side surface of the first inorganic material layer and a side surface of the second inorganic material layer are positioned on the same line extending from a side surface of the patterned mask substrate.

20. The method according to claim 15, wherein The first inorganic material layer and the second inorganic material layer are patterned up to an edge of the mask substrate.

21. An electronic device, wherein: The electronic device comprises: A display device including a display panel formed using a deposition mask, Wherein, the deposition mask comprises: a mask substrate comprising a plurality of unit regions and a unit peripheral region surrounding the plurality of unit regions; a mask film overlapping the plurality of unit regions of the mask substrate; and a mask frame overlapping the cell peripheral region of the mask substrate, wherein the mask film includes a mask shadow defining a pixel opening, wherein the mask frame comprises a first mask inorganic layer on the mask substrate and a second mask inorganic layer on the first mask inorganic layer, and The first mask inorganic layer and the second mask inorganic layer are formed in a specific pattern up to the edge of the mask substrate.

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