Optical interconnection chip based on silicon and III-V compound and preparation method thereof
By preparing active and passive devices on silicon photonic wafers, cutting III-V epitaxial wafers into bare wafers and bonding them to silicon photonic wafers, the problems of high power consumption of electrical signal interconnection and high cost of III-V compound materials are solved, and efficient integration of functions such as lasers, modulators, and detectors is achieved, reducing costs and improving the accuracy of optical interconnection.
Patent Information
- Application Number
- CN202510875452.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-26
- Publication Date
- 2025-09-26
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
In the existing technology, the power consumption of electrical signal interconnection increases as the bandwidth increases, and the cost of preparing large-size wafers using III-V compound materials is high, resulting in an imperfect method for preparing heterogeneous optical interconnection chips for optoelectronic heterogeneous integrated architectures.
By preparing active and passive devices on silicon photonic wafers, cutting the III-V epitaxial wafers into bare wafers and bonding them to silicon photonic wafers, removing the substrate and performing wafer-level processing, and combining metal interconnect layers and via formation, heterogeneous integration of integrated circuit chips and III-V devices is achieved.
It achieves wafer-level integration of functions such as lasers, modulators, and detectors, improves production efficiency, reduces costs, and improves the accuracy of optical interconnection and reduces optical loss.
Smart Images
Figure CN120703907A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of chips, and in particular to an optical interconnection chip based on silicon and III-V compounds and a preparation method thereof. Background Art
[0002] With the rapid development of information technology, especially artificial intelligence, power supply has become a limiting factor that cannot be ignored. It is estimated that data centers consume 2% of the world's electricity supply, and 15% to 30% of it is used for electrical signal interconnection. As artificial intelligence has higher and higher requirements for data bandwidth, the current electrical signal interconnection consumes more and more power as the bandwidth increases. Therefore, more and more attention has been paid to optical interconnection technology, especially silicon photonics technology. In recent years, silicon photonics technology has played a role in long-distance signal transmission, but electrical signals are still used for transmission between circuit boards, between chips, and within chips. This is also the problem addressed by the optical interconnection chip and its preparation method of this application.
[0003] CMOS-based CPUs / GPUs and other electronic chips are widely used in the field of artificial intelligence. Adhering to Moore's Law, these chips offer high performance and low cost, but they still face power consumption and bandwidth issues with long-distance electrical signal interconnection. Silicon photonics platforms based on CMOS processes include a range of active and passive devices, offering low loss and low cost. However, due to the low luminous efficiency and weak photoelectric effect of silicon-based materials, silicon photonics platforms require additional light source devices. III-VV compound materials are widely used in light source preparation and high-speed modulation, but due to material property limitations, large-scale wafers cannot be produced, resulting in high costs.
[0004] Optoelectronic heterogeneous integrated architectures include different modules, such as silicon photonic modules, III-V compound modules, and integrated circuit modules. Silicon photonic modules can be used to manufacture various active and passive devices, such as modulators, waveguides, and detectors; III-V compound modules can be used to manufacture lasers, modulators, detectors, and other devices; and integrated circuit modules can be used to manufacture various driver circuits and detection circuits. In an optoelectronic heterogeneous integrated architecture, the positional relationship between different modules affects the overall performance of the optoelectronic integrated architecture and also determines the feasibility and manufacturability of the process. However, there is currently no complete heterogeneous optical interconnect chip and its preparation method that integrates different functionalities, such as lasers, modulators, detectors, and driver circuits, at the wafer level. Summary of the Invention
[0005] To solve the above technical problems, the present application provides a method for preparing an optical interconnection chip based on silicon and Group III-V compounds, which can heterogeneously integrate integrated circuit chip wafers, silicon photonic chip wafers, and Group III-V chip wafers, thereby realizing a complete heterogeneous optical interconnection chip and its preparation method that integrates different functional wafer-level devices such as lasers, modulators, detectors, and driving circuits.
[0006] The first aspect of the present application discloses a method for preparing an optical interconnect chip based on silicon and III-V compounds, comprising: step S1, preparing active devices and passive devices on a silicon photonic wafer; step S2, preparing at least one III-V epitaxial wafer, and then cutting the III-V epitaxial wafer into III-V epitaxial bare wafers; step S3, performing bare wafer-to-wafer bonding between the III-V epitaxial bare wafer and the silicon photonic wafer; step S4, removing the substrate of the III-V epitaxial bare wafer, retaining the III-V epitaxial bare wafer; and step S5, removing the substrate of the III-V epitaxial bare wafer. The epitaxial structure of the V epitaxial bare wafer is processed at the wafer level to prepare a III-V device; step S5, preparing a first via on the active device and the III-V device, and forming a metal electrode; step S6, removing the substrate of the silicon photonic wafer, and preparing a metal interconnection layer on the surface of the silicon photonic wafer with the substrate removed, the metal interconnection layer including a second via and a first pad; step S7, performing bare wafer-to-wafer bonding of the integrated circuit chip bare wafer and the silicon photonic wafer.
[0007] According to the preparation method of the first aspect of the present application, the step S1 also includes: forming a first dielectric layer on the silicon photonic wafer; the step S2 also includes: forming a second dielectric layer on the III-V epitaxial wafer; the step S3 also includes: performing surface planarization treatment on at least the first dielectric layer, performing room temperature hydrophilic bonding on the second dielectric layer and the first dielectric layer and then high temperature annealing, thereby performing bare wafer-to-wafer bonding on the III-V epitaxial bare wafer and the silicon photonic wafer, wherein the first dielectric layer and the second dielectric layer are silicon dioxide layers or other hydrophilic thin film layers.
[0008] According to the preparation method of the first aspect of the present application, the step S1 also includes: depositing silicon nitride material on the silicon material of the silicon photonic wafer, and using the silicon material and the silicon nitride material to prepare the active device and the passive device respectively, the active device includes at least one of a silicon modulator and a silicon germanium detector, and the passive device includes at least one of a silicon waveguide, a silicon grating, a silicon nitride waveguide, and a silicon nitride grating.
[0009] According to the preparation method of the first aspect of the present application, the III-V device includes a distributed feedback laser, an electro-absorption modulator, and a photodiode detector. The distributed feedback laser is aligned with the silicon nitride waveguide and / or silicon waveguide for optical coupling, thereby transmitting light from the distributed feedback laser to the silicon nitride waveguide and / or silicon waveguide.
[0010] According to the preparation method of the first aspect of the present application, step S5 further includes: using metal to prepare at least one of the following devices: a heater, a MIM capacitor, and a reflector.
[0011] According to the preparation method of the first aspect of the present application, the step S5 also includes: forming a third dielectric layer on the metal electrode, and bonding the third dielectric layer to the first carrier wafer by direct bonding, wherein the third dielectric layer is a silicon dioxide layer or a silicon nitride layer, and the material of the first carrier wafer is silicon.
[0012] According to the preparation method of the first aspect of the present application, step S6 also includes: on the surface of the silicon optical wafer from which the substrate has been removed, using metal to prepare alignment marks for aligning the silicon grating and / or the silicon nitride grating, and preparing microlenses for converging external light onto the silicon grating and / or the silicon nitride grating.
[0013] According to the preparation method of the first aspect of the present application, step S6 also includes: forming a first micro-bump on the first pad; coating a first epoxy resin type material on the surface of the silicon photonic wafer from which the substrate has been removed for filling the gap, and then temporarily bonding a second carrier wafer on the first epoxy resin type material; thinning the first carrier wafer, preparing a third via on the first carrier wafer, and using a redistribution layer process to prepare a second pad on the surface of the first carrier wafer, forming a second micro-bump on the second pad, wherein the second micro-bump includes a micro-bump without electrical connection for heat dissipation; debonding the surface of the silicon photonic wafer from which the substrate has been removed, removing the first epoxy resin type material and the second carrier wafer; coating a second epoxy resin type material on the surface of the first carrier wafer for filling the gap, and then temporarily bonding a third carrier wafer on the second epoxy resin type material.
[0014] According to the preparation method of the first aspect of the present application, the step S6 further includes: redistributing the first pad using a redistribution layer process before forming the first micro bump on the first pad.
[0015] According to the preparation method of the first aspect of the present application, step S7 also includes: forming a third micro-bump on the integrated circuit chip bare wafer, and bonding the integrated circuit chip bare wafer to the silicon photonic wafer using one of the following bonding methods: flip-chip bonding, thermal compression bonding, or copper-copper hybrid bonding.
[0016] According to the preparation method of the first aspect of the present application, the step S7 further includes: performing capillary bottom filling on the bottom of the bare integrated circuit chip using a first bottom filling glue for heat dissipation and mechanical support.
[0017] According to the preparation method of the first aspect of the present application, step S7 also includes: debonding the surface of the first carrier wafer, removing the second epoxy resin type material and the third carrier wafer; cutting the silicon photonic wafer into optical interconnect chip bare wafers, and using the second micro-bumps to flip the optical interconnect chip bare wafer onto the packaging substrate, thereby preparing an optical interconnect chip.
[0018] According to the preparation method of the first aspect of the present application, the step S7 further includes: performing capillary bottom filling with a second bottom filling glue at the bottom of the optical interconnect chip bare sheet for heat dissipation and mechanical support; and performing plastic sealing and heat sink treatment on the integrated circuit chip bare sheet and the packaging substrate.
[0019] According to the preparation method of the first aspect of the present application, step S7 also includes: using the alignment mark to encapsulate the optical fiber array unit connector on the optical interconnection chip, and the optical fiber array unit connector has a built-in reflector, so that horizontally incident light is vertically incident into the optical interconnection chip.
[0020] The second aspect of the present application discloses an optical interconnect chip based on silicon and Group III-V compounds, wherein the optical interconnect chip is prepared by the preparation method described above.
[0021] The second aspect of the present application discloses an optical interconnect chip, which includes, in sequence, an integrated circuit chip bare wafer, a silicon photonic wafer, and at least one III-V epitaxial bare wafer, on which active devices and passive devices are prepared. The III-V epitaxial bare wafer is bare-wafer-bonded to the silicon photonic wafer, the substrate of the silicon photonic wafer is removed, and the integrated circuit chip bare wafer is bare-wafer-bonded to the silicon photonic wafer with the substrate removed.
[0022] According to the optical interconnect chip disclosed in the second aspect of the present application, the integrated circuit chip bare wafer includes a driving circuit and a detection circuit, the active device includes at least one of a silicon modulator and a silicon germanium detector, the passive device includes at least one of a silicon waveguide, a silicon grating, a silicon nitride waveguide, and a silicon nitride grating, and the III-V epitaxial bare wafer includes at least one of a distributed feedback laser, an electro-absorption modulator, and a photodiode detector.
[0023] According to the optical interconnection chip disclosed in the second aspect of the present application, a first via is prepared on the active device and the III-V epitaxial bare wafer, and a metal electrode is formed. A metal interconnection layer is prepared on the surface of the silicon optical wafer with the substrate removed, and the metal interconnection layer includes a second via and a first pad.
[0024] According to the optical interconnect chip disclosed in the second aspect of the present application, alignment marks are prepared on the surface of the silicon optical wafer with the substrate removed, for aligning the silicon grating and / or the silicon nitride grating.
[0025] According to the optical interconnect chip disclosed in the second aspect of the present application, a microlens is prepared on the surface of the silicon optical wafer with the substrate removed, for converging external light onto the silicon grating and / or the silicon nitride grating.
[0026] According to the optical interconnect chip and its preparation method of the present application, integrated circuit chip wafers, silicon photonic chip wafers, and III-V chip wafers can be heterogeneously integrated, realizing a complete technical solution for integrating different functional wafer-level devices such as lasers, modulators, detectors, and driving circuits.
[0027] The architecture of the optical interconnect chip is that the integrated circuit chip is on the top, the silicon photonic chip is in the middle, and the III-V chip is on the bottom. Since the integrated circuit chip will generate a lot of heat, placing it on the upper layer can facilitate its heat dissipation through heat sinks and water cooling. The light source and detector in the III-V chip will also generate a lot of heat. Placing it on the bottom layer can facilitate its heat dissipation through the substrate.
[0028] The III-V epitaxial wafer is cut into III-V epitaxial bare wafers, and then the III-V epitaxial bare wafers are bare-wafer-to-wafer bonded to the silicon photonic wafer. The III-V epitaxial bare wafer can be reconstructed onto a larger-sized silicon photonic wafer for device processing, greatly improving production efficiency.
[0029] First, the III-V epitaxial bare wafer is bonded to the silicon photonic wafer by bare wafer-to-wafer bonding. The silicon photonic wafer can be subjected to wafer-level chip probe testing, which can test the optical interconnection yield of the chips on the wafer. The chips that have passed the yield test can be used for subsequent integrated circuit chip bare wafer bonding, avoiding material waste and saving production costs.
[0030] Alignment marks are set on the optical interconnect chip to facilitate the alignment of the external light source with the chip, and to accurately package the fiber array connector on the chip, thereby improving the accuracy of optical interconnection and reducing light loss. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figure 1 Schematic diagram of preparing silicon photonic wafer;
[0032] Figure 2 Schematic diagram of preparing three different III-V epitaxial wafers;
[0033] Figure 3 Schematic diagram of bare wafer-to-wafer bonding of a III-V epitaxial bare wafer to a silicon photonic wafer;
[0034] Figure 4 Schematic diagram of removing the substrate of a III-V epitaxial bare wafer;
[0035] Figure 5 Schematic diagram for preparing III-V devices;
[0036] Figure 6 Schematic diagram for preparing vias and multi-electrodes for active devices and III-V devices;
[0037] Figure 7 is a schematic diagram of bonding with a first carrier wafer;
[0038] Figure 8 Schematic diagram of preparing metal interconnection layer;
[0039] Figure 9 Schematic diagram of the preparation of microlenses;
[0040] Figure 10 A schematic diagram of wafer-level chip probe testing;
[0041] Figure 11 is a schematic diagram of forming a first micro bump on a first pad;
[0042] Figure 12 is a schematic diagram of temporarily bonding the second carrier wafer;
[0043] Figure 13 A schematic diagram of preparing a third via hole, a second pad, and forming a second micro-bump on a first carrier wafer;
[0044] Figure 14 Schematic diagram of debonding the surface of a silicon photonic wafer with the substrate removed and temporarily bonding a third carrier wafer to the surface of the first carrier wafer;
[0045] Figure 15 Schematic diagram of bare wafer-to-wafer bonding of an integrated circuit chip bare wafer and a silicon photonic wafer;
[0046] Figure 16 is a schematic diagram of debonding the surface of the first carrier wafer;
[0047] Figure 17 A schematic diagram of packaging an optical interconnect chip bare chip onto a packaging substrate;
[0048] Figure 18 Schematic diagram of plastic encapsulation and heat sinking of the bare integrated circuit chip and the package substrate;
[0049] Figure 19 Schematic diagram of packaging a fiber array connector on an optical interconnect chip. DETAILED DESCRIPTION
[0050] The present application will be further described below with reference to specific embodiments and accompanying drawings. It should be understood that the illustrative embodiments of the present disclosure are intended only to explain the present application and are not intended to limit the present application. In addition, for ease of description, the accompanying drawings only illustrate some, but not all, structures or processes relevant to the present application.
[0051] The following specific embodiments illustrate the implementation of the present application. Those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Although the description of the present application will be introduced in conjunction with the preferred embodiment, this does not mean that the features of this invention are limited to this implementation. On the contrary, the purpose of introducing the invention in conjunction with the implementation is to cover other options or modifications that may be extended based on the claims of this application. In order to provide an in-depth understanding of the present application, the following description will contain many specific details. The present application can also be implemented without using these details. In addition, in order to avoid confusion or blurring the focus of the present application, some specific details will be omitted in the description. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other unless there is a conflict.
[0052] Unless the context dictates otherwise, the terms "comprising," "having," and "including" are synonymous. The phrase "A / B" means "A or B." The phrase "A and / or B" means "(A and B) or (A or B)."
[0053] It should be understood that although the terms "first," "second," and the like may be used herein to describe various components, units, or data, these components, units, or data should not be limited by these terms. These terms are used only to distinguish one feature from another. For example, a first feature may be referred to as a second feature, and similarly, a second feature may be referred to as a first feature without departing from the scope of the exemplary embodiments.
[0054] It should be understood that although directional terms such as "up", "down", "left" and "right" may be used here to describe the positional relationship of each component, these directional terms are only used to indicate the directions in the drawings for the convenience of understanding and cannot be used to limit the scope of protection of this application.
[0055] It should be noted that in this specification, like reference numerals and letters denote similar items in the drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.
[0056] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.
[0057] The present application provides an optical interconnect chip suitable for intra-chip signal transmission and a preparation method thereof, which is integrated through a heterogeneous combination of integrated circuit chip wafers, silicon photonic chip wafers and III-V chip wafers.
[0058] In this application, the optical interconnect chip architecture includes three types of wafers: the first type is integrated circuit chip wafers (such as 8 inches, 12 inches or any size), for example, integrated circuit chips include CPU, GPU, ASIC, FPGA or any type of electronic computing chip; the second type is silicon photonic wafers (such as 8 inches, 12 inches or any size), for example, silicon photonic devices include silicon waveguides, silicon modulators, germanium silicon detectors, silicon gratings, silicon nitride waveguides, and silicon nitride gratings, etc.; the third type is III-V epitaxial wafers (such as 3 inches, 4 inches, 6 inches or any size of GaAs, InP epitaxial wafers), which are used to manufacture light sources, modulators, and detectors and other devices.
[0059] The three types of wafers can be connected through direct bonding or hybrid bonding to support optical and electrical transmission between wafers.
[0060] In this application, the working mechanisms of the three types of wafers are as follows: the integrated circuit chip drives the light source to emit light and / or modulate through electrical interconnection, the light emitted by the light source is coupled to the waveguide through optical interconnection and transmitted to the detector with low loss, and the signal of the detector is transmitted to the electrical chip through electrical interconnection for signal analysis.
[0061] According to the technical solution of the present application, the method for preparing an optical interconnect chip based on silicon and Group III-V compounds comprises the following steps:
[0062] Step S1, preparing active devices and passive devices on a silicon photonic wafer;
[0063] Step S2, preparing at least one III-V epitaxial wafer, and then cutting the III-V epitaxial wafer into III-V epitaxial bare wafers;
[0064] Step S3, performing bare wafer-to-wafer bonding of the III-V epitaxial bare wafer and the silicon photonic wafer;
[0065] Step S4, removing the substrate of the III-V epitaxial bare wafer, retaining the epitaxial structure of the III-V epitaxial bare wafer, and performing wafer-level processing on the epitaxial structure to prepare a III-V device;
[0066] Step S5, preparing first via holes on the active device and the III-V device, and forming metal electrodes;
[0067] Step S6, removing the substrate of the silicon photonic wafer, and preparing a metal interconnection layer on the surface of the silicon photonic wafer from which the substrate is removed, wherein the metal interconnection layer includes a second via hole and a first pad;
[0068] In step S7, the integrated circuit chip bare wafer is bonded to the silicon photonic wafer by bare wafer-to-wafer bonding.
[0069] The following further describes the method for preparing the optical interconnect chip with reference to the accompanying drawings.
[0070] Figure 1 Schematic diagram of preparing silicon photonic wafer. Reference numeral 1 represents the substrate of the silicon photonic wafer, which is preferably an SOI (Silicon-On-Insulator) substrate. Various active and passive devices are prepared using the silicon material of the silicon photonic wafer, including silicon waveguides 2 and 3, a silicon modulator 4, a germanium silicon detector 5, and a silicon grating 6, wherein the germanium silicon detector is prepared by epitaxially growing germanium material on the silicon material. Silicon nitride (SiN) material can also be deposited on the silicon material of the silicon photonic wafer by PECVD (Plasma-Enhanced Chemical Vapor Deposition) or LPCVD (Low-Pressure Chemical Vapor Deposition), and silicon nitride waveguides 7 and 8 and a silicon nitride grating 9 can be prepared using the silicon nitride material, thereby reducing optical loss. After preparing the above active and passive devices, a first dielectric layer 10 is formed on the silicon photonic wafer. The dielectric of the first dielectric layer 10 is preferably highly hydrophilic silicon dioxide, but the present application is not limited to this. The first dielectric layer 10 can also be other hydrophilic thin film layers. The first dielectric layer 10 is then subjected to a surface planarization process to make its surface flat and smooth. The surface planarization process is preferably chemical mechanical polishing (CMP), but the present application is not limited to this. Other suitable methods commonly used in the art can also be used.
[0071] Figure 2Schematic diagram for preparing three different III-V epitaxial wafers. Different III-V epitaxial wafers need to be prepared according to the device type. The III-V epitaxial wafer includes a substrate and a III-V epitaxial structure, wherein the III-V epitaxial wafer 11 is used to prepare a distributed feedback (DFB) laser, the III-V epitaxial wafer 12 is used to prepare an electro-absorption modulator (EAM), and the III-V epitaxial wafer 13 is used to prepare a photodiode (PD) detector. A second dielectric layer 10' is formed on each of the three different III-V epitaxial wafers. The medium of the second dielectric layer 10' is preferably silicon dioxide with strong hydrophilicity, but the present application is not limited thereto. The second dielectric layer may also be other hydrophilic thin film layers. If necessary, the second dielectric layer 10' may also be subjected to surface planarization treatment, such as chemical mechanical polishing.
[0072] Figure 3 Schematic diagram of bare wafer to wafer bonding of III-V epitaxial wafer to silicon photonic wafer. Different III-V epitaxial wafers 11-13 are cut into III-V epitaxial bare wafers (Die), and then the III-V epitaxial bare wafer is bare wafer to silicon photonic wafer for wafer to wafer bonding (Die to Wafer Bonding). Specifically, high-reliability bonding is achieved by performing room-temperature hydrophilic bonding and high-temperature annealing on the second dielectric layer and the first dielectric layer. The III-V epitaxial bare wafer 11 used to prepare the distributed feedback laser is aligned with the silicon nitride waveguide 7 on the silicon photonic wafer, so that the processed distributed feedback laser can be optically coupled with the silicon nitride waveguide 7 through the dielectric layer, thereby transmitting light from the distributed feedback laser to the silicon nitride waveguide 7. Since the silicon thickness of the silicon photonic wafer on the SOI substrate is 220nm, it does not match the mode field of the distributed feedback laser and the coupling efficiency is low. Therefore, in this application, silicon nitride waveguides are preferably used to solve this problem. However, this application is not limited to this. According to needs, silicon nitride waveguides can be aligned with the distributed feedback laser and the silicon waveguide 2 instead of being prepared on the silicon photonic wafer, so as to directly couple the light into the silicon waveguide 2.
[0073] Figure 4 Schematic diagram of removing the substrate of a III-V epitaxial bare wafer. The substrate of the III-V epitaxial bare wafer can be removed by mechanical grinding, wet etching, or other processes, leaving the epitaxial structures 14-16 of the III-V epitaxial bare wafer for fabricating corresponding devices.
[0074] Figure 5Schematic diagram for preparing III-V devices. The epitaxial structures 14-16 of the retained III-V epitaxial bare wafer are respectively processed at the wafer level to prepare a distributed feedback laser 17, an electro-absorption modulator 18, and a photodiode detector 19. Here, wafer-level processing refers to bonding the III-V epitaxial bare wafer to a silicon photonic wafer, that is, reconstructing the III-V epitaxial bare wafer into a part of the silicon photonic wafer, so that III-V device processing can be performed on the basis of a larger silicon photonic wafer, which can increase the number of III-V devices processed at one time and improve production efficiency. Due to the limitations of current production processes, the size of III-V epitaxial wafers is usually 3 inches, 4 inches or 6 inches. Compared with conventional 12-inch silicon photonic wafers, the size of III-V epitaxial wafers is smaller, and the number of III-V devices that can be processed on a III-V epitaxial wafer at one time is relatively small. According to the technical solution of the present application, the III-V epitaxial wafer is cut into III-V epitaxial bare wafers, and then the III-V epitaxial bare wafers are bare-wafer-to-wafer bonded to the silicon photonic wafer. The III-V epitaxial bare wafer can be reconstructed onto a larger-sized silicon photonic wafer for device processing, greatly improving production efficiency.
[0075] Figure 6 Schematic diagram of the vias and multi-metal electrodes used to fabricate active devices and Group III-V devices. First vias 4', 5', 17', 18', and 19' are fabricated on the silicon modulator 4, SiGe detector 5, distributed feedback laser 17, electro-absorption modulator 18, and photodiode detector 19, respectively. Corresponding metal electrodes 4", 5", 17", 18", and 19" are also fabricated to achieve electrical connections. Furthermore, heaters, MIM (Metal-Insulator-Metal) capacitors, and reflectors 20 can also be fabricated using metal materials. Metal materials include tungsten (W), copper (Cu), aluminum (Al), and titanium (Ti).
[0076] Figure 7 Schematic diagram of bonding with the first carrier wafer. A third dielectric layer 21 is formed on the above metal electrodes and devices made of metal materials by a deposition method. The dielectric of the third dielectric layer 21 is preferably silicon dioxide or silicon nitride. The third dielectric layer 21 is bonded to the first carrier wafer 22 by direct bonding (fusion bonding), wherein the material of the first carrier wafer 22 is generally silicon. Figure 7 As shown, the upper portion of the silicon photonic wafer bonded with the III-V epitaxial bare wafer is the first carrier wafer 22 for direct bonding, and the lower portion is the substrate 1 of the silicon photonic wafer.
[0077] Figure 8 Schematic diagram of preparing metal interconnection layer. Figure 8 Middle pair Figure 7The silicon photonic wafer shown is flipped upside down, and the III-V epitaxial bare wafer and the first carrier wafer 22 are located below the silicon photonic wafer. Figure 8 As shown, the substrate 1 of the silicon photonic wafer is removed, and a metal interconnect layer is formed on the surface of the silicon photonic wafer from which the substrate 1 is removed. The metal interconnect layer includes a second via 23 and a first pad 25. On the surface of the silicon photonic wafer from which the substrate 1 is removed, alignment marks 24 can also be formed using metal materials for aligning the silicon grating 6 and / or silicon nitride grating 9.
[0078] Figure 9 Schematic diagram of fabricating a microlens. A microlens 26 can also be fabricated on the surface of the silicon photonic wafer, after substrate 1 has been removed, to converge light introduced by an external optical fiber 27 onto the silicon grating 6 and / or silicon nitride grating 9. Light generated by the laser within the silicon photonic wafer can also be transmitted through the microlens 26 to the external optical fiber 27 via the silicon grating 6 and / or silicon nitride grating 9.
[0079] Figure 10 Schematic diagram of wafer-level chip probe testing. By performing wafer-level chip probe (CP) testing on a silicon photonic wafer bonded with a III-V epitaxial bare wafer, the optical interconnect yield of the chips on the wafer can be tested, so that subsequent integrated circuit chip bare wafer bonding can be performed on the chips that have passed the yield test. When performing wafer-level chip probe testing, the alignment mark 24 on the wafer surface can be used to align the external optical fiber 27. The wafer-level chip probe tests involved in this application include the following tests.
[0080] Laser and modulator testing: The probe 28 of the external test source stimulates an electrical signal on the first pad 25, driving the distributed feedback laser 17 to emit light. The optical signal passes through the silicon nitride waveguides 7 and 8 and enters the electro-absorption modulator 18. The excitation electrical signal of the external test source can also drive the electro-absorption modulator 18 to modulate the light, and is transmitted to the external optical fiber 27 through the waveguide, silicon grating 6 and / or silicon nitride grating 9, and microlens 26, and then converted into an electrical signal for testing.
[0081] Detector test: The externally modulated optical signal passes through the external optical fiber 27, the microlens 26, and the silicon grating 6 and / or the silicon nitride grating 9, and enters the waveguide. The reflector 20 can reduce some of the light loss, thereby transmitting it to the silicon germanium detector 4 or the photodiode detector 19, converting it into an electrical signal, and then transmitting it to the external test equipment via the first pad 25 and the probe 28 for signal analysis.
[0082] System link test: The external electrical signal drives the distributed feedback laser 17 to emit an optical signal through the probe 28 and the first pad 25. The external electrical signal is optically modulated by the electro-absorption modulator 18, passes through the internal waveguide, enters the silicon-germanium detector 4 or the photodiode detector 19, is converted into an electrical signal, and is read out through the probe 29. This test method can use electrical input and output, without the need for external photoelectric conversion, and is suitable for mass production testing.
[0083] Figure 11 Figure 2 is a schematic diagram of forming a first microbump on a first pad. A first microbump 30 is formed on the first pad 25 for subsequent bonding to the bare wafer of the integrated circuit chip. Before forming the first microbump 30 on the first pad 25, the first pad can be redistributed using a redistribution layer (RDL) process. This allows for a more rational distribution of the first pads on the chip surface, enabling more flexible electrical connections.
[0084] Figure 12 Schematic diagram of temporarily bonding a second carrier wafer. A first epoxy resin type material 31 is applied to the surface of the silicon photonic wafer with the substrate 1 removed to fill the gaps, thereby protecting the first pads 25 and the first microbumps 30. Then, a second carrier wafer 32 is temporarily bonded to the first epoxy resin type material 31.
[0085] Figure 13 Schematic diagram of fabricating a third via, a second pad, and a second microbump on a first carrier wafer. First carrier wafer 22 is thinned, and then third vias 33 are fabricated on the thinned first carrier wafer 22. A second pad 34 is fabricated on the surface of first carrier wafer 22 using a redistribution layer process. Second microbumps 35 and 36 are formed on second pad 34. Second microbump 36 is a non-electrically connected microbump used for heat dissipation.
[0086] Figure 14 Schematic diagram of debonding the surface of the silicon photonic wafer with the substrate removed and temporarily bonding the third carrier wafer to the surface of the first carrier wafer. Figure 14 The upper surface of the silicon photonic wafer bonded with the III-V epitaxial bare wafer is debonded to remove the first epoxy resin type material 31 and the second carrier wafer 32, and then the surface of the first carrier wafer 22 ( Figure 14 A second epoxy resin type material 37 is coated on the lower surface of the first carrier wafer 22 in the wafer 20 for filling the gap, thereby protecting the second pads 34 and the second micro bumps 35 and 36, and then a third carrier wafer 38 is temporarily bonded on the second epoxy resin type material 37.
[0087] Figure 15Schematic diagram of bare-wafer bonding of an integrated circuit chip to a silicon photonic wafer. After the fab process and CP test of the integrated circuit wafer are completed, a third micro-bump 40 is formed on the integrated circuit wafer, and then the integrated circuit wafer is cut into integrated circuit chip bare wafers, so that the third micro-bump 40 is formed on the integrated circuit chip bare wafer. An integrated circuit chip bare wafer that can work normally is selected, and one of the bonding methods including flip-chip bonding (Flip-Chip Bonding), thermal compression bonding (TCB, Thermal Compression Bonding), or copper-copper hybrid bonding (Cu-Cu hybrid bonding) is used to bond the integrated circuit chip bare wafer to the silicon photonic wafer through the first micro-bump 30 and the third micro-bump 40. Capillary underfill is performed on the bottom of the integrated circuit chip bare wafer using a first bottom filler 41 for heat dissipation and mechanical support of the integrated circuit chip bare wafer.
[0088] Figure 16 Schematic diagram of debonding the surface of the first carrier wafer. Figure 15 In contrast, Figure 16 FIG. 3 shows debonding the surface of the first carrier wafer 22, removing the second epoxy resin material 37 and the temporarily bonded third carrier wafer 38. Then, the silicon photonic wafer bonded with the III-V epitaxial bare wafer and the integrated circuit chip bare wafer is cut into optical interconnect chip bare wafers.
[0089] Figure 17 This diagram illustrates encapsulating the bare optical interconnect chip onto a packaging substrate. The bare optical interconnect chip is flip-chip mounted onto a packaging substrate 42 using second microbumps 35 and 36. The packaging substrate 42 is preferably made of a ceramic material with improved heat dissipation. A second underfill 43 is applied to the bottom of the bare optical interconnect chip for capillary underfill, providing heat dissipation and mechanical support.
[0090] Figure 18 This diagram illustrates the encapsulation and heat sinking of an integrated circuit chip bare die and a packaging substrate. The bare IC chip and packaging substrate 42 are encapsulated using an encapsulation material 44, such as epoxy resin. Heat sink material 45, such as ceramic or metal, is placed outside the encapsulation material 44 to further enhance heat sinking. The top of the encapsulated optical interconnect chip can be cooled using liquid cooling, while the bottom of the chip is cooled by the packaging substrate 42.
[0091] Figure 19A schematic diagram of the fiber array connector packaged on an optical interconnect chip. Fiber array unit connector 46 is packaged on the optical interconnect chip using alignment marks 24. Fiber array unit connector 46 has a built-in reflector that allows light emitted by horizontally inserted optical fibers 47 to be incident vertically downward into the optical interconnect chip. Fiber array unit connector 46 can be internally configured with various alignment features, such as V-groove alignment, to ensure precise insertion of optical fibers 47.
[0092] The present application also relates to an optical interconnect chip based on silicon and III-V compounds prepared using the above-described preparation method. Figure 1-19 As shown, the optical interconnect chip involved in the present application includes an integrated circuit chip bare wafer, a silicon photonic wafer, and at least one III-V epitaxial bare wafer in sequence. Active devices and passive devices are prepared on the silicon photonic wafer. The III-V epitaxial bare wafer is bare-wafer bonded to the silicon photonic wafer. The substrate of the silicon photonic wafer is removed, and the integrated circuit chip bare wafer is bare-wafer bonded to the silicon photonic wafer with the substrate removed.
[0093] In one embodiment of the optical interconnect chip involved in the present application, the integrated circuit chip bare wafer includes a driving circuit and a detection circuit, the active device includes at least one of a silicon modulator 4 and a silicon germanium detector 5, the passive device includes at least one of silicon waveguides 2 and 3, a silicon grating 6, silicon nitride waveguides 7 and 8, and a silicon nitride grating 9, and the III-V epitaxial bare wafer includes at least one of a distributed feedback laser 17, an electro-absorption modulator 18, and a photodiode detector 19.
[0094] In another embodiment of the optical interconnection chip involved in the present application, first vias 4', 5', 17', 18', and 19' are prepared on the active device and the III-V epitaxial bare wafer, and metal electrodes 4", 5", 17", 18", and 19" are formed. A metal interconnection layer is prepared on the surface of the silicon optical wafer with the substrate removed, and the metal interconnection layer includes a second via 23 and a first pad 25.
[0095] In another embodiment of the optical interconnect chip involved in the present application, alignment marks 24 are prepared on the surface of the silicon optical wafer with the substrate removed, for aligning the silicon grating 6 and / or the silicon nitride grating 9 .
[0096] In another embodiment of the optical interconnect chip involved in the present application, a microlens 26 is prepared on the surface of the silicon optical wafer with the substrate removed, for converging external light onto the silicon grating 6 and / or the silicon nitride grating 9.
[0097] The above are only specific embodiments of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be imagined by any person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. The embodiments of the present application and the features of the embodiments can be combined with each other unless there is a conflict. Therefore, the scope of protection of the present application shall be based on the scope of protection of the claims.
Claims
1. A method for preparing an optical interconnect chip based on silicon and Group III-V compounds, characterized in that: include: Step S1, preparing active devices and passive devices on a silicon photonic wafer; Step S2, preparing at least one III-V epitaxial wafer, and then cutting the III-V epitaxial wafer into III-V epitaxial bare wafers; Step S3, performing bare wafer-to-wafer bonding of the III-V epitaxial bare wafer and the silicon photonic wafer; Step S4, removing the substrate of the III-V epitaxial bare wafer, retaining the epitaxial structure of the III-V epitaxial bare wafer, and performing wafer-level processing on the epitaxial structure to prepare a III-V device; Step S5, preparing first via holes on the active device and the III-V device, and forming metal electrodes; Step S6, removing the substrate of the silicon photonic wafer, and preparing a metal interconnection layer on the surface of the silicon photonic wafer from which the substrate is removed, wherein the metal interconnection layer includes a second via hole and a first pad; Step S7: performing bare wafer-to-wafer bonding of the integrated circuit chip bare wafer and the silicon photonic wafer.
2. The preparation method according to claim 1, wherein The step S1 further includes: forming a first dielectric layer on the silicon photonic wafer; The step S2 further includes: forming a second dielectric layer on the III-V epitaxial wafer; The step S3 further includes: performing surface planarization treatment on at least the first dielectric layer, performing room temperature hydrophilic bonding on the second dielectric layer and the first dielectric layer and then performing high temperature annealing, thereby performing bare wafer-to-wafer bonding on the III-V epitaxial bare wafer and the silicon photonic wafer, The first dielectric layer and the second dielectric layer are silicon dioxide layers or other hydrophilic thin film layers.
3. The preparation method according to claim 1, wherein The step S1 also includes: depositing silicon nitride material on the silicon material of the silicon photonic wafer, and using the silicon material and the silicon nitride material to prepare the active device and the passive device respectively, the active device includes at least one of a silicon modulator and a silicon germanium detector, and the passive device includes at least one of a silicon waveguide, a silicon grating, a silicon nitride waveguide, and a silicon nitride grating.
4. The preparation method according to claim 3, wherein The III-V device includes a distributed feedback laser, an electro-absorption modulator, and a photodiode detector. The distributed feedback laser is aligned with the silicon nitride waveguide and / or silicon waveguide for optical coupling, so that light is guided from the distributed feedback laser into the silicon nitride waveguide and / or silicon waveguide.
5. The preparation method according to claim 1, wherein The step S5 further includes: using metal to prepare at least one of the following devices: a heater, a MIM capacitor, and a reflector.
6. The preparation method according to claim 3, wherein The step S5 also includes: forming a third dielectric layer on the metal electrode, and bonding the third dielectric layer to the first carrier wafer by direct bonding, wherein the third dielectric layer is a silicon dioxide layer or a silicon nitride layer, and the material of the first carrier wafer is silicon.
7. The preparation method according to claim 6, wherein The step S6 also includes: preparing alignment marks on the surface of the silicon optical wafer with the substrate removed using metal for aligning the silicon grating and / or the silicon nitride grating, and preparing microlenses for converging external light onto the silicon grating and / or the silicon nitride grating.
8. The preparation method according to claim 7, wherein The step S6 also includes: forming a first micro-bump on the first pad; coating a first epoxy resin type material on the surface of the silicon photonic wafer with the substrate removed for filling the gap, and then temporarily bonding a second carrier wafer on the first epoxy resin type material; thinning the first carrier wafer, preparing a third via on the first carrier wafer, and using a redistribution layer process to prepare a second pad on the surface of the first carrier wafer, forming a second micro-bump on the second pad, wherein the second micro-bump includes a micro-bump without electrical connection for heat dissipation; debonding the surface of the silicon photonic wafer with the substrate removed, removing the first epoxy resin type material and the second carrier wafer; coating a second epoxy resin type material on the surface of the first carrier wafer for filling the gap, and then temporarily bonding a third carrier wafer on the second epoxy resin type material.
9. The preparation method according to claim 8, wherein The step S6 further includes: redistributing the first pads by using a redistribution layer process before forming the first micro bumps on the first pads.
10. The preparation method according to claim 8, characterized in that The step S7 further includes: forming a third micro-bump on the integrated circuit chip bare wafer, and performing chip bare wafer-to-wafer bonding between the integrated circuit chip bare wafer and the silicon photonic wafer using one of the following bonding methods: flip chip bonding, thermal compression bonding, or copper-copper hybrid bonding.
11. The preparation method according to claim 10, characterized in that The step S7 further includes: performing capillary underfilling on the bottom of the bare integrated circuit chip using a first underfill adhesive for heat dissipation and mechanical support.
12. The preparation method according to claim 10, wherein The step S7 also includes: debonding the surface of the first carrier wafer, removing the second epoxy resin material and the third carrier wafer; cutting the silicon photonic wafer into optical interconnect chip bare wafers, and using the second micro-bumps to flip the optical interconnect chip bare wafers onto the packaging substrate, thereby preparing an optical interconnect chip.
13. The preparation method according to claim 12, wherein The step S7 further includes: performing capillary underfilling on the bottom of the optical interconnect chip bare chip using a second underfill glue for heat dissipation and mechanical support; and performing plastic encapsulation and heat sinking treatment on the integrated circuit chip bare chip and the packaging substrate.
14. The preparation method according to claim 12, wherein The step S7 further includes: packaging the optical fiber array unit connector on the optical interconnection chip using the alignment mark, wherein the optical fiber array unit connector has a built-in reflector, so that horizontally incident light is vertically incident into the optical interconnection chip.
15. An optical interconnect chip based on silicon and III-V compounds, characterized in that: The optical interconnect chip is prepared by the preparation method according to any one of claims 1 to 14.
16. An optical interconnect chip based on silicon and III-V compounds, characterized in that: It includes an integrated circuit chip bare wafer, a silicon photonic wafer, and at least one III-V epitaxial bare wafer in sequence. Active devices and passive devices are prepared on the silicon photonic wafer. The III-V epitaxial bare wafer is bare-wafer-bonded to the silicon photonic wafer. The substrate of the silicon photonic wafer is removed, and the integrated circuit chip bare wafer is bare-wafer-bonded to the silicon photonic wafer with the substrate removed.
17. The optical interconnect chip according to claim 16, wherein: The integrated circuit chip bare wafer includes a driving circuit and a detection circuit, the active device includes at least one of a silicon modulator and a silicon germanium detector, the passive device includes at least one of a silicon waveguide, a silicon grating, a silicon nitride waveguide, and a silicon nitride grating, and the III-V epitaxial bare wafer includes at least one of a distributed feedback laser, an electro-absorption modulator, and a photodiode detector.
18. The optical interconnect chip according to claim 16, wherein: A first via hole is prepared on the active device and the III-V epitaxial bare wafer, and a metal electrode is formed. A metal interconnection layer is prepared on the surface of the silicon photonic wafer with the substrate removed, and the metal interconnection layer includes a second via hole and a first pad.
19. The optical interconnect chip according to claim 17, wherein: Alignment marks are prepared on the surface of the silicon optical wafer with the substrate removed, for aligning the silicon grating and / or the silicon nitride grating.
20. The optical interconnect chip according to claim 17, wherein: A microlens is prepared on the surface of the silicon optical wafer with the substrate removed, for converging external light onto the silicon grating and / or the silicon nitride grating.