Random number generation circuit and system thereof, memory device and memory system

Abstract

The embodiment of the invention provides a random number generation circuit, a random number generation system, a memory device and a memory system. The random number generation circuit includes: a counter including m flip-flops; the clock end of the first trigger of the m triggers is coupled to a clock signal; the output end of one trigger of the m triggers is coupled to the input end of the trigger through the first logic gate and is coupled to the clock end of the next trigger; the linear feedback shift register comprises (n-m) triggers; the clock ends of the (n-m) triggers are coupled to a clock signal; the input end of the first trigger of the (n-m) triggers and the output end of the (n-m) th trigger are coupled to the first input end of each second logic gate; the output end of one trigger of the (n-m) triggers is coupled to the input end of the next trigger through the second input end of a second logic gate; m and n are positive integers, and m is smaller than n.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to, but not limited to, a random number generation circuit and system thereof, a memory device, and a memory system. Background Art

[0002] A linear feedback shift register (LFSR) is a special type of shift register where the current input depends on the previous output. LFSRs are widely used in random number generation, cyclic redundancy check (CRC) calculation, encryption, decryption, and signal modulation. However, the performance of LFSRs for random number generation remains to be improved. Summary of the Invention

[0003] In view of this, embodiments of the present application provide a random number generation circuit and system thereof, a memory device, and a memory system.

[0004] In a first aspect, an embodiment of the present application provides a random number generating circuit, which comprises: a counter, comprising m flip-flops; the clock terminal of the first flip-flop of the m flip-flops is coupled to a clock signal; the output terminal of one flip-flop of the m flip-flops is coupled to its input terminal through a first logic gate, and is coupled to the clock terminal of the next flip-flop; a linear feedback shift register, comprising (nm) flip-flops; the clock terminal of the (nm) flip-flops is coupled to the clock signal; the input terminal of the first flip-flop of the (nm) flip-flops and the output terminal of the (nm)th flip-flop are coupled to the first input terminal of each second logic gate; the output terminal of one flip-flop of the (nm) flip-flops is coupled to the input terminal of the next flip-flop through the second input terminal of a second logic gate; m and n are both positive integers, and m is less than n; wherein, the output of the random number generating circuit comprises n bits from the least significant bit to the most significant bit; the least significant bit is based on the current clock cycle state of the m flip-flops of the counter; the most significant bit is based on the current clock cycle state of the (nm) flip-flops of the linear feedback shift register.

[0005] In some embodiments, the output terminals of the first to mth flip-flops of the counter output the least significant bits 0 to (m-1) respectively; the output terminal of one of the m flip-flops is connected to the input terminal of an inverter, and the output terminal of an inverter is connected to the input terminal of a flip-flop and to the clock terminal of the next flip-flop.

[0006] In some embodiments, the output terminals of the first to the (nm)th triggers of the linear feedback shift register output the most significant bits 0 to (nm-1) respectively; the input terminals of the first trigger of the (nm)th trigger and the output terminal of the (nm)th trigger are connected to the first input terminal of each XOR gate; the output terminal of a trigger of the (nm)th trigger is connected to the second input terminal of an XOR gate, and the output terminal of the XOR gate is connected to the input terminal of the next trigger.

[0007] In some embodiments, the data generated by the m flip-flops of the counter and the data generated by the (nm) flip-flops of the linear feedback shift register have a greatest common divisor of 1.

[0008] In some embodiments, the random number generation circuit is configured to generate a target value after k clock cycle states; wherein k is a positive integer less than or equal to 3; and the target value is less than a preset threshold.

[0009] In some embodiments, the data generated by the m flip-flops of the counter are repeated through 2 m status.

[0010] In some embodiments, the data generated by the m flip-flops of the counter range from 0 to 2 m -1.

[0011] In some embodiments, the data generated by the (nm) flip-flops of the linear feedback shift register are repeatedly passed through 2 (n -m) -1 status.

[0012] In some embodiments, the data generated by the (nm) flip-flops of the linear feedback shift register ranges from 0 to 2 (n-m) -2.

[0013] In some embodiments, the flip-flop comprises a D flip-flop.

[0014] In a second aspect, an embodiment of the present application provides a random number generation system, comprising: any one of the random number generation circuits of the first aspect, configured to generate a target value based on a clock cycle state; a comparator, configured to determine whether the target value is less than a preset threshold; based on the target value being less than the preset threshold, using the target value as an output of the random number generation system; and based on the target value being greater than or equal to the preset threshold, enabling a pulse generation circuit, configured to generate an enable pulse; the enable pulse serving as an input to the random number generation system, and configured to enable the random number generation circuit to generate the target value.

[0015] In a third aspect, an embodiment of the present application provides a memory device comprising a memory cell array and a peripheral circuit coupled to the memory cell array; wherein the peripheral circuit comprises the random number generation system of the second aspect; the random number generation system is configured to generate an address to detect and / or mitigate a row hammering effect on the memory device.

[0016] In some embodiments, the memory device includes dynamic random access memory.

[0017] In a fourth aspect, an embodiment of the present application provides a memory system, comprising: a memory device comprising a memory cell array and a peripheral circuit coupled to the memory cell array; a memory controller coupled to the memory device and comprising the random number generation system of the second aspect; the random number generation system is configured to generate an address; and the memory device is configured to receive the address to detect and / or mitigate a row hammering effect on the memory device.

[0018] In each embodiment of the present application, a random number generation circuit includes a counter and a linear feedback shift register, which are connected to a clock signal. The output of the counter constitutes m least significant bits out of n bits, and the output of the linear feedback shift register constitutes (nm) most significant bits out of n bits. The output of the counter and the output of the linear feedback shift register are combined to obtain n-bit output data. The random number generation circuit is configured to generate a random number (or target value) that meets the requirements, which can reduce the number of triggers and obtain the required random number in a shorter time. The logic overhead of the counter is less than the logic overhead of the linear feedback shift register, which can reduce the logic overhead of the random number generation circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram of a first random number generation system provided in an embodiment of the present application;

[0020] Figure 2 for Figure 1 The circuit generates random numbers corresponding to the timing diagram;

[0021] Figure 3 for Figure 1 A schematic diagram of an exemplary random number generated by a circuit;

[0022] Figure 4 A schematic diagram of a first random number generation circuit provided in an embodiment of the present application;

[0023] Figure 5 for Figure 4 Schematic diagram of the counter in the circuit;

[0024] Figure 6 for Figure 4Schematic diagram of the linear feedback shift register in the circuit;

[0025] Figure 7 for Figure 4 A schematic diagram of an exemplary random number generated by a circuit;

[0026] Figure 8 A schematic diagram of all data of the 3 least significant bits generated by the ergodic counter and the 3 most significant bits generated by the linear feedback shift register provided in an embodiment of the present application;

[0027] Figure 9 A schematic diagram of a second random number generation circuit provided in an embodiment of the present application;

[0028] Figure 10 A schematic diagram of all data of the 3 least significant bits generated by the linear feedback shift register and the 3 most significant bits generated by the counter provided in an embodiment of the present application;

[0029] Figure 11 A schematic diagram of a third random number generation circuit provided in an embodiment of the present application;

[0030] Figure 12 A schematic diagram of a second random number generation system provided in an embodiment of the present application;

[0031] Figure 13 A schematic diagram of a memory cell in a memory cell array of a DRAM provided in an embodiment of the present application;

[0032] Figure 14 A schematic diagram of a control circuit for a DRAM memory cell array provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] The following will be combined with the embodiments of this application and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0034] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0035] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0036] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. And when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part is present in the present application.

[0037] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0038] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, identify the presence of features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0039] In order to fully understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may also have other implementation methods.

[0040] The behavior of LFSR can be described by a characteristic polynomial, which is a binary polynomial whose degree is equal to the number of bits of the LFSR. Each term in the characteristic polynomial corresponds to a feedback point, with a coefficient of 1 indicating feedback and 0 indicating no feedback. The characteristic polynomial can not only determine the period of the LFSR, but can also be used to calculate the next vector sequence. LFSR is used to generate random numbers. For example, an n-bit LFSR has a total of 2 n -1 state, whose numerical sequence is determined by the characteristic polynomial used.

[0041] Row Hammer is a security vulnerability discovered in memory, such as dynamic random access memory (DRAM). It exploits the unexpected electrical interactions caused by high-density memory cells, allowing frequent accesses to one row of memory to affect the contents of adjacent rows, or even change the data in adjacent rows—a form of unaddressed data tampering.

[0042] In memory products (such as DRAM), row hammering is becoming increasingly prominent as process geometries shrink. For data security reasons, algorithms are being applied to repair row hammer (RHR). In this case, LFSR can be used in row hammer repair algorithms.

[0043] The LFSR output is pseudorandom because the sequence of values ​​produced is both deterministic and repeatable. Given a sufficiently large LFSR (i.e., one formed with a sufficient number of storage bits) and a sufficiently long sequence of values ​​before the LFSR repeats, the LFSR appears to be generating random numbers. For clarity, the terms "pseudorandom" and "random" are used interchangeably herein to refer to the output of a random number generating circuit.

[0044] Figure 1 This is a schematic diagram of the first random number generation system provided in the embodiment of the present application. Figure 1 As shown, the random number generation system includes n bits (i.e. <n-1:0>)LFSR, comparator, OR gate, flip-flop, and delay element. The output of the n-bit LFSR is connected to the first input of the comparator. The second input of the comparator is coupled to a reference signal (signal B). The output of the comparator is connected to the input of the flip-flop. The output of the flip-flop is connected to the input of the delay element and the input of the n-bit LFSR. The output of the delay element is connected to the second input of the OR gate. The first input of the OR gate is coupled to a clock signal (signal CLK). The output of the OR gate is connected to the clock input of the flip-flop. The output of the n-bit LFSR outputs signal A. The value of signal A is the target random number. If the value of signal A is less than the value of signal B, then the values that meet the requirements are selected from the original numerical sequence of the n-bit LFSR, and those that do not meet the requirements are filtered out. By continuously generating a number of pulses, the signal Y received at the input of the n-bit LFSR is continuously triggered several times, thereby switching the value of signal A until the value of signal A is less than the value of signal B.

[0045] However, memory, such as DRAM, is a high-speed product. If an n-bit LFSR is used, to obtain a signal A that meets the requirements, the number of continuous triggers of the signal Y received at the input of the n-bit LFSR is limited by time. For example, a relatively large number of trigger times or a relatively long time is required to obtain a random number that meets the requirements.

[0046] Figure 2 For Figure 1 the circuit that generates random numbers, the corresponding timing diagram is as follows. As Figure 1 and Figure 2 shown, signal CLK is the start signal, and it is expected to obtain a random number (the value of signal A) with a value of signal B in each clock cycle. It can be seen that when the value of signal A is greater than or equal to the value of signal B (A1, A2, A n-1 ≥B, or, C1, C2, C m-1 ≥B), signal Y will be triggered until the value of signal A is less than the value of signal B (A n <B, or, C m <B), and the value of A n or C m is the desired random number. Then, the entire process takes a time duration of T2, and the period of signal CLK is a time duration of T1, where T1 is less than T2 (T1 < T2). If T2 is greater than T1 (T2 > T1), then it means that the current operation will have problems and affect the operation of the next clock cycle.

[0047] Figure 3 For Figure 1 the circuit, the schematic diagram of the exemplary random numbers generated is as follows. As Figure 3 As shown in the figure, taking a 7-bit LFSR as an example, assuming the value of signal B is 70, the 7-bit LSFR needs to be triggered at most six times in a row to reach a random number that meets the requirements (the value "63" or "31"). The 7-bit LSFR needs to be triggered at most six times in a row to generate the values ​​"126", "125", "123", "119", "111", and "95" before the value "63" is smaller than the value "70". The 7-bit LSFR needs to be triggered five times in a row to generate the values ​​"124", "121", "115", "103", and "79" before the value "31" is smaller than the value "70".

[0048] In view of this, embodiments of the present application provide a random number generation circuit and system thereof, a memory device, and a memory system. The random number generation circuit is configured to generate a random number (or target value) that meets requirements, thereby reducing the number of triggers, obtaining the required random number in a shorter time, and achieving rapid output of the target random number with minimal logic overhead.

[0049] Figure 4 A schematic diagram of a first random number generation circuit provided in an embodiment of the present application. Figure 5 for Figure 4 Schematic diagram of the counter in the circuit. Figure 6 for Figure 4 Schematic diagram of the linear feedback shift register in the circuit. Figure 7 for Figure 4 Schematic diagram of an exemplary random number generated by a circuit.

[0050] In the first aspect, the embodiment of the present application is a random number generating circuit, referring to Figure 4 、 Figure 5 and Figure 6 , the random number generation circuit 102 includes: a counter 202, including m flip-flops; the clock terminal of the first flip-flop of the m flip-flops is coupled to the clock signal CLK; the output terminal of one flip-flop of the m flip-flops is coupled to its input terminal through a first logic gate, and is coupled to the clock terminal of the next flip-flop; a linear feedback shift register 302, including (nm) flip-flops; the clock terminal of the (nm) flip-flops is coupled to the clock signal CLK; the input terminal of the first flip-flop of the (nm) flip-flops and the output terminal of the (nm)-th flip-flop are coupled to the first input terminal of each second logic gate; the output terminal of one flip-flop of the (nm) flip-flops is coupled to the input terminal of the next flip-flop through the second input terminal of a second logic gate; m and n are both positive integers, and m is less than n; wherein, the output of the random number generation circuit includes n bits from the least significant bit to the most significant bit; the least significant bit is based on the current clock cycle state of the m flip-flops of the counter; the most significant bit is based on the current clock cycle state of the (nm) flip-flops of the linear feedback shift register. In an embodiment of the present application, a random number generation circuit includes a counter and a linear feedback shift register, which are connected to a clock signal. The output of the counter constitutes m least significant bits out of n bits, and the output of the linear feedback shift register constitutes (nm) most significant bits out of n bits. The output of the counter and the output of the linear feedback shift register are combined to obtain n-bit output data. The random number generation circuit is configured to generate a random number (or target value) that meets the requirements, which can reduce the number of triggers and obtain the required random number in a shorter time. The logic overhead of the counter is less than the logic overhead of the linear feedback shift register, which can reduce the logic overhead of the random number generation circuit.

[0051] refer to Figure 5 In some embodiments, the output terminals of the first to the mth flip-flops of the counter 202 output the least significant bits 0 to (m-1) respectively; the output terminal of one of the m flip-flops is connected to the input terminal of an inverter, and the output terminal of the inverter is connected to the input terminal of a flip-flop and to the clock terminal of the next flip-flop.

[0052] like Figure 5 As shown, the output terminals of the first flip-flop 204_1 to the m-th flip-flop 204_m are respectively connected to the input terminals of the NOT gate 206_1 to the NOT gate 206_m, the output terminals of the NOT gate 206_1 to the NOT gate 206_m are respectively connected to the input terminals of the first flip-flop 204_1 to the m-th flip-flop 204_m, and the input terminals of the NOT gate 206_1 to the NOT gate 206_m-1 are respectively connected to the clock terminals of the second flip-flop 204_2 to the m-th flip-flop 204_m; the clock terminal of the first flip-flop 204_1 is coupled to the clock signal CLK; the output terminals of the first flip-flop 204_1 to the m-th flip-flop 204_m respectively output the signal P <0> To signal P <m-1>Signal P <0> To signal P <m-1>The values ​​of are taken as the least significant bits 0 to (m-1), that is, <m-1:0>.

[0053] In some embodiments, the data generated by the m flip-flops of the counter 202 are repeated through 2 m status.

[0054] In some embodiments, the data generated by the m flip-flops of the counter 202 range from 0 to 2. m -1 or 1 to 2 m .

[0055] refer to Figure 6 In some embodiments, the output terminals of the first to the (nm)th flip-flops of the linear feedback shift register 302 output the most significant bits 0 to (nm-1) respectively; the input terminal of the first flip-flop of the (nm)th flip-flop and the output terminal of the (nm)th flip-flop are connected to the first input terminal of each exclusive OR gate; the output terminal of a flip-flop of the (nm)th flip-flop is connected to the second input terminal of an exclusive OR gate, and the output terminal of the exclusive OR gate is connected to the input terminal of the next flip-flop.

[0056] like Figure 6 As shown, the output terminals of the first flip-flop 304_1 to the (nm-1)th flip-flop 304_n-m-1 are respectively connected to the second input terminals of the XOR gates 306_1 to the XOR gates 306_n-m-1, and the output terminals of the XOR gates 306_1 to the XOR gates 306_n-m-1 are respectively connected to the input terminals of the second flip-flop 304_2 to the (nm)th flip-flop 304_n-m; the input terminal of the first flip-flop 304_1 and the output terminal of the (nm)th flip-flop 304_n-m are both connected to the first input terminals of the XOR gates 306_1 to the XOR gates 306_n-m-1; the clock terminals of the first flip-flop 304_1 to the (nm-1)th flip-flop 304_n-m are all coupled to the clock signal CLK; the output terminals of the first flip-flop 304_1 to the (nm-1)th flip-flop 304_n-m respectively output the signal P <m>To signal P <n-1>Signal P <m>To signal P <n-1>The values ​​of are taken as the most significant bits 0 to (nm-1), that is, <n-m-1:0>.

[0057] In some embodiments, the data generated by the (nm) flip-flops of the linear feedback shift register 302 are repeatedly passed through 2 (n-m) -1 status.

[0058] In some embodiments, the data generated by the (nm) flip-flops of the linear feedback shift register 302 range from 0 to 2 (n-m) -2 or 1 to 2 m -1.

[0059] In the case of the same number of flip-flops, since the logic overhead of the NOT gate is less than that of the XOR gate, the logic overhead of the counter is less than that of the linear feedback shift register. Figure 1 The random number generation circuit (n-bit LFSR) shown in the embodiment of the present application can reduce logic overhead and achieve rapid output of the target random number with less logic overhead.

[0060] refer to Figure 7 In some embodiments, the random number generation circuit is configured to generate a target value after k clock cycle states; wherein k is a positive integer less than or equal to 3; and the target value is less than a preset threshold.

[0061] like Figure 7 As shown, taking the output of the random number generation circuit 102 including 7 bits as an example, and the preset threshold value is 70, the random number generation circuit 102 needs to be triggered at most three times in a row (understood as passing through three clock cycles) to achieve a random number that meets the requirements (the value "60" or "31"). The random number generation circuit 102 needs to be triggered at most three times in a row to generate the values ​​"113", "106", and "91" to obtain the value "60", which is smaller than the value "70". The random number generation circuit 102 needs to be triggered at most two times in a row to generate the values ​​"101" and "78" to obtain the value "31", which is smaller than the value "70".

[0062] Compared to Figure 1 The random number generating circuit (n-bit LFSR) shown in FIG. Figure 3 ), the random number generating circuit provided by the embodiment of the present application (reference Figure 4 ) can reduce the number of triggers and obtain the required random number in a shorter time (refer to Figure 7 ).

[0063] In some embodiments, the data generated by the m flip-flops of the counter and the data generated by the (nm) flip-flops of the linear feedback shift register have a greatest common divisor of 1.

[0064] In this way, the random number generating circuit is configured to be able to traverse all data, that is, to traverse the data range from 0 to [2 (n-m) -1]ⅹ2 m -1 or 1 to [2 (n-m) -1]ⅹ2 m .

[0065] Figure 8 A schematic diagram of all data of the 3 least significant bits generated by the ergodic counter and the 3 most significant bits generated by the linear feedback shift register provided in an embodiment of the present application. Figure 8 The data sequence shown is from left to right and from top to bottom. For example, the data sequence generated by the counter or linear feedback shift register is the first row of data from left to right, the third row of data, ... the fifteenth row of data from left to right, a total of 64 data.

[0066] refer to Figure 8 Taking the example of a 6-bit output from random number generation circuit 102, the 3 least significant bits of data generated by the counter are referred to as the lower 3-bit counter (or 3-bit counter); the 3 most significant bits of data generated by the linear feedback shift register are referred to as the upper 3-bit linear feedback shift register (or 3-bit linear feedback shift register). The data range generated by the lower 3-bit counter is 0 to 7, meaning that the data generated by the lower 3-bit counter has a cycle of 8 data. The data range generated by the upper 3-bit linear feedback shift register is 0 to 6, meaning that the data generated by the upper 3-bit linear feedback shift register has a cycle of 7 data. The random number generation circuit needs to be triggered 56 times to traverse the data range of 0 to 55, meaning that it can traverse all data in a cycle of 56 data.

[0067] Figure 9 A schematic diagram of a second random number generation circuit provided in an embodiment of the present application. Figure 9 The linear feedback shift register 602 in the random number generating circuit 502 can refer to Figure 6 The linear feedback shift register 302 is shown. Figure 9 The counter 702 in the random number generating circuit 502 shown can refer to Figure 5 Counter 202 is shown.

[0068] Figure 10 A schematic diagram of all data provided by an embodiment of the present application that traverses the 3 least significant bits generated by a linear feedback shift register and the 3 most significant bits generated by a counter. Figure 10 The order of data shown is from left to right and from top to bottom.

[0069] refer to Figure 9 and Figure 10 Taking 6 bits as an example, the 3 least significant bits of data generated by the linear feedback shift register are called the lower 3-bit linear feedback shift register (or 3-bit linear feedback shift register); the 3 most significant bits of data generated by the counter are called the higher 3-bit counter (or 3-bit counter). Figure 6 Based on the circuit shown in FIG, additional logic overhead is required to increase the data range generated by the lower 3-bit linear feedback shift register from 0 to 6 to 0 to 7. The data generated by the lower 3-bit linear feedback shift register is 8 data as a cycle. Figure 5 Based on the circuit shown, the upper 3-bit counter does not have additional logic overhead, and the data generated by the upper 3-bit counter is a cycle of 8 data. Figure 10 As shown, because the greatest common divisor between the data generated by the lower 3-bit linear feedback shift register and the data generated by the upper 3-bit counter is no longer 1, the random number generation circuit cannot traverse all the data.

[0070] If the lower 3 bits do not make additional logic overhead for the linear feedback shift register, the data range generated by the lower 3 bits of the linear feedback shift register is still 0 to 6, so that the data generated by the lower 3 bits of the linear feedback shift register is 7 data as a cycle. Then the data range formed by combining the 3 least significant bits of data generated by the lower 3 bits of the linear feedback shift register and the 3 most significant bits of data generated by the upper 3 bits of the counter is discontinuous. There will be data missing (in this case Figure 10 not shown).

[0071] Figure 11 A schematic diagram of a third random number generation circuit provided in an embodiment of the present application. Figure 11 The random number generating circuit shown can be understood as Figure 9 The random number generation circuit shown is based on an embodiment that does not have additional logic overhead.

[0072] like Figure 11 As shown, in Figure 9 Based on the random number generation circuit shown, additional logic overhead is added to the counter, for example, a logic comparator and corresponding timing control circuit are added. The input of logic comparator 704 is coupled to the output of counter 702, and the output of logic comparator 704 is coupled to the control terminal of counter 702. Logic comparator 704 is configured to output a Reset signal to control the timing of counter 702, so that the data generated by counter 702 ranges from 0 to 6. That is, the data generated by the counter has a cycle of 7 data, so that the greatest common divisor of the data generated by the linear feedback shift register and the data generated by the counter is 1.

[0073] In some embodiments, the flip-flop includes a D flip-flop (Data Flip-Flop, DFF). In alternative embodiments, the flip-flop includes an RS flip-flop, a JK flip-flop, or a T flip-flop.

[0074] Figure 12 A schematic diagram of a second random number generation system provided in an embodiment of the present application.

[0075] In the second aspect, the embodiment of the present application provides a random number generation system, referring to Figure 12 The random number generation system 100 includes: any one of the random number generation circuits 102 of the first aspect, configured to generate a target value 102A based on a clock cycle state; a comparator 104, configured to determine whether the target value 102A is less than a preset threshold 102B; based on the target value 102A being less than the preset threshold 102B, using the target value 102A as an output of the random number generation system; and based on the target value 102A being greater than or equal to the preset threshold 102B, an enabling pulse generating circuit 106, configured to generate an enabling pulse 102Y; the enabling pulse 102Y being an input of the random number generation circuit 102, and configured to enable the random number generation circuit 102 to generate the target value 102A.

[0076] The specific details of the random number generating circuit 102 in the embodiment of the present application can be understood by referring to the various implementations of the first aspect, and will not be repeated here.

[0077] In the embodiment of the present application, the value of the target value 102A is a target random number. The value of the target value 102A must be smaller than the value of the preset threshold value 102B. By continuously generating a number of pulses, the enable pulse 102Y received by the input end of the random number generating circuit 102 is continuously triggered several times, thereby switching the value of the target value 102A until the value of the target value 102A is smaller than the value of the preset threshold value 102B.

[0078] Compared to Figure 1 The random number generation system shown in the embodiment of the present application can reduce the number of triggers, obtain the required random number in a shorter time, and achieve rapid output of the target random number with less logic overhead.

[0079] like Figure 12 As shown, the random number generation circuit system 100 includes a random number generation circuit 102, a comparator 104, and an enable pulse generation circuit 106. The output of the random number generation circuit 102 is connected to a first input of the comparator 104, a second input of the comparator 104 is coupled to a reference signal (preset threshold 102B), the output of the comparator 104 is connected to an input of the enable pulse generation circuit 106, and the output of the enable pulse generation circuit 106 is connected to an input of the random number generation circuit 102.

[0080] In some embodiments, the enable pulse generation circuit 106 includes an OR gate 1062, a flip-flop 1064, and a delay 1066. The output of the comparator 104 is connected to the input of the flip-flop 1064, the output of the flip-flop 1064 is connected to the input of the delay 1066 and the input of the random number generation circuit 102, the output of the delay 1066 is connected to the second input of the OR gate 1062, the first input of the OR gate 1062 is coupled to the clock signal CLK, and the output of the OR gate 1062 is connected to the clock terminal of the flip-flop 1064.

[0081] In a third aspect, an embodiment of the present application provides a memory device comprising a memory cell array and a peripheral circuit coupled to the memory cell array; wherein the peripheral circuit comprises the random number generation system of the second aspect; the random number generation system is configured to generate an address to detect and / or mitigate a row hammering effect on the memory device.

[0082] In some embodiments, the peripheral circuit includes a row decoder, which may include one or more random number generation systems to generate random sampling signals. The memory device is configured to use the random sampling signals to sample row addresses to be used for detecting and / or mitigating row hammering effects.

[0083] In some embodiments, the memory device may be a random access memory (RAM). Random access memory may include, for example, dynamic random access memory (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), double data rate SDRAM (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, phase change RAM (PRAM), magnetic RAM (MRAM), or resistive RAM (RRAM). In some embodiments, multiple memory devices may constitute a high bandwidth memory (HBM) DRAM. For example, four stacked memory devices constitute a high bandwidth memory DRAM; optionally, the number of multiple memory devices in the high bandwidth memory DRAM is less than or greater than any number of four layers.

[0084] In some embodiments, the memory device includes a DRAM. The control logic of the DRAM can independently access each memory cell in a memory cell array of the DRAM and perform read, write, or refresh operations on the data stored therein.

[0085] Figure 13 Schematic diagram of a memory cell in a memory cell array of a DRAM provided in an embodiment of the present application. Figure 13 As shown, the drain of the transistor T is electrically connected to the bit line BL (Bite Line), the source of the transistor T is electrically connected to one of the electrode plates of the capacitor C, the other electrode plate of the capacitor C is grounded through the ground terminal GND (Ground), and the gate of the transistor T is connected to the word line WL (Word Line); a voltage is applied through the word line WL to control the transistor T to be turned on or off, and the bit line BL is used to perform a read or write operation on the transistor T when the transistor T is turned on.

[0086] Figure 14 This is a schematic diagram of a control circuit for a DRAM memory cell array provided in an embodiment of the present application. Figure 14 As shown, the drains of multiple transistors T are electrically connected to a row address strobe pulse RAS (Row Address Strobe, RAS), the sources of transistors T are electrically connected to one electrode plate of capacitor C, the other electrode plate of capacitor C is grounded via a ground terminal GND (Ground), and the gates of multiple transistors T are connected to a column address strobe pulse CAS (Column Address Strobe, CAS). The row address strobe pulse RAS applies a voltage to control whether transistors T are turned on or off, and the column address strobe pulse CAS is used to perform a read or write operation on the transistors T when the transistors T are turned on. The address associated with RAS is a row address, and the address associated with CAS is a column address. In DRAM, a data bit is stored in the cell at the intersection of the column address and the row address, and CAS makes the column address valid.

[0087] In a fourth aspect, an embodiment of the present application provides a memory system, comprising: a memory device comprising a memory cell array and a peripheral circuit coupled to the memory cell array; a memory controller coupled to the memory device and comprising the random number generation system of the second aspect; the random number generation system is configured to generate an address; and the memory device is configured to receive the address to detect and / or mitigate a row hammering effect on the memory device.

[0088] In some embodiments, the random number generation system is configured to generate a row address; and the memory device is configured to receive the row address to detect and / or mitigate a row hammering effect on the memory device.

[0089] In some embodiments, a memory controller is coupled to a memory device and configured to control operations of the memory device, such as read or write operations. In some embodiments, the memory controller may include, for example, a central processing unit (CPU), a digital signal processor (DSP), a field programmable gate array (FPGA), a microcontroller unit (MCU), or an application-specific integrated circuit (ASIC).

[0090] In some embodiments, the memory device includes a DRAM (eg, an LPDD DRAM). The control logic of the DRAM can independently access each memory cell in a memory cell array of the DRAM and perform read, write, or refresh operations on the data stored therein.

[0091] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0092] The above description is only a preferred embodiment of the present application and does not limit the scope of protection of the present application. All equivalent structural transformations made using the contents of the present application description and drawings under the inventive concept of the present application, or direct / indirect application in other related technical fields are included in the scope of protection of the present application. < / m> < / m>

Claims

1. A random number generating circuit, characterized in that: include: A counter comprising m flip-flops; a clock terminal of a first flip-flop of the m flip-flops being coupled to a clock signal; The output terminal of one of the m flip-flops is coupled to its input terminal through a first logic gate, and is coupled to the clock terminal of the next flip-flop; A linear feedback shift register, comprising (nm) flip-flops; clock terminals of the (nm) flip-flops are coupled to the clock signal; an input terminal of a first flip-flop of the (nm) flip-flops and an output terminal of the (nm)th flip-flop are coupled to a first input terminal of each second logic gate; an output terminal of one of the (nm) flip-flops is coupled to an input terminal of a next flip-flop through a second input terminal of the second logic gate; m and n are both positive integers, and m is less than n; wherein the output of the random number generating circuit comprises n bits from the least significant bit to the most significant bit; the least significant bit is based on the current clock cycle state of the m flip-flops of the counter; The most significant bit is based on a current clock cycle state of the (nm) flip-flops of the linear feedback shift register.

2. The random number generating circuit according to claim 1, wherein: Output terminals of the first to the m-th flip-flops of the counter respectively output the least significant bits 0 to (m-1); An output terminal of one of the m flip-flops is connected to an input terminal of an inverter, and an output terminal of the inverter is connected to an input terminal of one of the flip-flops and to a clock terminal of the next flip-flop.

3. The random number generating circuit according to claim 1, wherein: Output terminals of the first to the (nm)th flip-flops of the linear feedback shift register respectively output the most significant bits (0) to (nm-1); The input terminal of the first of the (nm) triggers and the output terminal of the (nm)th trigger are connected to the first input terminal of each XOR gate; the output terminal of one of the (nm) triggers is connected to the second input terminal of an XOR gate, and the output terminal of an XOR gate is connected to the input terminal of the next trigger.

4. The random number generating circuit according to claim 1, wherein: The data generated by the m flip-flops of the counter and the data generated by the (nm) flip-flops of the linear feedback shift register have a greatest common divisor of 1.

5. The random number generating circuit according to claim 1, wherein: The random number generating circuit is configured to generate a target value after k clock cycle states; wherein k is a positive integer less than or equal to 3; and the target value is less than a preset threshold.

6. The random number generating circuit according to claim 1, wherein: The data generated by the m flip-flops of the counter are repeated through 2 m status.

7. The random number generating circuit according to claim 6, wherein: The data generated by the m flip-flops of the counter range from 0 to 2 m -1 or 1 to 2 m .

8. The random number generating circuit according to claim 1, wherein: The data generated by the (nm) flip-flops of the linear feedback shift register are repeatedly passed through 2 (n-m) -1 status.

9. The random number generating circuit according to claim 8, wherein: The data range generated by the (nm) flip-flops of the linear feedback shift register is 0 to 2 (n-m) -2 or 1 to 2 m -1.

10. The random number generating circuit according to claim 1, wherein: The flip-flop includes a D flip-flop.

11. A random number generation system, characterized in that: include: The random number generating circuit according to any one of claims 1 to 10, configured to generate a target value based on a clock cycle state; a comparator configured to determine whether the target value is less than a preset threshold; Based on the target value being less than the preset threshold, taking the target value as the output of the system; as well as Based on the target value being greater than or equal to the preset threshold, an enabling pulse generating circuit is configured to generate an enabling pulse; The enable pulse serves as an input to the system and is configured to enable the random number generation circuit to generate the target value.

12. A memory device, characterized in that: comprising a memory cell array and a peripheral circuit coupled to the memory cell array; The peripheral circuit comprises the random number generation system according to claim 11; the random number generation system is configured to generate addresses to detect and / or mitigate row hammering effects on the memory device.

13. The memory device according to claim 12, wherein: The memory device includes a dynamic random access memory.

14. A memory system, characterized in that: include: A memory device comprising a memory cell array and a peripheral circuit coupled to the memory cell array; a memory controller coupled to the memory device, comprising the random number generation system of claim 11; The random number generation system is configured to generate an address; as well as The memory device is configured to receive the address to detect and / or mitigate row hammering on the memory device.

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