High-security configuration method and configuration system for FPGA (Field Programmable Gate Array) chip
By controlling the configuration port signal and increasing disturbance during the configuration process of the FPGA chip, the security problem of FPGA chips under side channel attacks in the existing technology is solved, low-cost and efficient security configuration is achieved, and the protection capability is improved.
Patent Information
- Application Number
- CN202510666348.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-22
- Publication Date
- 2025-09-26
AI Technical Summary
Existing SRAM-type FPGA chips are difficult to effectively protect against security threats when facing side-channel attacks, and existing protection methods are costly and difficult to apply in practical engineering.
By controlling the configuration port signal during the configuration process of the FPGA chip, adding disturbances, using random or preset signal intervals and duration changes, and changing the signal transmission strategy of the configuration port, secure configuration is achieved.
Without modifying the circuit or configuration logic, the security of the FPGA chip configuration process is improved, the cost is reduced, and the protection capability against side-channel attacks is improved, making it difficult to be cracked by reverse engineering.
Smart Images
Figure CN120705922A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of chip security technology, and in particular to a high-security configuration method and configuration system for an FPGA chip. Background Art
[0002] As key components in electronic systems, SRAM-based FPGAs pose severe information security challenges if they are compromised by inherent security vulnerabilities or external attacks. For many years, SRAM-based FPGAs have employed encryption and decryption algorithms to safeguard configuration data and user designs. However, these algorithms are not foolproof and are susceptible to non-invasive attacks such as side-channel attacks, posing the risk of user design data leakage.
[0003] Existing side-channel protection methods typically employ methods such as masking, obfuscation, internal authentication, and round keys. However, these methods require significant circuit modifications or software logic configuration, resulting in high costs and difficulty in practical engineering applications in FPGA chip design. Summary of the Invention
[0004] The technical problem solved by the present invention is to overcome the shortcomings of the existing technology and provide a high-security configuration method and configuration system for FPGA chips that can be used in practical engineering applications. During the configuration process of the FPGA chip, a secure configuration strategy is implemented by controlling the configuration port signal, thereby improving the security of the configuration process at an extremely low cost.
[0005] The technical solution of the present invention is: a high-security configuration method for FPGA chips, comprising:
[0006] Get the configuration code stream of the target FPGA chip;
[0007] Determine a security configuration strategy; the security configuration strategy is determined according to the configuration mode selected by the target FPGA chip, and according to the configuration ports involved in the selected configuration mode, selectively and periodically adds disturbances to the configuration ports to change the signals transmitted by the configuration ports; the configuration modes are divided into JTAG configuration mode and non-JTAG configuration mode;
[0008] According to the security configuration policy, the configuration code stream is sent to the configuration memory of the target FPGA chip through the corresponding configuration port.
[0009] Furthermore, the configuration method is JTAG configuration method, and the security configuration strategy is:
[0010] The JTAG state machine jumps from the SHIFT_DR state to other states and then back to the SHIFT_DR state by sending a state jump signal to the TMS port at random TCK cycle intervals or preset fixed TCK cycle intervals. When the JTAG state machine is in the SHIFT_DR state, the configuration code stream data is sent through the TDI port in each TCK cycle. When the JTAG state machine is in the non-SHIFT_DR state, 0 or 1 is sent through the TDI port in each TCK cycle.
[0011] Furthermore, the configuration method is JTAG configuration method, and the security configuration strategy is:
[0012] Send a 0 or 1 signal with a random duration or a preset fixed duration to the TCK port in units of random TCK cycle intervals or preset fixed TCK cycle intervals; in each TCK cycle, send the configuration code stream data in sequence through the TDI port.
[0013] Furthermore, while sending a 0 or 1 signal of random duration or preset fixed duration to the TCK port, a 0 or 1 signal of the same duration is also sent to the TMS port and the TDI port.
[0014] Furthermore, the configuration method is non-JTAG configuration method, and the security configuration strategy is:
[0015] A 0 or 1 signal with a random duration or a preset fixed duration is sent to the configuration clock port at a random configuration clock cycle interval or a preset fixed configuration clock cycle interval; in each configuration clock cycle, the configuration code stream data is sent sequentially through the configuration data port.
[0016] Furthermore, while a 0 or 1 signal of a random duration or a preset fixed duration is sent to the configuration clock port, a 0 or 1 signal of the same duration is also sent to the configuration data port.
[0017] The present invention also provides a high-security configuration system for an FPGA chip, comprising:
[0018] The first module is used to obtain the configuration code stream of the target FPGA chip;
[0019] The second module is used to determine a secure configuration strategy; the secure configuration strategy is determined according to the configuration mode selected by the target FPGA chip, and according to the configuration ports involved in the selected configuration mode, disturbances are selectively and periodically added to the configuration signal ports to change the signals transmitted by the configuration ports; the configuration modes are divided into JTAG configuration mode and non-JTAG configuration mode;
[0020] The third module is used to send the configuration code stream to the configuration memory of the target FPGA chip through the corresponding configuration port according to the security configuration policy.
[0021] Furthermore, in the second module, if the selected configuration mode is the JTAG configuration mode, the security configuration strategy is: with random TCK cycle intervals or preset fixed TCK cycle intervals as units, by sending a state jump signal to the TMS port, the JTAG state machine jumps from the SHIFT_DR state to other states, and then jumps back to the SHIFT_DR state; when the JTAG state machine is in the SHIFT_DR state, the configuration code stream data is sent through the TDI port in each TCK cycle; when the JTAG state machine is in the non-SHIFT_DR state, 0 or 1 is sent through the TDI port in each TCK cycle.
[0022] Furthermore, in the second module, if the selected configuration method is the JTAG configuration method, the security configuration strategy is: send a 0 or 1 signal of random duration or preset fixed duration to the TCK port in units of random TCK cycle intervals or preset fixed TCK cycle intervals; within each TCK cycle, send configuration code stream data through the TDI port.
[0023] Furthermore, in the second module, if the selected configuration method is a non-JTAG configuration method, the security configuration strategy is: sending a 0 or 1 signal of random duration or preset fixed duration to the configuration clock port in units of random configuration clock cycle intervals or preset fixed configuration clock cycle intervals; in each configuration clock cycle, sending configuration code stream data through the configuration data port.
[0024] The advantages of the present invention compared with the prior art are:
[0025] (1) The present invention innovatively proposes a method of adding signal disturbances during configuration to protect against side channels during FPGA chip configuration. This method is different from traditional protection methods such as masking, obfuscation, internal authentication, and round keys. It does not require modification of circuits or configuration logic. It is also different from the commonly used interference methods of adding electromagnetic or current signals, which require additional interference design on the chip shell or internal circuits. It only changes the configuration strategy, reducing the cost of achieving secure configuration.
[0026] (2) The technical solution of the present invention is difficult to be cracked by reverse engineering because it does not involve additional circuit design and does not use additional interference equipment or devices. In addition, since FPGA chips usually must be configured and downloaded using supporting download software and download tools, this method changes the configuration strategy by using clock control or state machine control methods that are fixed in the supporting download software. This method cannot be easily changed or eliminated, and can effectively improve the protection capability against side channel attacks.
[0027] (3) This method utilizes the characteristics of the JTAG configuration mode that uses a state machine to control the configuration process, and the configuration process uses a configuration clock to control the configuration process. It purely uses configuration software for security protection, does not require modifying the chip's hardware configuration circuit, and does not affect the chip's configuration process. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 Flow chart of the method of the present invention;
[0029] Figure 2 Schematic diagram of the system of the present invention. DETAILED DESCRIPTION
[0030] In order to better understand the technical solution of the present invention, the specific implementation methods of the present invention are described below.
[0031] like Figure 1 As shown, the present invention proposes a high-security configuration method for an FPGA chip, comprising the following steps:
[0032] Step 1: Obtain the configuration code stream of the target FPGA chip.
[0033] Here, the configuration code stream is typically an encrypted configuration code stream, as side-channel attacks are typically performed against the encryption key of the encrypted code stream. In the present invention, there is no need to limit the size or integrity of the configuration code stream; it can be a complete or partial configuration code stream.
[0034] Step 2: Determine the security configuration strategy.
[0035] Common configuration methods for target FPGA chips include JTAG and non-JTAG configuration methods (master serial, slave serial, SPI, BPI, SelectMAP, etc.). Regardless of the configuration mode, the method of the present invention can be used for high-security configuration. The difference is that the security configuration strategy varies depending on the configuration method. In the present invention, the security configuration strategy is determined solely based on the configuration method.
[0036] The specific implementation steps include:
[0037] Step 2.1: According to the selected configuration mode of the target FPGA chip, determine each configuration port involved in the selected configuration mode;
[0038] For example, when using JTAG configuration, the configuration ports involved include TCK, TDI, and TMS. The TDO port is an output port and is not included in the security configuration policy. For another example, when using SelectMAP configuration, the configuration ports involved include the configuration clock port and the configuration data port.
[0039] Step 2.2: Determine a security configuration strategy based on each configuration port involved in the configuration method; the security configuration strategy is a signal transmission strategy for each configuration port, that is, selectively and periodically adding disturbances to the configuration signal port to change the signal transmitted by the configuration port.
[0040] That is, for example, when using the JTAG configuration mode, the secure configuration policy is the signal transmission policy for the TCK, TDI, and TMS ports. For another example, when using the SelectMAP configuration mode, the secure configuration policy is the signal transmission policy for the configuration clock port and the configuration data port.
[0041] Step 3: According to the security configuration policy, the configuration code stream is sent to the configuration memory of the target FPGA chip through the corresponding configuration port.
[0042] Here, the transmission signal of each configuration port is still the original clock signal, control signal or configuration code stream data bit. The security configuration strategy is implemented through the signal transmission strategy. Here, the signal transmission strategy is that each configuration port transmits a signal in each clock cycle.
[0043] Step 4: After all the configuration code streams are burned, enter the chip startup process.
[0044] The chip boot process here refers to the original boot process for the FPGA chip, which typically includes verifying the integrity and correctness of the configuration code stream and determining whether the target FPGA chip can be booted normally based on the verification results. If the burned configuration code stream passes the integrity and correctness verification, the target FPGA chip can be booted normally and the user-designed functions can be executed according to the burned configuration code stream. If the burned configuration code stream fails to pass the integrity and correctness verification, the target FPGA chip cannot be booted normally and an error is reported.
[0045] Example 1
[0046] When the selected configuration mode is JTAG configuration, a high-security configuration method for an FPGA chip includes the following steps:
[0047] Step 1: Obtain the configuration code stream of the target FPGA chip.
[0048] Step 2: Determine the security configuration strategy.
[0049] When JTAG is selected as the configuration method, two methods can be used to add disturbances to the configuration signal port to increase the configuration noise and defend against side-channel attacks.
[0050] The first method is to add disturbances to the TMS port. By periodically or irregularly jumping the JTAG state machine, noise is added, making the collected side channel leakage unaligned. The specific steps are:
[0051] The JTAG state machine jumps from the SHIFT_DR state to other states and then back to the SHIFT_DR state by sending a preset state jump signal to the TMS port at random TCK cycle intervals or preset fixed TCK cycle intervals. When the JTAG state machine is in the SHIFT_DR state, the TDI port sends 1 bit of configuration code stream data in each TCK cycle. When the JTAG state machine is in the non-SHIFT_DR state, the TDI port sends 1 bit of 0 or 1 in each TCK cycle.
[0052] Here, the operation of the TDI port sending 1 bit of configuration code stream data in each TCK cycle is no different from the way of sending configuration code stream data in the normal configuration state. In each TCK clock cycle, that is, at the rising or falling edge of each TCK clock, 1 bit of configuration code stream data is sent. The configuration code stream data is sent in sequence until the last bit of configuration code stream data is sent.
[0053] The second method is to add disturbances to the TCK port, and achieve random or periodic shutdown effects through TCK control, increase noise, and make the collected side channel leakage misaligned. The specific steps are:
[0054] A 0 or 1 signal of random duration or preset fixed duration is sent to the TCK port at a random TCK cycle interval or a preset fixed TCK cycle interval. At this time, a 0 or 1 signal of the same duration is also sent to the TMS port and TDI port. In each TCK cycle, the configuration code stream data is sent through the TDI port.
[0055] It should be noted that sending 0 or 1 signals of equal duration to the TMS port and the TDI port simultaneously is a preferred method but not a necessary step.
[0056] Here, the operation of sending configuration code stream data through the TDI port in each TCK cycle is no different from the method of sending configuration code stream data in the normal configuration state. In each TCK cycle, that is, at the rising or falling edge of each TCK clock, 1 bit of configuration code stream data is sent. The configuration code stream data are sent in sequence until the last configuration code stream data is sent.
[0057] Step 3: According to the security configuration policy, the configuration code stream is burned into the configuration memory of the target FPGA chip through the corresponding configuration port.
[0058] Step 4: After all the configuration code streams are burned, enter the chip startup process.
[0059] Example 2
[0060] When the selected configuration mode is non-JTAG configuration, for example, when the selected configuration mode is any one of the configuration modes such as master serial, slave serial, SPI, BPI, SelectMAP, etc., the controlled ports are the configuration clock port and the configuration data port. In this case, a high-security configuration method for an FPGA chip includes the following steps:
[0061] Step 1: Obtain the configuration code stream of the target FPGA chip.
[0062] Step 2: Determine the security configuration strategy.
[0063] At random configuration clock cycle intervals or preset fixed configuration clock cycle intervals, a 0 or 1 signal of random duration or preset fixed duration is sent to the configuration clock port. At this time, a 0 or 1 signal of the same duration is also sent to the configuration data port. At each configuration clock cycle, the configuration stream data is sent through the configuration data port. It should be noted that sending a 0 or 1 signal of the same duration to the configuration data port is a preferred method and is not a required step.
[0064] Here, the operation of sending configuration stream data through the configuration data port during each configuration clock cycle is no different from the method of sending configuration stream data in the normal configuration state. Configuration stream data is sent during each configuration clock cycle, that is, on each rising or falling edge of the TCK clock. The bit width of the configuration stream data sent is determined by the selected configuration mode and can be 1 bit, 4 bits, 8 bits, or 32 bits, matching the bit width of the configuration stream data required to be sent under normal circumstances in this configuration mode. Configuration stream data is still sent sequentially until the last configuration stream data is sent.
[0065] This method is achieved by adding disturbances to the configuration clock port. By controlling the configuration clock port, the effect of random or periodic shutdown is achieved, which increases noise and makes it impossible to align the collected side channel leakage.
[0066] Step 3: According to the security configuration policy, the configuration code stream is burned into the configuration memory of the target FPGA chip through the corresponding configuration port.
[0067] Step 4: After all the configuration code streams are burned, enter the chip startup process.
[0068] like Figure 2 As shown, the present invention also provides a high-security configuration system for FPGA chips, comprising:
[0069] Configuration code stream acquisition module: used to obtain the configuration code stream of the target FPGA chip;
[0070] Security configuration strategy selection module: used to determine the security configuration strategy; the security configuration strategy is determined according to the configuration mode selected by the target FPGA chip. According to the configuration ports involved in the selected configuration mode, the module selectively and periodically adds disturbances to the configuration signal ports to change the signals transmitted by the configuration ports. The configuration modes are divided into JTAG configuration mode and non-JTAG configuration mode;
[0071] Configuration process control module: used to send the configuration code stream to the configuration memory of the target FPGA chip through the corresponding configuration port according to the security configuration policy;
[0072] Startup module: used to enter the chip startup process after all the configuration code streams are burned and programmed.
[0073] It will be understood that the present invention is described by way of example, and it will be appreciated by those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and any embodiment that falls within the scope of the claims of this application is intended to be within the scope of protection of the present invention.
[0074] The contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.
Claims
1. A high-security configuration method for an FPGA chip, characterized in that: include: Get the configuration code stream of the target FPGA chip; Determine security configuration strategies; The secure configuration strategy is determined according to the configuration mode selected by the target FPGA chip. According to the configuration ports involved in the selected configuration mode, disturbances are selectively and periodically added to the configuration ports to change the signals transmitted by the configuration ports. The configuration modes are divided into JTAG configuration mode and non-JTAG configuration mode. According to the security configuration policy, the configuration code stream is sent to the configuration memory of the target FPGA chip through the corresponding configuration port.
2. The high-security configuration method for an FPGA chip according to claim 1, wherein: The configuration method is JTAG configuration method, and the security configuration strategy is: The JTAG state machine jumps from the SHIFT_DR state to other states and then back to the SHIFT_DR state by sending a state jump signal to the TMS port at random TCK cycle intervals or preset fixed TCK cycle intervals. When the JTAG state machine is in the SHIFT_DR state, the configuration code stream data is sent through the TDI port in each TCK cycle. When the JTAG state machine is in the non-SHIFT_DR state, 0 or 1 is sent through the TDI port in each TCK cycle.
3. The high-security configuration method for an FPGA chip according to claim 1, wherein: The configuration method is JTAG configuration method, and the security configuration strategy is: Send a 0 or 1 signal with a random duration or a preset fixed duration to the TCK port in units of random TCK cycle intervals or preset fixed TCK cycle intervals; in each TCK cycle, send the configuration code stream data in sequence through the TDI port.
4. The high-security configuration method for an FPGA chip according to claim 3, wherein: While sending a 0 or 1 signal of random duration or preset fixed duration to the TCK port, a 0 or 1 signal of the same duration is also sent to the TMS port and TDI port.
5. The high-security configuration method for an FPGA chip according to claim 1, wherein: The configuration mode is non-JTAG configuration mode, and the security configuration policy is: A 0 or 1 signal with a random duration or a preset fixed duration is sent to the configuration clock port at a random configuration clock cycle interval or a preset fixed configuration clock cycle interval; in each configuration clock cycle, the configuration code stream data is sent sequentially through the configuration data port.
6. The high-security configuration method for an FPGA chip according to claim 5, wherein: While sending a 0 or 1 signal of random duration or preset fixed duration to the configuration clock port, a 0 or 1 signal of the same duration is also sent to the configuration data port.
7. A high-security configuration system for FPGA chips, characterized in that: include: The first module is used to obtain the configuration code stream of the target FPGA chip; The second module: used to determine the security configuration strategy; The secure configuration strategy is determined according to the configuration mode selected by the target FPGA chip. According to the configuration ports involved in the selected configuration mode, disturbances are selectively and periodically added to the configuration signal ports to change the signals transmitted by the configuration ports. The configuration modes are divided into JTAG configuration mode and non-JTAG configuration mode. The third module is used to send the configuration code stream to the configuration memory of the target FPGA chip through the corresponding configuration port according to the security configuration policy.
8. The high-security configuration system for FPGA chips according to claim 7, characterized in that: In the second module, if the selected configuration mode is JTAG configuration mode, the security configuration strategy is: The JTAG state machine jumps from the SHIFT_DR state to other states and then back to the SHIFT_DR state by sending a state jump signal to the TMS port at random TCK cycle intervals or preset fixed TCK cycle intervals. When the JTAG state machine is in the SHIFT_DR state, the configuration code stream data is sent through the TDI port in each TCK cycle. When the JTAG state machine is in the non-SHIFT_DR state, 0 or 1 is sent through the TDI port in each TCK cycle.
9. The high-security configuration system for FPGA chips according to claim 7, characterized in that: In the second module, if the selected configuration mode is JTAG configuration mode, the security configuration strategy is: Send a 0 or 1 signal of random duration or preset fixed duration to the TCK port in units of random TCK cycle intervals or preset fixed TCK cycle intervals; send configuration code stream data through the TDI port within each TCK cycle.
10. The high-security configuration system for FPGA chips according to claim 7, characterized in that: In the second module, if the selected configuration method is non-JTAG configuration method, the safe configuration strategy is: A 0 or 1 signal of random duration or preset fixed duration is sent to the configuration clock port in units of random configuration clock cycle intervals or preset fixed configuration clock cycle intervals; configuration code stream data is sent through the configuration data port in each configuration clock cycle.