Quantitative compensation calculation method for silicon carbide MOSFET multi-chip parallel current sharing and related device
By constructing and compensating an equivalent circuit model of multi-chip parallel-connected SiC MOSFET devices, the uneven current problem is solved, current utilization and reliability are improved, and costs are reduced.
Patent Information
- Application Number
- CN202510834914.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-20
- Publication Date
- 2025-09-26
AI Technical Summary
There is uneven current distribution in multi-chip parallel devices of silicon carbide power semiconductors, which leads to insufficient utilization of current capacity, different chip losses and reduced reliability, and may even cause thermal runaway.
An equivalent circuit model of multi-chip parallel MOSFETs is constructed, the equivalent parasitic parameters of the package structure are extracted, and it is divided into drain, gate, and source parasitic impedance networks. The parameters of each network are calculated and compensated to achieve current sharing.
The current sharing compensation of multi-chip parallel-connected silicon carbide MOSFET devices is realized, which improves the current capacity utilization and reliability, avoids the introduction of additional components, and reduces costs.
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Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of silicon carbide power device design, and relates to a quantitative compensation calculation method for current sharing of multiple silicon carbide MOSFET chips connected in parallel and a related device. Background Art
[0002] Silicon carbide power semiconductor devices are gaining increasing popularity due to their advantages over traditional silicon-based semiconductor devices in high frequency, high temperature, and high voltage. However, due to the production process challenges of silicon carbide power semiconductor chips, single silicon carbide power semiconductor chips still have significant shortcomings in terms of maximum current flow capacity. In high-power applications such as electric vehicles, photovoltaic inverters, energy storage systems, and solid-state transformers, multiple chips need to be connected in parallel to form silicon carbide multi-chip parallel devices to increase the current capacity of the power devices and meet actual application needs. However, in actual applications, due to various influencing factors such as device parameter differences and asymmetric packaging structures, significant current imbalance will occur in the parallel branches within the multi-chip parallel device, resulting in the current capacity of some parallel chips not being fully utilized. In addition, the uneven current flow in each branch will further lead to differences in chip losses, which in turn leads to uneven chip temperatures, reduced reliability, and even thermal runaway, causing device failure. Therefore, in-depth research on the formation mechanism of uneven current in parallel SiC multi-chips, analysis and summary of the key influencing factors of current equalization in parallel SiC multi-chips, and development of corresponding suppression methods based on this are the key to improving the current capacity utilization and reliability of SiC multi-chip parallel devices and further promoting their application in high-power fields.
[0003] The existing current sharing methods for parallel-connected SiC multi-chip power devices can be mainly divided into three types, including device screening, active current sharing, and passive current sharing.
[0004] Chip screening relies on a detailed classification of chip parameters and can only be used for specific layouts. It cannot effectively compensate for layouts with high uneven flow or varying chip parameters.
[0005] Active current sharing primarily utilizes current parameter feedback, measuring current using a current transformer or sampling the induced electromotive force of the source's equivalent parasitic inductance. However, current transformers are bulky, and sampling the electromotive force requires complex conditioning and filtering circuits, negatively impacting the overall reliability of devices using multi-chip parallel power devices. Furthermore, this solution requires individual drive for each parallel branch, further increasing drive complexity. Different control strategies are required for different numbers of parallel chips, making it difficult to meet the requirements of commonly used single-drive multi-chip parallel power devices.
[0006] Passive current sharing methods can be further divided into two categories. The first category uses the method of integrating additional components, including integrating magnetic components to directly filter out differential mode current, or integrating decoupling capacitors or RC filtering circuits to change the original commutation circuit, thereby improving current distribution. However, magnetic components have a large volume and will introduce additional parasitic parameters in the branch, resulting in increased overshoot and oscillation of power devices. The method of integrating decoupling capacitors and RC filtering will reduce the reliability of power devices due to the introduction of additional components. The second category starts from the key parasitic parameters that cause uneven current, and realizes multi-chip parallel current sharing through various methods of adjusting parasitic parameters. It does not require the insertion of additional components and is more economical. However, the existing related compensation schemes are basically qualitative compensation methods, which are difficult to apply to actual designs and lack a simple and easy-to-use quantitative compensation method. Summary of the Invention
[0007] The purpose of the present invention is to overcome the shortcomings of the above-mentioned prior art and provide a quantitative compensation calculation method and related device for parallel current sharing of multiple silicon carbide MOSFET chips. This method and related device can achieve quantitative compensation for parallel current sharing of multiple silicon carbide MOSFET chips.
[0008] To achieve the above-mentioned object, the present invention discloses a quantitative compensation calculation method for current sharing of multiple parallel silicon carbide MOSFET chips, comprising:
[0009] Construct an equivalent circuit model of multi-chip parallel MOSFETs and extract the equivalent parasitic parameters of the interconnect structure in the package structure;
[0010] Dividing the equivalent circuit model into a drain parasitic impedance network, a gate parasitic impedance network, and a source parasitic impedance network;
[0011] Calculating compensation parameters of a drain parasitic impedance network, a gate parasitic impedance network, and a source parasitic impedance network according to equivalent parasitic parameters of the interconnect structure;
[0012] The drain parasitic impedance network, the gate parasitic impedance network and the source parasitic impedance network are compensated respectively according to the compensation parameters of the drain parasitic impedance network, the gate parasitic impedance network and the source parasitic impedance network.
[0013] The further improvement of the quantitative compensation calculation method for current sharing of multiple parallel silicon carbide MOSFET chips described in the present invention is:
[0014] Furthermore, the specific operations of step 1) are:
[0015] Based on the typical layout of multi-chip parallel MOSFETs, an equivalent circuit model of multi-chip parallel MOSFETs is constructed, and the equivalent parasitic parameters of the interconnection structure in the packaging structure are extracted. The equivalent parasitic parameters include the equivalent parasitic inductance under high frequency conditions and the equivalent parasitic resistance under low frequency conditions.
[0016] Furthermore, the specific operations of step 2) are:
[0017] According to the characteristics of the parasitic impedance network, the equivalent circuit model is divided into a drain parasitic impedance network, a gate parasitic impedance network and a source parasitic impedance network.
[0018] Furthermore, the compensation parameters of the source parasitic impedance network are:
[0019]
[0020] Among them, Z a1 , Z a2 , Z a3 , Z a4 , Z b1 , Z b2 , Z b3 , and Z b4 They are:
[0021]
[0022] Among them, Z ss1 、Z ss2 、Z ss3 is the common source parasitic impedance under non-Kelvin source connection, Z s1 , Z s2 , Z s3 is the source parasitic impedance, Z k1 , Z k2 , Z k3 is the parasitic impedance of the driving source. s23 is the additional source parasitic impedance of the 2nd and 3rd parallel branches, Z k12 is the additional driving source parasitic impedance of the 2nd and 3rd parallel branches.
[0023] Furthermore, the compensation parameters of the gate parasitic impedance network are:
[0024]
[0025] Among them, Z ss1 , Z ss2 , Z ss3 is the common source parasitic impedance under non-Kelvin source connection, Z s1 , Z s2 , Z s3 is the source parasitic impedance, Z k1 , Z k2 , Z k3 is the parasitic impedance of the driving source. s23 is the additional source parasitic impedance of the 2nd and 3rd parallel branches, Z k12is the additional driving source parasitic impedance of the 2nd and 3rd parallel branches, Z g1 , Z g2 , Z g3 Gate parasitic impedance under split resistor. Z g12 is the additional gate parasitic impedance of the parallel branches 1 and 2, Z a1 , Z a2 , Z a3 , Z a4 , Z b1 , Z b2 , Z b3 , and Z b4 The impedance is defined by (2).
[0026] Furthermore, the compensation parameters of the drain parasitic impedance network are:
[0027]
[0028] Among them, Z d1 , Z d2 , Z d3 is the drain parasitic impedance, Z d23 is the additional source parasitic impedance of the parallel branches 2 and 3.
[0029] The present invention discloses a quantitative compensation calculation system for current sharing of multiple silicon carbide MOSFET chips connected in parallel, comprising:
[0030] A construction module is used to construct an equivalent circuit model of multi-chip parallel MOSFETs and extract the equivalent parasitic parameters of the interconnect structure in the package structure;
[0031] A division module, configured to divide the equivalent circuit model into a drain parasitic impedance network, a gate parasitic impedance network, and a source parasitic impedance network;
[0032] a calculation module, configured to calculate compensation parameters of a drain parasitic impedance network, a gate parasitic impedance network, and a source parasitic impedance network according to equivalent parasitic parameters of the interconnect structure;
[0033] The compensation module is used to compensate the drain parasitic impedance network, the gate parasitic impedance network and the source parasitic impedance network according to the compensation parameters of the drain parasitic impedance network, the gate parasitic impedance network and the source parasitic impedance network respectively.
[0034] The further improvement of the quantitative compensation calculation system for parallel current sharing of multiple silicon carbide MOSFET chips described in the present invention is:
[0035] Furthermore, the specific operations of step 1) are:
[0036] Based on the typical layout of multi-chip parallel MOSFETs, an equivalent circuit model of multi-chip parallel MOSFETs is constructed, and the equivalent parasitic parameters of the interconnection structure in the packaging structure are extracted. The equivalent parasitic parameters include the equivalent parasitic inductance under high frequency conditions and the equivalent parasitic resistance under low frequency conditions.
[0037] The present invention discloses a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the quantitative compensation calculation method for current sharing of multiple parallel silicon carbide MOSFET chips are implemented.
[0038] The present invention discloses a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps of the quantitative compensation calculation method for parallel current sharing of multiple silicon carbide MOSFET chips are implemented.
[0039] The present invention has the following beneficial effects:
[0040] The quantitative compensation calculation method and related device for parallel current sharing of multi-chip silicon carbide MOSFETs described in the present invention calculate the compensation parameters of the drain parasitic impedance network, the gate parasitic impedance network and the source parasitic impedance network according to the equivalent parasitic parameters of the interconnection structure during specific operation, and compensate the drain parasitic impedance network, the gate parasitic impedance network and the source parasitic impedance network respectively to solve the current problem of multi-chip parallel current sharing when silicon carbide adopts traditional packaging. It can be applied to various situations such as parallel connection of discrete devices and design of multi-chip parallel power modules. In addition to being applied to non-Kelvin source connections, the compensation formula can also be used to optimize the design of power modules with Kelvin source connections. In addition, the present invention does not require the insertion of additional components, but only requires changing some of the original layout parameters, which is a low-cost, effective and reliable solution. BRIEF DESCRIPTION OF THE DRAWINGS
[0041] The accompanying drawings, which constitute part of the present invention, are intended to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are intended to explain the present invention and do not constitute an undue limitation of the present invention. In the accompanying drawings:
[0042] Figure 1 This is an equivalent circuit diagram based on the typical layout of three-chip parallel silicon carbide power devices currently in common use.
[0043] Figure 2 is a layout diagram of the equivalent circuit diagram in this embodiment;
[0044] Figure 3 A diagram showing the corresponding relationship between the drain interconnect wire and the parasitic parameters in the corresponding equivalent circuit diagram in the present invention;
[0045] Figure 4 A diagram showing the corresponding relationship between the source interconnect wire and the parasitic parameters in the corresponding equivalent circuit diagram in the present invention;
[0046] Figure 5 A diagram showing the corresponding relationship between the gate interconnect wires and the parasitic parameters in the corresponding equivalent circuit diagram in the present invention;
[0047] Figure 6 This is a comparison diagram of the turn-on and turn-off waveforms of the double pulse test after compensation using the current sharing compensation scheme for the three-chip parallel layout of the MOSFET given in the present invention. DETAILED DESCRIPTION
[0048] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.
[0049] In the description of the present invention, it is to be understood that the terms “include” and “comprise” indicate the presence of the described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or collections thereof.
[0050] It should also be understood that the terms used in the present specification are only for the purpose of describing particular embodiments and are not intended to limit the present invention. As used in the present specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms unless the context clearly indicates otherwise.
[0051] It should be further understood that the term "and / or" as used in the present specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in the present invention generally indicates that the associated objects are in an "or" relationship.
[0052] It should be understood that although the terms "first," "second," and "third" may be used to describe preset ranges in embodiments of the present invention, these preset ranges should not be limited to these terms. These terms are merely used to distinguish one preset range from another. For example, without departing from the scope of embodiments of the present invention, the first preset range may also be referred to as the second preset range, and similarly, the second preset range may also be referred to as the first preset range.
[0053] The word "if," as used herein, may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to the determination" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)," depending on the context.
[0054] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.
[0055] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments disclosed herein. These figures are not drawn to scale; for clarity, some details are exaggerated and some details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.
[0056] Example 1
[0057] The quantitative compensation calculation method for current sharing of multiple silicon carbide MOSFET chips in parallel according to the present invention comprises the following steps:
[0058] 1) Based on the typical layout of multi-chip parallel MOSFETs, an equivalent circuit model of the multi-chip parallel MOSFETs is constructed, and the equivalent parasitic parameters of the interconnect structure in the package structure are extracted through simulation software. The equivalent parasitic parameters include the equivalent parasitic inductance under high frequency conditions and the equivalent parasitic resistance under low frequency conditions;
[0059] 2) According to the characteristics of each parasitic impedance network, the equivalent circuit model is divided into drain parasitic impedance network, gate parasitic impedance network and source parasitic impedance network;
[0060] 3) Analyze the actual required compensation parameters based on the equivalent parasitic parameters of the interconnect structure. Analyze whether the MOSFET uses a Kelvin source connection. For Kelvin source connections, use a parameter distribution control method. For non-Kelvin source connections, use a compensation plus control parameter method.
[0061] 4) Adjust the parallel MOSFET interconnection structure according to the obtained compensation parameters or control methods, so that the parallel MOSFET interconnection structure reaches a fully compensated state, at which time the three parallel chips achieve current sharing.
[0062] In step 1), the equivalent circuit model includes the drain interconnect wire equivalent parasitic impedance Z d1 , Z d2 , Z d3 , Z d23 , Z d ; Gate interconnect equivalent parasitic impedance Z g1 , Z g2 , Z g3 , Z g12 , Z g ; Equivalent parasitic impedance Z of source interconnect wire ss1 , Z ss2 , Z ss3 , Z s1 , Z s2 , Z s3 , Z s23 , Z s , Z k1 , Z k2 , Z k3 , Z k12 , Z k , where the driving voltage is V G , the DC bus voltage is V DC , the load inductance is L dpt .
[0063] The specific process of step 3) is:
[0064] 31) Based on the equivalent parasitic parameters of the interconnect structure, the compensation value of the equivalent parasitic impedance network of the source interconnect structure is calculated. The calculation formula is summarized as follows:
[0065]
[0066] Among them, Z a1 , Z a2 , Z a3 , Z a4 , Z b1 , Z b2 , Z b3 , and Z b4 They are:
[0067]
[0068] 32) For non-Kelvin source connections, two methods are used to achieve current sharing control: a) parasitic impedance compensation, by performing impedance compensation at the common source inductor position, so that the actual impedance difference satisfies the calculated value of formula (1); b) parasitic impedance control, by adjusting the distribution of the source parasitic impedance, so that the actual impedance difference satisfies the calculated value of formula (1). Among them, for Kelvin source connection, the actual impedance difference can only be satisfied by adjusting the distribution of the source parasitic impedance, and it is necessary to further satisfy:
[0069] Z ss1 =Z ss2 =Z ss3 =0 (3)
[0070] At this point, full current sharing compensation of the source equivalent parasitic impedance network is achieved.
[0071] 33) Calculate the compensation value of the gate equivalent parasitic impedance network, specifically:
[0072]
[0073] For the compensation of the gate equivalent parasitic impedance network, the Kelvin and non-Kelvin source connections are the same. By compensating the compensation value obtained by formula (4) in the gate interconnect structure, the complete current sharing compensation of the gate equivalent impedance network is achieved.
[0074] 34) Calculate the compensation value of the drain equivalent parasitic impedance network, specifically:
[0075]
[0076] For the compensation of the drain equivalent parasitic impedance network, the Kelvin and non-Kelvin source connections are the same. By compensating the compensation value obtained by formula (1.5) in the drain interconnect structure, the complete current sharing compensation of the drain equivalent impedance network is achieved.
[0077] The complete compensation state in step 4) satisfies the complete current sharing compensation state of the source, gate and drain in step 3), wherein the current sharing is dynamic and static complete current sharing.
[0078] Example 2
[0079] refer to Figure 2 , Figure 2 It indicates a three-chip parallel design using discrete SiC MOSFETs, consisting of two completely independent interconnect structures, including a power interconnect structure and a drive interconnect structure. The power interconnect structure includes an equivalent drain parasitic impedance network and a source parasitic impedance network, while the drive interconnect structure includes an equivalent gate parasitic impedance network. Figure 2 In the figure, 101 is the drain parasitic impedance compensation point, 102 is the discrete SiC MOSFET device, 103 is the load inductor, 104 is the freewheeling diode, 105 is the drive circuit connection point, 106 is the decoupling capacitor, 107 is the first gate transfer point, 108 is the source parasitic impedance compensation point, 109 is the gate parasitic impedance compensation point, 110 is the gate confluence point, 111 is the first split drive resistor, 112 is the second split drive resistor, 113 is the third split drive resistor, and 114 is the second gate transfer point. The power interconnection structure and the drive interconnection structure are electrically interconnected through the first gate transfer point 107 and the second gate transfer point 114.
[0080] Figure 3 、 Figure 4 and Figure 5 Indicates the corresponding relationship between each interconnection wire and the actual parasitic parameters. According to the characteristics of the interconnection structure in the example provided, Z is omitted. k1 and Z k2 Two equivalent parasitic impedances, or set their values to 0 for analysis. Use simulation software to segment each interconnect structure and independently extract the parasitic parameters of each interconnect structure. Specifically, first set the simulation frequency to 10MHz. At this time, through simulation, the equivalent parasitic inductance of each part of the interconnect structure during the switching transient process is obtained, and the simulation data is recorded and used as the inductance part of the equivalent impedance; then set the simulation condition to DC, that is, the direct current condition. At this time, the equivalent parasitic resistance of each part of the interconnect structure during the conduction process can be obtained through simulation software, and the recorded simulation data is used as the resistance part of the equivalent impedance; by merging the inductance part and the resistance part, the initial equivalent circuit impedance parameters of the currently designed SiCMOSFET multi-chip parallel instance can be obtained.
[0081] Since this embodiment is a non-Kelvin source connection case, a compensation method is adopted. The initial equivalent circuit impedance parameters of the SiCMOSFET multi-chip parallel example interconnection structure extracted by simulation are substituted into formula (1) to calculate the compensation value of the source parasitic impedance network; substituted into formula (4) to calculate the compensation value of the gate parasitic impedance network; and substituted into formula (5) to calculate the compensation value of the drain parasitic impedance network.
[0082] Since the calculated compensation value is the difference, a compensation reference value is set first. In order to minimize the current and voltage overshoot and oscillation caused by parasitic parameters during the switching process, the total parasitic inductance of each parallel branch needs to be reduced as much as possible. Therefore, the initial value should be set to the theoretical minimum value. The theoretical minimum value should also ensure that all compensation parasitic parameters are not less than zero to meet the actual compensation requirements. After determining the compensation reference value, Figure 2By inserting corresponding parasitic inductors at the drain parasitic impedance compensation point 101 , the source parasitic impedance compensation point 108 and the gate parasitic impedance compensation point 109 , the compensation requirement for current sharing of multiple chips in parallel can be met.
[0083] like Figure 6 As shown in the figure, the waveforms of the three parallel SiC MOSFETs before and after compensation during the turn-on and turn-off transient processes are shown. Initially, the maximum turn-on transient current of the parallel SiC MOSFET is 137.8A, and the minimum turn-on transient current is 63.1A. After compensation, the maximum turn-on transient current of the three parallel chips is 95.9A, and the current waveforms during the turn-on process are completely consistent. The transient current waveforms during the turn-off process are also completely consistent after compensation. Figure 6 It can be seen from the initial value of the compensated turn-off transient waveform that the parallel SiC MOSFETs also achieve static current sharing after compensation.
[0084] Example 3
[0085] The quantitative compensation calculation system for current sharing of multiple parallel silicon carbide MOSFET chips of the present invention comprises:
[0086] A construction module is used to construct an equivalent circuit model of multi-chip parallel MOSFETs and extract the equivalent parasitic parameters of the interconnect structure in the package structure;
[0087] A division module, configured to divide the equivalent circuit model into a drain parasitic impedance network, a gate parasitic impedance network, and a source parasitic impedance network;
[0088] a calculation module, configured to calculate compensation parameters of a drain parasitic impedance network, a gate parasitic impedance network, and a source parasitic impedance network according to equivalent parasitic parameters of the interconnect structure;
[0089] The compensation module is used to compensate the drain parasitic impedance network, the gate parasitic impedance network and the source parasitic impedance network according to the compensation parameters of the drain parasitic impedance network, the gate parasitic impedance network and the source parasitic impedance network respectively.
[0090] In this embodiment, the specific operations of step 1) are:
[0091] Based on the typical layout of multi-chip parallel MOSFETs, an equivalent circuit model of multi-chip parallel MOSFETs is constructed, and the equivalent parasitic parameters of the interconnection structure in the packaging structure are extracted. The equivalent parasitic parameters include the equivalent parasitic inductance under high frequency conditions and the equivalent parasitic resistance under low frequency conditions.
[0092] The division of modules in the embodiments of the present application is illustrative and is merely a logical functional division. In actual implementation, other division methods may be used. Furthermore, the functional modules in the various embodiments of the present application may be integrated into a single processor, or may exist physically separately, or two or more modules may be integrated into a single module. The aforementioned integrated modules may be implemented in the form of hardware or software functional modules.
[0093] Example 4
[0094] A computer device comprises a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the quantitative compensation calculation method for current sharing of multiple parallel-connected silicon carbide MOSFET chips are implemented. For example, the steps include: constructing an equivalent circuit model of the multi-chip parallel-connected MOSFETs and extracting equivalent parasitic parameters of the interconnect structure in the package structure; dividing the equivalent circuit model into a drain parasitic impedance network, a gate parasitic impedance network, and a source parasitic impedance network; calculating compensation parameters of the drain parasitic impedance network, the gate parasitic impedance network, and the source parasitic impedance network based on the equivalent parasitic parameters of the interconnect structure; and compensating the drain parasitic impedance network, the gate parasitic impedance network, and the source parasitic impedance network, respectively, based on the compensation parameters of the drain parasitic impedance network, the gate parasitic impedance network, and the source parasitic impedance network. The memory may include internal memory, such as high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device. The processor, network interface, and memory are interconnected via an internal bus. This internal bus may be an Industry Standard Architecture bus, a Peripheral Component Interconnect Standard bus, an Extended Industry Standard Architecture bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. The memory is used to store programs. Specifically, the program may include program code, and the program code includes computer operating instructions. The memory may include internal memory and non-volatile memory, and provides instructions and data to the processor.
[0095] Example 5
[0096] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of a quantitative compensation calculation method for current sharing of multi-chip parallel silicon carbide MOSFETs, including: constructing an equivalent circuit model of multi-chip parallel MOSFETs, extracting equivalent parasitic parameters of the interconnect structure in the package structure; dividing the equivalent circuit model into a drain parasitic impedance network, a gate parasitic impedance network, and a source parasitic impedance network; calculating compensation parameters of the drain parasitic impedance network, the gate parasitic impedance network, and the source parasitic impedance network based on the equivalent parasitic parameters of the interconnect structure; and compensating the drain parasitic impedance network, the gate parasitic impedance network, and the source parasitic impedance network based on the compensation parameters of the drain parasitic impedance network, the gate parasitic impedance network, and the source parasitic impedance network. Specifically, the computer-readable storage medium includes, but is not limited to, volatile memory and / or non-volatile memory. The volatile memory may include random access memory (RAM) and / or cache memory, etc. The non-volatile memory may include a read-only memory (ROM), a hard disk, a flash memory, an optical disk, a magnetic disk, and the like.
[0097] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.
[0098] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0099] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.
[0100] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.
[0101] Those skilled in the art will readily identify other embodiments of the present invention after considering the specification and disclosure of the invention. This application is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the invention being indicated by the following claims.
[0102] It should be understood that the present invention is not limited to the exact construction described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.
[0103] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any simple modification, change and equivalent structural change made to the above embodiment based on the technical essence of the present invention shall still fall within the scope of protection of the technical solution of the present invention.
Claims
1. A quantitative compensation calculation method for current sharing of multiple silicon carbide MOSFET chips in parallel, characterized in that: include: Construct an equivalent circuit model of multi-chip parallel MOSFETs and extract the equivalent parasitic parameters of the interconnect structure in the package structure; Dividing the equivalent circuit model into a drain parasitic impedance network, a gate parasitic impedance network, and a source parasitic impedance network; Calculating compensation parameters of a drain parasitic impedance network, a gate parasitic impedance network, and a source parasitic impedance network according to equivalent parasitic parameters of the interconnect structure; The drain parasitic impedance network, the gate parasitic impedance network and the source parasitic impedance network are compensated respectively according to the compensation parameters of the drain parasitic impedance network, the gate parasitic impedance network and the source parasitic impedance network.
2. The quantitative compensation calculation method for parallel current sharing of multiple silicon carbide MOSFET chips according to claim 1 is characterized in that: The specific operations of step 1) are: Based on the typical layout of multi-chip parallel MOSFETs, an equivalent circuit model of multi-chip parallel MOSFETs is constructed, and the equivalent parasitic parameters of the interconnection structure in the packaging structure are extracted. The equivalent parasitic parameters include the equivalent parasitic inductance under high frequency conditions and the equivalent parasitic resistance under low frequency conditions.
3. The quantitative compensation calculation method for parallel current sharing of multiple silicon carbide MOSFET chips according to claim 1, characterized in that: The specific operations of step 2) are: According to the characteristics of the parasitic impedance network, the equivalent circuit model is divided into a drain parasitic impedance network, a gate parasitic impedance network and a source parasitic impedance network.
4. The quantitative compensation calculation method for parallel current sharing of multiple silicon carbide MOSFET chips according to claim 1, characterized in that: The compensation parameters of the source parasitic impedance network are: Among them, Z a1 , Z a2 , Z a3 , Z a4 , Z b1 , Z b2 , Z b3 , and Z b4 They are: Among them, Z ss1 , Z ss2 , Z ss3 is the common source parasitic impedance under non-Kelvin source connection, Z s1 , Z s2 , Z s3 is the source parasitic impedance, Z k1 , Z k2 , Z k3 is the driving source parasitic impedance, Z s23 is the additional source parasitic impedance of the 2nd and 3rd parallel branches, Z k12 is the additional driving source parasitic impedance of the 2nd and 3rd parallel branches.
5. The quantitative compensation calculation method for parallel current sharing of multiple silicon carbide MOSFET chips according to claim 1, characterized in that: The compensation parameters of the gate parasitic impedance network are: Among them, Z ss1 , Z ss2 , Z ss3 is the common source parasitic impedance under non-Kelvin source connection, Z s1 , Z s2 , Z s3 is the source parasitic impedance, Z k1 , Z k2 , Z k3 is the driving source parasitic impedance, Z s23 is the additional source parasitic impedance of the 2nd and 3rd parallel branches, Z k12 is the additional driving source parasitic impedance of the 2nd and 3rd parallel branches, Z g1 , Z g2 , Z g3 Gate parasitic impedance under split resistor, Z g12 is the additional gate parasitic impedance of the parallel branches 1 and 2, Z a1 , Z a2 , Z a3 , Z a4 , Z b1 , Z b2 , Z b3 , and Z b4 The impedance is defined by (2).
6. The quantitative compensation calculation method for parallel current sharing of multiple silicon carbide MOSFET chips according to claim 1, characterized in that: The compensation parameters of the drain parasitic impedance network are: Among them, Z d1 , Z d2 , Z d3 is the drain parasitic impedance, Z d23 is the additional source parasitic impedance of the parallel branches 2 and 3.
7. A quantitative compensation calculation system for parallel current sharing of multiple silicon carbide MOSFET chips, characterized in that: include: A construction module is used to construct an equivalent circuit model of multi-chip parallel MOSFETs and extract the equivalent parasitic parameters of the interconnect structure in the package structure; A division module, configured to divide the equivalent circuit model into a drain parasitic impedance network, a gate parasitic impedance network, and a source parasitic impedance network; a calculation module, configured to calculate compensation parameters of a drain parasitic impedance network, a gate parasitic impedance network, and a source parasitic impedance network according to equivalent parasitic parameters of the interconnect structure; The compensation module is used to compensate the drain parasitic impedance network, the gate parasitic impedance network and the source parasitic impedance network according to the compensation parameters of the drain parasitic impedance network, the gate parasitic impedance network and the source parasitic impedance network respectively.
8. The quantitative compensation calculation system for parallel current sharing of multiple silicon carbide MOSFET chips according to claim 7, characterized in that: The specific operations of step 1) are: Based on the typical layout of multi-chip parallel MOSFETs, an equivalent circuit model of multi-chip parallel MOSFETs is constructed, and the equivalent parasitic parameters of the interconnection structure in the packaging structure are extracted. The equivalent parasitic parameters include the equivalent parasitic inductance under high frequency conditions and the equivalent parasitic resistance under low frequency conditions.
9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the quantitative compensation calculation method for parallel current sharing of multiple silicon carbide MOSFET chips are implemented as described in any one of claims 1 to 6.
10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the quantitative compensation calculation method for current sharing of multiple silicon carbide MOSFET chips in parallel are implemented as described in any one of claims 1 to 6.