Signal transmission method and device and semiconductor test equipment

Abstract

The embodiment of the invention provides a signal transmission method and device and semiconductor testing equipment, and relates to the technical field of semiconductor testing. The method is applied to semiconductor test equipment, and comprises the following steps: acquiring an input signal sent by an upper computer; the input signal can support different communication protocols; determining a trigger source mode of the semiconductor test equipment based on a currently supported communication protocol determined by decoding the input signal, so as to configure corresponding parameters for the semiconductor test equipment in the determined trigger source mode, and generate a corresponding trigger source signal; according to the parameters and the trigger source signal, driving the semiconductor test equipment to output along with the input signal in a trigger source mode to obtain an output signal; and sending the output signal to the tested unit, so that the tested unit can perform a corresponding test based on the output signal. According to the embodiment of the invention, the problem that logic control is too complex when signals supporting different communication protocols are transmitted on semiconductor test equipment in the prior art is solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor testing technology, and more specifically, to a signal transmission method, device, and semiconductor testing equipment. Background Art

[0002] In the field of semiconductor testing technology, semiconductor testing equipment is usually required to measure the device under test (DUT). Specifically, the host computer first sends a corresponding signal to the semiconductor testing equipment based on the test requirements of the unit under test, and then the semiconductor testing equipment transmits the signal to the unit under test, so that the unit under test can perform corresponding tests based on the received signal, and the test results are fed back to the host computer through the semiconductor testing equipment.

[0003] In order to meet various testing requirements, the signals sent to the unit under test often need to support different communication protocols. For example, the communication protocol can be LVDS protocol, MIPI protocol, RGB protocol, IIC protocol, SPI protocol, etc. This leads to the current semiconductor test equipment being configured with a variety of control ports for the transmission of these signals supporting different communication protocols, which makes the logical control of the semiconductor test equipment too complicated when transmitting these signals supporting different communication protocols. Summary of the Invention

[0004] The embodiments of the present application provide a signal transmission method, apparatus, and semiconductor test equipment that can solve the problem of overly complex logic control when signals supporting different communication protocols are transmitted on semiconductor test equipment in related technologies. The technical solution is as follows:

[0005] According to one aspect of an embodiment of the present application, a signal transmission method is applied to a semiconductor test device, wherein the semiconductor test device is connected between a host computer and a unit under test, and the method includes: obtaining an input signal sent by the host computer; the input signal can support different communication protocols; determining a trigger source mode of the semiconductor test device based on the currently supported communication protocol determined by decoding the input signal, so as to configure corresponding parameters for the semiconductor test device under the determined trigger source mode and generate a corresponding trigger source signal; according to the parameters and the trigger source signal, driving the semiconductor test device under the trigger source mode to follow the input signal output to obtain an output signal; the output signal corresponds to the communication protocol currently supported by the input signal; and sending the output signal to the unit under test so that the unit under test can perform corresponding tests based on the output signal.

[0006] In an exemplary embodiment, the generating of the corresponding trigger source signal includes: if the trigger source mode is the first mode, generating at least one first trigger source signal; each of the first trigger source signals is used to drive the semiconductor test device to output the output signal of one channel; if the trigger source mode is the second mode, generating at least one second trigger source signal; each of the second trigger source signals is used to drive the semiconductor test device to output the output signal of a pair of channels.

[0007] In an exemplary embodiment, if the trigger source mode is the second mode, at least one second trigger source signal is generated, including: when the trigger source mode is the second mode, at least one trigger source signal pair is generated; each of the trigger source signal pairs includes two of the first trigger source signals; and at least one second trigger source signal is generated based on the signal edge transition of the two first trigger source signals in at least one of the trigger source signal pairs.

[0008] In an exemplary embodiment, generating at least one second trigger source signal based on the signal edge transition of two first trigger source signals in at least one of the trigger source signal pairs includes: traversing one of the first trigger source signals in each of the trigger source signal pairs, the traversing including: when the first trigger source signal is at a rising edge or a falling edge, generating a rising edge of the second trigger source signal, and keeping the second trigger source signal at a high level; traversing the other first trigger source signal in each of the trigger source signal pairs, the traversing including: when the first trigger source signal is at a rising edge or a falling edge, generating a falling edge of the second trigger source signal, and keeping the second trigger source signal at a low level.

[0009] In an exemplary embodiment, according to the parameters and the trigger source signal, driving the semiconductor test equipment in the trigger source mode to follow the input signal output to obtain an output signal, including: based on the parameters and each of the first trigger source signals, in the first mode, respectively controlling the output signals of different channels to follow the input signal output; based on the parameters and each of the second trigger source signals, in the second mode, respectively controlling the output signals of the two channels in each pair of channels to follow the input signal output in reverse.

[0010] In an exemplary embodiment, before obtaining the input signal sent by the host computer, the method includes: receiving the input signal sent by the host computer in a specified packaging method; storing the input signal in a specified storage area so that the semiconductor testing equipment can obtain the input signal from the specified storage area.

[0011] In an exemplary embodiment, the trigger source mode of the semiconductor testing device is determined based on the communication protocol currently supported by the input signal, including: if the communication protocol currently supported by the input signal is the LVDS protocol or the MIPI protocol, then determining the trigger source mode to be the second mode; if the communication protocol currently supported by the input signal is the IIC protocol or the SPI protocol, then determining the trigger source mode to be the first mode.

[0012] In an exemplary embodiment, the parameter includes at least one of the following: an electrical parameter and a trigger source parameter.

[0013] According to one aspect of an embodiment of the present application, a signal transmission device is deployed in a semiconductor test device, and the semiconductor test device is connected between a host computer and a unit under test, and the device includes: a signal acquisition module, used to obtain an input signal sent by the host computer; the input signal can support different communication protocols; a mode configuration module, used to determine the trigger source mode of the semiconductor test device based on the currently supported communication protocol determined by decoding the input signal, so as to configure corresponding parameters for the semiconductor test device under the trigger source mode and generate a corresponding trigger source signal; a signal decoding module, used to drive the semiconductor test device under the trigger source mode according to the parameters and the trigger source signal, to follow the input signal output to obtain an output signal; the output signal corresponds to the communication protocol currently supported by the input signal; and a signal sending module, used to send the output signal to the unit under test, so that the unit under test can perform corresponding tests based on the output signal.

[0014] According to one aspect of an embodiment of the present application, a semiconductor testing device includes: a memory and a processor; wherein the memory is used to store a computer program; the processor is used to read the computer program in the memory and execute the signal transmission method as described above.

[0015] The beneficial effects of the technical solution provided by this application are:

[0016] In the above technical solution, an input signal that can support different communication protocols sent by a host computer is first obtained, and then the trigger source mode of the semiconductor test equipment is determined based on the communication protocol currently supported by the input signal determined by decoding the input signal, so that corresponding parameters are configured for the semiconductor test equipment under the determined trigger source mode and a corresponding trigger source signal is generated. Then, according to the parameters and the trigger source signal, the semiconductor test equipment is driven to follow the obtained input signal under the trigger source mode, and finally an output signal corresponding to the communication protocol currently supported by the input signal is output and sent to the unit under test, so that the unit under test can perform corresponding tests based on the output signal. Based on this, the semiconductor test equipment only needs a small number of trigger source signals to output output signals that support different communication protocols. Not only does it require fewer control ports, it is also beneficial to reduce the complexity of logic control, thereby solving the problem of overly complex logic control when signals supporting different communication protocols are transmitted between the host computer and the unit under test, and it is also beneficial to reduce testing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments of the present application.

[0018] Figure 1 It is a structural block diagram of the signal transmission system involved in this application;

[0019] Figure 2 is a flow chart showing a signal transmission method according to an exemplary embodiment;

[0020] Figure 3 yes Figure 2 A flowchart of an embodiment corresponding to step 310 in an embodiment;

[0021] Figure 4 is a schematic diagram illustrating a process of generating a second trigger source signal according to an exemplary embodiment;

[0022] Figure 5 yes Figure 2 A flowchart of an embodiment corresponding to step 350 in an embodiment;

[0023] Figure 6 is a schematic diagram illustrating a process of generating an output signal of a first channel according to an exemplary embodiment;

[0024] Figure 7 is a schematic diagram illustrating a process of generating output signals of different channels according to an exemplary embodiment;

[0025] Figure 8 is a structural block diagram of a signal transmission device according to an exemplary embodiment;

[0026] Figure 9 The figure is a structural block diagram of a semiconductor testing device according to an exemplary embodiment. DETAILED DESCRIPTION

[0027] The following describes in detail embodiments of the present application, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout identify the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present application and are not to be construed as limiting the present application.

[0028] Those skilled in the art will understand that, unless otherwise stated, the singular forms "a," "an," "the," and "the" used herein may also include the plural forms, and "a plurality" refers to two or more, and other quantifiers are similar. It should be further understood that the term "comprising" used in the specification of this application refers to the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. In addition, "connected" or "coupled" as used herein may include wireless connection or wireless coupling. The term "and / or" used herein describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0029] As mentioned above, in the related art, there is a problem that the logic control is too complicated when signals supporting different communication protocols are transmitted on semiconductor testing equipment.

[0030] To this end, the signal transmission method, device and semiconductor testing equipment provided by this application only require a small amount of trigger source signal to drive the semiconductor testing equipment to output output signals that support different communication protocols. Not only does it require fewer control ports, which is beneficial to reducing the complexity of logic control, but it also helps to reduce testing costs, aiming to solve the above-mentioned technical problems in related technologies.

[0031] To make the purpose, technical solutions, and advantages of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0032] Figure 1 This is a structural block diagram of a signal transmission system involved in a signal transmission method. Figure 1 In the present invention, the signal transmission system includes a host computer, a unit under test, and a semiconductor testing device connected between the host computer and the unit under test.

[0033] The host computer can be a desktop computer, laptop computer, server, etc. The host computer is used to send input signals that can support different communication protocols to the semiconductor test equipment according to the test requirements of the unit under test, and is also used to determine whether the test is normal based on the test results fed back by the unit under test.

[0034] The unit under test can be a display driver chip supporting various communication protocols, a camera module or image sensor module supporting various communication protocols, or other chips supporting various communication protocols, without limitation. The unit under test can perform corresponding tests based on the output signals supporting different communication protocols transmitted by semiconductor test equipment, and feed the test results back to the host computer to determine whether the test is normal.

[0035] Semiconductor testing equipment can be automated test equipment (ATE, Automatic Test Equipment) and other semiconductor testing equipment with testing functions. Figure 1 As shown, the semiconductor testing device includes a signal transmission unit, a signal storage unit, a signal control unit, a signal module unit, a signal processing unit and a signal receiving unit.

[0036] Specifically, the signal transmission unit is used to transmit the input signal that can support different communication protocols sent by the host computer to the semiconductor testing equipment for storage.

[0037] The signal storage unit can be a memory chip with storage function such as DDR, which is used to store the input signal sent by the host computer, so that the semiconductor test equipment can read the input signal and then process it through a series of decoding and other processes to form an output signal and then send it to the unit under test.

[0038] As one of the cores of the semiconductor testing equipment, the signal control unit will determine the trigger source mode of the signal module unit in the semiconductor testing equipment based on the communication protocol currently supported by the input signal determined by decoding the input signal, so as to configure corresponding parameters for the signal module unit in the semiconductor testing equipment under the determined trigger source mode, and generate a trigger source signal corresponding to the communication protocol currently supported by the input signal.

[0039] As another core of the semiconductor test module, the signal module unit will drive the semiconductor test equipment in the trigger source mode according to the parameters configured by the signal control unit and the generated trigger source signal, follow the input signal output to obtain the output signal corresponding to the communication protocol currently supported by the input signal, and transmit the output signal to the signal processing unit in the semiconductor test equipment. Figure 1 In the figure, only two subunits of the signal module unit are shown, namely subunit A and subunit B. Each subunit is used to form the output signal of a channel. The semiconductor test equipment can configure different numbers of subunits for the signal module unit according to the hardware resources, which does not constitute a specific limitation here. Based on this, the subunits of the signal module unit can be used as independent modules with the characteristics of non-interference with each other, so that they can flexibly form output signals supporting different communication protocols according to the test requirements of the unit under test. For example, subunit A forms an output signal supporting the MIPI protocol, and subunit B forms an output signal supporting the LVDS protocol. In this way, not only the scalability of the signal transmission system is enhanced, each subunit can be combined for output to meet different application scenarios, but also the independence and accuracy of the signals transmitted by each subunit are guaranteed.

[0040] The signal processing unit can be used to filter, amplify, and shape the output signal so that the output signal formed by the signal module unit can meet the subsequent signal transmission requirements. It is worth mentioning that in Figure 1 In the figure, only two subunits of the signal processing unit are shown, namely subunit A and subunit B. Each subunit is connected to a subunit of the signal module unit and is used to process the output signal of one channel. The semiconductor test equipment can configure different numbers of subunits for the signal processing unit based on hardware resources, provided that the number of subunits is consistent with the number of subunits configured by the semiconductor test equipment for the aforementioned signal module unit. This does not constitute a specific limitation. In this way, the output signals generated by the subunits of the signal module unit will be transmitted to the corresponding subunits of the signal processing unit for processing, further ensuring the independence and accuracy of the signals transmitted by each subunit.

[0041] The signal receiving unit is used to transmit the test results fed back by the tested unit to the host computer via the signal control unit and the signal transmission unit, so that the host computer can determine whether the test is normal based on the test results.

[0042] Based on the semiconductor testing equipment in the above-mentioned signal control system, it is possible to drive the semiconductor testing equipment to output output signals supporting different communication protocols while generating a small amount of trigger source signals. Not only does it require fewer control ports, which is beneficial to reducing the complexity of logic control, but it is also beneficial to reducing testing costs, and ultimately effectively solves the problem of overly complex logic control when signals supporting different communication protocols are transmitted on semiconductor testing equipment in related technologies.

[0043] See also Figure 2 , the embodiment of the present application provides a signal transmission method, which is applied to semiconductor testing equipment. The structure of the semiconductor testing equipment can be as follows Figure 1 As shown, it is connected between the host computer and the unit under test.

[0044] like Figure 2 As shown, the method may include the following steps:

[0045] Step 310: Acquire the input signal sent by the host computer.

[0046] The input signal can support different communication protocols. In one possible implementation, the communication protocols include, but are not limited to, LVDS, MIPI, RGB, IIC, and SPI. In other words, the input signal is encoded by the host computer based on the communication protocol supported by the unit under test and the corresponding test requirements. For example, if the unit under test is a display driver chip that supports the MIPI protocol, the input signal also supports the MIPI protocol.

[0047] In this embodiment, the input signal sent by the host computer is pre-stored in a designated storage area of ​​the semiconductor test equipment, so that the semiconductor test equipment can obtain the input signal from the designated storage area.

[0048] Specifically, the semiconductor test equipment first receives the input signal sent by the host computer in a specified packaging method, and then stores the input signal in a specified storage area so that the semiconductor test equipment can obtain the input signal from the specified storage area. Figure 1 In this context, the designated storage area refers to the signal storage unit. The host computer transmits the input signal line to the semiconductor test equipment. Within the semiconductor test equipment, the signal is then transmitted via the signal transmission unit to the signal storage unit for storage. This section explains that different communication protocols can be configured with different packetization methods to avoid information loss or errors due to incompatibility between devices.

[0049] Of course, in other embodiments, the semiconductor testing equipment can also transmit the input signal sent by the host computer in real time, that is, the host computer sends the input signal to the semiconductor testing equipment, and in the semiconductor testing equipment, it is directly sent to the signal control unit for subsequent processing, so as to improve the real-time performance of signal transmission and thus improve the testing efficiency of the unit under test. This embodiment does not constitute a specific limitation to this.

[0050] Step 330 , based on the currently supported communication protocol determined by decoding the input signal, determine the trigger source mode of the semiconductor test equipment, configure corresponding parameters for the semiconductor test equipment under the determined trigger source mode, and generate a corresponding trigger source signal.

[0051] As mentioned above, the input signal is encoded by the host computer according to the communication protocol supported by the unit under test and the corresponding test requirements. Then, after the host computer sends and stores the input signal to the semiconductor test equipment, the semiconductor test equipment can determine the communication protocol currently supported by the input signal by decoding the input signal, and then determine the trigger source mode corresponding to the communication protocol currently supported by the input.

[0052] Among them, the trigger source mode is used to indicate the follow-up output mode of the semiconductor test equipment for the input signal under the currently supported communication protocol. In one possible implementation, the follow-up output mode includes following the input signal output and following the input signal reverse output. Accordingly, in one possible implementation, the trigger source mode includes a first mode and a second mode. Specifically, the first mode means that the output signal of any channel follows the input signal output; the second mode means that the output signals of the two channels in each pair of channels follow the input signal reverse output. For example, assuming the input signal is 0, in the first mode, the output signal of the first channel is 0; in the second mode, if the output signal of the first channel is 0, the output signal of the second channel is 1.

[0053] In one possible implementation, when the communication protocol supported by the input signal is the IIC protocol or the SPI protocol, it can be considered that the input signal transmitted between the host computer and the unit under test is a low-speed single-ended signal, and the trigger source mode can be specified as the first mode for the semiconductor test equipment. Then, if the communication protocol currently supported by the input signal is the IIC protocol or the SPI protocol, it can be determined that the trigger source mode of the semiconductor test equipment is the first mode. Of course, in other embodiments, when the trigger source mode of the semiconductor test equipment is the first mode, it is not limited to the input signal being a low-speed single-ended signal supporting the IIC protocol or the SPI protocol. The input signal can also be a low-speed single-ended signal supporting other communication protocols, which does not constitute a specific limitation here.

[0054] In one possible implementation, when the communication protocol supported by the input signal is the LVDS protocol or the MIPI protocol, it can be considered that the input signal transmitted between the host computer and the unit under test is a high-speed differential signal, and the trigger source mode can be specified as the second mode for the semiconductor test equipment. Then, if the communication protocol currently supported by the input signal is the LVDS protocol or the MIPI protocol, it can be determined that the trigger source mode of the semiconductor test equipment is the second mode. Of course, in other embodiments, when the trigger source mode of the semiconductor test equipment is the second mode, it is not limited to the input signal being a low-speed single-ended signal supporting the LVDS protocol or the MIPI protocol. The input signal can also be a high-speed differential signal supporting other communication protocols. This does not constitute a specific limitation here.

[0055] In one possible implementation, parameters that can be configured for semiconductor test equipment in different trigger source modes include, but are not limited to, electrical parameters and trigger source parameters. Electrical parameters include, but are not limited to, output signal level, output signal phase delay, and line loss compensation. Trigger source parameters include, but are not limited to, the number of channels, inter-channel delay, and polarity inversion.

[0056] Step 350 : According to the parameters and the trigger source signal, the semiconductor test equipment is driven in a trigger source mode to output an output signal following the input signal.

[0057] The output signal corresponds to the communication protocol currently supported by the input signal.

[0058] As previously mentioned, the trigger source mode includes a first mode and a second mode, wherein the first mode means that the output signal of any channel follows the input signal for output; the second mode means that the output signals of the two channels in each pair of channels follow the input signal for output in the opposite direction. Based on this, in this embodiment, the output signal following output process includes, in the first mode, driving the output signal of any channel to follow the input signal for output based on the corresponding trigger source signal, and the level, phase delay, line loss compensation, etc. of the output signal of any channel are output according to the corresponding parameters; in the second mode, driving the output signals of the two channels in each pair of channels to follow the input signal for output in the opposite direction based on the corresponding trigger source signal, and the level, phase delay, line loss compensation, etc. of the output signals of different channels are output according to the corresponding parameters.

[0059] Step 370: Send the output signal to the unit under test, so that the unit under test can perform corresponding tests based on the output signal.

[0060] For semiconductor test equipment, after obtaining the output signal, it can be sent to the unit under test. Figure 1In semiconductor testing equipment, after obtaining the output signals of different channels, each sub-unit in the signal module unit is first transmitted to the corresponding sub-unit in the signal processing unit, and then transmitted to the unit under test through the sub-units in the signal processing unit.

[0061] As for the unit under test, after receiving the output signal, it can perform corresponding tests based on the output signal to obtain test results. In one possible implementation, the test results include but are not limited to: the voltage of the output signal and the phase delay of the output signal.

[0062] It is worth mentioning that the host computer can also adjust and optimize the signal transmission system according to the test results fed back by the unit under test, thereby realizing closed-loop control of the signal transmission system and fully ensuring the test accuracy of the unit under test. Figure 1 The test results are first fed back to the semiconductor test equipment through the unit under test. In the semiconductor test equipment, they are first transmitted to the signal control unit through the signal receiving unit, and then the signal control unit finally feeds back to the host computer through the signal transmission unit.

[0063] For example, if the hardware circuit wiring of the semiconductor test equipment is too long, resulting in line loss, the voltage of the output signal transmitted to the unit under test may be low. In this case, a reference voltage can be set for the comparator in the semiconductor test equipment. If the voltage of the output signal indicated by the test result fed back by the unit under test is less than the reference voltage, the comparator output is 0, indicating that the test is abnormal. If the voltage of the output signal indicated by the test result is greater than or equal to the reference voltage, the comparator output is 1, indicating that the test is normal. Then, the level of the output signal generated by the signal module unit can be adjusted until the comparator output changes from 0 to 1, thereby ensuring that the test is normal. For example, assuming that the test result indicates that the output signal received by the unit under test is 000011110000, if the comparator output is also 000011110000, there is no phase delay in the output signal sent to the unit under test, indicating that the test is normal. Conversely, if the comparator output is 0000011110000, there is a phase delay in the output signal sent to the unit under test, that is, it is delayed by 1 CLK cycle, indicating that the test is abnormal. At this time, the delay of the corresponding pin of the signal module unit can be adjusted until the test is normal.

[0064] Through the above process, using the semiconductor test equipment connected between the host computer and the unit under test, only a small amount of trigger source signal is needed to drive the semiconductor test equipment to output output signals that support different communication protocols. Not only does it require fewer control ports, which is beneficial to reducing the complexity of logic control, but it also helps to reduce testing costs, and effectively solves the problem of overly complex logic control when signals supporting different communication protocols are transmitted on semiconductor test equipment.

[0065] See also Figure 3 In an exemplary embodiment of the present application, the generating of the corresponding trigger source signal in step 330 may include the following steps:

[0066] Step 311: If the trigger source mode is the first mode, generate at least one first trigger source signal.

[0067] Wherein, each first trigger source signal is used to drive the semiconductor testing equipment to output an output signal of one channel.

[0068] As previously mentioned, the input signal is encoded by the host computer according to the communication protocol supported by the UUT and the corresponding test requirements, wherein the test requirements at least include the output state of the output signal of the UUT for testing (such as the level of the output signal). Then, after the host computer transmits and stores the input signal to the semiconductor test equipment, the semiconductor test equipment can determine the output state of the output signal by decoding the input signal, and then drive the semiconductor test equipment to generate the corresponding first trigger source signal in the first mode based on the determined output state of the output signal.

[0069] Step 313: If the trigger source mode is the second mode, generate at least one second trigger source signal.

[0070] Each second trigger source signal is used to drive the semiconductor test equipment to output a pair of channel output signals.

[0071] Specifically, in the first step, when the trigger source mode is the second mode, at least one trigger source signal pair is generated, wherein each trigger source signal pair includes two first trigger source signals.

[0072] Similarly to the process of generating the first trigger source signal, after the host computer sends and stores the input signal to the semiconductor test equipment, the semiconductor test equipment can determine the output state of the output signal used for testing of the unit under test (such as the level of the output signal) by decoding the input signal, and then drive the semiconductor test equipment to generate a corresponding trigger source signal pair in the second mode based on the determined output state of the output signal. The trigger source signal pair can include at least two first trigger source signals.

[0073] In the second step, at least one second trigger source signal is generated according to the signal edge transition conditions of two first trigger source signals in at least one trigger source signal pair.

[0074] Specifically, one of the first trigger source signals in each trigger source signal pair is traversed, and the traversal includes: when one of the first trigger source signals is at a rising edge or a falling edge, generating a rising edge of the second trigger source signal, and keeping the second trigger source signal at a high level; or, the other first trigger source signal in each trigger source signal pair is traversed, and the traversal includes: when the other first trigger source signal is at a rising edge or a falling edge, generating a falling edge of the second trigger source signal, and keeping the second trigger source signal at a low level.

[0075] Figure 4 The generation process of the second trigger source signal in an exemplary embodiment is shown. Figure 4 In the figure, R0 represents the first trigger source signal in the trigger source signal pair, R1 represents the other trigger source signal in the trigger source signal pair, and S0 represents the second trigger source signal. Figure 5 For example, if the first trigger source signal R0 changes from 0 to 1, it can also be understood as changing from a low level to a high level, indicating that the first trigger source signal R0 is on a rising edge. At this time, the second trigger source signal S0 synchronously changes from 0 to 1, that is, the second trigger source signal S0 is on a rising edge, and then remains at a high level until the next falling edge. Similarly, if the first trigger source signal R0 changes from 1 to 0, it can also be understood as changing from a high level to a low level, indicating that the first trigger source signal R0 is on a falling edge. At this time, the second trigger source signal S0 synchronously changes from 0 to 1, that is, the second trigger source signal S0 is on a rising edge, and then remains at a high level until the next falling edge.

[0076] Continue reading Figure 4 If the first trigger source signal R1 changes from 0 to 1, it can also be understood as changing from a low level to a high level, indicating that the first trigger source signal R1 is on a rising edge. At this time, the second trigger source signal S0 synchronously changes from 1 to 0, that is, the second trigger source signal S0 is on a falling edge, and then remains at a low level until the next rising edge. Similarly, if the first trigger source signal R1 changes from 1 to 0, it can also be understood as changing from a high level to a low level, indicating that the first trigger source signal R1 is on a falling edge. At this time, the second trigger source signal S0 synchronously changes from 1 to 0, that is, the second trigger source signal S0 is on a falling edge, and then remains at a low level until the next rising edge.

[0077] Under the action of the above-mentioned embodiments, the generation of a small number of trigger source signals is realized. Since the generation process involves different trigger source modes, the generation of a small number of trigger source signals is actually related to the communication protocol currently supported by the input signal, thereby enabling the semiconductor test equipment to output output signals supporting different communication protocols based on a small number of trigger source signals. This can effectively solve the problem of overly complex logical control when signals supporting different communication protocols are transmitted between the host computer and the unit under test.

[0078] See also Figure 5 In an exemplary embodiment provided in the present application, step 350 may include the following steps:

[0079] Step 351 : Based on the parameters and the first trigger source signals, in the first mode, the output signals of different channels are controlled to follow the output of the input signals.

[0080] As mentioned above, the output signal following output process of step 351 means that, in the first mode, the output signal of any channel is driven to follow the input signal output based on the corresponding trigger source signal, and the level, phase delay, line loss compensation, etc. of the output signal of any channel are output according to the corresponding parameters.

[0081] Figure 6 FIG. 1 shows a process of generating an output signal of a first channel in a first mode in an exemplary embodiment. Figure 6 In the figure, D0 represents the input signal, R0 represents the first trigger source signal, and DUT0 represents the output signal of the first channel. Figure 6 As shown in the figure, if the input signal D0 is 0, the output signal DUT0 of the first channel is 0. Conversely, if the input signal D0 is 1, the output signal DUT0 of the first channel is 1. It is worth mentioning that the transition edge of the output signal DUT0 of the first channel remains consistent with the transition edge of the first trigger source signal R0. It can also be understood that the signal edge of the output signal DUT0 of the first channel transitions under the drive of the first trigger source signal R0.

[0082] In addition, please refer to Figure 1 The signal module unit can include multiple subunits, which can accordingly generate multiple channels of output signals. Based on this, in the first mode, the output signal of each channel is controlled by a different first trigger source signal. For example, in the signal module unit, for subunit A, the first trigger source signal R0 controls the output of the first channel's output signal DUT0; for subunit B, the first trigger source signal R1 controls the output of the second channel's output signal DUT1.

[0083] Step 353 : Based on the parameters and each second trigger source signal, in the second mode, the output signals of the two channels in each pair of channels are controlled to be output in the opposite direction of the input signal.

[0084] As mentioned above, the output signal following output process of step 353 means that, in the second mode, the output signals of the two channels in each pair of channels are driven to follow the input signal in reverse output based on the corresponding trigger source signal, and the levels, phase delays, line loss compensation, etc. of the output signals of different channels are output according to the corresponding parameters.

[0085] Figure 7 FIG. 4 shows a process of generating output signals of different channels in the second mode in an exemplary embodiment. Figure 7 In the figure, D0 represents the input signal, S0 represents the second trigger source signal, DUT0 represents the output signal of the first channel in the first pair of channels, and DUT1 represents the output signal of the second channel in the first pair of channels. Figure 7 As shown in the figure, when the input signal is D0, when the output signal DUT0 of the first channel is 0, the output signal DUT1 of the second channel is 1. Conversely, when the output signal DUT0 of the first channel is 1, the output signal DUT1 of the second channel is 0. It is worth mentioning that the transition edge of the output signal DUT0 / DUT1 remains consistent with the transition edge of the second trigger source signal S0. It can also be understood that the signal edge of the output signal DUT0 / DUT1 transitions under the drive of the second trigger source signal S0.

[0086] In addition, please refer to Figure 1 , the signal module unit may include multiple sub-units, and accordingly, multiple channels of output signals may be formed. Based on this, in the second mode, the output signals of the two channels in each pair of channels are controlled by a trigger source signal pair (including two first trigger source signals), which can also be considered to be controlled by the same second trigger source signal. For example, in the signal module unit, for sub-unit A, the output signal DUT0 of the first channel is output, and for sub-unit B, the output signal DUT1 of the second channel is output, and the output signal DUT0 of the first channel and the output signal DUT1 of the second channel are controlled by the first trigger source signal R0 and the first trigger source signal R1 (that is, the second trigger source signal S0), and so on, DUT2 and DUT3 are controlled by S1.

[0087] Under the effect of the above-mentioned embodiments, it is realized that the semiconductor test equipment can output output signals supporting different communication protocols based on a small number of trigger source signals. This not only greatly reduces the number of required control ports, but also helps to reduce the complexity of logical control when transmitting signals between the host computer and the unit under test, and it also helps to reduce testing costs. It can effectively solve the problem of overly complex logical control when signals supporting different communication protocols are transmitted between the host computer and the unit under test.

[0088] The following are embodiments of the apparatus of the present application, which can be used to perform the signal transmission method involved in the present application. For details not disclosed in the apparatus embodiments of the present application, please refer to the method embodiments of the signal transmission method involved in the present application.

[0089] See also Figure 8 In an embodiment of the present application, a signal transmission device 900 is provided, which is deployed in a semiconductor testing device connected between a host computer and a unit under test.

[0090] like Figure 8 As shown, the signal transmission device 900 includes but is not limited to: a signal acquisition module 910 , a mode configuration module 930 , a signal decoding module 950 and a signal sending module 970 .

[0091] The signal acquisition module 910 is used to acquire the input signal sent by the host computer. The input signal can support different communication protocols.

[0092] The mode configuration module 930 is used to determine the trigger source mode of the semiconductor test equipment based on the currently supported communication protocol determined by decoding the input signal, so as to configure corresponding parameters for the semiconductor test equipment in the trigger source mode and generate corresponding trigger source signals.

[0093] The signal decoding module 950 is used to drive the semiconductor test equipment in the trigger source mode according to the parameters and the trigger source signal, and output the output signal according to the input signal. The output signal corresponds to the communication protocol currently supported by the input signal.

[0094] The signal sending module 970 is configured to send the output signal to the unit under test, so that the unit under test can perform corresponding tests based on the output signal.

[0095] In an exemplary embodiment, the mode configuration module 930 is also used to generate at least one first trigger source signal if the trigger source mode is the first mode; each first trigger source signal is used to drive the semiconductor test equipment to output an output signal of a channel; if the trigger source mode is the second mode, at least one second trigger source signal is generated; each second trigger source signal is used to drive the semiconductor test equipment to output an output signal of a pair of channels.

[0096] In an exemplary embodiment, the mode configuration module 930 is also used to generate at least one trigger source signal pair when the trigger source mode is the second mode; each trigger source signal pair includes two first trigger source signals; and at least one second trigger source signal is generated based on the signal edge transition of the two first trigger source signals in at least one trigger source signal pair.

[0097] In an exemplary embodiment, the mode configuration module 930 is further used to traverse one of the first trigger source signals in each of the trigger source signal pairs, and the traversal includes: when one of the first trigger source signals is at a rising edge or a falling edge, generating a rising edge of the second trigger source signal, and keeping the second trigger source signal at a high level; and traversing the other first trigger source signal in each of the trigger source signal pairs, and the traversal includes: when the other first trigger source signal is at a rising edge or a falling edge, generating a falling edge of the second trigger source signal, and keeping the second trigger source signal at a low level.

[0098] In an exemplary embodiment, the mode configuration module 930 is also used to determine that the trigger source mode is the second mode if the communication protocol currently supported by the input signal is the LVDS protocol or the MIPI protocol; if the communication protocol currently supported by the input signal is the IIC protocol or the SPI protocol, then the trigger source mode is determined to be the first mode.

[0099] In an exemplary embodiment, the signal decoding module 950 is also used to control the output signals of different channels to follow the input signal output in the first mode based on the parameters and each first trigger source signal; and to control the output signals of the two channels in each pair of channels to follow the input signal output in the reverse direction in the second mode based on the parameters and each second trigger source signal.

[0100] In an exemplary embodiment, the signal transmission device 900 is further configured to receive input signals sent by a host computer in a specified packaging manner; and store the input signals in a specified storage area so that semiconductor testing equipment can obtain the input signals from the specified storage area.

[0101] It should be noted that the division of units and / or modules in the embodiments of the present application is schematic and is merely a logical functional division. In actual implementation, there may be other division methods. In addition, the functional units and / or modules in the various embodiments of the present application may be integrated into one processing unit and / or module, or each unit and / or module may exist physically alone, or two or more units and / or modules may be integrated into one unit and / or module. The above-mentioned integrated units and / or modules may be implemented in the form of hardware or in the form of software functional units and / or modules.

[0102] If the integrated units and / or modules are implemented in the form of software functional units and / or modules and sold or used as independent products, they can be stored in a processor-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the relevant technology or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0103] Figure 9 A structural block diagram of a semiconductor testing device according to an exemplary embodiment is shown. Figure 9 As shown, the semiconductor testing device 1100 at least includes: a processor 1110 and a memory 1120 .

[0104] exist Figure 9 In the embodiment of the present invention, the bus architecture may include any number of interconnected buses and bridges, specifically linking various circuits such as one or more processors represented by processor 1110 and memory represented by memory 1120. The bus architecture may also link various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be further described in this application. The bus interface provides an interface.

[0105] The processor 1110 is responsible for managing the bus architecture and general processing, and the memory 1120 can store data used by the processor 1110 when performing operations, such as computer programs.

[0106] Optionally, the processor 1110 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or a complex programmable logic device (CPLD). The processor 1110 may also employ a multi-core architecture. The processor 1110 and the memory 1120 may also be physically separated.

[0107] The processor 1110 calls the computer program stored in the memory 1120 to execute any one of the signal transmission methods provided in the above embodiments of the present application according to the obtained computer program.

[0108] It should be noted here that the above-mentioned device provided in the embodiment of the present application can implement all the method steps implemented in the above-mentioned method embodiment and can achieve the same technical effect. The parts and beneficial effects of this embodiment that are the same as those in the method embodiment will not be described in detail here.

[0109] Compared with related technologies, using semiconductor test equipment connected between a host computer and a unit under test, only a small amount of trigger source signals is needed to drive the semiconductor test equipment to output output signals that support different communication protocols. Not only does it require fewer control ports, which is beneficial to reducing the complexity of logic control, but it also helps to reduce testing costs, and effectively solves the problem of overly complex logic control when signals supporting different communication protocols are transmitted between the host computer and the unit under test.

[0110] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage and optical storage, etc.) that contain computer-usable program code.

[0111] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer-executable instructions. These computer-executable instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0112] These processor-executable instructions may also be stored in a processor-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the processor-readable memory produce an article of manufacture comprising an instruction device that implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0113] These processor-executable instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are performed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable device to implement the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0114] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown in sequence as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the flowcharts of the accompanying drawings may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0115] The above description is only a partial implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A signal transmission method, characterized in that: Applied to semiconductor testing equipment, the semiconductor testing equipment is connected between a host computer and a unit under test, and the method includes: Obtaining an input signal sent by the host computer; the input signal can support different communication protocols; Determining a trigger source mode of the semiconductor test equipment based on a currently supported communication protocol determined by decoding the input signal, so as to configure corresponding parameters for the semiconductor test equipment under the determined trigger source mode and generate a corresponding trigger source signal; According to the parameters and the trigger source signal, the semiconductor test device is driven in the trigger source mode to follow the input signal output to obtain an output signal; the output signal corresponds to the communication protocol currently supported by the input signal; The output signal is sent to the unit under test, so that the unit under test can perform corresponding tests based on the output signal.

2. The method according to claim 1, wherein The generating of the corresponding trigger source signal includes: If the trigger source mode is the first mode, at least one first trigger source signal is generated; each first trigger source signal is used to drive the semiconductor test device to output the output signal of one channel; If the trigger source mode is the second mode, at least one second trigger source signal is generated; each second trigger source signal is used to drive the semiconductor test equipment to output the output signal of a pair of channels.

3. The method according to claim 2, wherein If the trigger source mode is the second mode, generating at least one second trigger source signal includes: When the trigger source mode is the second mode, generating at least one trigger source signal pair; each of the trigger source signal pairs includes two of the first trigger source signals; At least one second trigger source signal is generated according to the signal edge transition conditions of two first trigger source signals in at least one trigger source signal pair.

4. The method according to claim 3, wherein Generating at least one second trigger source signal according to the signal edge transition conditions of two first trigger source signals in at least one trigger source signal pair includes: Traversing one of the first trigger source signals in each of the trigger source signal pairs, the traversing comprising: generating a rising edge of the second trigger source signal when one of the first trigger source signals is at a rising edge or a falling edge, and maintaining the second trigger source signal at a high level; The other first trigger source signal in each of the trigger source signal pairs is traversed, and the traversal includes: when the other first trigger source signal is at a rising edge or a falling edge, generating a falling edge of the second trigger source signal, and keeping the second trigger source signal at a low level.

5. The method according to claim 2, wherein The step of driving the semiconductor test device in the trigger source mode according to the parameter and the trigger source signal to output an output signal following the input signal includes: Based on the parameters and each of the first trigger source signals, in the first mode, the output signals of different channels are respectively controlled to follow the output of the input signal; Based on the parameters and each second trigger source signal, in the second mode, the output signals of the two channels in each pair of channels are respectively controlled to be output in the reverse direction following the input signal.

6. The method according to any one of claims 1 to 5, characterized in that Before obtaining the input signal sent by the host computer, the method includes: Receive the input signal sent by the host computer according to the specified packaging method; The input signal is stored in a designated storage area, so that the semiconductor testing equipment can obtain the input signal from the designated storage area.

7. The method according to any one of claims 1 to 5, characterized in that The determining of the trigger source mode of the semiconductor test equipment based on the communication protocol currently supported by the input signal includes: If the communication protocol currently supported by the input signal is the LVDS protocol or the MIPI protocol, determining that the trigger source mode is the second mode; If the communication protocol currently supported by the input signal is the IIC protocol or the SPI protocol, the trigger source mode is determined to be the first mode.

8. The method according to any one of claims 1 to 5, characterized in that The parameters include at least one of the following: electrical parameters and trigger source parameters.

9. A signal transmission device, characterized in that: Deployed in a semiconductor test device connected between a host computer and a unit under test, the device includes: A signal acquisition module, used to acquire the input signal sent by the host computer; the input signal can support different communication protocols; a mode configuration module, configured to determine a trigger source mode of the semiconductor test device based on a currently supported communication protocol determined by decoding the input signal, so as to configure corresponding parameters for the semiconductor test device under the trigger source mode and generate a corresponding trigger source signal; a signal decoding module, configured to drive the semiconductor test device in the trigger source mode according to the parameter and the trigger source signal, to output an output signal following the input signal; the output signal corresponds to the communication protocol currently supported by the input signal; The signal sending module is used to send the output signal to the unit under test, so that the unit under test can perform corresponding tests based on the output signal.

10. A semiconductor testing device, characterized in that: include: memory and a processor; wherein, The memory is used to store computer programs; The processor is configured to read the computer program in the memory and execute the signal transmission method according to any one of claims 1 to 8.

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