Super junction JFET, method for manufacturing super junction JFET, and electronic circuit

Abstract

The invention discloses a super junction JFET, a method for manufacturing the super junction JFET and an electronic circuit comprising the super junction JFET. The super junction JFET has a threshold voltage and a depletion voltage. According to one example, the depletion voltage is less than four times the magnitude of the threshold voltage. According to another example, the depletion voltage is less than 40 V or less than 30 V.

Description

[0001] This description relates generally to superjunction JFETs and electronic circuits having superjunction JFETs.

[0002] A superjunction JFET is a JFET (junction field-effect transistor) that operates according to the compensation principle. It includes a drift region in which n-doped and p-doped semiconductor regions are arranged adjacent to each other. When the device is in the blocking state, the n-doped and p-doped regions deplete each other.

[0003] One example involves a superjunction JFET having a threshold voltage and a depletion voltage, wherein the magnitude of the depletion voltage is less than 4 times the magnitude of the threshold voltage.

[0004] Another example relates to a superjunction JFET having a depletion voltage less than 40 V. According to one example, the depletion voltage is less than 30 V.

[0005] Another example relates to an electronic circuit comprising a superjunction JFET according to one of these examples, and further comprising an electronic switch connected in series with the drain-source path of the superjunction JFET, and an inductive circuit connected in parallel with the drain-source path of the superjunction JFET.

[0006] Yet another example relates to a method. The method includes forming implanted trenches in a semiconductor body, such that the trenches are spaced apart from one another in a first lateral direction of the semiconductor body and separated from one another by semiconductor mesa regions, forming a first region of a first doping type in each mesa region using a first implantation process, forming a second region of a second doping type complementary to the first doping type using a second implantation process, and filling the implanted trenches with a single crystalline semiconductor material in an epitaxial growth process. The method also includes forming a gate trench in the semiconductor body; forming a third region of the second doping type along sidewalls of the gate trench and a fourth region of the second doping type along a bottom of the gate trench, such that each second region abuts at least one of the third region or the fourth region; and forming a gate electrode in the gate trench.

[0007] The following examples are explained with reference to the accompanying drawings. The accompanying drawings are used to illustrate certain principles and therefore only illustrate aspects necessary for understanding these principles. The accompanying drawings are not to scale. In the accompanying drawings, the same reference numerals represent the same features.

[0008] Figure 1 shows the circuit symbol of a superjunction JFET;

[0009] Figure 2 shows the characteristic curve of the output capacitance of the super junction device;

[0010] Figure 3 Shown according to Figure 1 Application circuit of super junction JFET;

[0011] Figure 4 schematically shows a cross-sectional view of a section of a superjunction JFET;

[0012] Figure 5 Schematically shows the Figure 4 The line AA' shown is based on Figure 4 The doping concentration in the JFET;

[0013] Figure 6 Shown along Figure 4 The effective doping concentration (net doping concentration) of the line AA' is shown;

[0014] Figure 7 shows that when the JFET is blocked, the Figure 4 The horizontal electric field along the line AA' is shown; and

[0015] Figures 8A-8D Shown for forming Figure 4 One example of an approach to a superjunction JFET of the type shown.

[0016] In the following detailed description, reference is made to the accompanying drawings, which form part of the specification and, for illustrative purposes, show examples of how the invention may be used and implemented. It should be understood that the features of the various embodiments described herein may be combined with each other unless otherwise specifically indicated.

[0017] Figure 1 The circuit symbol of the superjunction JFET 1 is shown, and the internal capacitance of the JFET is shown. The superjunction JFET includes a drive input for applying a drive voltage Vgs. Figure 1 In the example shown, the drive input is formed by the gate terminal (gate node) G and the source terminal (source node) S of the JFET. The JFET also includes a load path extending between a first load path terminal (first load path node) and a second load path node terminal (second load path node). Figure 1 In the example shown, the first load path terminal is the drain terminal D of the JFET and the second load path terminal is the source terminal S of the JFET.

[0018] The JFET is turned on or off depending on the voltage level of the drive voltage Vgs. When the drive voltage Vgs is higher than the threshold voltage, the JFET is turned on, and when the drive voltage is lower than the threshold voltage, the JFET is blocked. Hereinafter, the operating state in which the JFET is turned on is referred to as the on-state, and the operating state in which the JFET is blocked is referred to as the blocking state.

[0019] When a voltage Vds is applied across the load path and a load current Ids flows through the load path, the JFET is in the on-state. In this case, the load current Ids flowing through the load path in the on-state is a current that is higher than the leakage current that may flow through the load path when the JFET is in the blocking state. According to one example, the drive voltage Vgs is equal to the threshold voltage so that the JFET enters the on-state when the load current reaches a predefined current density threshold. Thus, the JFET is in the on-state when the current density in the JFET is equal to or higher than the predefined current density threshold, and the drive voltage Vgs is equal to the threshold voltage when the current density has reached the predefined current density threshold.

[0020] According to one example, the current density is given by the load current Ids through the JFET 1 divided by the size of the active area of ​​the JFET. The current density threshold depends on the specific implementation of the JFET 1. According to one example, the current density threshold is 10 mA / mm 2 (per 1mm 2 Size of active area 10mA (milliampere)) and 100mA / mm 2 (per 1mm 2 The size of the active area is the size of the area occupied by the transistor cell of the JFET in the semiconductor body. An example of a transistor cell will be further explained below in this article.

[0021] For example, the JFET is implemented as a silicon carbide (SiC) JFET or a silicon (Si) JFET. In particular, 10 mA / mm 2 and 100mA / mm 2 Current density thresholds between 0 and 100 Å are applicable to SiC JFETs.

[0022] According to one example, the JFET is an N-type (N-channel) JFET. In this example, the threshold voltage is negative. The threshold voltage is, for example, in the range between -5V and -30V, so that the magnitude of the threshold voltage is, for example, in the range between 5V and 30V.

[0023] In the on-state, the JFET is configured to conduct current through the load path. In the blocking state, the JFET is configured to block as long as the load path voltage Vds across the load path is lower than the rated blocking voltage of the JFET. The rated blocking voltage depends on the device size and is in the range of several hundred volts, for example, between 400V and 800V. The rated blocking voltage is the highest allowable load path voltage Vds at which the JFET safely blocks. In the blocking state, at most leakage current can flow through the load path. For example, the leakage current is in the range between a few nanoamperes (nA) and a few microamperes (μA).

[0024] The JFET has a drain-source capacitance. The drain-source capacitance is the internal capacitance of the JFET that is effective between the drain and source terminals D, S. For illustration purposes, Figure 1 In FIG, the drain-source capacitance is represented by a first capacitor 11 connected between the drain and source terminals D, S. In addition, the JFET has a gate-drain capacitance. The gate-drain capacitance is also the internal capacitance of the JFET. For the purpose of illustration, Figure 1 In Figure 1, the gate-drain capacitance is represented by a second capacitor 12 connected between the gate terminal G and the drain current terminal D. Together, the drain-source capacitance 11 and the gate-drain capacitance 12 form the output capacitance of the JFET. In a superjunction JFET (in the same manner as in a superjunction MOSFET), the output capacitance is nonlinear. This means that the capacitance value Coss of the output capacitor depends on the load path voltage Vds. Furthermore, the capacitance value of the output capacitor decreases as the load path voltage Vds increases.

[0025] The characteristic curve of this nonlinear output capacitor is Figure 2 It is shown in the figure and marked with 101. Figure 2 The graph in FIG is semi-logarithmic. As can be seen from characteristic curve 101, when the device is blocked, the capacitance value Coss initially decreases very rapidly, and the load path voltage Vds begins to increase from zero. After this rapid decrease, the capacitance value Coss decreases only very slowly as the load path voltage Vds increases further.

[0026] Superjunction JFETs have a depletion charge. The depletion charge is the integral of the output capacitance Coss over the load path voltage Vds range from zero to the rated blocking voltage. The depletion charge is the charge that flows out of the device (or, depending on the view, into the device) when the load path voltage Vds increases from zero to the rated blocking voltage. Figure 1 For a device with a load path voltage Vds equal to the rated blocking voltage of the JFET, the depletion charge is the charge stored in the drain-source capacitance 11 plus the charge stored in the gate-drain capacitance 12.

[0027] The superjunction JFET has a depletion voltage. The depletion voltage is equal to the voltage value (voltage level) of the load path voltage Vds, at which 80% of the depletion charge has flowed out of the JFET (or flowed into the JFET).

[0028] According to an example, the magnitude of the depletion voltage is lower than 4 times the magnitude of the threshold voltage. According to an example, the magnitude of the depletion voltage is lower than 3 times, 2 times or 1.5 times the magnitude of the threshold voltage. According to an example, the depletion voltage is lower than the magnitude of the threshold voltage.

[0029] According to another example, the superjunction JFET 1 is dimensioned such that its depletion voltage is below 50V, and in particular below 40V, below 30V or even below 20V.

[0030] Implementing the superjunction JFET 1 such that the depletion voltage is related to the threshold voltage according to one of the examples outlined above or below 50 V helps to reduce losses when the superjunction JFET is in operation. This is explained below.

[0031] Figure 3 Shown include Figure 1 The application circuit of the superjunction JFET 1 of the type shown. Figure 3 In the circuit shown, superjunction JFET 1 serves as the low-side switch of the half-bridge. Superjunction JFET 1, acting as the low-side switch, is connected in series with high-side switch 31. The series circuit comprising superjunction JFET 1, acting as the low-side switch, and high-side switch 31 is connected between power supply terminals, between which a power supply voltage Vsup is available. A load 32, such as an inductive load, is connected in parallel with JFET 1. JFET 1 is driven by a driver circuit 33, for example. High-side switch 31, which can be any type of electronic switch, can be controlled by the same driver circuit 33 or any other suitable driver circuit.

[0032] According to one example, inductive load 32 includes at least one inductor 33. According to one example (not shown), inductive load 32 and a half-bridge form a buck converter. In this example, inductive load 33 includes an output capacitor connected in series with inductor 33, and an output voltage is available across the output capacitor. Inductor 33 and the output capacitor form a series circuit connected in parallel with the load path of JFET 11.

[0033] According to one example, the high-side switch 31 and the JFET 1 are alternately driven in an on state and a blocked state. That is, the high-side switch 31 and the JFET 1 are alternately turned on and off. This includes the high-side switch 31 being on when the JFET 1 is blocked, and vice versa. When the high-side switch 31 is on and the JFET 1 is blocked, the power supply voltage Vsup drops across the load 32. When the high-side switch 31 is blocked and the JFET 1 is on, the JFET 1 acts as a freewheeling element or a synchronous rectifier, which enables the current I32 through the inductive load 32 to continue to flow after the high-side switch 31 is turned off. In this operating mode, the current I32 through the inductive load 32 continues to flow along Figure 3 The source-drain current Isd flows in the direction indicated by the arrow, and the source-drain current Isd flows along Figure 3 The direction indicated by the arrow is where the current flows through the JFET.

[0034] According to one example, to avoid crossover current through the half-bridge, a dead time is present between turning off the high-side switch 31 and turning on the JFET 1, which acts as the low-side switch. As explained above, turning on the JFET 1 involves adjusting the voltage level of the drive voltage Vgs to be higher than the threshold voltage of the JFET. In the off state of the JFET 1, the voltage level of the drive voltage is lower than the threshold voltage. If, for example, the threshold voltage is -10V, the voltage level of the drive voltage Vgs is between -15V and -18V to safely maintain the JFET 1 in the off state.

[0035] During the dead time, i.e., when JFET 1 is in the off state, JFET 1 may have received a current I32 flowing through inductor 33. In this operating state, the inductor 33 causes the potential at the drain node of JFET 1 to decrease, causing the gate-drain voltage, which is the voltage between the gate node G and the drain node D, to become higher than the negative threshold voltage of the transistor device, which causes JFET 1 to turn on. In this operating state, the JFET is controlled by the gate-drain voltage rather than the gate-source voltage. If, for example, the gate-source voltage Vgs is -18V in the off state and the threshold voltage is -10V, then when the inductive load 33 reduces the potential at the drain node to approximately -8V relative to the potential at the source node S, JFET 1 begins to turn on.

[0036] When JFET 1 is turned on by adjusting the gate-source voltage above the (negative) threshold voltage, JFET 1 is in the on-state and continues to conduct current 32 through the inductive load 33 .

[0037] As explained above, turning off the JFET is associated with a current flow that charges the output capacitor (depletion current). This current flow causes losses. Basically, the higher the voltage across the circuit path through which the current associated with the charging process flows, the higher the losses.

[0038] Assume that Figure 3 In an electronic circuit of the type shown, the JFET 1 is a conventional JFET. In this example, most of the depletion current flows in the load branch, which is the circuit branch comprising the half-bridge. That is, the load branch is the circuit branch comprising the high-side switch 31 connected in series and the JFET 1 acting as a low-side switch, and across which the supply voltage Vsup is available. The supply voltage Vsup can be in the range of several hundred volts.

[0039] It is desirable to provide a JFET in which such losses are reduced. This is achieved by implementing the superjunction JFET 1 such that the threshold voltage and the depletion voltage are adapted to each other so that the magnitude of the depletion voltage is less than 4 times the magnitude of the threshold voltage, less than 3 times the magnitude of the threshold voltage, less than 2 times (twice) the magnitude of the threshold voltage, less than 1.5 times the magnitude of the threshold voltage, or even less than the magnitude of the threshold voltage, or by implementing the superjunction JFET 1 such that the threshold voltage is less than 50V.

[0040] With such dimensioning of the superjunction MOSFET 1, a large part of the depletion current associated with the depletion charge can flow via the gate terminal G (and the drive circuit 33), so that this current does not flow via the load branch, across which a significantly higher voltage is available and where this current would result in significantly higher losses.

[0041] Figure 4 shows a cross-section of a superjunction JFET 1, which, with respect to its depletion voltage, can be dimensioned according to one of the examples explained previously in this document. More specifically, Figure 4 A cross-sectional view of a semiconductor body 100 is shown, in which the active region of a superjunction JFET 1 is integrated.

[0042] According to one example, the superjunction JFET 1 is a silicon carbide (SiC) superjunction JFET. In this example, the semiconductor body 100 is a SiC semiconductor body. According to another example, the superjunction JFET 1 is a silicon (Si) JFET, and thus the semiconductor body 100 is a silicon semiconductor body.

[0043] like Figure 4 As shown, the superjunction JFET 1 comprises several transistor cells, each of which comprises a first region 22 doped with a first doping type and a second region 23 doped with a second doping type. The first and second regions are arranged adjacent to each other in a first lateral direction x of the semiconductor body 100. Furthermore, each transistor cell 2 comprises a gate electrode 21 connected to a gate terminal G. The connection between the gate electrode 21 and the gate terminal G is only at Figure 4 It is shown schematically in FIG.

[0044] For example, JFET 1 is an N-type JFET (N-channel JFET). In this example, first region 22 is an N-type (N-doped) region, and second region 23 is a P-type (P-doped) region. According to another example, JFET 1 is a P-type JFET (P-channel JFET). In this example, first and second regions 22, 23 have a doping type that is complementary to the doping type of first and second doping regions 22, 23 of the N-type JFET.

[0045] The first region 22 is ohmically coupled between the source terminal S and the drain terminal D of the JFET 1. This includes the first region 22 being ohmically connected to the source terminal S and the drain terminal D. This includes the absence of a PN junction between the first region 22 and the source terminal S on one side and the drain terminal D on the other side.

[0046] exist Figure 4 In the example shown, first and second regions 22, 23 are arranged in first semiconductor layer 110, which may have a basic doping of a first doping type. Between first and second regions 22, 23, a region 27 having a basic doping of first semiconductor layer 110 may be arranged. These regions are hereinafter referred to as basic regions. According to one example, first and second regions 22, 23 and basic region 27 form the drift region of JFET 1.

[0047] For example, the basic doping of the first semiconductor layer 110 is less than 8E14 cm -3 According to one example, the drain terminal D is connected to or formed by the second semiconductor layer 120 of the first doping type. The second semiconductor layer 120 may also be referred to as the drain region of the JFET 1. The doping concentration of the second semiconductor layer 120 is higher than the doping concentration of the first semiconductor layer 110. According to one example, the doping concentration of the second semiconductor layer 120 is higher than 1E18 cm -3 Optionally, the third semiconductor layer 130 of the first doping type is arranged between the first semiconductor layer 110 and the second semiconductor layer 120, wherein the doping concentration of the third semiconductor layer 130 is between the doping concentration of the first semiconductor layer 110 and the doping concentration of the second semiconductor layer 120. For example, the doping concentration of the third semiconductor layer 130 is 1E16 cm -3 and 1E17 cm -3 between.

[0048] exist Figure 4 In the example shown, the first region 22 adjoins the third semiconductor layer 130 and is connected via the third semiconductor layer 130 to the second semiconductor layer 120 and the drain terminal D. The first semiconductor layer 110 and the optional third semiconductor layer 130 in which the first and second doped regions 22 , 23 are arranged form a drift region of the superjunction JFET 1 .

[0049] For example, the vertical dimension of the first semiconductor layer 110 is between 1 micrometer (μm) and 5 micrometers. For example, the vertical dimension of the third semiconductor layer 130 is between 1 micrometer (μm) and 15 micrometers.

[0050] refer to Figure 4 , the JFET 1 comprises a source electrode 31 arranged above the first surface 140 of the semiconductor body 100. The source electrode 31 is connected to the source terminal S or forms the source terminal S. Figure 4 The device is a vertical device. This includes: the source electrode 31 and the second semiconductor layer 120 forming the drain terminal D or connected to the drain terminal D are spaced apart from each other in the vertical direction z of the semiconductor body 100 .

[0051] The “vertical direction” is a direction in which the source electrode 31 and the second semiconductor layer 120 are spaced apart from each other and are substantially perpendicular to the first surface 140. The vertical dimensions of the semiconductor layers 110, 130 explained above are dimensions of the respective layers 110, 130 in the vertical direction z of the semiconductor body 100. The vertical direction z is perpendicular to the first lateral direction x, in which the first and second regions 22, 23 are arranged adjacent to each other.

[0052] refer to Figure 4 , the first region 22 is connected to the source electrode 31. To this end, the first region 22 may extend in the vertical direction z to the source electrode 31. In this example, part of the first region 22 forms the source region of the JFET.

[0053] Alternatively, as Figure 4 As shown, the first region 22 is connected to the source electrode 31 via the doped third region 24 of the first doping type and the source region 28 of the first doping type. The third region 24 can have a higher or lower area-related charge than the first doped region 22. The "area-related charge" of a doped region such as the first region 22, the second region 23 or the third region 24 is given by the integral of the doping concentration of the corresponding region in the first lateral direction x. The area-related charge is given by per square centimeter (cm -2 ) is given by the amount of dopant atoms.

[0054] The third region 24 connects the first region 22 to the source region 28, and the source region 28 is connected to the source electrode 31. The third region 24 is also referred to as a first connection region 24 hereinafter.

[0055] According to one example, the area-related charges of the first and second regions 22, 23 are selected such that the respective area-related charges are between 30% and 90%, in particular between 40% and 80%, of a critical area-related charge of the semiconductor material of the semiconductor body 100. For example, in silicon carbide (SiC), the critical area-related charge is between 1.5E13 cm -2 and 2E13cm -2 between.

[0056] exist Figure 4In the example shown, the gate electrode 21 is arranged in a trench extending from the first surface 140 into the semiconductor body 100. More specifically, the gate electrode 21 is arranged in a trench extending from the first surface 140 into the first semiconductor layer 110. For example, the third doped region (first connection region) 24 is a doped region in the mesa region of the semiconductor body 100 arranged between adjacent trenches. In this example, the drift region having the first and second doped regions 22, 23 is arranged in a region of the semiconductor body 100 that is located below the gate electrode 21 in the vertical direction z.

[0057] In each transistor cell 2, the second region 23 is ohmically connected to the gate electrode 21 of the corresponding transistor cell 2 (wherein, as shown, two transistor cells may share one gate electrode). Figure 4 In the example shown, the second doped region 23 is connected to the gate electrode 21 via a doped fourth region 25 of the second doping type. Figure 4 In the example shown, the fourth region 25 adjoins the gate electrode 21 in the mesa region. According to one example, the fourth region 25 has a higher area-related charge than the second doped region 23. Because the fourth region 25 connects the second region 23 to the gate electrode 21, the fourth region 25 is also referred to as the second connection region hereinafter.

[0058] According to one example, the area-related charge of the fourth doping region (second connection region) 25 is high enough so that the fourth doping region 25 is not completely depletable when the device is in the blocking state. In this example, the area-related charge of the fourth doping region 25 is higher than the critical area-related charge of the semiconductor material of the fourth doping region 25.

[0059] The gate electrode 21 is separated from the regions of the first semiconductor layer 110 having the first doping type by doping regions of the second doping type. These doping regions of the second doping type may include the second connection region 25 explained above. Figure 4 In the example shown, the second connection region 25 extends along the sidewalls of the gate trench including the gate electrode 21. In this example, a fifth region 26 doped with the second doping type extends along the bottom of the gate trench and separates the gate electrode 21 from the doped region of the first doping type along the bottom of the gate trench. The first region 26 may also be referred to as a bottom region. According to one example, the doping concentration of the bottom region 26 is sufficiently high so that the bottom region 26 is not completely depleted when the device is in the blocking state.

[0060] exist Figure 4 In the example shown, the gate electrode 21 may be perpendicular to Figure 4The electrodes are shown as elongated in the direction of the drawing plane, ie perpendicular to the first lateral direction x. Equivalently, the first and second regions 22, 23, the first and second connection regions 24, 25 and the bottom region 26 may be elongated regions in a direction perpendicular to the drawing plane.

[0061] According to another example (not shown), the longitudinal directions of the gate electrode 21, the first and second connection regions 24, 25, and the bottom region 26 arranged in the mesa region are perpendicular to the longitudinal directions of the first and second doped regions 22, 23. In this example, the longitudinal directions of the first doped regions 22 are perpendicular to the longitudinal directions of the first connection regions 24 to which they are adjacent, and the longitudinal directions of the second doped regions 23 are perpendicular to the longitudinal directions of the second connection regions 25 to which they are adjacent. In addition, in this example, each first region 22 is adjacent to a plurality of first connection regions 24, and each second region 23 is adjacent to a plurality of second connection regions 24.

[0062] The following is a brief explanation Figure 4 Functionality of the JFET 1 shown. When the device is in the on-state, a conducting channel exists between the source terminal S and the drain terminal D via the source electrode 31 , the first region 22 and the optional first connection region 24 , the optional third semiconductor layer 130 and the second semiconductor layer 120 .

[0063] When the device is placed in a blocking state by applying a suitable voltage between the gate terminal G and the source terminal S, at least one first doped region 22 or at least one optional first connection region 24 in each mesa region arranged between two adjacent gate electrodes 21 is pinched off in the mesa region, so that the conductive channel between the source terminal S and the drain terminal D is interrupted. As the load path voltage between the drain terminal D and the source terminal S increases, an electric field propagates in the horizontal direction (first lateral direction x). This electric field is associated with the depletion of the first and second doped regions 22, 23 from each other, as is common in superjunction devices. The mesa region arranged between adjacent gate electrodes can be referred to as the channel region of the JFET 1.

[0064] exist Figure 4 In the example shown, the first and second doped regions 22, 23 are arranged in such a way that in a first lateral direction x, two first regions 22 are arranged adjacent to each other, followed by two second regions 23. According to another example (not shown), the first and second regions 22, 23 are arranged alternately in the lateral direction x. In each case, the first region 22 is adjacent to the second region 23, so that when the device is in the blocking state, the adjacent regions can deplete each other. In addition, between each pair of two adjacent first regions 22, each pair of two adjacent second regions 23 and each pair of two adjacent first and second regions 22, 23, a basic region 27 can be arranged. However, this is only an example. According to one example, adjacent first and second regions 22, 23 are adjacent to each other.

[0065] Figure 5 Schematically shows the Figure 4 The line A-A' shown Figure 4 An example of a doping profile for the device shown. Figure 5 In FIG. 2 , line 201 shows the doping concentration of the first region 22, line 202 shows the doping concentration of the second doping region 23, and line 203 shows the doping concentration of the basic doping of the first semiconductor layer 110. The fact that the first and second doping regions 22, 23 have complementary doping types is facilitated by the fact that Figure 5 Considered in the figure, the doping concentration of the first doping region 22 (line 201 ) is plotted as negative, whereas the doping concentration of the second doping region 23 (line 202 ) is plotted as positive.

[0066] As mentioned above, the semiconductor body 100 is, for example, a SiC semiconductor body. In this type of semiconductor body 100, P-type doping can be achieved, for example, by doping with aluminum (Al) or boron (B), and N-type doping can be achieved, for example, by doping with nitrogen (N) or phosphorus (P).

[0067] According to another example, the semiconductor body 100 is a silicon (Si) semiconductor body.

[0068] Figure 6 Shown Figure 5 The curves shown and an additional curve 204 , which shows the effective doping (net doping) resulting from doping of the first and second doping types shown by the curves 201 , 202 , 203 .

[0069] In addition to the distribution of effective doping shown by curve 204 explained above, Figure 7 Also shown is the electric field generated in the horizontal direction (i.e., the first lateral direction x) when the device is blocked (see line 205). Figure 7 It can be seen that the maximum value of the electric field in the first lateral direction x occurs where the doping type of the effective doping changes. When each of the first and second doping regions 22, 23 is completely depleted, the horizontal electric field E hor The value (amplitude) of the maximum electric field depends on the area-dependent charges in the first and second doping regions 22 , 23 .

[0070] Every semiconductor material has a critical electric field. The critical electric field represents the electric field value at which avalanche breakdown occurs. The relationship between the maximum electric field and the critical electric field is the same as the relationship between the area-related charge of the first and second doping regions 22, 23 and the critical area-related charge. For example, if the area-related charge in the first and second doping regions 22, 23 is 50% of the critical area charge, the maximum electric field is 50% of the critical electric field. Therefore, the maximum electric field that occurs when the device is blocked can be adjusted via the area-related charge of the first and second doping regions 22, 23.

[0071] like Figure 7 As shown, the electric field occurring in the region of two adjacent first and second regions 22, 23 has a substantially triangular profile. The depletion voltage is the integral of the electric field occurring in the region of two adjacent doped regions 22, 23 in the first lateral direction x. At a given maximum electric field (adjusted by the area charge of the first and second regions 22, 23), the shorter the extension of the first and second regions 22, 23 in the first lateral direction x, the lower the integral.

[0072] According to one example, the first and second regions 22, 23 are formed such that the dimension in the first lateral direction x is less than 500 nm, less than 400 nm, less than 300 nm or less than 250 nm. The dimension of the first region 22 in the first lateral direction x corresponds to Figure 6 Furthermore, the dimensions of the second doped region 23 in the first lateral direction x correspond to the dimensions of those segments with negative doping shown in the doping profile of FIG. Figure 6 The dimensions of those segments with positive doping are shown in the doping profile diagram of FIG.

[0073] The dimensions of the first and second regions 22, 23 in the first lateral direction x correspond at least approximately to the distance in the first lateral direction x between the doping peaks of two adjacent first and second regions 22, 23. Figure 7 In, d pn The segments of the electric field formed in the regions of two adjacent first and second regions 22, 23 are approximately triangular and have a width at the bottom that is approximately the width of the first region 22 plus the width of the second region 23, and thus approximately twice the distance between the two peaks. Therefore, the maximum horizontal electric field E can be calculated based on hor_max To calculate the depletion voltage, it is approximately as follows:

[0074]

[0075] For example, when d pn =200nm and E hor_max =1.5MV / cm, the depletion voltage is 30V.

[0076] Figures 8A-8DAn example of a method for forming a superjunction JFET with first and second regions 22 , 23 having a dimension in the first lateral direction x smaller than the above mentioned 500 nm is shown. Figures 8A-8D Each shows a cross-sectional view of a section of the semiconductor body 100 during a different process step of the method.

[0077] refer to Figure 8A The method includes etching trenches 150 extending from the surface 140′ into the semiconductor body 100. Etching the trenches 150 includes, for example, using an etch mask 200 formed on top of the first surface 140. Each trench 150 includes a first sidewall 151, a second sidewall 152 opposite the first sidewall, and a bottom 153.

[0078] For example, the width w150 of the trench 150 in the first lateral direction x is between 0.5 micrometers (μm) and 2 micrometers. The pitch p, which is the distance between the corresponding sidewalls of two adjacent trenches 150 (between the first sidewalls 151 or between the second sidewalls 152), is, for example, between 2 micrometers and 3 micrometers. According to one example, the trench 150 is formed in the first portion 110 ′ of the first semiconductor layer 110. Figure 8A In the example shown, the first portion 110' is an epitaxial layer grown on the third semiconductor layer 130 (as shown) or on the second semiconductor layer 120. The surface 140' where the trench 150 is formed is a horizontal surface of the first layout portion 110'.

[0079] refer to Figure 8A , the trenches 150 can be formed so that they extend completely through the first portion 110′ of the first semiconductor layer 110 into the second semiconductor layer 120 or the optional third semiconductor layer 130 (as shown). As further explained herein below, the trenches 150 are used to implant first and second type dopant atoms into the mesa region separating the trenches 150. Therefore, the trenches 150 can be referred to as implantation trenches.

[0080] refer to Figure 8B , forming the first doping region 22 of the first doping type includes implanting dopant atoms of the first doping type into the mesa region between adjacent trenches 150 via the sidewalls 151 and 152 of the trenches 150, and forming the second doping region 23 of the second doping type includes implanting dopant atoms of the second doping type into the mesa region via the sidewalls 151 and 152 of the trenches 150. During the implantation of the dopant atoms of the first and second doping types, the implantation energies are adapted to each other so that the first and second doping regions 22 and 23 are arranged adjacent to each other after the implantation. Figure 8B , dopant atoms of both the first and second doping types are implanted into each of the first and second sidewalls 151 , 152 of the trench 150 .

[0081] The formation of the first and second doped regions 22, 23 also includes a thermal treatment, in which the semiconductor body 100 is heated at least in the mesa region so that the implanted dopant atoms are activated. When SiC is used as the semiconductor material of the semiconductor body 100, this thermal activation process is not associated with a significant diffusion of the implanted dopant atoms, so that the dimensions of the first and second doped regions 22, 23 produced in the first lateral direction x are substantially defined by the implantation process. By using substantially only one implantation energy in each implantation process, the small dimensions of the first and second doped regions 22, 23 produced in the first lateral direction x can be achieved. The value (amplitude) of the implantation energy can be used to adjust the depth to which the dopant atoms are implanted in the mesa region in the first lateral direction x.

[0082] refer to Figure 8B , forming the first and second regions 22 and 23 may include: a first implantation process in which first-type dopant atoms are implanted into the first sidewall 151 of the trench; a second implantation process in which second-type dopant atoms are implanted into the first sidewall 151 of the trench 150; a third implantation process in which the first-type dopant atoms are implanted into the second sidewall 152 opposite to the first sidewall 151 of the trench 150; and a fourth implantation process in which the second-type dopant atoms are implanted into the second sidewall 152 of the trench 150. In the first and third implantation processes, implanted regions including the first-type dopant atoms are formed, and based on the implanted regions, the first region 22 is formed in the thermal treatment. In the second and fourth implantation processes, implanted regions including the second-type dopant atoms are formed, and based on the implanted regions, the second region is formed in the thermal treatment.

[0083] The etching mask 200 used to form the trench 150 may remain in place during the implantation process. The implantation process is a tilted implantation process, which is an implantation process in which the implantation angle deviates from zero, the implantation angle being the angle between the implantation direction and the vertical direction z. Figure 8B As shown, the implantation angle can be adjusted so that the dopant atoms are implanted into each sidewall 151, 152 along the entire depth of the corresponding trench 150, but not into the bottom of the trench. In a conventional manner, the implantation angle can be adjusted according to the trench width w150, the trench depth and the thickness of the etch mask 200 to achieve that the dopant atoms are essentially implanted only into the sidewalls 151, 152. The trench depth is the dimension of the trench 150 in the vertical direction z.

[0084] refer to Figure 8C The method further includes filling the trench 150 with a single crystalline semiconductor material by forming a second portion 110 ″ of the first semiconductor layer 110 in an epitaxial process. Figure 8CAs shown, the second portion 110 ″ fills the trench 150 and may be grown on top of the horizontal surface of the first portion 110 ′ outside the trench 150. Thus, the first semiconductor layer 110 including the first and second layer portions 110 ′, 110 ″ may extend beyond the first and second doped regions 22, 23 in the vertical direction z of the semiconductor body 100. The first and second layer portions 110 ′, 110 ″ may be formed to have substantially the same basic doping.

[0085] Figure 8D shows that by performing further processing steps from Figure 8C The completed device is obtained by the structure shown. These processing steps include forming a gate trench 20 in the first semiconductor layer 110 and forming a gate electrode 21 in the gate trench 20. After forming the gate trench 20 and before forming the gate electrode 21, first and second connection regions 24, 25 and a bottom region 26 can be formed. Forming the first connection region 24 can include: implanting first type dopant atoms into opposite sidewalls of the gate trench 20 to form an implanted region adjacent to the first region 22; and an annealing process to activate the implanted dopant atoms. Forming the second connection region 25 can include: implanting first and second dopant atoms into opposite sidewalls of the gate trench 20 to form an implanted region adjacent to the second region 23; and an annealing process to activate the implanted dopant atoms. Forming the bottom region 26 can include implanting second type dopant atoms into the bottom of the gate trench 20, and an annealing process to activate the implanted dopant atoms.

[0086] Furthermore, further processing steps may include forming source regions 28. This may include implanting dopant atoms of the first doping type into the first semiconductor layer 110, and an annealing process to activate the implanted dopant atoms. The dopant atoms may be implanted into the first semiconductor layer 110 via the first surface 140.

[0087] It should be noted that an annealing process for activating each implanted dopant atom may be performed after the implantation process is completed. This may include the implantation process for forming the first and second regions 22, 23 and the implantation process for forming the first and second connection regions 24, 25, the bottom region 26 and the source region 28.

[0088] Optionally, before forming the gate trench, a portion of the first semiconductor layer 110 is removed from above the first and second doped regions 22 , 23 . This may include simply planarizing the surface of the first semiconductor layer 110 or substantially removing portions of the first semiconductor layer 110 .

[0089] Without the optional removal process, the horizontal surface of the second layer portion 110 ″ forms the first surface 140 of the semiconductor body 100 . In the presence of the optional removal process, after the removal process, the horizontal surface of the first semiconductor layer 110 forms the first surface 140 of the semiconductor body 100 .

[0090] Some of the aspects explained above are briefly summarized below with reference to numbered examples.

[0091] Example 1. A superjunction JFET comprising a threshold voltage and a depletion voltage, wherein a magnitude of the depletion voltage is less than 4 times the magnitude of the threshold voltage.

[0092] Example 2. The superjunction JFET of Example 1, wherein the magnitude of the depletion voltage is less than 3 times the magnitude of the threshold voltage, less than 2 times the magnitude of the threshold voltage, less than 1.5 times the magnitude of the threshold voltage, or less than the magnitude of the threshold voltage.

[0093] Example 3. A superjunction JFET includes a depletion voltage less than 50V.

[0094] Example 4. The superjunction JFET of Example 3, wherein the depletion voltage is less than 40V or less than 30V.

[0095] Example 5. The superjunction JFET of any of Examples 1 to 4, wherein the superjunction JFET includes a rated blocking voltage and a depletion charge, wherein the depletion charge is a charge that flows out of the superjunction JFET when the superjunction JFET changes from an on-state to a blocking state and a load path voltage between a drain terminal and a source terminal of the superjunction JFET increases from zero to the rated blocking voltage, and wherein the depletion voltage is equal to the load path voltage at which 80% of the depletion charge has flowed out of the superjunction JFET.

[0096] Example 6. The superjunction JFET of any of Examples 1 to 5, wherein the superjunction JFET is configured to receive a drive voltage and conduct a load current associated with a current density, and wherein the threshold voltage is equal to a voltage level of the drive voltage at which the current density associated with the load current reaches a current density threshold.

[0097] Example 7. The superjunction JFET of Example 6, wherein the current density threshold is 10 mA / mm 2 and 100mA / mm 2 between.

[0098] Example 8. The superjunction JFET according to any one of Examples 1 to 7, further comprising: a semiconductor body; a plurality of transistor cells, each transistor cell comprising a gate electrode, a first doping region of a first doping type and a second doping region of a second doping type arranged adjacent to each other in a first lateral direction of the semiconductor body, wherein the first doping region is ohmically connected between a source terminal and a drain terminal of the superjunction JFET, and wherein the second doping region is ohmically connected to the gate electrode.

[0099] Example 9. The superjunction JFET of Example 8, wherein the gate electrodes are arranged in gate trenches that are spaced apart from each other and separated from each other by a mesa region of the semiconductor body, and wherein each transistor cell further comprises: a source region arranged in the mesa region and connected to the source terminal; and a first connection region of the first doping type connecting the first region to the source region.

[0100] Example 10. The superjunction JFET according to example 8 or 9, wherein each of the first doped region and the second doped region has an area charge in a region perpendicular to the first lateral direction, wherein in each case the area charge is between 30% and 90%, in particular between 50% and 80%, of a critical area charge of the semiconductor material of the semiconductor body.

[0101] Example 11. The superjunction JFET of any of Examples 1 to 10, wherein the superjunction JFET is a silicon (Si) superjunction JFET.

[0102] Example 12. The superjunction JFET of any of Examples 1 to 10, wherein the superjunction JFET is a silicon carbide (SiC) superjunction JFET.

[0103] Example 13. The superjunction JFET of Example 12, wherein each of the first and second doped regions has a dimension in the first lateral direction (x) that is less than 500 nanometers.

[0104] Example 14. The superjunction JFET of Example 13, wherein a dimension of each of the first and second doped regions in the first lateral direction is less than 400 nanometers, less than 300 nanometers, or less than 250 nanometers.

[0105] Example 15. An electronic circuit comprising: a superjunction JFET according to any one of Examples 1 to 12; an electronic switch connected in series with a drain-source path of the superjunction JFET; and an inductive circuit connected in parallel with the drain-source path of the superjunction JFET.

[0106] Example 16. A method comprising: forming implant trenches in a semiconductor body such that the trenches are spaced apart from one another in a first lateral direction of the semiconductor body and separated from one another by semiconductor mesa regions; forming a first region of a first doping type in each mesa region using a first implantation process; forming a second region of a second doping type complementary to the first doping type using a second implantation process; filling the implant trenches with single-crystalline semiconductor material in an epitaxial growth process; forming a gate trench in the semiconductor body; forming additional regions of the second doping type along sidewalls and a bottom of the gate trench such that each second region abuts at least one additional region; and forming a gate electrode in the gate trench.

[0107] Example 17. The method of Example 16, wherein the first implantation process comprises implanting dopant atoms of a first doping type into a first sidewall of the implantation trench, wherein the second implantation process comprises implanting dopant atoms of a second doping type into the first sidewall of the implantation trench, and wherein implantation energies in the first and second implantation processes are adapted to each other such that the first region and the second region are arranged adjacent to each other in the first lateral direction.

[0108] Example 18. The method according to Example 16 or 17, further comprising: forming another first region of the first doping type in each mesa region using a third implantation process; and forming another second region of the second doping type in each mesa region using a fourth implantation process, wherein the third implantation process comprises implanting dopant atoms of the first doping type into a second sidewall opposite to the first sidewall of the implantation trench, wherein the fourth implantation process comprises implanting dopant atoms of the second doping type into the second sidewall of the implantation trench, and wherein the implantation energies in the third and fourth implantation processes are adapted to each other so that the another first region and the another second region are arranged adjacent to each other in the first lateral direction.

[0109] Example 19. The method of any one of Examples 16 to 18, further comprising: forming a source electrode ohmically connected to the first region over a surface of the semiconductor body.

[0110] Example 20. The method of Example 19, wherein forming the source electrode comprises forming the source electrode to abut the first region.

[0111] Example 21. The method of Example 19, wherein the method further comprises forming source regions of the first doping type in the mesa regions between the gate trenches, and forming first connection regions of the first doping type in the mesa regions such that each first connection region abuts at least one of the first regions, and wherein forming the source electrode comprises forming the source electrode to abut the source regions.

[0112] Example 22. The method of any one of Examples 16 to 21, wherein forming the first region comprises forming the first region to abut the semiconductor layer of the first doping type.

Claims

1. A superjunction JFET including a threshold voltage and a depletion voltage, The magnitude of the depletion voltage is less than 4 times the magnitude of the threshold voltage.

2. The superjunction JFET according to claim 1, The magnitude of the depletion voltage is less than 3 times the magnitude of the threshold voltage, less than 2 times the magnitude of the threshold voltage, less than 1.5 times the magnitude of the threshold voltage, or less than the magnitude of the threshold voltage.

3. The superjunction JFET includes a depletion voltage of less than 50V. The superjunction JFET of claim 3 , wherein the depletion voltage is less than 40 V or less than 30 V.

5. The superjunction JFET according to any one of claims 1 to 4, Wherein the superjunction JFET (1) includes the rated blocking voltage and depletion charge (Qoss), wherein the depletion charge (Qoss) is the charge that flows out of the superjunction JFET (1) when the superjunction JFET changes from an on-state to a blocking state and a load path voltage (Vds) between the drain terminal (D) and the source terminal (S) of the superjunction JFET increases from zero to a rated blocking voltage, and The depletion voltage is equal to the load path voltage when 80% of the depletion charge has flowed out of the superjunction JFET.

6. The superjunction JFET according to any one of claims 1 to 5, wherein the superjunction JFET (1) is configured to receive a drive voltage (Vgs) and conduct a load current (Ids) associated with a current density, and Wherein the threshold voltage is equal to the voltage level of the drive voltage (Vgs) at which the current density associated with the load current (Ids) reaches a current density threshold.

7. The superjunction JFET according to claim 6, The current density threshold is 10mA / mm 2 and 100mA / mm 2 between.

8. The superjunction JFET according to any one of the preceding claims, further comprising: a semiconductor body (100); A plurality of transistor units (2), each transistor unit comprising a gate electrode (21), a first doping region (22) of a first doping type and a second doping region (23) of a second doping type arranged adjacent to each other in a first lateral direction (x) of a semiconductor body (100), wherein the first doped region (22) is ohmically connected between the source terminal (S) and the drain terminal (D) of the superjunction JFET, and The second doped region (23) is ohmically connected to the gate electrode (21).

9. The superjunction JFET according to claim 8, wherein the gate electrodes (21) are arranged in gate trenches (20) that are spaced apart from each other and separated from each other by mesa regions of the semiconductor body (100), and Each transistor unit (2) further comprises: a source region (28) disposed in the mesa region and connected to the source terminal (S); and The first region (22) is connected to a first connection region (24) of a first doping type of the source region (28).

10. The superjunction JFET according to claim 8 or 9, wherein each of the first doping region (22) and the second doping region (23) has an area charge in a region perpendicular to a first lateral direction (x), in, In each case, the area charge is between 30% and 90%, in particular between 50% and 80%, of a critical area charge of the semiconductor material of the semiconductor body (100).

11. The superjunction JFET according to any one of claims 1 to 10, The super junction JFET is a silicon (Si) super junction JFET.

12. The superjunction JFET according to any one of claims 1 to 10, The super junction JFET is a silicon carbide (SiC) super junction JFET.

13. The superjunction JFET according to claim 10, The dimension of each of the first and second doped regions (22, 23) in the first lateral direction (x) is less than 500 nanometers.

14. The superjunction JFET according to claim 13, The dimension of each of the first and second doped regions (22, 23) in the first lateral direction (x) is less than 400 nanometers, less than 300 nanometers, or less than 250 nanometers.

15. An electronic circuit comprising: A superjunction JFET (1) according to any one of claims 1 to 14; an electronic switch (31) connected in series with the drain-source path of the superjunction JFET (1); and An inductive circuit (32) is connected in parallel with the drain-source path of the superjunction JFET (1).

16. A method comprising: forming implantation trenches (150) in a semiconductor body (100), such that the trenches (150) are spaced apart from one another in a first lateral direction (x) of the semiconductor body (100) and separated from one another by semiconductor mesa regions; forming a first region (22) of a first doping type in each mesa region using a first implantation process; forming a second region (23) of a second doping type complementary to the first doping type using a second implantation process; filling the implantation trench (150) with a single crystal semiconductor material in an epitaxial growth process; forming a gate trench (20) in a semiconductor body (100); forming further regions (25, 26) of the second doping type along the sidewalls and bottom of the gate trench such that each second region (23) adjoins at least one further region (25, 26); and A gate electrode (21) is formed in the gate trench (20).

17. The method according to claim 16, The first implantation process comprises implanting dopant atoms of a first doping type into a first sidewall (151) of the implantation trench (150), wherein the second implantation process comprises implanting dopant atoms of the second doping type into the first sidewall (151) of the implantation trench, and The implantation energies in the first and second implantation processes are adapted to each other such that the first region (22) and the second region (23) are arranged adjacent to each other in a first lateral direction (x).

18. The method according to claim 16 or 17, further comprising: forming another first region (22) of the first doping type in each mesa region using a third implantation process; and forming another second region (23) of the second doping type in each mesa region using a fourth implantation process, wherein the third implantation process comprises implanting dopant atoms of the first doping type into a second sidewall (152) opposite to the first sidewall (151) of the implantation trench (150), wherein the fourth implantation process comprises implanting dopant atoms of the second doping type into the second sidewall (152) of the implantation trench (150), and The implantation energies in the third and fourth implantation processes are adapted to each other such that the further first region (22) and the further second region (23) are arranged adjacent to each other in the first lateral direction (x).

19. The method according to any one of claims 16 to 18, further comprising: A source electrode (31) is formed over the surface (140) of the semiconductor body (100) and is ohmically connected to the first region (22).

20. The method of claim 19, wherein forming the source electrode (31) comprises forming the source electrode (31) to abut the first region (22).

21. The method of claim 19, further comprising: forming a source region (28) of a first doping type in the mesa region between the gate trenches (20), and forming first connection regions (24) of a first doping type in the mesa region such that each first connection region (24) adjoins at least one of the first regions (22), and The forming of the source electrode (31) includes forming the source electrode (31) to be adjacent to the source region (28).

22. The method according to any one of claims 16 to 21, The forming of the first region (22) includes forming the first region (22) to be adjacent to the semiconductor layer (120, 130) of the first doping type.

Images