Consistency verification method, chip design verification method and related device

Abstract

The embodiment of the invention provides a consistency verification method, a chip design verification method and a related device.The consistency verification method comprises the steps that design definition information of a to-be-verified chip design is obtained; extracting each communication interconnection module included in the interconnection network in the defined to-be-verified chip design; classifying the communication interconnection modules according to functions and behaviors to obtain a communication interconnection module group comprising the communication interconnection modules with the same functions and behaviors; establishing a representative communication interconnection module for each communication interconnection module group, wherein the function and behavior of the representative communication interconnection module are the same as those of each communication interconnection module of the corresponding communication interconnection module group; and performing consistency verification on each representative communication interconnection module according to a system-level verification requirement of the to-be-verified chip design. According to the technical scheme provided by the embodiment of the invention, the consistency verification efficiency of chip design can be improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip verification technology, and specifically to a consistency verification method, a chip design verification method, and related devices. Background Art

[0002] Consistency verification is a key step in chip design, covering multiple aspects such as the internet, functional modules, and protocols. Internet consistency verification is a crucial component, especially in multi-core processor and SoC (System on Chip) designs.

[0003] However, as chip design becomes more complex, the complexity of interconnect networks also increases, significantly increasing the difficulty, workload, and resource requirements of chip design consistency verification. Therefore, finding a technical solution to improve the efficiency of chip design consistency verification has become a pressing technical challenge for those skilled in the art. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a consistency verification method, a chip design verification method, and related devices to improve the consistency verification efficiency of chip design.

[0005] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions.

[0006] In a first aspect, an embodiment of the present invention provides a consistency verification method, including:

[0007] Obtaining design definition information of the chip design to be verified;

[0008] Extracting each communication interconnection module included in the interconnection network in the chip design to be verified, as defined in the design definition information;

[0009] Classifying the extracted communication and interconnection modules according to their functions and behaviors to obtain classified groups of communication and interconnection module groups; each group of communication and interconnection module groups includes communication and interconnection modules with the same functions and behaviors;

[0010] A representative communication interconnection module is established for each communication interconnection module group, and the functions and behaviors of the representative communication interconnection module are the same as the functions and behaviors of each communication interconnection module included in the corresponding communication interconnection module group;

[0011] According to the system-level verification requirements of the chip design to be verified, consistency verification is performed on each of the representative communication and interconnection modules.

[0012] In a second aspect, an embodiment of the present invention provides a chip design verification method, comprising:

[0013] Obtain consistency verification completion information of the chip design to be verified; the consistency verification completion information is generated after consistency verification of each representative communication interconnection module in the chip design to be verified based on the consistency verification method as described in the first aspect;

[0014] Performing simulation verification and regression convergence check on the chip design to be verified to complete verification of the chip design to be verified;

[0015] The test stimulus and verification component used when performing simulation verification and regression convergence detection on the chip design to be verified are: the test stimulus and verification component used when performing consistency verification on each of the representative communication interconnection modules.

[0016] In a third aspect, an embodiment of the present invention provides a consistency verification device, including:

[0017] A design definition information acquisition module, used to obtain design definition information of the chip design to be verified;

[0018] An extraction module, configured to extract each communication interconnection module included in the interconnection network in the chip design to be verified, as defined in the design definition information;

[0019] a classification module for classifying the extracted communication interconnection modules according to their functions and behaviors to obtain classified groups of communication interconnection module groups; each group of communication interconnection module groups includes communication interconnection modules with the same functions and behaviors;

[0020] An establishment module, configured to establish a representative communication interconnection module for each communication interconnection module group, wherein the functions and behaviors of the representative communication interconnection module are the same as the functions and behaviors of each communication interconnection module included in the corresponding communication interconnection module group;

[0021] The consistency verification module is used to perform consistency verification on each of the representative communication interconnection modules according to the system-level verification requirements of the chip design to be verified.

[0022] In a fourth aspect, an embodiment of the present invention provides a chip design verification device, comprising:

[0023] An information acquisition module, configured to obtain consistency verification completion information of the chip design to be verified; the consistency verification completion information is generated after consistency verification of each representative communication interconnection module in the chip design to be verified is performed based on the consistency verification device as described in the third aspect;

[0024] A simulation convergence module, configured to perform simulation verification and regression convergence check on the chip design to be verified, thereby completing verification of the chip design to be verified;

[0025] The test stimulus and verification component used when performing simulation verification and regression convergence detection on the chip design to be verified are: the test stimulus and verification component used when performing consistency verification on each of the representative communication interconnection modules.

[0026] In a fifth aspect, an embodiment of the present invention provides an electronic device comprising a memory and a processor, wherein the memory stores a program, and the processor calls the program stored in the memory to execute the consistency verification method as described in the first aspect, or executes the chip design verification method as described in the second aspect.

[0027] A consistency verification method provided by an embodiment of the present invention includes: obtaining design definition information of a chip design to be verified; extracting each communication interconnection module defined by the design definition information and included in the interconnection network in the chip design to be verified; classifying the extracted communication interconnection modules according to function and behavior to obtain classified groups of communication interconnection module groups; each group of communication interconnection module groups includes each communication interconnection module with the same function and behavior; establishing a representative communication interconnection module for each group of communication interconnection module groups, the function and behavior of the representative communication interconnection module being the same as the function and behavior of each communication interconnection module included in the corresponding communication interconnection module group; and performing consistency verification on each of the representative communication interconnection modules according to the system-level verification requirements of the chip design to be verified.

[0028] In the technical solution provided by the embodiment of the present invention, since the consistency verification of the interconnection network is a key link in the consistency verification process of the chip design, when the chip design is consistency verified, the various communication interconnection modules included in the interconnection network in the chip design to be verified are first extracted based on the design definition information of the chip design to be verified. The communication interconnection modules in the interconnection network have different types according to the functional modules of the chip design to which they are connected (the behavior of the communication interconnection modules) and their own functions (the functions of the communication interconnection modules). Therefore, in the embodiment of the present invention, after all the communication interconnection modules are extracted, the communication interconnection modules are further classified according to the functions and behaviors of the communication interconnection modules to obtain groups of communication interconnection module groups containing communication interconnection modules with the same functions and behaviors; and a representative communication interconnection module is established for each group of communication interconnection module groups, that is, a representative communication interconnection module is established for multiple communication interconnection modules of the same type. Since the functions and behaviors of the representative communication interconnection module are the same as the functions and behaviors of each communication interconnection module in the corresponding communication interconnection module group, the consistency verification of each type of communication interconnection module in the chip design to be verified can be achieved by performing consistency verification on each representative communication interconnection module; therefore, in the process of performing consistency verification on each of the representative communication interconnection modules according to the system-level verification requirements of the chip design to be verified, it is possible to ensure the consistency verification of the chip design to be verified, and reduce the complexity of verifying all communication interconnection modules in the chip design to be verified, thereby improving the verification efficiency of the chip design. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0030] Figure 1 This is a flow chart of a consistency verification method provided by an embodiment of the present invention;

[0031] Figure 2 is another flow chart of the consistency verification method provided by an embodiment of the present invention;

[0032] Figure 3 This is a schematic diagram of a heterogeneous chip design provided by an embodiment of the present invention;

[0033] Figure 4 Yes Figure 3 A simplified schematic diagram of the chip design structure to be verified after the structure is processed;

[0034] Figure 5 This is a flow chart of a chip design verification method provided by an embodiment of the present invention;

[0035] Figure 6 1 is a schematic structural diagram of a consistency verification device provided by an embodiment of the present invention;

[0036] Figure 7 Schematic diagram of a chip design verification device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0037] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0038] With the rapid development of the integrated circuit industry, the complexity of chip design has increased significantly. System-on-chip (SoC) designs have continued to expand, supporting an increasing number of threads and cores. At the same time, heterogeneous chips (dies) and intellectual property (IP) modules are increasingly being used in various application scenarios. These changes place higher demands on the reusability, functionality, and iteration speed of IP modules. Chip design verification ensures that the designed chip's functionality meets application requirements.

[0039] Chip design verification is a complex and multi-layered process designed to ensure that the chip design meets design specifications in terms of functionality, performance, compatibility, and other aspects, and can operate stably under various conditions. The verification process generally includes the following main stages:

[0040] Phase 1: Requirements Analysis and Verification Plan:

[0041] Requirements analysis refers to clarifying the functions, performance, interfaces and other requirements of chip design.

[0042] Verification plan refers to: formulating a detailed verification strategy, including verification objectives, verification methods, verification tools, etc.

[0043] The information formed in the first stage is the design definition information.

[0044] The second stage: Unit Verification, also known as sub-module (non-communication interconnection module) verification:

[0045] Its goal is to verify whether the functionality of a single module or submodule meets the design specifications.

[0046] The verification methods used can be:

[0047] Unit Simulation: Use simulation tools (such as SystemVerilog and VHDL) to perform detailed logic verification on each module.

[0048] Formal Verification: Use formal verification tools to verify the correctness of key logic and discover hidden errors.

[0049] Output: Generate unit verification report to ensure the correct functionality of each module.

[0050] The third stage: Consistency Verification:

[0051] Its goal is to verify whether the communication protocols, data consistency and interfaces between modules (each non-communication interconnection module and each communication interconnection module in the Internet) meet the design specifications.

[0052] In modern CPU (central processing unit) design, splitting the CPU into an I / O die (input / output die) and a core die (core die) has become a common strategy. This division effectively reduces the core die area, thereby improving core performance. However, this architecture also introduces new challenges, particularly in maintaining data consistency.

[0053] The Data Flow (DF) module, as the processor's critical data path routing module, is the core IP for maintaining data consistency. Because the I / O chip and the core chip connect to different devices (functional modules) upstream and downstream, the DF module requires independent design. Furthermore, any changes to the DF interconnect consistency protocol require a comprehensive verification strategy, and the structural characteristics of heterogeneous architectures further complicate consistency verification.

[0054] At the same time, as the scale of single-chip chip designs has become extremely large, simulation time and resource consumption have also increased significantly. Furthermore, in the simulation environment of multi-chip chip designs and multi-path chip designs, comprehensive large-scale iteration and regression testing is almost impossible.

[0055] Therefore, how to more quickly and comprehensively verify the consistency of the interconnection network for the chip design of heterogeneous chips and other structural types of chips has become a huge challenge.

[0056] To solve the above technical problems, an embodiment of the present invention provides a consistency verification method to improve the consistency verification efficiency of chip design.

[0057] Please refer to Figure 1 , Figure 1 This is a flow chart of a consistency verification method provided by an embodiment of the present invention.

[0058] like Figure 1 As shown, the method includes the following steps:

[0059] Step S101: Obtain design definition information of a chip design to be verified.

[0060] The chip design to be verified refers to the chip design that is to be verified.

[0061] Step S102: extracting various communication interconnection modules included in the interconnection network in the chip design to be verified, as defined in the design definition information.

[0062] Based on the design definition information generated by the requirements analysis and verification plan defined in the first phase, each communication and interconnection module is extracted. Specifically, the extraction of each communication and interconnection module involves extracting all the communication and interconnection modules contained in the chip design, based on its specific design structure or type.

[0063] For example, when the type of the chip design to be verified is a heterogeneous chip design of a heterogeneous type, the extracted communication and interconnection modules are: the communication and interconnection modules included in the heterogeneous chip design to be verified and the interconnection networks of the chip designs.

[0064] Step S103 , classifying the extracted communication and interconnection modules according to their functions and behaviors to obtain classified groups of communication and interconnection modules.

[0065] Each communication interconnection module group includes communication interconnection modules with the same functions and behaviors.

[0066] Step S104: establishing a representative communication interconnection module for each communication interconnection module group. The functions and behaviors of the representative communication interconnection module are the same as those of the respective communication interconnection modules included in the corresponding communication interconnection module group.

[0067] Based on the above, it can be seen that when chip designs are usually verified for consistency, the consistency verification of the entire chip design system (mainly the entire internet network) is performed using the above-mentioned consistency verification method. As the scale of chip designs increases, the design of the internet network that enables interaction between various functional modules in the chip design is also becoming more and more complex, such as the design of the DF module mentioned above. As a result, the consistency verification process of the entire chip design system is relatively complex and time-consuming.

[0068] Therefore, in an embodiment of the present invention, based on the characteristics of the interconnection communication modules in the internetwork: the functions and behaviors of each interconnection communication module under each type are the same. Therefore, for each group of interconnection communication modules, an interconnection communication module is established as a representative communication interconnection module, so that the consistency of the representative communication interconnection module can be subsequently verified to achieve the consistency verification of each communication interconnection module in each group of representative interconnection module groups, and the consistency verification of the entire internetwork can be completed, thereby reducing the complexity of the internetwork consistency verification of the entire chip design and reducing the time consumption of the consistency verification.

[0069] Step S105 : performing consistency verification on each of the representative communication and interconnection modules according to the system-level verification requirements of the chip design to be verified.

[0070] The consistency verification may include:

[0071] Cache coherence: Ensures that cache data in a multi-core processor remains consistent across cores.

[0072] Protocol consistency: Verify that the communication protocol between modules complies with the design specifications, such as AMBA (Advanced Microcontroller Bus Architecture, an open standard bus structure) and PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard).

[0073] Data consistency: Ensures that data remains consistent and complete when transmitted between different modules.

[0074] The consistency verification process mainly includes the verification of the non-communication interconnection modules of the chip design to be verified and the various communication interconnection modules in the Internet.

[0075] Conformance verification is typically performed after unit verification and before system verification. It is an independent phase that focuses on the interactions and communication protocols between the various modules of the chip design (i.e., non-communication interconnect modules and communication interconnect modules in the internetwork).

[0076] By performing consistency verification on each representative communication and interconnection module, we can not only reflect the consistency verification of each communication and interconnection module under each type in the Internet, but also reduce the workload and complexity of consistency verification of the Internet as a whole, so as to ensure the implementation of consistency verification of the Internet and reduce the verification complexity of consistency verification of the Internet, thereby improving verification efficiency.

[0077] It can be seen that in the technical solution provided by the embodiment of the present invention, since the consistency verification of the interconnection network is a key link in the consistency verification process of the chip design, when the chip design is consistency verified, the various communication interconnection modules included in the interconnection network in the chip design to be verified are first extracted based on the design definition information of the chip design to be verified. The communication interconnection modules in the interconnection network have different types according to the functional modules of the chip design to which they are connected (the behavior of the communication interconnection module) and their own functions (the functions of the communication interconnection module). Therefore, in the embodiment of the present invention, after all the communication interconnection modules are extracted, the communication interconnection modules are further classified according to the functions and behaviors of the communication interconnection modules to obtain groups of communication interconnection modules with the same functions and behaviors; and a representative communication interconnection module is established for each group of communication interconnection module groups, that is, a representative communication interconnection module is established for multiple communication interconnection modules of the same type (with the same functions and behaviors). Since the functions and behaviors of the representative communication interconnection module are the same as the functions and behaviors of each communication interconnection module in the corresponding communication interconnection module group, the consistency verification of each type of communication interconnection module in the chip design to be verified can be achieved by performing consistency verification on each representative communication interconnection module; therefore, in the process of performing consistency verification on each of the representative communication interconnection modules according to the system-level verification requirements of the chip design to be verified, it is possible to ensure the consistency verification of the chip design to be verified, and reduce the complexity of verifying all communication interconnection modules in the chip design to be verified, thereby improving the verification efficiency of the chip design.

[0078] In order to ensure the consistency verification of each of the representative communication interconnection modules and to reliably represent the verification effect of the consistency verification of the Internet in the chip design to be verified, in one embodiment, each of the representative communication interconnection modules can be connected accordingly according to the specific structural composition of the Internet in the chip design to be verified, so that the structure formed after the connection of each representative communication interconnection module can be equivalent to the Internet of the chip design to be verified, that is, it can simulate the core functions, typical behaviors and some performance indicators of the Internet.

[0079] The topology structure formed by the interconnection relationship between the various communication and interconnection modules in the internet network may be, for example, a mesh topology structure (mesh topology structure), a star topology structure, or the like.

[0080] Please refer to Figure 2 , Figure 2 This is another flowchart of the consistency verification method provided by an embodiment of the present invention.

[0081] like Figure 2 As shown, the method includes the following steps:

[0082] Step S210: Obtain design definition information of the chip design to be verified.

[0083] Step S211 , extracting various communication interconnection modules included in the interconnection network in the chip design to be verified, as defined in the design definition information.

[0084] In step S212 , the extracted communication and interconnection modules are classified according to their functions and behaviors to obtain classified groups of communication and interconnection module groups, and a representative communication and interconnection module is established for each group of communication and interconnection module groups.

[0085] The functions and behaviors of the representative communication interconnection module are the same as the functions and behaviors of each communication interconnection module included in the corresponding communication interconnection module group.

[0086] The design definition information describes the functions and behaviors of each communication and interconnection module in the chip design. For example, the behavior of a communication and interconnection module can be understood as the objects connected to the communication and interconnection module. For example, a routing module connects a master module and a slave module. The functions of the routing module can be described as forwarding requests from the master module to the corresponding target slave module, and returning responses from the slave module to the master module based on requests from the master module.

[0087] Therefore, after classifying the extracted communication interconnection modules according to the functions and behaviors of each communication interconnection module in the design definition information, the behaviors and functions of the communication interconnection modules in each obtained group of communication interconnection modules are the same, so that a communication interconnection module with the same functions and behaviors can be used as a representative communication interconnection module, so as to achieve consistency verification of the communication interconnection module group corresponding to the representative communication interconnection module through consistency verification of the representative communication interconnection module.

[0088] Step S213 , correspondingly connecting the representative communication interconnection modules according to the interconnection relationship between the various communication interconnection modules in the chip design to be verified, to form a simplified chip design to be verified that is equivalent to the chip design to be verified.

[0089] The simplified chip design to be verified simulates the behavior and interaction of the chip design to be verified.

[0090] Since the consistency verification of the interconnection network in the chip design to be verified is a holistic verification of all the communication and interconnection modules it includes, the consistency verification is relatively complex and time-consuming.

[0091] Based on this, in the present invention, a representative communication interconnection module is established for the multiple communication interconnection modules in each communication interconnection module group to represent or simulate the various communication interconnection modules belonging to the same communication interconnection module group. Therefore, the functions and behaviors of the representative communication interconnection module are the same as the functions and behaviors of the various communication interconnection modules included in the corresponding communication interconnection module group. Then, when connecting the various representative communication interconnection modules, corresponding connections can be made according to the interconnection relationship between the various communication interconnection modules in the chip design to be verified, so that the simplified chip design to be verified is equivalent to the original chip design to be verified, that is, the simplified chip design to be verified simulates the behavior and interaction of the chip design to be verified, so that by performing consistency verification on the simplified chip design to be verified, the effect of consistency verification of the chip design to be verified as a whole is achieved, the complexity of consistency verification is reduced, and the efficiency of consistency verification is improved.

[0092] Step S214 : determining a system-level verification requirement of a corresponding type according to the type of the chip design, wherein the system-level verification requirement includes at least one sub-verification requirement.

[0093] When performing consistency verification, the system-level verification requirements are closely related to the type of chip design to be verified. Different types of chip designs to be verified have significant differences in functions, performance, application scenarios, complexity, etc., so the system-level verification requirements will also vary depending on the type of chip design to be verified. Accordingly, for each type of chip design, the system-level verification requirements usually include multiple sub-verification requirements. For example, sub-verification requirements may include:

[0094] Functional verification requirements: Under functional verification requirements, verification can include: protocol consistency verification, which verifies whether the internet correctly implements the designed protocol, such as AXI (Advanced eXtensible Interface) and OCP (Open Core Protocol). Data transmission integrity verification, which verifies whether data transmission in the internet is complete, without loss or errors. Address mapping and routing verification, which verifies whether the internet's address mapping and routing mechanisms are correct, ensuring that data reaches the correct destination.

[0095] Interface verification requirements: Verification content may include: Internal interface consistency: Verifying whether the interfaces between modules within the internet network meet design requirements. External interface consistency: Verifying whether the interfaces between the internet network and external devices (such as processors, memory, I / O devices, etc.) meet protocol specifications. Protocol compatibility: Verifying whether the internet network is compatible with multiple protocols to ensure interoperability with different devices.

[0096] The above is only an example, and the sub-verification requirements can be determined according to the specific type of chip design to be verified.

[0097] Therefore, in step S214 , the corresponding system-level verification requirements can be determined according to the specific type of the chip design to be verified, that is, the multiple sub-verification requirements included in the system-level verification requirements can be clarified.

[0098] Step S215 : For each sub-verification requirement in the determined system-level verification requirement, a verification strategy matching each sub-verification requirement is used to perform consistency verification on the simplified chip design to be verified.

[0099] Because system-level verification requirements include multiple sub-verification requirements, each corresponding to a verification objective. Different verification objectives for sub-verification requirements necessitate different verification strategies. For example, in a chip design with a complex structure, if a sub-verification requirement is an interface verification requirement for verifying multiple interface protocols, a cross-validation strategy can be employed to perform consistency verification on a simplified chip design.

[0100] Cross-validation is applicable to scenarios such as complex functional verification, high-performance verification, interface verification, power consumption verification, reliability verification, security verification, and system integration verification. By combining multiple verification methods and approaches, it verifies the chip design from different perspectives, ensuring comprehensiveness and credibility. Cross-validation is chosen to improve verification coverage, identify potential issues, and enhance the credibility of verification results.

[0101] Exemplarily, the types of chip designs to be verified may include: heterogeneous chip designs of heterogeneous types, single-chip designs of single-chip types, multi-way chip designs of multi-way types, and single-way chip designs of single-way types; the simplified chip designs to be verified may include: simplified heterogeneous chip designs to be verified, simplified single-chip designs to be verified, simplified multi-way chip designs to be verified, and simplified single-way chip designs to be verified.

[0102] In the heterogeneous chip design, the communication interconnection modules included in the interconnection network may include: a master module (Master Module) for actively initiating communication, a slave module (Slave Module) for passively responding to communication, a routing module (Routing Module) for forwarding data packets, an end-to-end cross-chip module for cross-chip communication, and an input / output management module (Input / Output Management System Module) for managing data transmission between the interconnection network and external devices.

[0103] The design definition information based on the type definition of heterogeneous chip design includes descriptions of the master module, slave module, routing module, end-to-end cross-chip module, and input / output management module. Therefore, when classifying the communication interconnection modules extracted based on the design definition information, the modules can be classified according to the functions and behaviors of each communication interconnection module. For example, the routing module can be divided into: a routing module R1 for transmitting the interaction information between the master module and the slave module and connecting the master module / slave module, and a routing module R2 for transmitting the interaction information between the master module and the slave module and connecting the input / output management module (Input / Output Management System Module); each slave module is divided into one category, each master module is divided into one category, each input / output management module is divided into one category, and each end-to-end cross-chip module belonging to each chip design in the heterogeneous design chip is divided into one category, that is, the number of categories of the end-to-end cross-chip modules corresponds to the number of chip designs included in the heterogeneous chip design.

[0104] In the single-chip design and the single-channel chip design interconnection network, the end-to-end cross-chip module is not included, and all others are included. In the multi-channel chip design interconnection network, the end-to-end cross-chip module depends on the specific needs and design goals of the system. In scenarios where efficient cross-chip communication is required, including this module can significantly improve performance; in cases where communication requirements are simple or cost is limited, this module can be excluded to simplify the design. Except for the end-to-end cross-chip module, all other modules mentioned above are included.

[0105] Based on the above content, it can be seen that when verifying a chip design, a demand analysis and a definition of a verification plan are performed based on the type of chip design to be verified. The content formed by the definition is the design definition information. Therefore, when dividing each communication and interconnection module, it can be divided according to the specific design definition information.

[0106] Please continue to refer to Figure 2 , step S210 may include:

[0107] Step S2110 : Determine the type of the chip design to be verified, and obtain design definition information corresponding to the type of the chip design to be verified.

[0108] The design definition information corresponds to the type of the chip design to be verified, and includes description information of all components of the chip design to be verified of this type.

[0109] After classifying each communication interconnection module and establishing a corresponding representative communication interconnection module, each representative communication interconnection module is connected according to the connection relationship between the various communication interconnection modules in the chip design to be verified, forming a simplified chip design to be verified, and then performing consistency verification on the simplified chip design to be verified. Optionally, the implementation of step S215 may include:

[0110] Among the various sub-verification requirements of the system-level verification requirement, determine the current sub-verification requirement; based on the verification target of the current sub-verification requirement, determine the verification strategy that matches the verification target; and use the verification strategy to perform consistency verification on the simplified chip design to be verified.

[0111] The current sub-verification requirements may be interface verification requirements, functional verification requirements, reliability verification requirements, and security verification requirements, and may be determined based on a specific verification process.

[0112] Different sub-verification requirements have different verification objectives. For example, the interface verification requirement's objective is to clearly identify the internal and external interfaces that need to be verified. The functional verification requirement's objective is to clearly identify the functional modules and subsystems that need to be verified. The reliability verification requirement's objective is to clearly identify the fault tolerance and high-load stability that need to be verified. The security verification requirement's objective is to clearly identify the security functions and data integrity that need to be verified.

[0113] Verification strategy is the specific method and means to achieve system-level verification requirements. According to the different verification goals of different sub-verification requirements, appropriate verification strategy can be selected to meet the realization of verification goals.

[0114] For example, when the current sub-verification requirement is an interface verification requirement, the verification strategies selected for the target of the interface verification requirement may include:

[0115] Simulation verification: Use simulation tools to verify whether the internal and external interfaces of the Internet network comply with protocol specifications.

[0116] Protocol analyzer: Use a protocol analyzer to test the communication effect of the actual interface and verify protocol compatibility.

[0117] Interface test tools: Use interface test tools to verify the interoperability of the internetwork and external devices.

[0118] If the current sub-verification requirement is a functional verification requirement, the verification strategy selected for the functional verification requirement can include:

[0119] Simulation verification: Use simulation tools to simulate the behavior of the Internet and verify protocol consistency and data transmission integrity.

[0120] Formal verification: Use formal verification tools to prove whether the logical design of the internetwork complies with the protocol specifications.

[0121] Hardware-in-the-loop testing: Testing is performed in conjunction with hardware prototypes to verify functional performance in actual operation.

[0122] Of course, for verification requirements that are highly complex, difficult to verify, and require extremely high reliability, cross-validation, as described above, can be employed. Cross-validation can employ multiple different verification strategies or methods during the verification process to ensure the comprehensiveness and reliability of the verification results. By combining multiple verification strategies, cross-validation can help discover issues that a single verification strategy might miss, thereby improving the coverage and credibility of the verification.

[0123] In one embodiment, when the chip design to be verified is the heterogeneous chip design, determining the current sub-verification requirement among the sub-verification requirements of the system-level verification requirement includes:

[0124] Among the sub-verification requirements of the system-level verification requirement, determining that the current sub-verification requirement is to verify the interaction between the various chip designs in the heterogeneous chip design;

[0125] The step of determining a verification strategy that matches the verification target based on the current sub-verification requirement includes:

[0126] A verification goal based on the current sub-verification requirement: verifying the interaction consistency of each chip, and determining that the verification strategy that matches the verification goal is cross-verification;

[0127] The using the verification strategy to perform consistency verification on the simplified chip design to be verified includes:

[0128] Cross-validation is used to perform consistency verification on the topology structure formed by each chip design constituting the heterogeneous chip design; wherein, the topology structure is a simplified heterogeneous chip design to be verified formed by interconnecting the representative communication interconnection modules corresponding to the end-to-end cross-chip modules in each representative communication interconnection module of each chip design.

[0129] Due to the high complexity, verification difficulty and extremely high reliability requirements of heterogeneous chip design, a cross-validation verification strategy is adopted.

[0130] Based on the above, we can see that the heterogeneous chip design includes a master module, a slave module input / output management module, a routing module, and an end-to-end cross-chip module. Therefore, for each group of divided communication interconnection modules, the representative communication interconnection modules established can be connected according to the interconnection relationship between the various communication interconnection modules in the heterogeneous chip design.

[0131] To illustrate the connection implementation of representative communication interconnection modules corresponding to each communication interconnection module group under heterogeneous chip design, please refer to Figure 3 and Figure 4 , Figure 3 1 is a schematic diagram of a heterogeneous chip design provided by an embodiment of the present invention. Figure 4 Yes Figure 3 The simplified schematic diagram of the chip design structure to be verified is formed after the structure is processed.

[0132] Figure 3 The figure shows a typical interconnection network of a heterogeneous chip design, which includes a master module, a slave module, an input and output management system module, a routing module, and an end-to-end cross-chip module.

[0133] The Master module is usually connected to various Master devices, such as the CPU (Central Processing Unit) / DCU (Deep Computing Unit);

[0134] The Input / Output Management System (IOMS) module typically connects to NBIO (non-blocking I / O module) peripherals. The I / O Master / Slave (IOMS) module is a specialized module that handles I / O-related data transmission and communication. The IOMS module typically combines the functionality of both Master and Slave modules, specifically managing I / O operations and ensuring efficient and accurate transmission of I / O data across interconnected networks (such as NoCs). It serves as a key interface between external devices and internal processing modules within the NoC architecture.

[0135] The slave module is connected to DDR (Double Data Rate SDRAM) / CXL MEMORY (Compute Express Link Memory), etc.

[0136] The routing modules form a complex network to forward data packets between master modules or slave modules;

[0137] The end-to-end cross-chip module connects different chip designs in heterogeneous chip designs to complete server expansion.

[0138] certainly, Figure 3 This is just a typical scale of a heterogeneous chip design. A type of chip design (including heterogeneous chip design) may include hundreds of combinations of master modules, slave modules, routing modules, and end-to-end cross-chip modules. The structure and design of each communication and interconnection module are relatively complex. The compilation and simulation time of each chip design (die) composed of various communication and interconnection modules is relatively long.

[0139] Moreover, because heterogeneous chip designs have different functional focuses, the master modules and slave modules that make up different chip designs have different focuses, which ultimately leads to multiple combinations of single chip designs. In a server product, there can be dozens of chip designs with different combinations, making the overall system debugging cycle of heterogeneous chip designs very complicated.

[0140] In order to reduce the complexity of consistency verification of heterogeneous chip designs and improve the efficiency of consistency verification, the method provided in the embodiment of the present invention is adopted to classify the various communication interconnection modules of heterogeneous chip designs, and establish a representative communication interconnection module corresponding to each group of communication interconnection modules, so that the various representative communication interconnection modules are connected according to the interconnection method of the chip design to be verified (for example, heterogeneous chip design), forming a simplified chip design to be verified, and then performing consistency verification on the simplified chip design to be verified.

[0141] Therefore, based on Figure 3 The number and interconnection relationships of the communication interconnection modules of the heterogeneous chip design shown are first extracted, and then the communication interconnection modules are classified, and the classified communication interconnection modules are connected to form a simplified heterogeneous chip design to be verified.

[0142] To simplify the design of heterogeneous chips to be verified, you can refer to Figure 4 , Figure 4 In accordance with Figure 3 The complex routing structure (such as Mesh structure) composed of the various Dies shown connects the various representative communication interconnection modules to form a simplified heterogeneous chip design to be verified. The topology structure formed by the various Dies can still be a Mesh structure.

[0143] Figure 3The heterogeneous chip design shown includes four dies, defined based on end-to-end cross-chip modules. Each die, defined for each of the four end-to-end cross-chip modules, has different functions and behaviors. The communication and interconnection modules included in each die are: multiple slave modules, multiple master modules, multiple routing modules, and multiple IOMS modules.

[0144] For Figure 3 The heterogeneous design chip shown here simplifies the establishment of the heterogeneous chip design to be verified. Please refer to Figure 4 .

[0145] Figure 4 In the example, for each Die determined based on each end-to-end cross-chip module, a representative Slave module is established for each Salve module, a representative Master module is established for each Master module, a representative IOMS module is established for each IOMS module, a representative routing module R1 is established for each routing module connected to the master module / slave module, and a representative routing module R2 is established for each routing module connected to the IOMS module.

[0146] Then, follow Figure 3 The interconnection relationship between each Die and each other in the heterogeneous chip design shown in the figure connects each representative communication interconnection module to form the following Figure 4 The topology shown.

[0147] Figure 4 As shown, when the chip design to be verified is a heterogeneous chip design, the corresponding topological structure is formed. Based on the simplified heterogeneous chip design to be verified, the complexity of consistency verification of the complete heterogeneous chip design can be reduced, thereby improving the consistency verification efficiency.

[0148] In other embodiments, a simplified chip design to be verified can also be established based on other types of chip designs to be verified. For example, when the chip design to be verified is a single-chip design of the aforementioned single-chip type, the simplified chip design to be verified can be a simplified single-chip design to be verified; when the chip design to be verified is a multi-way chip design of a multi-way type, the simplified chip design to be verified can be: a simplified multi-way chip design to be verified; when the chip design to be verified is a single-way chip design of a single-way type, the simplified chip design to be verified can be: a simplified single-way chip design to be verified.

[0149] It can be seen that in the embodiment of the present invention, when establishing a simplified chip design to be verified, it can be flexibly established according to the project needs (the specific type of chip design to be verified), and the overall scale of the simplified chip design to be verified is many times smaller than the actual specific type of chip design scale. And because the simplified chip design to be verified is composed of representative communication interconnection modules, and the representative communication interconnection modules can represent the behavior and function of each interconnected communication module under different communication interconnection module groups in the chip design to be verified, the simplified chip design to be verified can still have the same behavior as the chip design to be verified even if it is smaller in scale, and can simulate the behavior and interaction of the chip design to be verified. Therefore, consistency verification of the simplified chip design to be verified can achieve the same effect as consistency verification of the chip design to be verified, and because the scale of the simplified chip design to be verified is smaller, the time for consistency verification (such as simulation time) can be shortened, for example, it can be completed within half a day, which can improve the consistency verification efficiency of the chip design to be verified, and at the same time ensure that when the consistency-related design is updated (i.e., the consistency change visible to the system), it can be fully verified on the minimized simplified chip design to be verified.

[0150] In addition to verifying the simplified chip design to be verified as a whole, consistency verification also includes consistency verification of each sub-module of the chip design, which is the non-communication interconnection module mentioned above. Therefore, in one embodiment, before the step of performing consistency verification on each of the representative communication interconnection modules according to the system-level verification requirements of the chip design to be verified, the method further includes:

[0151] According to the system-level verification requirements of the chip design to be verified, consistency verification is performed on each non-communication interconnection module in the chip design to be verified, which is defined by the design definition information.

[0152] Perform consistency verification on non-communication interconnection modules, including functional consistency verification, interface consistency verification, timing consistency verification, performance consistency verification and other aspects.

[0153] Consistency verification of non-communication interconnect modules forms the foundation for consistency verification of the entire chip design system. This consistency verification of the entire chip design system is crucial for ensuring the overall performance and reliability of the chip design. In the actual chip design process, consistency verification of both non-communication interconnect modules and the overall chip design system ensures high quality and reliability.

[0154] To meet usage requirements, chip designs are often continuously updated, and these updates may include updates related to consistency features. For example, these updates may include protocol updates. As technology evolves, chip designs may adopt new communication protocols or optimize existing protocols. For example, upgrading from PCIe 3.0 (PCI Express 3.0, Peripheral Component Interconnect Express 3.0) to PCIe 4.0 (PCI Express 4.0, Peripheral Component Interconnect Express 4.0), or improving the communication protocols of the on-chip network (NoC).

[0155] Updates to the consistency features of chip designs have multiple impacts on consistency verification, including expanded verification scope, increased verification complexity, updates to verification tools and environments, and increased regression verification pressure.

[0156] Since consistency feature updates (such as protocol updates) are usually internal configuration attribute updates of certain modules in the chip design, there is no need to change the module hardware itself or the connection relationship between modules. Therefore, based on the establishment of representative communication interconnection modules and the connection of representative communication interconnection modules to form a simplified chip design to be verified, when it is determined that a consistency feature update has occurred in the chip design, the updated consistency feature can still be re-verified on the simplified chip design to be verified, thereby shortening the consistency verification time.

[0157] Specifically, the method may further include: when it is determined that the chip design to be verified is updated, obtaining design update information of the chip design to be verified;

[0158] When the design update information indicates that the update content is an update of the consistency characteristics, the steps of performing consistency verification on each non-communication interconnection module in the chip design to be verified as defined by the design definition information according to the system-level verification requirements of the chip design to be verified, and the steps of performing consistency verification on each of the representative communication interconnection modules according to the system-level verification requirements of the chip design to be verified are executed.

[0159] Determining whether there is a design update for the chip design to be verified can be performed by checking the chip design to be verified when starting to perform consistency verification.

[0160] The update of the consistency characteristic also does not affect the structure of the non-communication interconnection module itself. Therefore, the consistency verification of the non-communication interconnection module can be performed again based on the updated consistency characteristic.

[0161] An embodiment of the present invention further provides a chip design verification method, which is implemented based on the consistency verification method described in the above embodiment.

[0162] Please refer to Figure 5 , Figure 5 1 is a flow chart of a chip design verification method provided by an embodiment of the present invention.

[0163] like Figure 5 As shown, the method includes the following steps:

[0164] Step S301: Obtain consistency verification completion information of the chip design to be verified.

[0165] The consistency verification completion information is generated after consistency verification is performed on each representative communication interconnection module in the chip design to be verified based on the consistency verification method as described in any of the aforementioned embodiments.

[0166] Step S302 : performing simulation verification and regression convergence check on the chip design to be verified, thereby completing verification of the chip design to be verified.

[0167] The test stimulus and verification component used when performing simulation verification and regression convergence detection on the chip design to be verified are: the test stimulus and verification component used when performing consistency verification on each of the representative communication interconnection modules.

[0168] The chip design verification process also includes:

[0169] System Verification:

[0170] Its goal is to verify that the overall system functionality and performance of the entire chip design meet the design specifications.

[0171] Methods that can be used include:

[0172] System Simulation: Use advanced simulation tools (such as SystemC) to simulate the entire system to verify the interaction between modules and the overall system functionality.

[0173] Hardware-in-the-Loop (HIL): Connecting actual hardware modules with simulation models to verify the performance of the system in the actual hardware environment.

[0174] Hardware Emulation: Use a hardware emulation platform (such as an FPGA or dedicated hardware emulator) to perform large-scale verification to verify the performance and functionality of the system.

[0175] Output: Generate a system verification report to ensure that the functionality and performance of the entire system meet the design specifications.

[0176] Regression Testing:

[0177] Its goal is to ensure that the system's functionality and performance continue to meet design specifications after the chip design is modified or updated.

[0178] Regression testing may involve the following aspects:

[0179] Functional regression testing: Verifies that the modified design still meets the functional specifications.

[0180] Performance regression testing: Verifies that the modified design still meets the performance specifications.

[0181] Compatibility regression testing: Verifies that the modified design is still compatible with external devices and systems.

[0182] Methods that can be used include:

[0183] Automated testing: Use automated testing tools to run a series of existing test cases to ensure that the changes do not introduce new problems.

[0184] Continuous Integration (CI): Continuously perform regression testing during the development process to ensure that each code submission passes verification.

[0185] Since the purpose of consistency verification of chip design is to ensure that the entire chip design can run correctly in various working scenarios and meet the design specifications. The ultimate goal of simulation verification and regression convergence check is also the correctness and reliability of the chip design to be verified. Therefore, the stimulus and verification components (UVC, Universal Verification Components) used in the consistency verification of the chip design to be verified are consistent with the stimulus and verification components used in simulation verification and regression convergence detection in terms of goals, both for the purpose of determining whether the chip design to be verified meets expectations. At the same time, the stimulus used in the consistency verification of the chip design to be verified usually covers the main functions and interaction scenarios of the chip design to be verified. These incentives are still applicable in simulation verification and regression convergence detection because they can effectively trigger and verify the key functions and boundary conditions of the chip design. Therefore, the test incentives and verification components used when each of the representative communication interconnection modules performs consistency verification can use the test incentives and verification components used when the chip design to be verified performs simulation verification and regression convergence detection.

[0186] The universality and reusability of test stimuli refer to:

[0187] The test stimuli used in consistency verification of the chip design under verification are typically carefully designed to cover a variety of functions and scenarios. These test stimuli are applicable not only to full-system verification but also to module-level simulation and regression testing. For example, a test stimulus used to verify a network-on-chip (NoC) can be used to test the network's routing functionality, bandwidth utilization, packet transmission, and other functions. These functions also need to be verified in module-level simulation and regression testing, so they can be used universally.

[0188] Reusability: The reusability of test stimuli can significantly improve verification efficiency. Test stimuli developed during consistency verification of the chip design to be verified can be directly used for simulation verification and regression convergence testing, reducing the workload of repeated development. For example, a test stimulus used to verify the interaction between the processor and memory can verify the processor's cache coherence in block-level simulation and the performance and reliability of the memory controller in regression convergence testing.

[0189] The versatility and scalability of UVC refer to:

[0190] UVC's versatility: UVCs are verification components based on universal interfaces and protocols, adaptable to diverse verification scenarios. They are typically highly flexible and scalable, allowing for configuration and expansion to meet diverse verification requirements. For example, a UVC used to verify data transmission can be configured to support different packet formats, transmission rates, and error injection mechanisms.

[0191] UVC's scalability: UVC can be easily extended to support new functions and protocols. UVC developed during full system consistency verification can be adapted to new verification requirements by adding new functional modules or modifying existing modules. For example, if a new communication protocol is introduced, UVC can be extended to support the new protocol without redeveloping the entire verification component.

[0192] Since the representative communication interconnection module has the same functions and behaviors as the communication interconnection module of the chip design to be verified, and the communication interconnection modules (routing module, Slave module, Master, IOMS module) all support standard interfaces, the difference between the representative communication interconnection module and the various communication interconnection modules of the interconnection network in the actual chip design is only the difference in quantity, and the functions and behaviors are unchanged. Therefore, the constraints and implementation of the test stimulus are essentially the same for simplifying the chip design to be verified and the consistency verification of the chip design to be verified, and the test stimulus and verification components used for consistency verification of each of the representative communication interconnection modules can be parameterized. When the overall system of the chip design to be verified is migrated to a simulation platform, the differentiation of heterogeneous chip designs can also be solved, so that the overall system of the chip design can be used in the simulation operation project, and the development and inspection parts of the verification interface module are well reused.

[0193] At the same time, due to the simplification of the chip design to be verified (such as Figure 4 In the simplified heterogeneous chip design to be verified shown in the figure, each Die and the representative interconnection communication module included in each Die are as similar as possible to the version of the communication interconnection module of the actual chip design. In this way, the verification environment used to fully verify and debug the simplified chip design to be verified can be directly migrated to its corresponding actual chip design to be verified, so that the actual chip design to be verified is mainly based on running simulation verification and regression convergence check, thereby solving a small number of random iteration problems and eliminating the need for large-scale iterative debugging.

[0194] In addition, during regression convergence testing, since sufficient verification and iteration can be performed on non-communication interconnection modules and simplified chip designs to be verified, simulation runs and a small amount of debugging are concentrated on the overall system of the chip design to be verified, achieving rapid convergence of verification.

[0195] It can be seen that in the chip design verification method provided by the embodiment of the present invention, since the test stimuli and verification components used when each of the representative communication interconnection modules is used for consistency verification are continued to be used, it is possible to further improve the verification efficiency, reduce duplication of work, and ensure the high quality and high reliability of the chip design on the basis of improving the consistency verification efficiency achieved when each of the representative communication interconnection modules is used for consistency verification.

[0196] An embodiment of the present invention further provides a consistency verification device as a structure for implementing the consistency verification method described in any of the aforementioned embodiments.

[0197] Please refer to Figure 6 , Figure 6 It is a structural diagram of a consistency verification device provided by an embodiment of the present invention.

[0198] like Figure 6 As shown, the device includes:

[0199] A design definition information acquisition module 60 is used to acquire design definition information of the chip design to be verified;

[0200] An extraction module 61 is configured to extract various communication interconnection modules included in the interconnection network in the chip design to be verified, as defined in the design definition information;

[0201] a classification module 62 for classifying the extracted communication interconnection modules according to their functions and behaviors to obtain classified groups of communication interconnection modules; each group of communication interconnection modules includes communication interconnection modules having the same functions and behaviors;

[0202] Establishing module 63, configured to establish a representative communication interconnection module for each communication interconnection module group, wherein the functions and behaviors of the representative communication interconnection module are the same as the functions and behaviors of the individual communication interconnection modules included in the corresponding communication interconnection module group;

[0203] The consistency verification module 64 is used to perform consistency verification on each of the representative communication and interconnection modules according to the system-level verification requirements of the chip design to be verified.

[0204] Optionally, the consistency verification device further includes:

[0205] A simplified chip design to be verified forms a module, which is used to connect each of the representative communication and interconnection modules according to the interconnection relationship between the various communication and interconnection modules in the chip design to be verified, so as to form a simplified chip design to be verified that is equivalent to the chip design to be verified; the simplified chip design to be verified simulates the behavior and interaction of the chip design to be verified.

[0206] Optionally, the consistency verification module 64 is configured to perform consistency verification on each of the representative communication interconnection modules according to the system-level verification requirements of the chip design to be verified, including:

[0207] Determining, according to the type of the chip design, a system-level verification requirement of the corresponding type, wherein the system-level verification requirement includes at least one sub-verification requirement;

[0208] For each sub-verification requirement in the determined system-level verification requirement, a verification strategy matching each sub-verification requirement is used to perform consistency verification on the simplified chip design to be verified.

[0209] Optionally, the consistency verification device further includes:

[0210] The non-communication interconnection module consistency verification module is used to perform consistency verification on each non-communication interconnection module in the chip design according to the system-level verification requirements of the chip design to be verified.

[0211] It can be seen that in the technical solution provided by the embodiment of the present invention, since the consistency verification of the interconnection network is a key link in the consistency verification process of the chip design, when the chip design is consistency verified, the various communication interconnection modules included in the interconnection network in the chip design to be verified are first extracted based on the design definition information of the chip design to be verified. The communication interconnection modules in the interconnection network have different types according to the functional modules of the chip design to which they are connected (the behavior of the communication interconnection modules) and their own functions (the functions of the communication interconnection modules). Therefore, in the embodiment of the present invention, after all the communication interconnection modules are extracted, the communication interconnection modules are further classified according to the functions and behaviors of the communication interconnection modules to obtain groups of communication interconnection modules with the same functions and behaviors; and a representative communication interconnection module is established for each group of communication interconnection modules, that is, a representative communication interconnection module is established for multiple communication interconnection modules of the same type. Since the functions and behaviors of the representative communication interconnection module are the same as the functions and behaviors of each communication interconnection module in the corresponding communication interconnection module group, the consistency verification of each type of communication interconnection module in the chip design to be verified can be achieved by performing consistency verification on each representative communication interconnection module; therefore, in the process of performing consistency verification on each of the representative communication interconnection modules according to the system-level verification requirements of the chip design to be verified, it is possible to ensure the consistency verification of the chip design to be verified, and reduce the complexity of verifying all communication interconnection modules in the chip design to be verified, thereby improving the verification efficiency of the chip design.

[0212] An embodiment of the present invention further provides a chip design verification device, which serves as a structure for implementing the chip design verification method described in any of the aforementioned embodiments.

[0213] Please refer to Figure 7 , Figure 7 Schematic diagram of a chip design verification device according to an embodiment of the present invention.

[0214] like Figure 7 As shown, the device includes:

[0215] An information acquisition module 70 is configured to acquire consistency verification completion information of the chip design to be verified; the consistency verification completion information is generated by performing consistency verification on each representative communication interconnection module in the chip design to be verified based on the consistency verification apparatus as described in any of the preceding items;

[0216] A simulation convergence module 71 is used to perform simulation verification and regression convergence check on the chip design to be verified, thereby completing verification of the chip design to be verified;

[0217] The test stimulus and verification component used when performing simulation verification and regression convergence detection on the chip design to be verified are: the test stimulus and verification component used when performing consistency verification on each of the representative communication interconnection modules.

[0218] It can be seen that in the chip design verification device provided by the embodiment of the present invention, since the test stimuli and verification components used when each of the representative communication and interconnection modules are used for consistency verification are continued to be used, it is possible to further improve the verification efficiency, reduce duplication of work, and ensure the high quality and high reliability of the chip design on the basis of improving the consistency verification efficiency achieved when each of the representative communication and interconnection modules is used for consistency verification.

[0219] An embodiment of the present invention provides an electronic device, such as a terminal device, a server device, or other computer device, including a memory and a processor, wherein the memory stores a program, and the processor calls the program stored in the memory to execute the consistency verification method as described in any of the foregoing embodiments, or executes the chip design verification method as described in any of the foregoing embodiments.

[0220] The above describes multiple embodiment schemes provided by the embodiments of the present invention. The various optional methods introduced in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible embodiment schemes, which can all be considered as embodiment schemes disclosed and open in the embodiments of the present invention.

[0221] Although the embodiments of the present invention are disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A consistency verification method, characterized in that: include: Obtaining design definition information of the chip design to be verified; Extracting each communication interconnection module included in the interconnection network in the chip design to be verified, as defined in the design definition information; Classifying the extracted communication and interconnection modules according to their functions and behaviors to obtain classified groups of communication and interconnection module groups; each group of communication and interconnection module groups includes communication and interconnection modules with the same functions and behaviors; A representative communication interconnection module is established for each communication interconnection module group, and the functions and behaviors of the representative communication interconnection module are the same as the functions and behaviors of each communication interconnection module included in the corresponding communication interconnection module group; According to the system-level verification requirements of the chip design to be verified, consistency verification is performed on each of the representative communication and interconnection modules.

2. The consistency verification method according to claim 1, wherein: Before the step of performing consistency verification on each of the representative communication interconnection modules according to the system-level verification requirements of the chip design to be verified, the method further includes: Each of the representative communication and interconnection modules is connected accordingly according to the interconnection relationship between the various communication and interconnection modules in the chip design to be verified, so as to form a simplified chip design to be verified that is equivalent to the chip design to be verified; the simplified chip design to be verified simulates the behavior and interaction of the chip design to be verified.

3. The consistency verification method according to claim 2, wherein: The consistency verification of each of the representative communication interconnection modules according to the system-level verification requirements of the chip design to be verified includes: Determining, according to the type of the chip design, a system-level verification requirement of the corresponding type, wherein the system-level verification requirement includes at least one sub-verification requirement; For each sub-verification requirement in the determined system-level verification requirement, a verification strategy matching each sub-verification requirement is used to perform consistency verification on the simplified chip design to be verified.

4. The consistency verification method according to claim 3, wherein: The obtaining of design definition information of the chip design to be verified includes: Determining the type of the chip design to be verified, and obtaining design definition information corresponding to the type of the chip design to be verified; The classifying of the extracted communication interconnection modules includes: The extracted communication and interconnection modules are classified according to the functions and behaviors of the communication and interconnection modules in the determined design definition information, and the communication and interconnection modules corresponding to each category are obtained.

5. The consistency verification method according to claim 4, wherein: The method further comprises: performing consistency verification on the simplified chip design to be verified for each sub-verification requirement in the determined system-level verification requirement by using a verification strategy that matches each sub-verification requirement, including: Determine the current sub-verification requirement among the sub-verification requirements of the system-level verification requirement; Determining, based on the verification target of the current sub-verification requirement, a verification strategy that matches the verification target; The verification strategy is used to perform consistency verification on the simplified chip design to be verified.

6. The consistency verification method according to claim 5, wherein: The types of chip designs to be verified include: heterogeneous chip designs of heterogeneous types, single-chip designs of single-chip types, multi-way chip designs of multi-way types, and single-way chip designs of single-way types; the simplified chip designs to be verified include: simplified heterogeneous chip designs to be verified, simplified single-chip designs to be verified, simplified multi-way chip designs to be verified, and simplified single-way chip designs to be verified.

7. The consistency verification method according to claim 6, wherein: When the chip design to be verified is the heterogeneous chip design, determining the current sub-verification requirement among the sub-verification requirements of the system-level verification requirement includes: Among the sub-verification requirements of the system-level verification requirement, determining that the current sub-verification requirement is to verify the interaction between the various chip designs in the heterogeneous chip design; The step of determining a verification strategy that matches the verification target based on the current sub-verification requirement includes: A verification goal based on the current sub-verification requirement: verifying the interaction consistency of each chip, and determining that the verification strategy that matches the verification goal is cross-verification; The using the verification strategy to perform consistency verification on the simplified chip design to be verified includes: Cross-validation is used to perform consistency verification on the topology structure formed by each chip design constituting the heterogeneous chip design; wherein, the topology structure is a simplified heterogeneous chip design to be verified formed by interconnecting the representative communication interconnection modules corresponding to the end-to-end cross-chip modules in each representative communication interconnection module of each chip design.

8. The consistency verification method according to any one of claims 1 to 7, wherein: Before the step of performing consistency verification on each of the representative communication interconnection modules according to the system-level verification requirements of the chip design to be verified, the method further includes: According to the system-level verification requirements of the chip design to be verified, consistency verification is performed on each non-communication interconnection module in the chip design to be verified, which is defined by the design definition information.

9. The consistency verification method according to claim 8, wherein: The method further comprises: When determining that the chip design to be verified has been updated, obtaining design update information of the chip design to be verified; When the design update information indicates that the update content is an update of the consistency characteristics, the steps of performing consistency verification on each non-communication interconnection module in the chip design to be verified as defined by the design definition information according to the system-level verification requirements of the chip design to be verified, and the steps of performing consistency verification on each of the representative communication interconnection modules according to the system-level verification requirements of the chip design to be verified are executed.

10. A chip design verification method, characterized in that: include: Obtain consistency verification completion information for the chip design to be verified; The consistency verification completion information is generated after consistency verification is performed on each representative communication interconnection module in the chip design to be verified based on the consistency verification method according to any one of claims 1 to 9; Performing simulation verification and regression convergence check on the chip design to be verified to complete verification of the chip design to be verified; The test stimulus and verification component used when performing simulation verification and regression convergence detection on the chip design to be verified are: the test stimulus and verification component used when performing consistency verification on each of the representative communication interconnection modules.

11. A consistency verification device, characterized in that: include: A design definition information acquisition module, used to obtain design definition information of the chip design to be verified; An extraction module, configured to extract each communication interconnection module included in the interconnection network in the chip design to be verified, as defined in the design definition information; a classification module for classifying the extracted communication interconnection modules according to their functions and behaviors to obtain classified groups of communication interconnection module groups; each group of communication interconnection module groups includes communication interconnection modules with the same functions and behaviors; An establishment module, configured to establish a representative communication interconnection module for each communication interconnection module group, wherein the functions and behaviors of the representative communication interconnection module are the same as the functions and behaviors of each communication interconnection module included in the corresponding communication interconnection module group; The consistency verification module is used to perform consistency verification on each of the representative communication interconnection modules according to the system-level verification requirements of the chip design to be verified.

12. The consistency verification device according to claim 11, wherein: Also includes: A simplified chip design to be verified forms a module, which is used to connect each of the representative communication and interconnection modules according to the interconnection relationship between the various communication and interconnection modules in the chip design to be verified, so as to form a simplified chip design to be verified that is equivalent to the chip design to be verified; the simplified chip design to be verified simulates the behavior and interaction of the chip design to be verified.

13. The consistency verification device according to claim 12, wherein: The consistency verification module is configured to perform consistency verification on each of the representative communication and interconnection modules according to the system-level verification requirements of the chip design to be verified, including: Determining, according to the type of the chip design, a system-level verification requirement of the corresponding type, wherein the system-level verification requirement includes at least one sub-verification requirement; For each sub-verification requirement in the determined system-level verification requirement, a verification strategy matching each sub-verification requirement is used to perform consistency verification on the simplified chip design to be verified.

14. The consistency verification device according to claim 13, wherein: Also includes: The non-communication interconnection module consistency verification module is used to perform consistency verification on each non-communication interconnection module in the chip design according to the system-level verification requirements of the chip design to be verified.

15. A chip design verification device, characterized in that: include: An information acquisition module is used to obtain consistency verification completion information of the chip design to be verified; The consistency verification completion information is generated after consistency verification is performed on each representative communication interconnection module in the chip design to be verified based on the consistency verification device according to any one of claims 11 to 14; A simulation convergence module, configured to perform simulation verification and regression convergence check on the chip design to be verified, thereby completing verification of the chip design to be verified; The test stimulus and verification component used when performing simulation verification and regression convergence detection on the chip design to be verified are: the test stimulus and verification component used when performing consistency verification on each of the representative communication interconnection modules.

16. An electronic device, characterized in that: It includes a memory and a processor, the memory stores a program, and the processor calls the program stored in the memory to execute the consistency verification method as described in any one of claims 1 to 9, or executes the chip design verification method as described in claim 10.

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