Semiconductor circuit board and method of arranging inspection elements thereon

Abstract

The application provides a semiconductor circuit substrate, a configuration method and device of an inspection element, a computer device, a readable storage medium and a program product. In the semiconductor circuit substrate, a plurality of chip parts of the same specification are arranged in a repeated arrangement, and a cutting path is arranged between each chip part. The chip part has a low-voltage region with more low-voltage devices arranged than high-voltage devices, and a high-voltage region with more high-voltage devices arranged than low-voltage devices. A low-voltage inspection element is arranged in a range adjacent to the low-voltage region in the cutting path, and a high-voltage inspection element is arranged in a range adjacent to the high-voltage region in the cutting path. The application can improve the detection accuracy of the detection element.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a semiconductor circuit substrate, a configuration method, device, computer equipment, readable storage medium and program product of an inspection element of the semiconductor circuit substrate. BACKGROUND

[0002] In a semiconductor circuit substrate, an inspection element for characteristic inspection is often arranged outside a chip portion that becomes a final product. The inspection element is often arranged on a dicing lane between chip portions. In the related art, there is a case where the inspection result of the inspection element before dicing is not accurate. SUMMARY

[0003] The present application relates to the technical field of semiconductor technology, and in particular to a semiconductor circuit substrate, a configuration method, device, computer equipment, readable storage medium and program product of an inspection element of the semiconductor circuit substrate.

[0004] A semiconductor circuit substrate in which a plurality of chip portions of the same specification are arranged in a repeated arrangement and a dicing lane is provided between each of the chip portions,

[0005] wherein

[0006] the chip portion has:

[0007] a low-voltage region in which a low-voltage device is arranged more than a high-voltage device; and

[0008] a high-voltage region in which a high-voltage device is arranged more than a low-voltage device,

[0009] a low-voltage inspection element is provided in a range adjacent to the low-voltage region in the dicing lane,

[0010] and a high-voltage inspection element is provided in a range adjacent to the high-voltage region in the dicing lane.

[0011] In one embodiment,

[0012] the chip portion is a long strip shape in which the size in the long direction is more than 10 times the size in the short direction.

[0013] A configuration method of an inspection element in a semiconductor circuit substrate in which a plurality of chip portions of the same specification are arranged in a repeated arrangement and a dicing lane is provided between each of the chip portions, the chip portion has a low-voltage region in which a low-voltage device is arranged more than a high-voltage device and a high-voltage region in which a high-voltage device is arranged more than a low-voltage device,

[0014] the configuration method of the inspection element in the semiconductor circuit substrate includes:

[0015] acquire division information of the low-voltage region and the high-voltage region in the chip portion;

[0016] determine whether a position on the dicing lane where an inspection element is to be arranged is in a range adjacent to the low-voltage region or in a range adjacent to the high-voltage region;

[0017] in a case where the result of the determination is that the position is in the range adjacent to the low-voltage region, arrange a low-voltage inspection element at the position;

[0018] in a case where the result of the determination is that the position is in the range adjacent to the high-voltage region, arrange a high-voltage inspection element at the position.

[0019] In one embodiment, the acquiring of the division information of the low-voltage region and the high-voltage region in the chip portion includes:

[0020] acquiring the division information of the low-voltage region and the high-voltage region in the chip portion based on information of a specification of the chip portion.

[0021] In one embodiment, the acquiring of the division information of the low-voltage region and the high-voltage region in the chip portion includes:

[0022] acquiring the division information of the low-voltage region and the high-voltage region in the chip portion based on information of a mask plate of the chip portion, the mask plate including a pattern that defines the low-voltage device or the high-voltage device in the chip portion.

[0023] In one embodiment,

[0024] dividing a region in which a distribution density of the low-voltage device is a first value or more into the low-voltage region,

[0025] dividing a region in which the distribution density of the low-voltage device is a second value or less into the high-voltage region, the second value being a value that is the same as or lower than the first value.

[0026] An arrangement device of an inspection element in a semiconductor circuit substrate in which a plurality of chip portions of the same specification are arranged in a repeating arrangement with a dicing lane provided between each of the chip portions, the chip portion having a low-voltage region and a high-voltage region, the low-voltage region in which a low-voltage device is arranged more than a high-voltage device, and the high-voltage region in which a high-voltage device is arranged more than a low-voltage device,

[0027] The device includes:

[0028] a region division acquisition module configured to acquire division information of the low-voltage region and the high-voltage region in the chip portion.

[0029] a determination module configured to determine whether a position on the scribe lane at which the inspection element is to be arranged is in a range adjacent to the low-voltage region or in a range adjacent to the high-voltage region;

[0030] an arrangement module configured to arrange a low-voltage inspection element at the position when the determination result is that the position is in the range adjacent to the low-voltage region, and to arrange a high-voltage inspection element at the position when the determination result is that the position is in the range adjacent to the high-voltage region.

[0031] A computer device includes a memory and a processor, the memory stores a computer program, and the processor implements the steps of the above method when executing the computer program.

[0032] A computer readable storage medium stores a computer program, and the computer program implements the steps of the above method when executed by a processor.

[0033] A computer program product includes a computer program, and the computer program implements the steps of the above method when executed by a processor.

[0034] The semiconductor circuit substrate and the arrangement method, device, computer device, readable storage medium, and program product of the inspection element thereof, when arranging the inspection element on the scribe lane of the semiconductor circuit substrate, consider whether the region in the chip portion adjacent to the arranged position is a low-voltage region or a high-voltage region. Then, in the case of a low-voltage region, a low-voltage inspection element is arranged at the position, and in the case of a high-voltage region, a high-voltage inspection element is arranged at the position. Thus, the detection accuracy of the detection element is improved by reducing the deviation of the measured value caused by the arrangement position of the inspection element. At this time, the inspection can be performed more accurately without preparing two kinds of inspection determination values for the low-voltage region and the high-voltage region, and thus the detection efficiency can also be improved. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 is a plan view of the configuration of the chip portion in an embodiment.

[0036] Figure 2 is a plan view of the semiconductor circuit substrate in an embodiment.

[0037] Figure 3 is a graph of the environmental dependence of the measured value of the polysilicon resistor in an embodiment.

[0038] Figure 4 is a graph of the difference between the measured values of the low-voltage element and the high-voltage element in an embodiment.

[0039] Figure 5This is a schematic diagram illustrating the relationship between the development model and the information of the inspection element in one embodiment of this application.

[0040] Figure 6 This is a flowchart illustrating a method for configuring inspection elements in a semiconductor circuit board in one embodiment;

[0041] Figure 7 This is a structural block diagram of a configuration device for inspection elements in a semiconductor circuit board in one embodiment.

[0042] Explanation of reference numerals in the attached figures:

[0043] 1-Chip section; 2-High voltage area; 3-Low voltage area; 4-Cutting channel; 10-Semiconductor circuit board; 100-Area acquisition module; 200-Judgment module; 300-Configuration module. Detailed Implementation

[0044] The following describes the specific implementation of this application.

[0045] In one embodiment, a semiconductor circuit substrate is provided. In this semiconductor circuit substrate, a plurality of chip portions 1 of the same specification are arranged in a repeating pattern and dicing lines 4 are provided between each chip portion 1.

[0046] First, the chip section 1 included in the semiconductor circuit board of this application will be described. For example... Figure 1 As shown, the internal portion of the chip section 1 in this application is divided into a high-voltage region 2 and a low-voltage region 3. The low-voltage region 3 contains more low-voltage devices than high-voltage devices. The high-voltage region 2 contains more high-voltage devices than low-voltage devices.

[0047] For example, the devices configured in the chip section 1 are classified according to their driving voltage into first voltage devices (e.g., devices with a driving voltage of 1.2V or less), third voltage devices (e.g., devices with a driving voltage of approximately 28~32V), and second voltage devices (e.g., devices with a driving voltage of approximately 5~8V). The first voltage devices are referred to as low-voltage devices. The third voltage devices and second voltage devices are collectively referred to as high-voltage devices. Therefore, high-voltage region 2 is the region where the number of third and second voltage devices is greater than that of first voltage devices. Low-voltage region 3 is the region where the number of first voltage devices is greater than that of third and second voltage devices.

[0048] For example, the chip portion 1 in this application can be an elongated chip portion with a length that is more than 10 times the length of its short side. Such a high aspect ratio chip portion 1 is commonly used, for example, in driver ICs. In the case of this type of chip portion 1, the high voltage region 2 and the low voltage region 3 are approximately along its length (…). Figure 1 The second direction in the middle is divided.Figure 1 In the example, the upper and lower parts of the second direction are high-pressure region 2, and a low-pressure region 3 is arranged in the middle.

[0049] like Figure 2 As shown, in the semiconductor circuit board 10, a plurality of chip sections 1 are arranged in a repeating pattern. Figure 2 The number of chip sections 1 arranged along the first direction can also be greater. Figure 2 Multiple chip sections 1 are also configured in the second direction. Figure 2 Multiple chip sections 1 in the middle can all be connected to Figure 1 The chip section 1 shown is the same. Therefore, in Figure 2 In this configuration, the high-voltage regions 2 of each chip section 1 are arranged side by side. The low-voltage regions 3 of each chip section 1 are also arranged side by side.

[0050] The dividing line between chip sections 1 is called a cutting track 4. Meanwhile, a low-voltage inspection element is provided in the cutting track 4 within the range adjacent to the low-voltage region, and a high-voltage inspection element is provided in the cutting track within the range adjacent to the high-voltage region.

[0051] exist Figure 2 In the diagram, eight black dots, P1 to P8, are used to depict one of the cutting paths 4. P1 to P8 are candidate positions for placing inspection components. Among them, P1 to P4, P7, and P8 are within the high-voltage region 2. Therefore, the corresponding regions of the chip sections 1 adjacent to these candidate positions are all in the high-voltage region 2. P5 and P6 are within the low-voltage region 3. Therefore, the corresponding regions of the chip sections 1 adjacent to these candidate positions are all in the low-voltage region 3.

[0052] exist Figure 2 In this process, only one black dot is marked on the cutting track 4, but inspection elements can also be arranged on multiple cutting tracks 4. However, it is not necessary to arrange inspection elements on all cutting tracks 4. The cutting track 4 is the position where the chip is cut off during cutting. Therefore, the inspection elements arranged on the cutting track 4 will not remain in the chip section 1 mounted on the final product. The inspection elements are used during product inspection before cutting.

[0053] In this embodiment, there are two types of inspection elements: low-voltage inspection elements and high-voltage inspection elements. The low-voltage inspection elements are tuned to be suitable for inspection in environments where there are many low-voltage devices and few high-voltage devices nearby. The high-voltage inspection elements are tuned to be suitable for inspection in environments where there are many high-voltage devices and few low-voltage devices nearby.

[0054] In the case where the inspection element is a polysilicon resistor, the polysilicon resistor as the low-voltage inspection element has a different resistance value from the polysilicon resistor as the high-voltage inspection element. The polysilicon resistor as the low-voltage inspection element has a higher resistance than the polysilicon resistor as the high-voltage inspection element. This is because the inspection result is affected by the adjacent environment at the time of product inspection. That is, this is because the measured value of the resistance of the polysilicon resistor appears lower in an environment where low-voltage devices are more numerous and appears higher in an environment where high-voltage devices are more numerous.

[0055] By Figure 3 This will be described. In Figure 3 the lower part of FIG. 6 shows the difference in the measured characteristics in the case where the same size of polysilicon resistor is arranged at each of the aforementioned positions P1 to P8. Figure 3 The lower part of FIG. 6 shows the saturation current when a certain voltage is applied to the polysilicon resistor. As is apparent from this, the current value obtained at the positions P5 and P6 in the low-voltage region 3 is approximately the expected current value, but the current value obtained at the other positions is lower than the expected current value. Therefore, as shown in the upper part of FIG. 6, the measured value as the resistance appears lower in the low-voltage region 3 and appears higher in the high-voltage region 2. Figure 3

[0056] In the present embodiment, the kind of inspection element is selected in accordance with the position where it is arranged. That is, the low-voltage inspection element is selected in the case where the candidate position is arranged in a range adjacent to the low-voltage region 3, and the high-voltage inspection element is selected in the case where the candidate position is arranged in a range adjacent to the high-voltage region 2. By this, the error of inspection caused by the environmental dependence of the measured value is reduced.

[0057] This will be described. Figure 4 Figure 4 A graph showing the position dependence of the saturation current shown in the lower part of FIG. 6 is shown in FIG. 7. In Figure 3 the lower part of FIG. 7, the graph in the case where the low-voltage inspection element is arranged at each of the candidate positions and the graph in the case where the high-voltage inspection element is arranged at each of the candidate positions are shown. The graph of "low-voltage" is approximately the same as the graph in the lower part of FIG. 6. The graph of "high-voltage" becomes a form in which the graph of "low-voltage" is moved in parallel to the high-current side as a whole. Figure 4 Figure 3

[0058] ​​​​Therefore, in the present embodiment, in a case where the inspection element is arranged at the candidate position of P5, P6, the low-voltage inspection element is selected. This is because the candidate position of P5, P6 is in a range adjacent to the low-voltage region 3. On the other hand, in a case where the inspection element is arranged at the candidate position of PI, P2, P8, etc. in a range adjacent to the high-voltage region 2, the high-voltage inspection element is selected. Thus, at the time of actual pre-dicing inspection, it is possible to reduce the deviation of the measured value due to the arrangement position of the inspection element. Therefore, it is possible to perform the inspection more accurately without preparing two kinds of inspection determination values for the low-voltage region 3 and the high-voltage region 2, and thus it is also possible to improve the detection efficiency.

[0059] In one embodiment, there is also provided a method of arranging an inspection element in a semiconductor circuit substrate in which a plurality of chip portions of the same specification are arranged in a repeating array and a dicing lane is provided between each chip portion, the chip portion having a low-voltage region in which a low-voltage device is arranged more than a high-voltage device and a high-voltage region in which a high-voltage device is arranged more than a low-voltage device.

[0060] Referring to Figure 6 , the method of arranging an inspection element in a semiconductor circuit substrate includes the steps of:

[0061] S1, obtaining division information of a low-voltage region 3 and a high-voltage region 2 in a chip portion 1;

[0062] S2, determining whether a position on a dicing lane 4 at which the inspection element is to be arranged is in a range adjacent to the low-voltage region 3 or a range adjacent to the high-voltage region 2;

[0063] S3, in a case where the result of the determination is that the position is in the range adjacent to the low-voltage region 3, arranging a low-voltage inspection element at the position;

[0064] S4, in a case where the result of the determination is that the position is in the range adjacent to the high-voltage region 2, arranging a high-voltage inspection element at the position.

[0065] Specifically, in a case where the arrangement of the inspection element is performed automatically using a computer, division information of the low-voltage region 3 and the high-voltage region 2 in the chip portion 1 and type information of the inspection element to be arranged are required.

[0066] The division information of the low-voltage region 3 and the high-voltage region 2 can be included in the information of the specification of the chip portion 1. At this time, the step S1 can include:

[0067] Step S11, obtaining the division information of the low-voltage region and the high-voltage region in the chip portion based on the information of the specification of the chip portion.

[0068] Alternatively, the division information on the low-voltage region 3 and the high-voltage region 2 can also be read from the information of the mask plate of the chip portion 1. In this case, the step S1 can include:

[0069] In step S12, the division information of the low-voltage region and the high-voltage region in the chip portion is acquired based on the information of the mask plate of the chip portion. The mask plate includes a pattern that defines the low-voltage device or the high-voltage device within the chip portion.

[0070] Exemplarily, the mask plate used to form the chip portion 1 can include a mask plate used in a process of removing the oxide film of the portion where the low-voltage device is arranged. Hereinafter, this mask plate is referred to as "mask plate A". The pattern in the mask plate A can define the arrangement position of the low-voltage device. According to the pattern in the mask plate A, the distribution condition of the low-voltage device within the region of the chip portion 1 can be known.

[0071] For the subdivided region that further subdivides the entire region of the chip portion 1, if the distribution density of the low-voltage device therein is high, it can be determined that the subdivided region belongs to the low-voltage region 3. If the distribution density of the low-voltage device is low, it can be determined that the subdivided region belongs to the high-voltage region 2.

[0072] For example, a threshold value (first value) can be set for the distribution density of the low-voltage device, and the region where the distribution density of the low-voltage device is equal to or higher than the first value is divided into the low-voltage region 3. Then, another threshold value (second value) can be set for the distribution density of the low-voltage device, and the region where the distribution density of the low-voltage device is equal to or lower than the second value is divided into the high-voltage region 2. The second value is a value that is the same as or lower than the first value. The specific numerical value of the first value and the second value can be set according to actual needs.

[0073] In the case of using the information of the mask plate A, the subdivided region can be determined according to the pattern occupancy rate of the mask plate A. For example, in the case where the pattern occupancy rate of the mask plate A in the subdivided region is 100%, the approximately entire region of the subdivided region is occupied by the low-voltage device. It can be determined that such a subdivided region belongs to the low-voltage region 3. In fact, even if it is not 100%, a reference value of about 80% can be set in advance, and it can be determined that the subdivided region with a pattern occupancy rate equal to or higher than the reference value belongs to the low-voltage region 3. The subdivided region with a pattern occupancy rate lower than the reference value can be determined to belong to the high-voltage region 2.

[0074] Generally, in the development stage of the chip portion 1, the data for simulators such as SPICE is extracted from the mask plate information. The information of the check element selected as above is also included in the SPICE data. Thus, in the actually manufactured semiconductor circuit substrate 10, the appropriate check element is included at the appropriate position. The information of the check element (TEG) is also included in the so-called "IP core" of the chip portion 1. This is schematically shown in Figure 5 .

[0075] The semiconductor circuit substrate 10 manufactured based on the configuration method of the inspection element in the present embodiment is such that, at a stage before dicing, a plurality of chip portions 1 of the same specification are arranged in a repeating pattern and the dicing lanes 4 are provided between the respective chip portions 1. In this semiconductor circuit substrate, the chip portions 1 have a low voltage region 3 and a high voltage region 2, a low voltage inspection element is arranged in a range of the dicing lane 4 adjacent to the low voltage region 3, a high voltage inspection element is arranged in a range of the dicing lane 4 adjacent to the high voltage region 2, the number of low voltage devices arranged in the low voltage region 3 is greater than the number of high voltage devices, and the number of high voltage devices arranged in the high voltage region 2 is greater than the number of low voltage devices.

[0076] As explained in detail above, according to the present embodiment, when the inspection element is arranged on the dicing lane 4 of the semiconductor circuit substrate 10, it is considered whether the region within the chip portion 1 adjacent to the arranged position is the low voltage region 3 or the high voltage region 2. Then, in the case of the low voltage region 3, a low voltage inspection element is arranged at the position, and in the case of the high voltage region 2, a high voltage inspection element is arranged at the position. Thereby, it is achieved to reduce the deviation of the measured value due to the arrangement position of the inspection element, and thus to improve the detection accuracy of the inspection element. Therefore, it is possible to perform the inspection more accurately without preparing two kinds of inspection determination values for the low voltage region 3 and the high voltage region 2, and thus it is also possible to improve the detection efficiency.

[0077] Further, the above-described embodiment is merely an example and does not limit the present application in any way. Therefore, the present application can of course be modified and deformed in various ways within the scope of the gist thereof. For example, the specific circuit element of the inspection element is not limited to the polysilicon resistor described above. It can be another kind of circuit element such as a capacitor. It is also possible to aggregate a plurality of kinds of circuit elements.

[0078] The voltage regions in the chip portion 1 are not limited to the two of the high voltage region 2 and the low voltage region 3, but can be three or more. In the case where the high voltage region and the low voltage region are determined based on the mask plate information, the mask plate used is not limited to the mask plate A described above, but can be a mask plate that specifies the arrangement position of the high voltage device.

[0079] The plate surface shape of the chip portion 1 is not limited to the high aspect ratio shape as described above. The distribution of the respective regions inside the chip portion 1 is not limited to the case where the same region is distributed to both ends as described above. The classification of the arrangement position on the dicing lane 4 can not be simply the two of adjacent to the high voltage region 2 or adjacent to the low voltage region 3 as described above. It is also possible to add an intermediate state such as the vicinity of the boundary of the region. Further, in the case where there is a portion where one of the chip portions 1 adjacent to both sides is the high voltage region 2 and the other is the low voltage region 3, it is also possible to add this to the classification. That is, the kinds of the inspection elements can be more than two.

[0080] Based on the same inventive concept, the embodiment of the present application also provides a device for implementing the configuration method of the inspection element in the semiconductor circuit substrate. The device provides a solution to the implementation scheme as described in the above method, and therefore the specific limitations in one or more device embodiments of the configuration of the inspection element in the semiconductor circuit substrate can refer to the limitations of the configuration method of the inspection element in the semiconductor circuit substrate described above, which will not be repeated here.

[0081] In one embodiment, as shown in Figure 7 A device for configuring an inspection element in a semiconductor circuit substrate is provided, in which a plurality of chip portions of the same specification are arranged in a repeated arrangement and a dicing lane is provided between each chip portion, the chip portion has a low-voltage region and a high-voltage region, the low-voltage region has more low-voltage devices than high-voltage devices, and the high-voltage region has more high-voltage devices than low-voltage devices.

[0082] The device comprises a region division obtaining module 100, a determination module 200 and a configuration module 300, wherein:

[0083] The region division obtaining module 100 is configured to obtain division information of the low-voltage region and the high-voltage region in the chip portion.

[0084] The determination module 200 is configured to determine whether the position on the dicing lane where the inspection element is to be configured is in a range adjacent to the low-voltage region or in a range adjacent to the high-voltage region.

[0085] The configuration module 300 is configured to, when the result of the determination is that the position is in the range adjacent to the low-voltage region, configure a low-voltage inspection element at the position; and when the result of the determination is that the position is in the range adjacent to the high-voltage region, configure a high-voltage inspection element at the position.

[0086] In one embodiment, the region division obtaining module 100 is configured to obtain the division information of the low-voltage region and the high-voltage region in the chip portion based on information of the specification of the chip portion.

[0087] In one embodiment, the region division obtaining module 100 is configured to obtain the division information of the low-voltage region and the high-voltage region in the chip portion based on information of a mask plate of the chip portion, the mask plate comprising a pattern defining low-voltage devices or high-voltage devices within the chip portion.

[0088] In one embodiment, a region in which the distribution density of low-voltage devices is greater than or equal to a first value is divided into a low-voltage region,

[0089] a region in which the distribution density of low-voltage devices is less than or equal to a second value is divided into a high-voltage region, the second value being the same as or lower than the first value.

[0090] Each module in the configuration device of the inspection element in the semiconductor circuit substrate described above can be realized by software, hardware, and a combination thereof, in whole or in part. The modules described above can be embedded in a processor in a computer device in hardware form or independent of the processor, or stored in a memory in the computer device in software form, so that the processor invokes and executes the operations corresponding to each module.

[0091] In one exemplary embodiment, a computer device is provided, comprising a memory and a processor, the memory storing a computer program, and the processor implementing the following steps when executing the computer program:

[0092] S1, obtaining division information of a low-voltage region and a high-voltage region in a chip part;

[0093] S2, determining whether a position on a cutting lane where an inspection element is to be configured is in a range adjacent to the low-voltage region or in a range adjacent to the high-voltage region;

[0094] S3, in a case where the result of the determination is that the position is in the range adjacent to the low-voltage region, configuring a low-voltage inspection element at the position;

[0095] S4, in a case where the result of the determination is that the position is in the range adjacent to the high-voltage region, configuring a high-voltage inspection element at the position.

[0096] In one embodiment, the processor further implements the following step when executing the computer program: obtaining the division information of the low-voltage region and the high-voltage region in the chip part based on information of a specification of the chip part.

[0097] In one embodiment, the processor further implements the following step when executing the computer program: obtaining the division information of the low-voltage region and the high-voltage region in the chip part based on information of a mask plate of the chip part, the mask plate comprising a pattern for specifying low-voltage devices or high-voltage devices in the chip part.

[0098] In one embodiment, a region in which a distribution density of the low-voltage devices is a first value or more is divided into the low-voltage region,

[0099] a region in which the distribution density of the low-voltage devices is a second value or less is divided into the high-voltage region, the second value being a value that is the same as or lower than the first value.

[0100] In one embodiment, a computer-readable storage medium is provided, storing a computer program, the computer program being executed by a processor to implement the following steps:

[0101] S1, obtaining division information of a low-voltage region and a high-voltage region in a chip part;

[0102] S2. Determine whether the location of the cutting track where the inspection element is to be installed is within the range adjacent to the low-pressure area or within the range adjacent to the high-pressure area.

[0103] S3. If the above determination result is within the range adjacent to the low-pressure area, a low-pressure inspection element shall be installed at that location.

[0104] S4. If the above determination result is within the range adjacent to the high-voltage area, a high-voltage inspection element shall be installed at that location.

[0105] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: based on the chip's specification information, it obtains the division information of the low-voltage region and the high-voltage region in the chip.

[0106] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: based on the information of the mask template of the chip section, it obtains the division information of the low-voltage region and the high-voltage region in the chip section, wherein the mask template includes a pattern defined for the low-voltage device or the high-voltage device in the chip section.

[0107] In one embodiment, the region where the distribution density of low-voltage devices is above a first value is defined as a low-voltage region.

[0108] The region where the distribution density of low-voltage devices is at or below the second value is classified as the high-voltage region. The second value is the same as or lower than the first value.

[0109] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, performs the following steps:

[0110] S1. Obtain the division information of the low-voltage region and the high-voltage region in the chip section;

[0111] S2. Determine whether the location of the cutting track where the inspection element is to be installed is within the range adjacent to the low-pressure area or within the range adjacent to the high-pressure area.

[0112] S3. If the above determination result is within the range adjacent to the low-pressure area, a low-pressure inspection element shall be installed at that location.

[0113] S4. If the above determination result is within the range adjacent to the high-voltage area, a high-voltage inspection element shall be installed at that location.

[0114] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: based on the chip's specification information, it obtains the division information of the low-voltage region and the high-voltage region in the chip.

[0115] In one embodiment, the computer program, when executed by the processor, further implements the following steps: based on information of a mask plate of the chip part, obtaining division information of a low-voltage area and a high-voltage area in the chip part, the mask plate including a pattern for defining a low-voltage device or a high-voltage device in the chip part.

[0116] In one embodiment, the region with a distribution density of the low-voltage device being greater than or equal to a first value is divided into a low-voltage area,

[0117] the region with a distribution density of the low-voltage device being less than or equal to a second value is divided into a high-voltage area, the second value being the same as or lower than the first value.

[0118] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0119] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0120] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A semiconductor circuit board, characterized in that, In this semiconductor circuit substrate, multiple chip sections of the same specification are arranged in a repeating pattern, and cleaving lines are provided between each chip section. in, The chip section has: The configuration includes a lower voltage region with more low-voltage components than high-voltage components; and The high-voltage components are configured to cover a larger high-voltage area than the low-voltage components. A low-pressure inspection element is provided in the cutting channel within the range adjacent to the low-pressure area. Furthermore, a high-pressure inspection element is provided in the cutting channel within the range adjacent to the high-pressure area.

2. The semiconductor circuit board according to claim 1, characterized in that, The chip section is a long strip shape in which the dimension of the long side is more than 10 times the dimension of the short side.

3. A method for arranging inspection elements in a semiconductor circuit board, characterized in that, In this semiconductor circuit substrate, multiple chip sections of the same specification are arranged in a repeating pattern, and dicing lines are provided between each chip section. Each chip section has a low-voltage region and a high-voltage region. The low-voltage region contains more low-voltage devices than high-voltage devices, and the high-voltage region contains more high-voltage devices than low-voltage devices. The method for configuring the inspection element in the semiconductor circuit board includes: Obtain the division information of the low-voltage region and the high-voltage region in the chip section; Determine whether the location of the inspection element on the cutting track is within the range adjacent to the low-pressure area or within the range adjacent to the high-pressure area; If the above determination result indicates that the area is adjacent to the low-pressure region, a low-pressure inspection element shall be installed at that location. If the above determination results in a location adjacent to the high-voltage area, a high-voltage inspection element shall be installed at that location.

4. The method for arranging inspection elements in a semiconductor circuit board according to claim 3, characterized in that, The step of obtaining the division information of the low-voltage region and the high-voltage region in the chip includes: Based on the specifications of the chip section, the division information of the low-voltage region and the high-voltage region in the chip section is obtained.

5. The method for arranging inspection elements in a semiconductor circuit board according to claim 3, characterized in that, The step of obtaining the division information of the low-voltage region and the high-voltage region in the chip includes: Based on the information of the mask template of the chip section, the division information of the low-voltage region and the high-voltage region in the chip section is obtained, and the mask template includes a specified pattern for the low-voltage device or the high-voltage device in the chip section.

6. The method for arranging inspection elements in a semiconductor circuit board according to claim 4 or 5, characterized in that, The region where the distribution density of the low-voltage devices is above a first value is defined as the low-voltage region. The area where the distribution density of the low-voltage device is a second value or lower is defined as the high-voltage area, where the second value is the same as or lower than the first value.

7. A device for arranging inspection elements in a semiconductor circuit board, characterized in that, In this semiconductor circuit substrate, multiple chip sections of the same specification are arranged in a repeating pattern, and dicing lines are provided between each chip section. Each chip section has a low-voltage region and a high-voltage region. The low-voltage region contains more low-voltage devices than high-voltage devices, and the high-voltage region contains more high-voltage devices than low-voltage devices. The device includes: A region division acquisition module is used to acquire the division information of the low-voltage region and the high-voltage region in the chip section; The determination module is used to determine whether the position on the cutting track where the inspection element is to be configured is within the range adjacent to the low-pressure area or within the range adjacent to the high-pressure area. The configuration module is used to configure a low-voltage inspection element at a location when the above determination result is within the range adjacent to the low-voltage area; and to configure a high-voltage inspection element at a location when the above determination result is within the range adjacent to the high-voltage area.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 3 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 3 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 3 to 6.

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