A rail-to-rail operational amplifier

Abstract

The embodiment of the application provides a rail-to-rail operational amplifier, and relates to the technical field of operational amplifiers. The rail-to-rail operational amplifier comprises an N-type current switch module, a P-type current switch module, an N-type differential input stage and a P-type differential input stage. Under the action of the N-type current switch module on an N input pair tube, the transconductance curve gm1 of the N-type differential input stage is translated along the horizontal axis direction. Under the action of the P-type current switch module on a P input pair tube, the transconductance curve gm2 of the P-type differential input stage is translated along the horizontal axis direction. The N-type current switch module and the P-type current switch module can make the rising and falling parts of the transconductance curves gm1 and gm2 tend to be straight lines. Finally, the total transconductance curve fluctuation amplitude of the N-type differential input stage and the P-type differential input stage is smaller, and the transconductance stability under different input voltages is realized.

Description

Technical Field

[0001] This application relates to the field of operational amplifier technology, and more particularly to a rail-to-rail operational amplifier. Background Technology

[0002] With the increasing prevalence of low-voltage power supplies, especially the rise of portable electronic devices (such as mobile phones, laptops, and IoT devices), systems require even lower operating voltages (such as 3.3V, 1.8V, or even lower) to reduce power consumption. Traditional op-amps cannot cover sufficient dynamic range at low voltages, limiting signal processing capabilities. Rail-to-rail designs address this by allowing input / output signals to be close to the power rails.

[0003] Traditional op-amps have limitations. Their input stages often use differential pairs of transistors (such as BJTs or MOSFETs), and their common-mode input range is typically at least 1V lower than the supply voltage (limited by transistor operating conditions). The output stage also cannot reach the supply rail due to saturation voltage drop. This has a smaller impact in high-voltage systems, but significantly compresses the usable signal range at low voltages.

[0004] Regarding the accuracy requirements of analog signal processing, in applications such as sensor interfaces and ADC drivers, the signal amplitude may be close to the power supply voltage. If the op-amp cannot handle the full-swing signal, it will lead to distortion or decreased accuracy. Rail-to-rail op-amps achieve linear amplification across the entire power supply range by improving the input stage (such as complementary differential pairs) and the output stage (such as push-pull structures).

[0005] Regarding energy saving and efficiency requirements, rail-to-rail output stages can provide a larger output swing, reducing unnecessary power losses. For example, when driving loads, a higher output voltage means lower current demand, thereby improving overall energy efficiency.

[0006] However, existing rail-to-rail operational amplifiers suffer from transconductance instability. How to achieve transconductance stability under different input voltages is the technical problem this application aims to solve. Summary of the Invention

[0007] The purpose of this application is to provide a rail-to-rail operational amplifier to achieve transconductance stability under different input voltages.

[0008] The rail-to-rail operational amplifier includes an N-type current switching module, a P-type current switching module, an N-type differential input stage, a P-type differential input stage, an intermediate stage, and an output stage.

[0009] The intermediate stage is connected to the N-type differential input stage, the P-type differential input stage, and the output stage, respectively.

[0010] The N-type differential input stage includes an N-input pair and a first current control transistor; the source of the N-input pair is connected to the first current control transistor; the current of the N-input pair is the current of the first current control transistor.

[0011] The P-type differential input stage includes a P-input pair transistor and a second current control transistor; the source of the P-input pair transistor is connected to the second current control transistor; the current of the P-input pair transistor is the current of the second current control transistor.

[0012] The N-type current switch module is used to provide voltage to the control terminal of the first current control transistor according to the two input voltages of the rail-to-rail operational amplifier, thereby affecting the current of the N-input pair transistors;

[0013] The P-type current switch module is used to provide voltage to the control terminal of the second current control transistor according to the two input voltages of the rail-to-rail operational amplifier, thereby affecting the current of the P input pair transistor;

[0014] Compared to the transconductance of the N-input pair transistors themselves, under the action of the N-type current switching module on the N-input pair transistors, the transconductance curve gm1 of the N-type differential input stage shifts along the horizontal axis; the transconductance curve is a curve showing the change of transconductance with the input voltage.

[0015] Compared to the transconductance of the P-input pair transistors themselves, under the action of the P-type current switching module on the P-input pair transistors, the transconductance curve gm2 of the P-type differential input stage is shifted along the horizontal axis.

[0016] The N-type current switch module and the P-type current switch module have the function of making the rising and falling portions of the transconductance curve gm1 and the transconductance curve gm2 tend to be straight lines.

[0017] After adjusting the transconductance curves gm1 and gm2, the total transconductance curves of the N-type differential input stage and the P-type differential input stage exhibit smaller fluctuations compared to before adjustment.

[0018] Optionally, the P-type current switch module includes a first transistor, a first current source, a second transistor, a second current source, a third transistor, a fourth transistor, a first current tube, a third current source, a second current tube, a fourth current source, a third current tube, a fifth current source, and a fourth current tube;

[0019] The first current source and the second current source have the same current; the third current source and the fourth current source have the same current.

[0020] The gate of the first transistor is used to receive the first input voltage of the rail-to-rail operational amplifier;

[0021] The gate of the second transistor is used to receive the second input voltage of the rail-to-rail operational amplifier;

[0022] The first transistor is connected in series with the first current source, and the first current source causes a voltage to be generated at the source of the first transistor. The source of the first transistor is connected to the gate of the third transistor.

[0023] The second transistor is connected in series with the second current source, and the second current source causes a voltage to be generated at the source of the second transistor. The source of the second transistor is connected to the gate of the fourth transistor.

[0024] The source of the third transistor and the source of the fourth transistor are connected and connected to the first current transistor; the drain of the third transistor and the drain of the fourth transistor are connected and connected to the third current source; the second current transistor and the fourth current source are connected, and the connection point of the second current transistor and the fourth current source is connected to the connection point of the third current source and the drain of the third transistor and the drain of the fourth transistor.

[0025] The sum of the currents of the third current source and the second current tube is equal to the sum of the currents of the first current tube and the fourth current source.

[0026] The third current transistor is used to replicate the current of the second current transistor proportionally; the current ratio of the fifth current source to the fourth current source is the current ratio of the third current transistor to the second current transistor.

[0027] The third current transistor and the fourth current transistor are connected to the fifth current source; the current of the fifth current source is equal to the sum of the currents of the third current transistor and the fourth current transistor.

[0028] The fourth current transistor and the second current control transistor form a current mirror.

[0029] Optionally, the current ratio of the fifth current source to the fourth current source is 2.

[0030] Optionally, the first transistor, the second transistor, the third transistor, and the fourth transistor are NMOS transistors;

[0031] The third current source, the second current transistor, the third current transistor, the fourth current transistor, the first current source, the second current source, the first current transistor, the fourth current source, and the fifth current source are PMOS transistors.

[0032] Optionally, the first transistor, the second transistor, the third transistor, and the fourth transistor are PMOS transistors;

[0033] The third current source, the second current transistor, the third current transistor, the fourth current transistor, the first current source, the second current source, the first current transistor, the fourth current source, and the fifth current source are NMOS transistors.

[0034] Optionally, the N-type current switch module includes a fifth transistor, a sixth current source, a sixth transistor, a seventh current source, a seventh transistor, an eighth transistor, a fifth current tube, an eighth current source, a sixth current tube, a ninth current source, a seventh current tube, and an eighth current tube.

[0035] The sixth current source and the seventh current source have the same current; the eighth current source and the ninth current source have the same current.

[0036] The gate of the fifth transistor is used to receive the first input voltage of the rail-to-rail operational amplifier;

[0037] The gate of the sixth transistor is used to receive the second input voltage of the rail-to-rail operational amplifier;

[0038] The fifth transistor is connected in series with the sixth current source, and the sixth current source generates a voltage at the source of the fifth transistor. The source of the fifth transistor is connected to the gate of the seventh transistor.

[0039] The sixth transistor is connected in series with the seventh current source, and the seventh current source generates a voltage at the source of the sixth transistor. The source of the sixth transistor is connected to the gate of the eighth transistor.

[0040] The source of the seventh transistor is connected to the source of the eighth transistor and is also connected to the fifth current transistor; the drain of the seventh transistor is connected to the drain of the eighth transistor and is also connected to the eighth current source; the sixth current transistor is connected to the ninth current source, and the connection point of the sixth current transistor and the ninth current source is connected to the connection point of the eighth current source and the drain of the seventh transistor and the drain of the eighth transistor.

[0041] The sum of the currents of the eighth current source and the sixth current tube is equal to the sum of the currents of the fifth current tube and the ninth current source.

[0042] The seventh current transistor is used to replicate the current of the sixth current transistor proportionally;

[0043] The eighth current transistor and the first current control transistor form a current mirror.

[0044] Optionally, the current ratio of the seventh current transistor to the sixth current transistor is 2.

[0045] Optionally, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are NMOS transistors;

[0046] The eighth current source, the sixth current transistor, the seventh current transistor, the eighth current transistor, the sixth current source, the seventh current source, the fifth current transistor, and the ninth current source are PMOS transistors.

[0047] Optionally, the first current control transistor includes two MOSFETs, and the two MOSFETs form a common source and common gate structure.

[0048] Optionally, the second current control transistor includes two MOSFETs, and the two MOSFETs form a common source and common gate structure.

[0049] Compared with the prior art, this application has the following advantages:

[0050] By using level shifting and current mirror structures, the slope of the transconductance curves of NMOS differential pairs and PMOS differential pairs is adjusted to the intersection point of the transconductance curves, thereby achieving a stable transconductance effect. At the same time, a gain compensation circuit with a special structure can be added to the intermediate stage to enable the intermediate stage to be stably biased, thereby realizing a high-gain, high-stable transconductance op-amp design and improving the stability of op-amp operation. Attached Figure Description

[0051] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 A schematic diagram of a rail-to-rail operational amplifier provided in an embodiment of this application;

[0053] Figure 2 A schematic diagram of an N-type differential input stage including an N-input pair and a first current control transistor, and a P-type differential input stage including a P-input pair and a second current control transistor, provided for embodiments of this application;

[0054] Figure 3 A schematic diagram of an input-stage transconductance curve provided in an embodiment of this application;

[0055] Figure 4 A schematic diagram of a P-type current switch module provided in an embodiment of this application;

[0056] Figure 5 A schematic diagram of an N-type current switch module provided in an embodiment of this application;

[0057] Figure 6 A schematic diagram showing how a current I2 generates a voltage VL21 at the source of a first transistor M1, as provided in an embodiment of this application.

[0058] Figure 7 This application provides a schematic diagram illustrating the effect of changing the rate of change of current with respect to input voltage in an embodiment of the present application.

[0059] Figure 8 A schematic diagram of an N-type differential input stage, a P-type differential input stage, an intermediate stage, and an output stage provided for embodiments of this application;

[0060] Figure 9 This is a schematic diagram of a gain compensation structure provided in an embodiment of this application. Detailed Implementation

[0061] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. The described embodiments are only some embodiments of this application, not all embodiments. The components of the embodiments of this application described in the accompanying drawings can generally be arranged and designed in various different configurations.

[0062] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0063] In the description of this application, it should be noted that:

[0064] Relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations;

[0065] "Connection" should be interpreted broadly. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0066] like Figure 1This application provides a rail-to-rail operational amplifier, which includes an N-type current switching module, a P-type current switching module, an N-type differential input stage, a P-type differential input stage, an intermediate stage, and an output stage. The N-type differential input stage includes an N-type input pair and a first current control transistor; the P-type differential input stage includes a P-type input pair and a second current control transistor.

[0067] The following connections exist:

[0068] like Figure 1 The intermediate stage is connected to the N-type differential input stage, the P-type differential input stage, and the output stage, respectively.

[0069] like Figure 2 The source of the N-input pair is connected to the first current control transistor, and the current of the N-input pair is the current of the first current control transistor; the N-type current switch module is connected to the control terminal of the first current control transistor.

[0070] The source of the P-input pair is connected to the second current control transistor, and the current of the P-input pair is the current of the second current control transistor; the P-type current switch module is connected to the control terminal of the second current control transistor.

[0071] The N-type and P-type current switch modules have the following functions:

[0072] The N-type current switch module is used to provide voltage to the control terminal of the first current control transistor based on the two input voltages of the rail-to-rail operational amplifier, thereby affecting the current of the N-input pair transistors, that is, affecting the transconductance and transconductance curve of the N-input pair transistors (the transconductance curve is the curve of transconductance changing with input voltage).

[0073] The P-type current switch module is used to provide voltage to the control terminal of the second current control transistor based on the two input voltages of the rail-to-rail operational amplifier, thereby affecting the current of the P input pair transistors, that is, affecting the transconductance and transconductance curve of the P input pair transistors.

[0074] like Figure 3 Let gm1 be the transconductance of the N-input pair and gm2 be the transconductance of the P-input pair. The sum of gm1 and gm2 is the total transconductance. However, because the center points of the transconductance curves are offset by a certain distance, the total transconductance curve gm1+gm2 exhibits significant fluctuations. This fluctuation can be reduced by shifting the curve. Therefore, the effect of the above on the transconductance curve can be set as a shifting mechanism.

[0075] Compared to the transconductance of the N-input pair transistors themselves, the transconductance curve of the N-type differential input stage shifts along the horizontal axis due to the effect of the N-type current switching module on the N-input pair transistors.

[0076] Compared to the transconductance of the P-type input pair transistors themselves, the transconductance curve of the P-type differential input stage shifts along the horizontal axis due to the effect of the P-type current switching module on the P-type input pair transistors.

[0077] After the transconductance curves of the N-type differential input stage and the P-type differential input stage are shifted, the total transconductance curves of the N-type differential input stage and the P-type differential input stage exhibit smaller fluctuations compared to before the shift.

[0078] Figure 4 This illustration demonstrates one implementation of a P-type current switching module. The P-type current switching module may include a first transistor M1, a first current source 101, a second transistor M2, a second current source 102, a third transistor M3, a fourth transistor M4, a first current source 201, a third current source 103, a second current source 202, a fourth current source 104, a third current source 203, a fifth current source 105, and a fourth current source 204. The following connections are established:

[0079] The gate of the first transistor M1 is used to receive the first input voltage VIN1 of the rail-to-rail operational amplifier;

[0080] The gate of the second transistor M2 is used to receive the second input voltage VIN2 of the rail-to-rail operational amplifier;

[0081] The first transistor M1 is connected in series with the first current source 101. The first current source 101 causes the source of the first transistor M1 to generate a voltage VL21. The source of the first transistor M1 is connected to the gate of the third transistor M3.

[0082] The second transistor M2 is connected in series with the second current source 102. The second current source 102 causes the source of the second transistor M2 to generate a voltage VL22. The source of the second transistor M2 is connected to the gate of the fourth transistor M4.

[0083] The source of the third transistor M3 and the source of the fourth transistor M4 are connected, and are also connected to the first current source 201; the drain of the third transistor M3 and the drain of the fourth transistor M4 are connected, and are also connected to the third current source 103; the second current source 202 and the fourth current source 104 are connected, and the connection point of the second current source 202 and the fourth current source 104 is connected to the connection point of the third current source 103 and the drain of the third transistor M3 and the drain of the fourth transistor M4. Therefore, the sum of the currents of the third current source 103 and the second current source 202 is equal to the sum of the currents of the first current source 201 and the fourth current source 104.

[0084] The third current transistor 203 is used to proportionally replicate the current of the second current transistor 202; the current ratio of the fifth current source 105 to the fourth current source 104 is the current ratio of the third current transistor 203 to the second current transistor 202.

[0085] The third current transistor 203 and the fourth current transistor 204 are connected together to the fifth current source 105; the current of the fifth current source 105 is equal to the sum of the currents of the third current transistor 203 and the fourth current transistor 204.

[0086] The fourth current transistor 204 and the second current control transistor form a current mirror, and the current of the fourth current transistor 204 and the second current control transistor can be ISSP.

[0087] The principle of ISSP control of the P-input pair transistors' on / off state is analyzed using the following example:

[0088] The current ratio of the fifth current source 105 to the fourth current source 104 and the current ratio of the third current tube 203 to the second current tube 202 are both 2. The currents of the first current source 101 and the second current source 102 are the same, both I2; the currents of the third current source 103 and the fourth current source 104 are the same, both I0.

[0089] Under the above settings, at a lower input voltage, the N-input pair is in the off state, and the third transistor M3 and the fourth transistor M4 are also in the off state. The current of the third current source 103 all flows through the fourth current source 104. Therefore, the current of the second current source 202 is 0, the current of the third current source 203 is 0, and the current of the fourth current source 204 is the current of the fifth current source 105, which is twice I0. Therefore, ISSP = 2I0, and the second current control transistor and the P-input pair are turned on.

[0090] Conversely, at higher input voltages, the P-input pair transistors are cut off.

[0091] Similar to Figure 4 The structure, Figure 5 This illustration demonstrates one implementation of an N-type current switching module, which may include a fifth transistor M5, a sixth current source 106, a sixth transistor M6, a seventh current source 107, a seventh transistor M7, an eighth transistor M8, a fifth current transistor 205, an eighth current source 108, a sixth current transistor 206, a ninth current source 109, a seventh current transistor 207, and an eighth current transistor 208. The following connections are established:

[0092] The gate of the fifth transistor M5 is used to receive the first input voltage VIN1 of the rail-to-rail operational amplifier;

[0093] The gate of the sixth transistor M6 is used to receive the second input voltage VIN2 of the rail-to-rail operational amplifier;

[0094] The fifth transistor M5 is connected in series with the sixth current source 106. The sixth current source 106 generates a voltage VL11 at the source of the fifth transistor M5. The source of the fifth transistor M5 is connected to the gate of the seventh transistor M7.

[0095] The sixth transistor M6 is connected in series with the seventh current source 107. The seventh current source 107 generates a voltage VL12 at the source of the sixth transistor M6. The source of the sixth transistor M6 is connected to the gate of the eighth transistor M8.

[0096] The source of the seventh transistor M7 and the source of the eighth transistor M8 are connected, and are also connected to the fifth current source 205; the drain of the seventh transistor M7 and the drain of the eighth transistor M8 are connected, and are also connected to the eighth current source 108; the sixth current source 206 and the ninth current source 109 are connected, and the connection point of the sixth current source 206 and the ninth current source 109 is connected to the connection point of the eighth current source 108 and the drain of the seventh transistor M7 and the drain of the eighth transistor M8. Therefore, the sum of the currents of the eighth current source 108 and the sixth current source 206 is equal to the sum of the currents of the fifth current source 205 and the ninth current source 109.

[0097] The seventh current transistor 207 is used to replicate the current of the sixth current transistor 206 proportionally;

[0098] The eighth current transistor 208 and the first current control transistor form a current mirror. The currents of the eighth current transistor 208 and the first current control transistor can be ISSN.

[0099] The ISSN current controls the on / off state of the N-input pair transistors. The principle is analyzed using the following example:

[0100] The sixth current source 106 and the seventh current source 107 are designed to have the same current, which is I1; the fifth current source 205 and the ninth current source 109 have the same current, which can be the same as the current of the third current source 103 and the fourth current source 104, which is I0.

[0101] Under the above settings, at a lower input voltage, the seventh transistor M7 and the eighth transistor M8 are in the off state, and the current of the eighth current source 108 all passes through the ninth current source 109. Therefore, the current of the sixth current transistor 206 is 0, and the currents of the seventh current transistor 207 and the eighth current transistor 208 are 0. Thus, ISSN=0, and the first current control transistor and the N-input pair transistor are off.

[0102] Conversely, at higher input voltages, the N-input pair transistors are turned on.

[0103] The above explains the principles of current ISSP and current ISSN. Regarding the principle of transconductance curve displacement, the principle is as follows:

[0104] by Figure 4 For example, Figure 4 The first current source 101, and other current sources close to the VSS terminal, can be a PMOS transistor controlled by an external bias circuit, such as... Figure 6The current I2 will generate a voltage VL21 at the source of the first transistor M1, and the voltage VL21 increases as the current I2 increases. Similarly, Figure 5 The medium current I1 will generate a voltage VL11 at the source of the fifth transistor M5. The following relationship can be obtained, where VgsM1 represents the gate-source voltage of the first transistor M1, and VgsM5 represents the gate-source voltage of the fifth transistor M5:

[0105] VL21=VIN1-VgsM1

[0106] VL11=VIN1-VgsM5

[0107] Calculate △Vgs =VL21-VL11=VgsM5-VgsM1

[0108] According to the formula for calculating Vgs:

[0109] .

[0110] Therefore, by adjusting the currents I1 and I2 of the current source, and the width-to-length ratio of the first transistor M1 and the fifth transistor M5, an adjustable offset ΔVgs can be obtained. This offset can shift the intersection point of the transconductance curves, thereby achieving the function of stable transconductance. Figure 3 The effect shown.

[0111] Furthermore, by adjusting the aspect ratio of the third transistor M3, the fourth transistor M4, the seventh transistor M7, and the eighth transistor M8, the rate of change of current with input voltage can be altered. By replicating I0 into the input stage using an additional current mirror, the slope of the transconductance curve can be adjusted. The current switch conduction speed can be expressed as:

[0112]

[0113] or

[0114]

[0115] The effect of changing the rate of change of current with respect to input voltage is as follows: Figure 7 This method can make the rising and falling slopes of the transconductance curves gm1 and gm2 the same, ultimately resulting in a flatter transconductance curve and reducing the average rate of change of transconductance to below 2%, thus achieving good transconductance stabilization. Compared to other methods that require a large number of current mirrors to construct the current summing circuit, this scheme requires very few current mirrors.

[0116] Regarding N-type differential input stage, P-type differential input stage, intermediate stage, and output stage Figure 8An implementation is shown in which MOSFETs M17-M20 form an N-type differential input stage, MOSFETs M9-M12 form a P-type differential input stage, MOSFETs M13-M16 and M21-M24 form an intermediate stage, and the rest form an output stage.

[0117] In the input stage, MOSFETs M19 and M20 form a common-source cascode structure, and MOSFETs M11 and M12 form a common-source cascode structure. The common-source cascode structure has a higher input resistance, which can increase the accuracy of the copy current.

[0118] Figure 8 The required bias voltages VGB1~VGB4 can be obtained from Figure 9 The gain compensation structure shown provides, Figure 9 The bias voltages VB1~VB4 in the circuit can be provided by an external bias circuit, which ultimately controls the gates of MOSFETs M24, M23, M16, and M15, providing a stable bias voltage while increasing the gain of the intermediate stage, and finally achieving high gain compensation for the op-amp.

[0119] Due to the use of a specially biased common-gate structure, the bias voltage of the intermediate stage circuit is constant, providing high gain compensation. By controlling the width and length of the source follower NMOS transistor and its current magnitude, a deterministic bias voltage output can be provided. This bias voltage output carries high gain, thus solving the problem that the gain compensation circuit structure cannot provide a deterministic bias voltage under low voltage.

[0120] For the output stage circuit: Figure 6 The MOSFETs M25-M38, along with capacitors C1 and C2 and resistor R1, form the output stage structure with a transconductance loop. The current of the NMOS transistor M38 in the CLASS AB structure can be determined by the linear relationship provided by the transconductance loop. Similarly, for the PMOS transistor M37, its current can be determined linearly by the MOSFET M33. The CLASS AB structure output stage circuit provides a full-swing output voltage.

[0121] In summary, this application provides a low-voltage rail-to-rail operational amplifier. By using level shifting and a current mirror structure, the slope of the transconductance curves of the NMOS differential pair and the PMOS differential pair is adjusted to the intersection point of the transconductance curves, thereby achieving a stable transconductance effect. At the same time, a gain compensation circuit with a special structure can be added to the intermediate stage to ensure that the intermediate stage can be stably biased, thereby realizing a high-gain, high-stable transconductance op-amp design and improving the stability of op-amp operation.

[0122] The apparatus and system embodiments described above are merely illustrative. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement these embodiments without any creative effort.

[0123] The above are merely preferred embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A rail-to-rail operational amplifier, characterized in that, It includes N-type current switching modules, P-type current switching modules, N-type differential input stages, P-type differential input stages, intermediate stages, and output stages; The intermediate stage is connected to the N-type differential input stage, the P-type differential input stage, and the output stage, respectively. The N-type differential input stage includes an N-input pair and a first current control transistor; the source of the N-input pair is connected to the first current control transistor. The current of the N-input pair transistors is the current of the first current control transistor; The P-type differential input stage includes a P-input pair transistor and a second current control transistor; The source of the P-input pair is connected to the second current control transistor; the current of the P-input pair is the current of the second current control transistor. The N-type current switch module is used to provide voltage to the control terminal of the first current control transistor according to the two input voltages of the rail-to-rail operational amplifier, thereby affecting the current of the N-input pair transistors; The P-type current switch module is used to provide voltage to the control terminal of the second current control transistor according to the two input voltages of the rail-to-rail operational amplifier, thereby affecting the current of the P input pair transistor; Compared to the transconductance of the N-input pair transistors themselves, under the action of the N-type current switching module on the N-input pair transistors, the transconductance curve gm1 of the N-type differential input stage shifts along the horizontal axis; the transconductance curve is a curve showing the change of transconductance with the input voltage. Compared to the transconductance of the P-input pair transistors themselves, under the action of the P-type current switching module on the P-input pair transistors, the transconductance curve gm2 of the P-type differential input stage is shifted along the horizontal axis. The N-type current switch module and the P-type current switch module have the function of making the rising and falling portions of the transconductance curve gm1 and the transconductance curve gm2 tend to be straight lines. After adjusting the transconductance curves gm1 and gm2, the total transconductance curves of the N-type differential input stage and the P-type differential input stage exhibit smaller fluctuations compared to before adjustment.

2. The rail-to-rail operational amplifier as described in claim 1, characterized in that, The P-type current switch module includes a first transistor, a first current source, a second transistor, a second current source, a third transistor, a fourth transistor, a first current tube, a third current source, a second current tube, a fourth current source, a third current tube, a fifth current source, and a fourth current tube. The first current source and the second current source have the same current; the third current source and the fourth current source have the same current. The gate of the first transistor is used to receive the first input voltage of the rail-to-rail operational amplifier; The gate of the second transistor is used to receive the second input voltage of the rail-to-rail operational amplifier; The first transistor is connected in series with the first current source, and the first current source causes a voltage to be generated at the source of the first transistor. The source of the first transistor is connected to the gate of the third transistor. The second transistor is connected in series with the second current source, and the second current source causes a voltage to be generated at the source of the second transistor. The source of the second transistor is connected to the gate of the fourth transistor. The source of the third transistor and the source of the fourth transistor are connected, and are also connected to the first current transistor; The drain of the third transistor is connected to the drain of the fourth transistor, and is also connected to the third current source; the second current transistor is connected to the fourth current source, and the connection point of the second current transistor and the fourth current source is connected to the connection point of the third current source and the drain of the third transistor and the drain of the fourth transistor. The sum of the currents of the third current source and the second current tube is equal to the sum of the currents of the first current tube and the fourth current source. The third current transistor is used to replicate the current of the second current transistor proportionally; the current ratio of the fifth current source to the fourth current source is the current ratio of the third current transistor to the second current transistor. The third current transistor and the fourth current transistor are connected to the fifth current source; the current of the fifth current source is equal to the sum of the currents of the third current transistor and the fourth current transistor. The fourth current transistor and the second current control transistor form a current mirror.

3. The rail-to-rail operational amplifier as described in claim 2, characterized in that, The current ratio of the fifth current source to the fourth current source is 2.

4. The rail-to-rail operational amplifier as described in claim 2, characterized in that, The first transistor, the second transistor, the third transistor, and the fourth transistor are NMOS transistors; The third current source, the second current transistor, the third current transistor, the fourth current transistor, the first current source, the second current source, the first current transistor, the fourth current source, and the fifth current source are PMOS transistors.

5. The rail-to-rail operational amplifier as described in claim 2, characterized in that, The first transistor, the second transistor, the third transistor, and the fourth transistor are PMOS transistors; The third current source, the second current transistor, the third current transistor, the fourth current transistor, the first current source, the second current source, the first current transistor, the fourth current source, and the fifth current source are NMOS transistors.

6. The rail-to-rail operational amplifier as described in claim 1, characterized in that, The N-type current switch module includes a fifth transistor, a sixth current source, a sixth transistor, a seventh current source, a seventh transistor, an eighth transistor, a fifth current tube, an eighth current source, a sixth current tube, a ninth current source, a seventh current tube, and an eighth current tube. The sixth current source and the seventh current source have the same current; the eighth current source and the ninth current source have the same current. The gate of the fifth transistor is used to receive the first input voltage of the rail-to-rail operational amplifier; The gate of the sixth transistor is used to receive the second input voltage of the rail-to-rail operational amplifier; The fifth transistor is connected in series with the sixth current source, and the sixth current source generates a voltage at the source of the fifth transistor. The source of the fifth transistor is connected to the gate of the seventh transistor. The sixth transistor is connected in series with the seventh current source, and the seventh current source generates a voltage at the source of the sixth transistor. The source of the sixth transistor is connected to the gate of the eighth transistor. The source of the seventh transistor is connected to the source of the eighth transistor and is also connected to the fifth current transistor; the drain of the seventh transistor is connected to the drain of the eighth transistor and is also connected to the eighth current source; the sixth current transistor is connected to the ninth current source, and the connection point of the sixth current transistor and the ninth current source is connected to the connection point of the eighth current source and the drain of the seventh transistor and the drain of the eighth transistor. The sum of the currents of the eighth current source and the sixth current tube is equal to the sum of the currents of the fifth current tube and the ninth current source. The seventh current transistor is used to replicate the current of the sixth current transistor proportionally; The eighth current transistor and the first current control transistor form a current mirror.

7. The rail-to-rail operational amplifier as described in claim 6, characterized in that, The current ratio of the seventh current transistor to the sixth current transistor is 2.

8. The rail-to-rail operational amplifier as described in claim 6, characterized in that, The fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are NMOS transistors; The eighth current source, the sixth current transistor, the seventh current transistor, the eighth current transistor, the sixth current source, the seventh current source, the fifth current transistor, and the ninth current source are PMOS transistors.

9. The rail-to-rail operational amplifier as described in claim 1, characterized in that, The first current control transistor includes two MOS transistors, and the two MOS transistors form a common source and common gate structure.

10. The rail-to-rail operational amplifier as described in claim 1, characterized in that, The second current control transistor includes two MOS transistors, and the two MOS transistors form a common source and common gate structure.

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