A starting circuit for a phase-locked loop oscillator which can be automatically turned off

Abstract

This invention discloses a startup circuit for an automatically shut-down phase-locked loop (PLL) oscillator, belonging to the field of integrated circuits. The startup circuit includes a reference current source and a startup current source. The startup current source initiates oscillation of the voltage-controlled oscillator (VCO) in the PLL from its initial state and mirrors the VCO's operating current. After the VCO reaches a preset oscillation frequency, the reference current source is used for comparison, causing the startup circuit to automatically shut down without affecting the normal operating performance of the PLL. The circuit structure proposed in this invention ensures that the VCO starts oscillating from the initial state of the circuit through the startup current source, and automatically shuts down the startup circuit after the PLL begins normal operation using the comparison of the reference current source, without affecting the normal operating performance of the PLL. This eliminates the problem of the PLL becoming deadlocked and unable to start due to power supply noise interference to the AC coupling buffer during the PLL startup process.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a startup circuit for a phase-locked loop oscillator that can be automatically shut down. Background Technology

[0002] A phase-locked loop (PLL) is a circuit structure that uses an externally input reference signal to control the frequency and phase of an internal oscillation signal. By responding to the feedback frequency and phase of the output signal, a dynamically locked output clock signal is obtained.

[0003] A phase-locked loop (PLL) typically consists of several main modules: a divider, a phase-frequency detector (PFD), a charge pump, a loop filter (LF), and a voltage-controlled oscillator (VCO). The VCO generates a clock signal, which is usually passed to an AC-coupled buffer for output. However, during PLL startup, the AC-coupled buffer may be amplified by power supply noise, prematurely generating a high-frequency signal that the PLL's phase-frequency detector cannot properly interpret, thus affecting the PLL's normal startup. Summary of the Invention

[0004] The purpose of this invention is to provide a startup circuit for a phase-locked loop oscillator that can be automatically shut down, in order to solve the problems in the prior art.

[0005] To address the aforementioned technical problems, this invention provides a startup circuit for an automatically shut-down phase-locked loop oscillator. The phase-locked loop includes a divider, a frequency and phase detector-charge pump, a loop filter, a voltage-controlled oscillator, and a low-dropout linear regulator.

[0006] The startup circuit includes a reference current source and a startup current source;

[0007] The starting current source causes the voltage-controlled oscillator in the phase-locked loop to start oscillating from the initial state and mirrors the operating current of the voltage-controlled oscillator.

[0008] After the voltage-controlled oscillator reaches the preset oscillation frequency, the reference current source is used for comparison, which causes the start-up circuit to automatically shut down without affecting the normal operation performance of the phase-locked loop.

[0009] In one embodiment, the startup circuit further includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first inverter, and a second inverter;

[0010] CLK_REF and DIVIDER_OUT are the input reference signal and feedback signal of the frequency and phase detector-charge pump, respectively. The output terminal of the frequency and phase detector-charge pump is connected to the gate terminal of the first PMOS transistor. The source terminal of the first PMOS transistor is connected to the low dropout linear regulator, and the drain terminal is connected to the voltage-controlled oscillator.

[0011] The input terminal of the starting current source is connected to the power supply voltage Vdd, and the output terminal is connected to the source terminal of the third PMOS transistor. The gate terminal of the third PMOS transistor is connected to the VBP node, and the drain terminal is connected to the drain terminal of the first PMOS transistor. The source terminal of the second PMOS transistor is connected to the source terminal of the first PMOS transistor. The gate terminals of the second PMOS transistor and the first PMOS transistor are both connected to the control voltage VCTRL output by the frequency and phase detector-charge pump. The drain terminal of the second PMOS transistor is connected to the VBP node.

[0012] The input terminal of the reference current source is connected to the power supply voltage Vdd, and the output terminal is connected to the drain and gate of the second NMOS transistor. The gate of the second NMOS transistor is connected to the gate of the first NMOS transistor, and the source of the second NMOS transistor is connected to the source of the first NMOS transistor. The drain of the first NMOS transistor is connected to the VBP node.

[0013] The voltage-controlled oscillator outputs the VCO_CLK frequency, which is AC-coupled to the input of the first inverter via a capacitor. The output of the first inverter and the input of the second inverter are connected to node N1. The output of the second inverter and the input of the divider are connected to node N2. The divider outputs a feedback signal DIVIDER_OUT. A resistor is connected between the input and output of the first inverter to determine the AC coupling common-mode voltage.

[0014] In one embodiment, the stable operating current of the voltage-controlled oscillator is reflected by the second PMOS transistor and is greater than the reference current source. The reference current source is 1 / 2n times the stable operating current of the voltage-controlled oscillator, where n is the size ratio of the first PMOS transistor and the second PMOS transistor. The stable operating current of the voltage-controlled oscillator is greater than the startup current provided by the startup current source.

[0015] This invention provides a startup circuit for an automatically shut-down phase-locked loop (PLL) oscillator, effectively solving the problem that the AC coupling buffer used in traditional PLLs may be amplified by power supply noise, prematurely generating a high-frequency signal that prevents the PLL's frequency and phase detector from making proper judgments, thus affecting the normal startup of the PLL. The circuit structure proposed in this invention ensures that the voltage-controlled oscillator starts oscillating from the initial circuit state through a startup current source, and automatically shuts down the startup circuit after the PLL begins normal operation by comparing a reference current source, without affecting the normal operating performance of the PLL. This eliminates the problem of the PLL becoming stuck and unable to start due to power supply noise interference from the AC coupling buffer during startup. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a start-up circuit structure for an automatically shut-down phase-locked loop oscillator provided by the present invention. Detailed Implementation

[0017] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a startup circuit for an automatically shut-down phase-locked loop oscillator based on the present invention. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0018] This invention provides a start-up circuit for an automatic shutdown phase-locked loop oscillator, the block diagram of which is shown below. Figure 1 As shown, CLK_REF and DIVIDER_OUT are the input reference signal and feedback signal detected by the frequency-phase detector, respectively. The output of the frequency-phase detector-charge pump (PFD-CP) is connected to the gate of PMOS transistor MP1. The source of PMOS transistor MP1 is connected to a low-dropout linear regulator (LDO), and its drain is connected to a voltage-controlled oscillator (VCO). VCTRL is the control voltage of the VCO and is determined by the behavior of the frequency-phase detector-charge pump. The loop filter is simply represented by the capacitor connected to point VCTRL. The input of the start-up current source IB2 is connected to the power supply voltage Vdd, and its output is connected to the source of PMOS transistor MP3. The gate of PMOS transistor MP3 is connected to the VBP node, and its drain is connected to the drain of PMOS transistor MP1. The source of PMOS transistor MP2 is connected to the source of PMOS transistor MP1. The gates of both PMOS transistor MP2 and PMOS transistor MP1 are connected to the control voltage VCTRL output by the frequency-phase detector-charge pump. The drain of PMOS transistor MP2 is connected to the VBP node.

[0019] The input of reference current source IB1 is connected to the power supply voltage Vdd, and its output is connected to the drain and gate of NMOS transistor MN2. The gate of NMOS transistor MN2 is connected to the gate of NMOS transistor MN1, and the source of NMOS transistor MN2 is connected to the source of NMOS transistor MN1. The drain of NMOS transistor MN1 is connected to node VBP. The voltage-controlled oscillator output frequency VCO_CLK is connected to the input of inverter INV1 through a capacitor. The output of inverter INV1 and the input of inverter INV2 are connected to node N1. The output of inverter INV2 and the input of divider DIVIDER are connected to node N2. The divider outputs the feedback signal DIVIDER_OUT. A resistor R1 is connected between the input and output of inverter INV1.

[0020] The size of PMOS transistor MP1 is n times the width of PMOS transistor MP2; IB2 is a startup current source sufficient to enable the voltage-controlled oscillator (VCO) to operate at a lower frequency; IB1 is a reference current source used to compare with the actual operating current of the VCO. Assuming the stable operating current of the VCO is IB, then IB1 can be IB / n / 2 and IB2 can be IB / n / 5.

[0021] During the startup process of a phase-locked loop (PLL), conventional AC coupling buffers may be amplified by power supply noise, i.e. Figure 1 As shown, before the voltage-controlled oscillator (VCO) starts, VCO_CLK is not yet oscillating and is in a low-level state. Due to power supply noise, a high-frequency noise signal will be generated in advance at node N1. After being amplified by the inverter INV2, an amplified high-frequency signal will be generated at node N2. This causes the phase detector in the phase-locked loop to mistakenly input the high-frequency signal DIVIDER_OUT, thereby incorrectly judging the feedback clock frequency and causing the phase-locked loop to enter deadlock and fail to start normally.

[0022] The technical solution of this invention employs, for example, the following during the startup process of the phase-locked loop: Figure 1The circuit is shown. Before the voltage-controlled oscillator (VCO) starts up, VCTRL is at a high level. The current through PMOS transistors MP1 and MP2 is approximately zero, while the current through NMOS transistor MN2 is IB1. The mirror relationship between NMOS transistors MN1 and MN2 pulls node VBP down to a low level, thus turning on PMOS transistor MP3. Current source IB2 provides the VCO with a startup current that allows it to operate at a lower frequency, enabling VCO_CLK to start oscillating. This further transmits the VCO_CLK frequency to nodes N1 and N2, masking the premature generation of high-frequency noise signals from power supply noise. Next, the phase-frequency discriminator (PFD) and charge pump (CP) begin to operate normally, gradually pulling VCTRL down to the voltage required for the VCO to operate normally. During the descent of VCTRL, the current flowing through PMOS transistors MP1 and MP2 continuously increases. When the mirror current flowing through PMOS transistor MP2 exceeds the current flowing through NMOS transistor MN1, node VBP will rise to a high level, thereby turning off PMOS transistor MP3. This prevents IB2 from continuing to charge the voltage-controlled oscillator VCO, and the startup circuit is shut down. At this time, the phase-locked loop has started normally, and the startup circuit does not affect the working performance of the phase-locked loop.

[0023] This invention utilizes a simple circuit structure to eliminate the problem of high-frequency interference from power supply noise during the start-up process of a phase-locked loop (PLL), which amplifies and causes the PLL to deadlock and fail to start. This invention utilizes... Figure 1 The circuit structure shown enables the voltage-controlled oscillator (VCO) to start oscillating from the initial state of the circuit through the starting current source IB2. The operating current of the VCO is mirrored, and after the VCO reaches a certain oscillation frequency, it is compared with the reference current source IB1, so that the starting circuit is automatically shut down without affecting the normal operation performance of the phase-locked loop (PLL). At this time, the PLL circuit has entered the normal operating state of dynamic locking, eliminating the problem that the PLL will become deadlocked and unable to start due to interference from power supply noise to the AC coupling buffer during the startup process.

[0024] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A startup circuit for an automatically shut-down phase-locked loop oscillator, the phase-locked loop comprising a divider, a frequency and phase detector-charge pump, a loop filter, a voltage-controlled oscillator, and a low-dropout linear regulator, characterized in that, The startup circuit includes a reference current source and a startup current source; The starting current source causes the voltage-controlled oscillator in the phase-locked loop to start oscillating from the initial state and mirrors the operating current of the voltage-controlled oscillator. After the voltage-controlled oscillator reaches the preset oscillation frequency, the reference current source is used for comparison, which causes the start-up circuit to automatically shut down without affecting the normal working performance of the phase-locked loop. The startup circuit also includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first inverter, and a second inverter; CLK_REF and DIVIDER_OUT are the input reference signal and feedback signal of the frequency and phase detector-charge pump, respectively. The output terminal of the frequency and phase detector-charge pump is connected to the gate terminal of the first PMOS transistor. The source terminal of the first PMOS transistor is connected to the low dropout linear regulator, and the drain terminal is connected to the voltage-controlled oscillator. The input terminal of the starting current source is connected to the power supply voltage Vdd, and the output terminal is connected to the source terminal of the third PMOS transistor. The gate terminal of the third PMOS transistor is connected to the VBP node, and the drain terminal is connected to the drain terminal of the first PMOS transistor. The source terminal of the second PMOS transistor is connected to the source terminal of the first PMOS transistor. The gate terminals of the second PMOS transistor and the first PMOS transistor are both connected to the control voltage VCTRL output by the frequency and phase detector-charge pump. The drain terminal of the second PMOS transistor is connected to the VBP node. The input terminal of the reference current source is connected to the power supply voltage Vdd, and the output terminal is connected to the drain and gate of the second NMOS transistor. The gate of the second NMOS transistor is connected to the gate of the first NMOS transistor, and the source of the second NMOS transistor is connected to the source of the first NMOS transistor. The drain of the first NMOS transistor is connected to the VBP node. The voltage-controlled oscillator outputs the VCO_CLK frequency, which is AC-coupled to the input of the first inverter via a capacitor. The output of the first inverter and the input of the second inverter are connected to node N1. The output of the second inverter and the input of the divider are connected to node N2. The divider outputs a feedback signal DIVIDER_OUT. A resistor is connected between the input and output of the first inverter to determine the AC coupling common-mode voltage. The stable operating current of the voltage-controlled oscillator is reflected by the second PMOS transistor and is greater than the reference current source. The reference current source is 1 / 2n times the stable operating current of the voltage-controlled oscillator, where n is the size ratio of the first PMOS transistor and the second PMOS transistor. The stable operating current of the voltage-controlled oscillator is greater than the startup current provided by the startup current source.

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