Clock signal synchronization circuit and system

Abstract

The application provides a clock signal synchronization circuit and system, which can be applied to the technical field of signal transmission. The circuit comprises: a first node, which comprises: a phase-locked loop unit configured to obtain a reference clock signal by frequency multiplication of a system clock signal according to a predetermined frequency multiplication coefficient; a first asynchronous storage unit configured to write to-be-transmitted data based on the system clock signal, read out the to-be-transmitted data based on the reference clock signal, and transmit the to-be-transmitted data to a second node, wherein the to-be-transmitted data comprises an identification code at a starting position; and the second node is configured to align a recovery clock signal with the to-be-transmitted data according to the identification code in the to-be-transmitted data and generate a clock reset signal, divide the recovery clock signal according to the clock reset signal and the predetermined frequency multiplication coefficient to obtain a divided clock signal, and output the to-be-transmitted data based on the divided clock signal.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of signal transmission, and more particularly to a clock signal synchronization circuit and system. BACKGROUND

[0002] In a high-energy physics experiment, a large-scale detection system, and a distributed detection node in a distributed measurement and control system, an independent local clock signal can be equipped. In the case where multiple distributed detection nodes exist, since each distributed detection node uses its own local clock signal as a reference for data transmission, it is difficult to effectively correspond the time sequence of the data collected from each distributed detection node. Therefore, it is necessary to unify the local clock signals of each distributed detection node to achieve time sequence consistency of data collection.

[0003] In the related art, the clock signal synchronization circuit is difficult to obtain a stable and synchronized local clock signal according to a system clock signal. SUMMARY

[0004] Therefore, the present application provides a clock signal synchronization circuit and system.

[0005] One aspect of the present application provides a clock signal synchronization circuit, the circuit comprising: a first node, the first node comprising: a phase-locked loop unit configured to obtain a reference clock signal by frequency multiplication of a system clock signal according to a predetermined frequency multiplication coefficient; a first asynchronous storage unit configured to write to-be-transmitted data based on the system clock signal, read the to-be-transmitted data based on the reference clock signal, and transmit the to-be-transmitted data to a second node, wherein the to-be-transmitted data includes an identification code at a starting position; and the second node configured to align a recovered clock signal with the to-be-transmitted data and generate a clock reset signal according to the identification code in the to-be-transmitted data, divide the recovered clock signal to obtain a divided clock signal according to the clock reset signal and the predetermined frequency multiplication coefficient, and output the to-be-transmitted data based on the divided clock signal.

[0006] According to the embodiment of the present application, the first asynchronous storage unit is further configured to: split the to-be-transmitted data based on the frequency of the reference clock signal to obtain a plurality of groups of to-be-transmitted sub-data, and transmit the plurality of groups of to-be-transmitted sub-data to the second node according to the position of the identification code and the reference clock signal.

[0007] According to an embodiment of the present application, the first asynchronous storage unit comprises: a first input end configured to receive the system clock signal; a second input end configured to write the to-be-transmitted data based on the system clock signal; a third input end configured to receive the reference clock signal; a first output end connected with the sending port of the first node and configured to transmit the plurality of groups of to-be-transmitted sub-data to the second node based on the reference clock signal; and / or the phase-locked loop unit comprises: a fourth input end configured to receive the system clock signal to obtain the reference clock signal by frequency multiplication of the system clock signal according to the predetermined frequency multiplication coefficient; and a second output end connected with the third input end of the first asynchronous storage unit and configured to transmit the reference clock signal to the first asynchronous storage unit.

[0008] According to an embodiment of the present application, the second node comprises: a frequency divider configured to obtain the frequency-divided clock signal by frequency division of the recovered clock signal according to the clock reset signal and the predetermined frequency multiplication coefficient; and a second asynchronous storage unit configured to output the to-be-transmitted data based on the frequency-divided clock signal.

[0009] According to an embodiment of the present application, the second asynchronous storage unit is further configured to: combine the plurality of groups of to-be-transmitted sub-data into the to-be-transmitted data, and output the to-be-transmitted data after aligning the to-be-transmitted data with a target position in the frequency-divided clock signal according to the position of the identification code.

[0010] According to an embodiment of the present application, the first asynchronous storage unit and the second asynchronous storage unit are both asynchronous first-in-first-out storage units.

[0011] According to an embodiment of the present application, the second node is further configured to: obtain a reverse reference clock signal according to the frequency-divided clock signal and the predetermined frequency multiplication coefficient, and transmit reverse to-be-transmitted data to the first node based on the reverse reference clock signal; and the first node is further configured to: generate a reverse clock reset signal according to the reverse reference clock signal, obtain a reverse frequency-divided clock signal by frequency division of a reverse recovered clock signal according to the reverse clock reset signal and the predetermined frequency division coefficient, and output the reverse to-be-transmitted data based on the reverse frequency-divided clock signal.

[0012] According to an embodiment of the present application, the first node and the second node are connected through a node transmission link, and the node transmission link comprises: an electro-optical conversion module configured to convert the to-be-transmitted data into an optical signal; an optical link configured to connect the electro-optical conversion module and an opto-electric conversion module and transmit the optical signal to the opto-electric conversion module; and the opto-electric conversion module configured to convert the optical signal into the to-be-transmitted data.

[0013] According to an embodiment of the present application, the first node is further configured to transmit the multiple groups of to-be-transmitted sub-data to the second node in a serial form via the node transmission link; and the second node is further configured to convert the multiple groups of to-be-transmitted sub-data in the serial form into a parallel form through a shift operation.

[0014] Another aspect of the present application provides a clock signal synchronization system, comprising: a clock source configured to provide a system clock signal; and the clock signal synchronization circuit of any one of the above.

[0015] According to an embodiment of the present application, in the first node, the phase-locked loop unit realizes frequency multiplication of the frequency of the system clock signal, obtains a reference clock signal and provides a frequency reference of the clock signal for data transmission of the first asynchronous storage unit; the first asynchronous storage unit realizes data writing and outputting under different frequencies of the clock signal, and provides a release time of the clock reset signal to the second node through the identification code of the start position in the to-be-transmitted data, so that the system clock signal is synchronized with the divided frequency clock signal obtained by the second node. The second node aligns the recovered clock signal with the to-be-transmitted data according to the identification code in the to-be-transmitted data, generates a clock reset signal, divides the recovered clock signal according to the clock reset signal and a predetermined frequency multiplication coefficient to obtain a divided frequency clock signal, and outputs the to-be-transmitted data based on the divided frequency clock signal, thereby realizing stable synchronization between the system clock signal and the recovered clock signal obtained by the second node, and maintaining the global clock signal synchronization relationship in the clock signal synchronization circuit. BRIEF DESCRIPTION OF DRAWINGS

[0016] The above and other objects, features and advantages of the present application will become more apparent from the following description of the embodiments of the present application taken with reference to the accompanying drawings.

[0017] Figure 1 A schematic diagram of a clock signal synchronization method in the related art is shown.

[0018] Figure 2 A schematic diagram of signal phases in a clock signal synchronization method of multiplying frequency first and then dividing frequency in the related art is shown.

[0019] Figure 3 A structural schematic diagram of a clock signal synchronization circuit according to an embodiment of the present application is shown.

[0020] Figure 4 A specific implementation structural diagram of a clock signal synchronization circuit according to an embodiment of the present application is shown.

[0021] Figure 5 A flowchart of an application method of a clock signal synchronization circuit according to an embodiment of the present application is shown.

[0022] Figure 6A timing diagram of clock signal synchronization is shown according to an embodiment of the present application.

[0023] Figure 7 A schematic diagram of a clock signal synchronization system is shown according to an embodiment of the present application. DETAILED DESCRIPTION

[0024] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. It is to be understood, however, the embodiments are merely exemplary of the application and should not be considered to narrow the scope of the application in any way. In the following detailed description of the embodiments, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to one of ordinary skill in the art that the present application can be practiced without these specific details. In other instances, well-known structures and functions have not been described in detail in order to avoid obscuring aspects of the application.

[0025] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the term "includes" and tautological equivalents thereof, means that the claimed features, steps, operations, and / or components are present, but does not exclude the presence or addition of one or more other features, steps, operations, or components.

[0026] All terms used herein including technical and scientific terms have the same meanings as commonly understood by one of ordinary skill in the art unless otherwise defined herein. It should be noted that the terms used herein should be interpreted as having a meaning that is consistent with the context of the specification, and not be interpreted in an idealized or overly formal way.

[0027] In situations where the term "at least one of A, B, and C" is used, it is to be understood that this includes the following situations: A alone, B alone, C alone, A and B together, A and C together, B and C together, and A and B and C together.

[0028] In the related art, a clock signal is synchronized by using a Multi-Gigabit Transceiver (MGT) module based on a Field Programmable Gate Array (FPGA). The basic principle of this method is that the master node embeds a reference clock signal into a high-speed serial data stream through the sending module of the MGT module and transmits it to the slave node; the slave node recovers the clock signal with the same frequency as the master node from the data stream by using the Clock Data Recovery (CDR) circuit in the receiving module of the MGT module, and then synchronizes it with the master node through a certain synchronization mechanism. This architecture was first proposed by the White Rabbit protocol, which can achieve a synchronization stability of tens of picoseconds. In recent years, further progress has been made in the temperature stability of fiber delay, the delay stability after the reset or re-powering of the MGT module, and other aspects, so that the synchronization accuracy of the clock signal distribution and synchronization link of the MGT module can be better than 10 picoseconds.

[0029] However, the frequency range of the clock signal supported by the FPGA-based MGT module is limited, for example, covering a certain frequency band. In different types of high-energy physics experiments, the system has different requirements for the frequency of the clock signal, and the required frequency in some application scenarios has exceeded the support range of the FPGA-based MGT module. In addition, in the fields of synchrotron radiation devices or industrial automation control networks, there is also a wide demand for high-precision configurable frequency clock signal distribution and synchronization, and the FPGA-based MGT module-based solution faces the problem of insufficient frequency adaptability in these applications.

[0030] To address the above problems, the White Rabbit protocol further introduces a Direct Digital Synthesis (DDS) method, which takes a standard frequency (such as 125MHz or 62.5MHz) as a reference, extracts the frequency of the target system clock signal and its phase relative to the reference clock signal in the master node, and encapsulates the frequency information of the target system clock signal and its phase relative to the reference clock signal as a data packet and sends it to the slave node. The slave node reconstructs the target system clock signal by using the DDS method. Although this method has good frequency flexibility, it needs to add additional circuits such as phase accumulators, waveform memories, and digital-to-analog converters, resulting in a complex circuit structure, high implementation cost, and decreased synchronization performance, which makes it difficult to meet the more demanding application requirements for synchronization error. Therefore, it is necessary to develop a clock signal synchronization method with a simple circuit structure and high frequency adaptability.

[0031] Figure 1 A schematic diagram of a clock signal synchronization method in the related art is shown.

[0032] As shown in Figure 1 , in the related art, a clock signal synchronization circuit divides or multiplies the original system clock signal CLK1 at a first node to obtain a reference clock signal, so that the frequency of the reference clock signal conforms to the range supported by the transmission port of the first node, and distributes the reference clock signal to a second node through a bottom layer link implemented by an MGT module. The second node recovers the system clock signal through reverse multiplication or division operation to obtain the system clock signal CLK2. Thus, the synchronization of the clock signal of the second node and the clock signal of the first node is realized.

[0033] As shown in Figure 1 (a), if the clock signal synchronization adopts the mode of division first and then multiplication, the phase of the system clock signal CLK2 obtained by multiplication at the second node remains stable relative to the original system clock signal CLK1.

[0034] As shown in Figure 1 (b), if the clock signal synchronization adopts the mode of multiplication first and then division, the phase of the system clock signal CLK2 recovered by division at the second node after the system is powered on or reset is unstable relative to the original system clock signal CLK1, thereby destroying the original synchronization state.

[0035] Figure 2 A schematic diagram of the phase of signals in the clock signal synchronization mode of multiplication first and then division in the related art is shown.

[0036] As shown in Figure 2 , taking the example of multiplication by 4 by a frequency multiplier and division by 4 by a frequency divider, the reason why the clock signal synchronization mode of multiplication first and then division leads to unstable phase of the system clock signal CLK2 is that there is a non-deterministic phase relationship between the release time of the clock reset signal of the frequency divider and the system clock signal CLK1. The phase of the system clock signal CLK2 can be any of , , or , that is, "asynchronous". If the reset signal can be synchronized with the system clock signal CLK1, that is, has a fixed phase delay relative to the rising edge, the phase of the system clock signal CLK2 output by the frequency divider will remain stable.

[0037] The clock signal synchronization mode of multiplication first and then division in the related art is difficult to realize the stable phase relationship between the original system clock signal CLK1 and the system clock signal CLK2 obtained by division.

[0038] Therefore, the application adds a first asynchronous storage unit and a phase-locked loop unit on the basis of the original distribution and synchronization link of the distribution frequency within the support range of the MGT module, and these modules can be implemented in the FPGA. By inserting an identification code at the starting position of each to-be-transmitted data, the receiving port of the second node can correctly identify the byte boundary and send a clock reset signal to recover the data, so as to expand the clock signal synchronization circuit to support the distribution and synchronization of the clock signal of any frequency, and determine the time when the second node sends the clock reset signal through the identification code at the starting position of the to-be-transmitted data, so that the clock signals of the first node and the second node can be stably synchronized.

[0039] Based on the above problems, the application provides a clock signal synchronization circuit and system, which can be applied to the technical field of signal transmission.

[0040] Figure 3 The structure diagram of the clock signal synchronization circuit according to the embodiment of the application is shown.

[0041] As shown in Figure 3 The clock signal synchronization circuit 300 includes a first node 310 and a second node 320. The first node 310 includes a phase-locked loop unit 311 and a first asynchronous storage unit 312.

[0042] The phase-locked loop unit 311 can be configured to multiply the system clock signal according to a predetermined frequency multiplication coefficient to obtain a reference clock signal. The first asynchronous storage unit 312 can be configured to write to-be-transmitted data based on the system clock signal, read the to-be-transmitted data based on the reference clock signal, and transmit the to-be-transmitted data to the second node, wherein the to-be-transmitted data includes an identification code at the starting position.

[0043] According to the embodiment of the application, the predetermined frequency multiplication coefficient can be a coefficient for multiplying the system clock signal by N, so that the frequency range of the reference clock signal obtained by multiplying the system clock signal by N can meet the clock signal frequency requirement of the MGT module, wherein N can be an integer greater than 1.

[0044] According to the embodiment of the application, the predetermined frequency multiplication coefficient N is determined by the frequency of the reference clock signal and the clock signal frequency range supported by the MGT module, so that the frequency of the reference clock signal obtained by multiplying the system clock signal by N according to the predetermined frequency multiplication coefficient can be within the frequency range supported by the MGT module. For example, the frequency of the system clock signal can be 40MHz, and the predetermined frequency multiplication coefficient can be 4, so that the reference clock signal with a frequency of 160MHz can be obtained.

[0045] According to an embodiment of the present application, the first node 310 can be configured to multiply the system clock signal to obtain a reference clock signal, and use the reference clock signal as a reference clock for transmitting the to-be-transmitted data. The identification code at the start position in the to-be-transmitted data is used to align the to-be-transmitted data with the recovered clock signal.

[0046] The second node 320 can be configured to align the recovered clock signal with the to-be-transmitted data according to the identification code in the to-be-transmitted data, and generate a clock reset signal. The recovered clock signal is divided according to the clock reset signal and a predetermined multiplication factor to obtain a divided clock signal, and the to-be-transmitted data is output based on the divided clock signal.

[0047] According to an embodiment of the present application, the recovered clock signal can be a signal with the same frequency as the reference clock signal, for example, 160 MHz. In the case that the second node 320 receives the to-be-transmitted data, the rising edge of the recovered clock signal can be aligned with the to-be-transmitted data according to the identification code in the to-be-transmitted data, and a clock reset signal is generated. Since the position of the identification code in the to-be-transmitted data is fixed, the phase delay between the to-be-transmitted data and the system clock signal at the second node is fixed, and therefore the phase delay between the recovered clock signal aligned with the to-be-transmitted data and the system clock signal is fixed, and the phase delay between the clock reset signal generated based on the recovered clock signal and the system clock signal is also fixed. Therefore, the clock reset signal can be used as the basis for the division of the frequency divider in the second node 320, so as to ensure that the divided clock signal of the second node 320 remains phase stable after each initialization or reset, thereby maintaining the synchronization relationship of the global clock signal.

[0048] According to an embodiment of the present application, in the first node, the phase-locked loop unit realizes multiplication of the frequency of the system clock signal to obtain a reference clock signal and provides a frequency reference for the first asynchronous storage unit data transmission; the first asynchronous storage unit realizes data writing and outputting under different clock signal frequencies, and provides the release time of the clock reset signal to the second node through the identification code at the start position in the to-be-transmitted data, so that the system clock signal is synchronized with the divided clock signal obtained by the second node. The second node aligns the recovered clock signal with the to-be-transmitted data according to the identification code in the to-be-transmitted data, and generates a clock reset signal. The recovered clock signal is divided according to the clock reset signal and a predetermined multiplication factor to obtain a divided clock signal, and the to-be-transmitted data is output based on the divided clock signal, thereby realizing stable synchronization between the system clock signal and the recovered clock signal obtained by the second node, and maintaining the synchronization relationship of the global clock signal in the clock signal synchronization circuit.

[0049] The first asynchronous storage unit can also be configured to split the to-be-transmitted data based on the frequency of the reference clock signal to obtain a plurality of groups of to-be-transmitted sub-data, and transmit the plurality of groups of to-be-transmitted sub-data to the second node according to the position of the identification code and the reference clock signal.

[0050] According to an embodiment of the present application, the to-be-transmitted data can be, for example, bits, where N is the same as the predetermined frequency multiplication coefficient N described above, and M is a positive integer, the first asynchronous storage unit can split the to-be-transmitted data into N groups of M-bit to-be-transmitted sub-data in input order based on the frequency of the reference clock signal, and insert an identification code at the beginning of the to-be-transmitted data, and transmit the plurality of groups of to-be-transmitted sub-data to the second node according to the reference clock signal.

[0051] According to an embodiment of the present application, the first asynchronous storage unit can split the to-be-transmitted data into a plurality of groups of to-be-transmitted sub-data in parallel form according to the frequency of the reference clock signal, and transmit the plurality of groups of to-be-transmitted sub-data to the second node in serial form through the sending port of the first node, thereby improving the data transmission efficiency under the same frequency of the clock signal, and placing the identification code in the beginning position of the to-be-transmitted data to enable the second node to generate a clock reset signal according to the position of the identification code.

[0052] The first asynchronous storage unit can include a first input end configured to receive a system clock signal, a second input end configured to write to-be-transmitted data based on the system clock signal, and a third input end configured to receive a reference clock signal. A first output end connected to the sending port of the first node is configured to transmit a plurality of groups of to-be-transmitted sub-data to the second node based on the reference clock signal. The phase-locked loop unit can include a fourth input end configured to receive the system clock signal to obtain the reference clock signal by multiplying the system clock signal by a predetermined frequency multiplication coefficient. A second output end connected to the third input end of the first asynchronous storage unit is configured to transmit the reference clock signal to the first asynchronous storage unit.

[0053] According to an embodiment of the present application, in the first asynchronous storage unit, the first input end can be used to receive a system clock signal. The second input end can be used to write to-be-transmitted data based on the system clock signal, and the to-be-transmitted data is written into the first asynchronous storage unit synchronously based on the rising edge of the system clock signal. The third input end can be used to receive a reference clock signal, and a plurality of groups of to-be-transmitted sub-data are transmitted based on the reference clock signal. The first output end is connected to the sending port of the first node, and the first output end can transmit a plurality of groups of to-be-transmitted sub-data to the sending port of the first node in parallel form based on the reference clock signal.

[0054] ​According to an embodiment of the present application, in the phase-locked loop unit, the fourth input terminal can be configured to receive a system clock signal, and the system clock signal is multiplied by a predetermined frequency multiplication factor to obtain a reference clock signal in the phase-locked loop unit. The second output terminal is connected to the third input terminal of the first asynchronous storage unit, and is configured to output the reference clock signal obtained after frequency multiplication, and transmit the reference clock signal to the first asynchronous storage unit.

[0055] According to an embodiment of the present application, the phase-locked loop unit multiplies the system clock signal by a predetermined frequency multiplication factor to obtain a reference clock signal. The first asynchronous storage unit writes the to-be-transmitted data according to the system clock signal, and sends a plurality of groups of to-be-transmitted sub-data according to the reference clock signal, realizing the conversion of the frequency of the clock signal and the data transmission under the frequency of different clock signals.

[0056] The second node can include a frequency divider and a second asynchronous storage unit. The frequency divider can be configured to divide the recovered clock signal by a clock reset signal and a predetermined frequency multiplication factor to obtain a frequency-divided clock signal. The second asynchronous storage unit can be configured to output the to-be-transmitted data based on the frequency-divided clock signal.

[0057] According to an embodiment of the present application, in the second node, the frequency divider can divide the recovered clock signal by a clock reset signal and a predetermined frequency multiplication factor to obtain a frequency-divided clock signal, and the frequency of the frequency-divided clock signal is consistent with that of the system clock signal, realizing the transmission of the frequency-divided clock signal with the same frequency as the system clock signal of the first node to the second node, so that the second asynchronous storage unit can also output the to-be-transmitted data based on the frequency-divided clock signal.

[0058] According to an embodiment of the present application, since the frequency-divided clock signal is obtained based on the clock reset signal, and the clock reset signal is generated based on the identification code, the delay between the identification code and the system clock signal is fixed, so the delay between the clock reset signal and the system clock signal is fixed, and thus the delay between the frequency-divided clock signal and the system clock signal is also fixed, improving the stability of the transmission of the system clock signal to the second node. Moreover, the transmission of data by the second asynchronous storage unit based on the frequency-divided clock signal can make the frequency of the data output from the second node consistent with that of the first node.

[0059] The second asynchronous storage unit can also be configured to combine a plurality of groups of to-be-transmitted sub-data into to-be-transmitted data, and output the to-be-transmitted data after aligning the to-be-transmitted data with a target position in the frequency-divided clock signal according to the position of the identification code.

[0060] According to the embodiment of the present application, the multiple groups of sub-data to be transmitted received by the second asynchronous storage unit can be serial, and the multiple groups of sub-data to be transmitted are recombined into parallel data to be transmitted according to the frequency division clock signal generated by the frequency divider and the position of the identification code in the data to be transmitted, and the position of the identification code is aligned with the target position in the frequency division clock signal (for example, any rising edge in the frequency division clock signal) and then outputted.

[0061] According to the embodiment of the present application, the recovery clock signal obtained based on the reference clock signal and the frequency division clock signal obtained by frequency dividing the recovery clock signal are clock signals of different frequencies, in the second asynchronous storage unit, the multiple groups of sub-data to be transmitted received based on the recovery clock signal are converted into parallel data to be transmitted in serial form, and the clock reset signal is generated according to the position of the identification code, the frequency divider generates the frequency division clock signal according to the generation time of the clock reset signal, and the synchronization of the frequency division clock signal and the system clock signal is realized. The second asynchronous storage unit outputs the parallel data to be transmitted based on the frequency division clock signal, and realizes the data transmission under the stable and synchronized clock signal.

[0062] The first asynchronous storage unit and the second asynchronous storage unit are both asynchronous first-in-first-out storage units.

[0063] According to the embodiment of the present application, the first asynchronous storage unit and the second asynchronous storage unit allow the data to be transmitted from one clock domain to another independent clock domain safely through the first-in-first-out storage mechanism, and the data transmission between different clock domains can be realized.

[0064] The second node can also be configured to obtain a reverse reference clock signal according to the frequency division clock signal and a predetermined frequency multiplication coefficient, and transmit reverse data to be transmitted to the first node based on the reverse reference clock signal. The first node can also be configured to generate a reverse clock reset signal according to the reverse reference clock signal, obtain a reverse frequency division clock signal by frequency dividing the reverse recovery clock signal according to the reverse clock reset signal and the predetermined frequency multiplication coefficient, and output the reverse data to be transmitted based on the reverse frequency division clock signal.

[0065] According to the embodiment of the present application, the transmission direction of the to-be-transmitted data is from the first node to the second node, and the frequency range of the system clock signal is converted into a frequency applicable to the transmission of the sending port (for example, the MGT module) of the first node through frequency multiplication and frequency division. The transmission direction of the to-be-transmitted data in the reverse direction is from the second node to the first node. In the case of transmitting data in the reverse direction, the frequency multiplication and frequency division can also be used, that is, in the second node, the reference clock signal in the reverse direction is obtained by multiplying the frequency of the frequency division clock signal according to the predetermined frequency multiplication coefficient, and the to-be-transmitted data in the reverse direction is transmitted to the first node based on the reference clock signal in the reverse direction. In the first node, the to-be-transmitted data in the reverse direction is output based on the reverse frequency division clock signal obtained by multiplying the frequency of the reverse recovery clock signal according to the reverse clock reset signal and the predetermined frequency multiplication coefficient.

[0066] According to the embodiment of the present application, the clock signal synchronization circuit can realize clock signal synchronization and data transmission through frequency multiplication and frequency division or frequency division and frequency multiplication, so that the frequency range of the clock signal after frequency multiplication or frequency division is within the frequency range of the sending module of the sending port of the first node and the second node. Through the above method, the synchronization of the clock signal and the transmission of the data at any frequency can be realized.

[0067] According to the embodiment of the present application, the second node can also be configured to transmit the to-be-transmitted data in the reverse direction to the first node according to the recovery clock signal. The first node can also be configured to receive the to-be-transmitted data in the reverse direction according to the reference clock signal, and output the to-be-transmitted data in the reverse direction according to the system clock signal.

[0068] Since the second node has obtained the recovery clock signal capable of realizing the transmission between the second node and the first node in the process of obtaining the synchronized frequency division clock signal, in the case of transmitting the to-be-transmitted data in the reverse direction from the second node to the first node, the to-be-transmitted data in the reverse direction can be transmitted to the first node based on the recovery clock signal.

[0069] Since the first node has also obtained the reference clock signal with the same frequency as the recovery clock signal, the to-be-transmitted data in the reverse direction can be received based on the reference clock signal, and the to-be-transmitted data in the reverse direction can be output based on the system clock signal of the first node.

[0070] The second node transmits the to-be-transmitted data in the reverse direction to the first node through the obtained recovery clock signal, the first node receives the to-be-transmitted data in the reverse direction through the obtained reference clock signal, and outputs the to-be-transmitted data in the reverse direction according to the system clock signal, which reduces the actions of frequency division of the second node and frequency multiplication of the first node, and improves the data transmission efficiency.

[0071] The node transmission link between the first node and the second node can include an electro-optical conversion module, an optical link and an optical-electric conversion module. The electro-optical conversion module can be configured to convert the data to be transmitted into an optical signal. The optical link can be configured to connect the electro-optical conversion module and the optical-electric conversion module and transmit the optical signal to the optical-electric conversion module. The optical-electric conversion module can be configured to convert the optical signal into the data to be transmitted.

[0072] According to an embodiment of the present application, the type of the node transmission link between the first node and the second node is not limited, for example, can include a fiber direct connection, a wavelength division multiplexing, a dense wavelength division multiplexing or a fiber circulator, but the present application is not limited thereto. In the case that the transmission delay of the node transmission link between the first node and the second node is stable and controllable, the delay of the identification code located at the starting position in the data to be transmitted received by the second node relative to the system clock signal of the first node is stable.

[0073] According to an embodiment of the present application, in the case that the node transmission link delay is stable, the recovery clock signal received by the second node also has a stable and controllable delay, and the frequency divider frequency-divides the recovery clock signal to obtain a frequency-divided clock signal having a fixed phase relationship relative to the system clock signal, so as to realize stable clock signal synchronization and data transmission.

[0074] The first node can also be configured to transmit the plurality of groups of data to be transmitted to the second node in a serial form via the node transmission link. The second node can also be configured to convert the plurality of groups of data to be transmitted in the serial form into a parallel form through a shift operation.

[0075] According to an embodiment of the present application, in the first node, the first asynchronous storage unit splits the data to be transmitted into a plurality of groups of data to be transmitted, and transmits the plurality of groups of data to be transmitted to the sending port of the first node in a parallel form. The sending port of the first node converts the plurality of groups of data to be transmitted into a serial form and transmits the plurality of groups of data to be transmitted to the receiving port of the second node via the node transmission link. The plurality of groups of data to be transmitted received by the second node from the node transmission link is in a serial form, and the plurality of groups of data to be transmitted in the serial form is converted into a parallel form through a shift operation in the second node and input into the second asynchronous storage unit.

[0076] According to an embodiment of the present application, the plurality of groups of data to be transmitted is transmitted in a serial form in the node transmission link during the transmission from the first node to the second node, which reduces the data crosstalk during the transmission in the node transmission link. The plurality of groups of data to be transmitted is converted into a parallel form in the second node, which reduces the timing conflict caused by the cross-clock domain transmission and facilitates the subsequent high-speed processing of the data.

[0077] Figure 4 A specific implementation structure diagram of a clock signal synchronization circuit according to an embodiment of the present application is shown.

[0078] As shown in Figure 4 the embodiment of the present application adds two asynchronous storage units (i.e. the first asynchronous storage unit and the second asynchronous storage unit), a phase-locked loop unit and a frequency divider in the first node and the second node to realize the distribution and synchronization of clock signals of any frequency.

[0079] According to the embodiment of the present application, the system clock signal provided by the clock source is input into the first asynchronous storage unit through the first input end. In the first node, the system clock signal is multiplied by a predetermined frequency multiplication coefficient through the phase-locked loop unit to obtain a reference clock signal. The phase-locked loop unit transmits the reference clock signal to the first asynchronous storage unit and the transmit port of the first node. The data to be transmitted is written into the first asynchronous storage unit through the second input end based on the rising edge of the system clock signal. In the first asynchronous storage unit, the data to be transmitted is split into multiple groups of data to be transmitted under the control of the reference clock signal and transmitted in parallel to the transmit port of the first node through the first output end. The transmit port of the first node converts the multiple groups of data to be transmitted into a serial form and transmits them to the receive port of the second node through the node transmission link. The node transmission link includes an electro-optical conversion module, an optical-electrical conversion module and an optical link. The electro-optical conversion module converts the multiple groups of data to be transmitted into optical signals, which are transmitted to the optical-electrical conversion module through the optical link. The optical-electrical conversion module converts the optical signals into the multiple groups of data to be transmitted and transmits them to the receive port of the second node. The start position of the data to be transmitted is provided with an identification code to assist the receive port (RX) of the second node to correctly identify the byte boundary and recover the data. The receive port of the second node can recover the multiple groups of data to be transmitted into the data to be transmitted in parallel form and transmit them to the second asynchronous storage unit, and transmit a recovered clock signal to the second asynchronous transmission to make the second asynchronous storage unit align the recovered clock signal with the data to be transmitted and generate a clock reset signal. After the recovered clock signal is divided by the clock reset signal and the predetermined frequency multiplication coefficient, a divided clock signal is obtained, and the data to be transmitted is output based on the divided clock signal.

[0080] According to the embodiment of the present application, since the first asynchronous storage unit operates at the same read-write speed, and the phase relationship between the system clock signal and the reference clock signal is kept fixed by the phase-locked loop unit, the identification code in the data to be transmitted transmitted in parallel form keeps synchronized with the rising edge of the system clock signal. In the case of realizing the stability of the data to be transmitted inside the transmit port of the first node, the delay of the start position of the identification code in the data to be transmitted in serial form transmitted by the transmit port of the first node relative to the rising edge of the system clock signal can be kept stable.

[0081] According to an embodiment of the present application, the data to be transmitted is transmitted to the receiving port of the second node via the transmitting port of the first node and the node transmission link. The type of the optical link in the node transmission link is not limited, and can include but is not limited to optical fiber direct connection, wavelength division multiplexing, dense wavelength division multiplexing, or fiber ring, etc. In the case that the delay of the optical link is stable and controllable, the first bit of the identification code in the data to be transmitted received by the receiving port of the second node also remains stable relative to the delay of the system clock signal of the first node. The serial form of the plurality of groups of data to be transmitted is converted into parallel form of the data to be transmitted by the shift operation at the receiving port of the second node, and the byte boundary is aligned. In the case that the identification code in the data to be transmitted is identified, the clock reset signal can be sent. The release time of the clock reset signal relative to the phase delay of the system clock signal of the first node is fixed, and thus can be used as the basis for frequency division of the frequency divider of the second node to generate the frequency division clock signal, so that the frequency division clock signal obtained by frequency division of the second node can still maintain phase stability after each system initialization or reset, thereby maintaining the synchronization relationship of the global clock signal.

[0082] According to an embodiment of the present application, the second node can also transmit reverse data to be transmitted to the first node. In the case that the first node transmits data to be transmitted to the second node, since the second node has obtained the recovered clock signal, in the case that the second node transmits data to the first node, the second node can use the recovered clock signal as a reverse reference clock signal to transmit data to the first node according to the reverse reference clock signal. The process of transmitting data from the second node to the first node is similar to the process of transmitting data from the first node to the second node, and thus the process of transmitting data from the second node to the first node can refer to the description of the process of transmitting data from the first node to the second node, which will not be described here.

[0083] Figure 5 A flow chart of the application method of the clock signal synchronization circuit according to an embodiment of the present application is shown.

[0084] As shown in Figure 5 The application method of the clock signal synchronization circuit includes operations S510-S540.

[0085] In operation S510, the system clock signal is frequency-multiplied according to a predetermined frequency multiplication coefficient to obtain a reference clock signal.

[0086] Taking a 40 megahertz (MHz) system clock signal and a predetermined frequency multiplication coefficient N=4 as an example for description.

[0087] In the first node, the system clock signal is frequency-multiplied by N according to the predetermined frequency multiplication coefficient by the phase-locked loop unit to obtain a reference clock signal, and the frequency of the reference clock signal can be 160 MHz.

[0088] According to the embodiment of the present application, the reference clock signal frequency should be within the range supported by the transmitting port (e.g. MGT module) of the first node. The phase-locked loop unit can call the resources in the clock management module (CMT) through the intellectual property core (IP Core) provided by the FPGA.

[0089] In operation S520, the to-be-transmitted data is written based on the system clock signal, the to-be-transmitted sub-data is output based on the reference clock signal, and the to-be-transmitted sub-data is transmitted to the second node.

[0090] The to-be-transmitted data is written to the first asynchronous storage unit based on the system clock signal, and is configured to bits, of which the first M bits are identification code for identifying byte boundary. After the to-be-transmitted data is written, the first asynchronous storage unit reads out the to-be-transmitted data in the form of to-be-transmitted sub-data in N M-bit parallel form based on the reference clock signal, and the transmitting port of the first node converts the multiple groups of to-be-transmitted sub-data into serial form and transmits to the receiving port of the second node through the node transmission link.

[0091] According to the embodiment of the present application, M=16 is taken, and the to-be-transmitted data is 64 bits, of which the first 16 bits are identification code, and the width of the to-be-transmitted data is 16 bits. The first asynchronous storage unit can be implemented through the IP Core in the FPGA.

[0092] In operation S530, the recovery clock signal is aligned with the to-be-transmitted data according to the identification code in the to-be-transmitted data, and a clock reset signal is generated.

[0093] The receiving port of the second node receives the to-be-transmitted data transmitted by the first node, detects the identification code from the to-be-transmitted data, and transmits the to-be-transmitted data to the second asynchronous storage unit in parallel form. In the case of detecting the identification code, the clock reset signal is used as the basis for frequency division of the frequency divider to generate the frequency-divided clock signal, so as to realize that the frequency-divided clock signal has a fixed phase relationship with the system clock signal of the first node.

[0094] In operation S540, the frequency-divided clock signal is obtained by frequency dividing the recovery clock signal according to the clock reset signal and a predetermined frequency multiplication coefficient, and the to-be-transmitted data is output based on the frequency-divided clock signal.

[0095] According to the clock reset signal, the second node frequency-divides the recovery clock signal of the receiving port by N through the frequency divider to obtain the frequency-divided clock signal. The second asynchronous storage unit recovers the to-be-transmitted data according to the frequency-divided clock signal and outputs it. The frequency of the recovery clock signal is 160 MHz. The second asynchronous storage unit can be implemented through the IP Core in the FPGA.

[0096] Figure 6 A timing diagram of clock signal synchronization is shown according to an embodiment of the present application.

[0097] As shown in Figure 6 , taking 40 megahertz (MHz) system clock signal and 64 bits data to be transmitted as an example, the system clock signal is frequency-multiplied by 4 through a phase-locked loop unit to obtain a reference clock signal with a frequency of 160 MHz, at this time, the 64 bits data to be transmitted is output as 4 groups of parallel 16 bits data to be transmitted through a first asynchronous storage unit, that is, TX parallel data in Figure 6 . Among them, C represents an 8 bits identification code, D1, D2, D3, D4, D5, D6, D7… represent 8 bits data arranged in order after the identification code position, and the starting position of each data stream is the identification code. The parallel data to be transmitted is output in a serial form through the output port of the first node, that is, TX serial data in Figure 6 . The transmission rate of TX serial data is 3.2 Gbps. After transmission through the node transmission link, the receiving port of the second node receives the serial data at a receiving rate of 3.2 Gbps, that is, RX serial data in Figure 6 . The RX serial data is converted into 16 bits parallel data, that is, RX parallel data, based on the 160 MHz recovery clock signal. According to the position of the identification code in the RX parallel data, a clock reset signal is generated at the next rising edge position of the recovery clock signal, and a frequency division clock signal is obtained based on the clock reset signal. Since the frequency division clock signal is obtained based on the clock reset signal, and the clock reset signal is generated based on the identification code, the delay between the identification code and the system clock signal is fixed, so the delay between the clock reset signal and the system clock signal is fixed, thereby realizing that the frequency division clock signal obtained based on the clock reset signal has a fixed phase relationship with the system clock signal, and improving the stability of the system clock signal in the synchronization between distributed systems.

[0098] Figure 7 A schematic diagram of a clock signal synchronization system is shown according to an embodiment of the present application.

[0099] As shown in Figure 7 , the clock signal synchronization system 700 includes a clock source 710 and a clock signal synchronization circuit 300.

[0100] The clock source 710 is configured to provide a system clock signal for the clock signal synchronization circuit.

[0101] The clock signal synchronization circuit 300 performs data transmission and synchronization with the system clock signal provided by the clock source 710 as a reference. The explanation of the clock signal synchronization circuit 300 can refer to the description of other embodiments of the present application, which will not be repeated here.

[0102] The flow and block diagrams in the drawings represent possible architectural, functional, and operational architectures of methods according to various embodiments of the present application. In this regard, each block can represent a module, a segment, or a portion of code that comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently or the blocks may be executed in the reverse order, depending on the functionality involved. It will also be noted that each block of the block diagrams and / or flowchart illustrations, and combinations thereof, can be implemented by a dedicated hardware-based system that performs the specified functions or operations, or combinations of hardware and software. Those skilled in the art will appreciate that the features of the various embodiments of the present application can be combined or recombined in a wide variety of configurations, all of which come within the scope of the present application. In particular, the features of the various embodiments of the present application can be combined or recombined in a wide variety of configurations, all of which come within the scope of the present application. In particular, the features of the various embodiments of the present application can be combined or recombined in a wide variety of configurations, all of which come within the scope of the present application.

[0103] The embodiments of the present application have been described above. However, these embodiments are merely meant to be illustrative, and not meant to limit the scope of the present application. Although each of the embodiments has been described above, this does not mean that the measures in each of the embodiments cannot be used advantageously in combination. Various alternatives and modifications can be made to the embodiments of the present application without departing from the scope of the present application, and all such alternatives and modifications are intended to fall within the scope of the present application.

Claims

1. A clock signal synchronization circuit, characterized in that, The circuit includes: The first node includes: The phase-locked loop unit is configured to multiply the system clock signal according to a predetermined multiplication factor to obtain a reference clock signal; The first asynchronous storage unit is configured to write data to be transmitted based on the system clock signal, read the data to be transmitted based on the reference clock signal, and transmit the data to be transmitted to the second node, wherein the data to be transmitted includes an identification code located at the starting position; The second node is configured to align the recovery clock signal with the data to be transmitted based on the identification code in the data to be transmitted and generate a clock reset signal, divide the recovery clock signal according to the clock reset signal and the predetermined multiplication factor to obtain a frequency-divided clock signal, and output the data to be transmitted based on the frequency-divided clock signal.

2. The circuit according to claim 1, characterized in that, The first asynchronous storage unit is further configured as follows: The data to be transmitted is split based on the frequency of the reference clock signal to obtain multiple sets of sub-data to be transmitted, and the multiple sets of sub-data to be transmitted are transmitted to the second node according to the position of the identification code and the reference clock signal.

3. The circuit according to claim 2, characterized in that, The first asynchronous storage unit includes: The first input terminal is configured to receive the system clock signal; The second input terminal is configured to write the data to be transmitted based on the system clock signal; The third input terminal is configured to receive the reference clock signal; A first output terminal connected to the transmitting port of the first node is configured to transmit the multiple sets of sub-data to be transmitted to the second node based on the reference clock signal; and / or The phase-locked loop unit includes: The fourth input terminal is configured to receive the system clock signal, and to multiply the system clock signal according to the predetermined multiplication factor to obtain the reference clock signal; The second output terminal, which is connected to the third input terminal of the first asynchronous memory unit, is configured to transmit the reference clock signal to the first asynchronous memory unit.

4. The circuit according to claim 2, characterized in that, The second node includes: The frequency divider is configured to divide the recovered clock signal according to the clock reset signal and the predetermined frequency multiplication factor to obtain the frequency-divided clock signal; The second asynchronous storage unit is configured to output the data to be transmitted based on the frequency division clock signal.

5. The circuit according to claim 4, characterized in that, The second asynchronous storage unit is also configured as follows: The multiple sets of sub-data to be transmitted are combined into the data to be transmitted, and the data to be transmitted is aligned with the target position in the frequency division clock signal according to the position of the identification code before being output.

6. The circuit according to claim 4, characterized in that, Both the first asynchronous storage unit and the second asynchronous storage unit are asynchronous first-in-first-out storage units.

7. The circuit according to claim 1, characterized in that, The second node is also configured as follows: A reverse reference clock signal is obtained based on the frequency division clock signal and the predetermined frequency multiplication factor, and the reverse data to be transmitted is transmitted to the first node based on the reverse reference clock signal; The first node is also configured as follows: A reverse clock reset signal is generated based on the reverse reference clock signal. The reverse recovery clock signal is divided by the reverse clock reset signal and the predetermined frequency multiplication factor to obtain a reverse frequency divided clock signal. The reverse data to be transmitted is output based on the reverse frequency divided clock signal.

8. The circuit according to claim 2, characterized in that, The first node and the second node are connected via a node transmission link, which includes: An electro-optical conversion module is configured to convert the data to be transmitted into an optical signal; An optical link is configured to connect the electro-optical conversion module and the photoelectric conversion module, and to transmit the optical signal to the photoelectric conversion module; The photoelectric conversion module is configured to convert the optical signal into the data to be transmitted.

9. The circuit according to claim 8, characterized in that, The first node is also configured as follows: The multiple sets of sub-data to be transmitted are transmitted serially to the second node via the node transmission link; The second node is also configured as follows: The multiple sets of sub-data to be transmitted in serial form are converted into parallel form through shifting operations.

10. A clock signal synchronization system, characterized in that, include: Clock source, configured to provide the system clock signal; The clock signal synchronization circuit as described in any one of claims 1 to 9.

Images