Method for manufacturing image sensor, image sensor, and electronic device

Abstract

The application discloses a preparation method of an image sensor, the image sensor and electronic equipment. The preparation method of the image sensor comprises the following steps: providing a substrate formed with a shallow trench isolation structure; forming an insulating layer above the shallow trench isolation structure; forming a plurality of spaced isolation regions on the insulating layer; forming a photodiode with a double-layer interlaced structure in each isolation region, wherein the photodiode with the double-layer interlaced structure comprises a first interlaced structure containing a group VA main group element, an epitaxial layer and a second interlaced structure; and forming a light filtering structure above the photodiode in each isolation region. Through the scheme, unnecessary damage to the substrate can be avoided, the photodiode with the double-layer interlaced structure is formed in each isolation region, the color mixing problem can be avoided, and more ions can be generated, so that the performance of the prepared image sensor is effectively improved.

Description

Technical Field

[0001] This application generally relates to the field of integrated circuit technology. More specifically, this application relates to a method for fabricating an image sensor, an image sensor, and an electronic device. Background Technology

[0002] An image sensor is a device that converts optical images into electronic signals, and it is widely used in digital cameras and other electro-optical devices. Back-illuminated (BSI) fabrication is commonly used to fabricate image sensors. However, traditional BSI processes require high-energy ion implantation in the front-end to form photodiodes (PDs). This ion implantation method inevitably damages the substrate surface and can even cause crosstalk, compromising the performance of the fabricated image sensor.

[0003] Therefore, there is an urgent need to provide a fabrication scheme for image sensors to improve the performance of the fabricated image sensors. Summary of the Invention

[0004] In order to at least solve one or more of the technical problems mentioned above, this application proposes a fabrication scheme for an image sensor in several aspects.

[0005] In a first aspect, this application provides a method for fabricating an image sensor, comprising: providing a substrate having a shallow trench isolation structure; forming an insulating layer above the shallow trench isolation structure; forming a plurality of spaced-apart isolation regions on the insulating layer; forming a photodiode having a double-layered interlaced structure in each of the isolation regions, wherein the double-layered interlaced photodiode includes a first interlaced structure containing a Group VA element, an epitaxial layer, and a second interlaced structure; and forming a filter structure above the photodiode in each of the isolation regions.

[0006] In some embodiments, forming a photodiode with a double-layered interlaced structure in each of the isolation regions includes: forming a first interlaced structure on an insulating layer in each of the isolation regions; forming an epitaxial layer over the first interlaced structure in each of the isolation regions; and forming a second interlaced structure on the epitaxial layer in each of the isolation regions, wherein the first interlaced structure and the second interlaced structure include a Si-Sb layer and a plurality of Si-P layers spaced apart in the Si-Sb layer.

[0007] In some embodiments, the first interleaved structure and the second interleaved structure are prepared by the following steps: depositing a Si-Sb layer on an insulating layer and on a Si-As layer in each of the isolation regions; etching the Si-Sb layer in each of the isolation regions to form a plurality of spaced grooves; and depositing a Si-P layer in the plurality of grooves.

[0008] In some embodiments, forming a plurality of spaced isolation regions on the insulating layer includes: planarizing a substrate located on the back side of the insulating layer; sequentially depositing multiple isolation layers on the insulating layer; and etching the multiple isolation layers to form the plurality of isolation regions.

[0009] In some embodiments, the sequential deposition of multiple isolation layers on the insulating layer includes: forming a first isolation layer, a second isolation layer, a third isolation layer, and a fourth isolation layer sequentially on top of the insulating layer using a deposition process.

[0010] In some embodiments, forming a filter structure above the photodiode in each of the isolation regions includes: forming multiple light-blocking layers above the photodiode in each of the isolation regions; etching the multiple light-blocking layers to form spaced-apart light-shielding areas; and providing a light-shielding sheet in each of the light-shielding areas.

[0011] In some embodiments, depositing multiple light-blocking layers over the photodiode in each of the isolation regions includes: sequentially forming a first light-blocking layer, a second first light-blocking layer, and a third light-blocking layer over the photodiode in each of the isolation regions using a deposition process.

[0012] In a second aspect, this application provides an image sensor, comprising: a substrate having a trench isolation structure formed thereon, an insulating layer formed above the trench isolation structure; a plurality of photodiodes having a double-layered interleaved structure, wherein each photodiode is located in a plurality of spaced-apart isolation regions of the insulating layer, and each photodiode includes a first interleaved structure containing a group VA element, an epitaxial layer, and a second interleaved structure; and a filter structure located above the photodiodes in each of the isolation regions.

[0013] In some embodiments, the first interleaved structure is located on an insulating layer in each of the isolation regions, the epitaxial layer is located above the first interleaved structure in each of the isolation regions, and the second interleaved structure is located above the epitaxial layer in each of the isolation regions. The first interleaved structure and the second interleaved structure include a Si-Sb layer and a plurality of Si-P layers spaced apart in the Si-Sb layer.

[0014] In a third aspect, this application provides an electronic device comprising: an image sensor fabricated using the image sensor fabrication method described in the first aspect; or an image sensor as described in the second aspect.

[0015] An unexpected and beneficial technical effect of this application is that, through the image sensor fabrication method, image sensor, and electronic device provided above, the embodiments of this application optimize the formation process and structure of photodiodes during the image sensor fabrication process. This effectively avoids unnecessary damage to the substrate caused by the traditional ion implantation method for fabricating photodiodes. At the same time, forming photodiodes with a double-layered interlaced structure in each isolation region can avoid color mixing problems and generate more ions, thereby effectively improving the performance of the fabricated image sensor. Attached Figure Description

[0016] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily understood by reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of this application are illustrated by way of example and not limitation, and the same or corresponding reference numerals denote the same or corresponding parts, wherein:

[0017] Figure 1 A schematic flowchart illustrating a method for fabricating an image sensor according to some embodiments of this application is shown;

[0018] Figure 2 Schematic flowcharts illustrating methods for fabricating image sensors according to other embodiments of this application are shown; and

[0019] Figures 3a-3k A cross-sectional schematic diagram of an image sensor prepared using some embodiments of this application is shown.

[0020] The following labels are used in the attached diagram:

[0021] 301-Substrate, 302-Shallow trench isolation structure, 303-Insulating layer, 304-First isolation layer, 305-Second isolation layer, 306-Third isolation layer, 307-Fourth isolation layer, 308-Isolation region, 309-First Si-Sb layer, 310-First Si-P layer, 311-Epipolar layer, 312-Second Si-Sb layer, 313-Second Si-P layer, 314-First light-blocking layer, 315-Second light-blocking layer, 316-Third light-blocking layer, 317-Light-shielding region, 318-First light-shielding sheet, 319-Second light-shielding sheet, 320-Third light-shielding sheet. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0023] It should be understood that the terms "comprising" and "including" used in the specification and claims of this application indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0024] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application. As used in this specification and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this specification and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0025] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0026] Figure 1 A schematic flowchart of a method 100 for fabricating an image sensor according to some embodiments of this application is shown.

[0027] like Figure 1 As shown, in step S101, a substrate with a shallow trench isolation structure can be provided.

[0028] In step S102, an insulating layer is formed above the aforementioned shallow trench isolation structure.

[0029] In step S103, a plurality of spaced isolation regions are formed on the aforementioned insulating layer.

[0030] In step S104, a photodiode with a double-layered interlaced structure is formed in each of the aforementioned isolation regions. This double-layered interlaced photodiode includes a first interlaced structure containing elements of the VA group, an epitaxial layer, and a second interlaced structure.

[0031] In step S105, a filter structure can be formed above the photodiode in each of the aforementioned isolation regions.

[0032] In this application, the substrate can be made of semiconductor material, insulating material, conductive material, or any combination thereof. For example, the substrate can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other semiconductor substrates. Alternatively, the substrate can be a layered substrate including materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. It should be noted that this application does not limit the material or shape of the substrate; it can be adjusted and configured according to actual application requirements.

[0033] In some embodiments, a shallow trench isolation (STI) structure can be formed in the front-end of the image sensor (FEOL) process. In practical applications, this STI structure is primarily formed by depositing, patterning, and etching silicon using a silicon nitride mask to create trenches, followed by filling the trenches with deposited oxide. It should be noted that currently common fabrication processes can be used to fabricate this STI structure; the specific fabrication process will not be elaborated upon here.

[0034] After the STI structure is fabricated in the front-end process, an insulating layer can be formed on top of the STI structure. For example, an insulating layer can be implanted on top of the STI structure using ion implantation technology. This insulating layer can be made of gallium (Ga)-doped silicon or other similar materials. Next, multiple spaced isolation regions can be formed on this insulating layer. Then, a photodiode is formed in each of these isolation regions. These photodiodes have a double-layered interleaved structure, specifically including a first interleaved structure, an epitaxial layer, and a second interleaved structure. The first interleaved structure, the epitaxial layer, and the second interleaved structure all contain elements from Group VA. After the photodiodes are fabricated, a filter structure can be formed on top of them. This completes the fabrication of the image sensor.

[0035] An unexpected and beneficial technical effect of this application is that the formation process and structure of photodiodes are optimized during the fabrication of image sensors, eliminating the need for ion implantation processes. The photodiodes in this application employ a double-layered, interlaced structure, which facilitates the generation of more ions. Increased ion generation leads to higher quantum efficiency, which in turn indicates a higher photoelectric conversion capability, higher photosensitivity, and more information provided by the image sensor. This effectively improves the performance of the image sensor. Furthermore, the effective isolation of the individual photodiodes by the isolation regions allows subsequent incident light to converge at the center of the photodiode region, thus reducing crosstalk.

[0036] Figure 2 A schematic flowchart of a method 200 for fabricating an image sensor according to other embodiments of this application is shown. It should be noted that... Figure 2 The preparation method 200 in the text can be understood as... Figure 1 This is a supplement or extension to the preparation method 100 shown. Therefore, in conjunction with the preceding text... Figure 1 The relevant descriptions also apply to the following text.

[0037] like Figure 2 As shown, in step S201, a substrate with a shallow trench isolation structure can be provided, and an insulating layer can be formed on top of the shallow trench isolation structure. As mentioned above, silicon, silicon-germanium, silicon-germanium-carbon, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, or other materials can be selected as the substrate. Then, the shallow trench isolation structure is fabricated on the selected substrate. After the shallow trench isolation structure is fabricated, an insulating layer can be fabricated on top of the shallow trench isolation structure.

[0038] refer to Figure 3a First, a substrate 301 is selected, and a shallow trench isolation structure 302 is formed on the substrate 301 in the front-end process of the image sensor. Then, after the shallow trench isolation structure 302 is fabricated, an insulating layer 303 (e.g., a Si-Ga layer) can be implanted on top of the shallow trench isolation structure 302 by means such as ion implantation.

[0039] After the insulating layer 303 is prepared, multiple spaced isolation regions can be formed on the insulating layer 303. Figure 2 Specifically, the isolation area can be formed through steps S202 to S204.

[0040] In step S202, the substrate located on the back side of the insulating layer can be planarized. In some embodiments, a chemical mechanical planarization (CMP) process can be used to planarize the substrate located on the back side of the insulating layer, thereby exposing the insulating layer from the substrate.

[0041] refer to Figure 3b The insulating layer 303 is located above the shallow trench isolation structure 302. The substrate 301, located on the back side of the insulating layer 303, is planarized to expose the insulating layer 303. It should be noted that CMP process or other processes can be used to achieve the substrate planarization, depending on the specific process requirements.

[0042] return Figure 2 In step S203, multiple isolation layers can be sequentially deposited on the aforementioned insulating layer. In some embodiments, the multiple isolation layers may specifically include four isolation layers. For example, a first isolation layer, a second isolation layer, a third isolation layer, and a fourth isolation layer can be sequentially formed on top of the insulating layer using a deposition process.

[0043] refer to Figure 3c In the front-end fabrication of the image sensor, a shallow trench isolation structure 302 is formed on a substrate 301. After the shallow trench isolation structure 302 is fabricated, an insulating layer 303 can be implanted on top of the shallow trench isolation structure 302 using methods such as ion implantation. Next, the substrate 301 on the back side of the insulating layer 303 is planarized to expose the insulating layer 303. Then, a first isolation layer 304, a second isolation layer 305, a third isolation layer 306, and a fourth isolation layer 307 are sequentially formed on top of the insulating layer 303. The first isolation layer 304, the second isolation layer 305, the third isolation layer 306, and the fourth isolation layer 307 can all be formed by deposition, which effectively avoids lattice defects. In some embodiments, the first isolation layer 304 can be a Ta2O5 layer, the second isolation layer 305 can be an Al layer, the third isolation layer 306 can be a TiN layer, and the fourth isolation layer 307 can be a SiO2 layer. It should be noted that the description of the materials used in each isolation layer is merely illustrative and the solution in this application does not impose any limitations on it.

[0044] return Figure 2 In step S204, the multilayer isolation layer can be etched to form multiple isolation regions.

[0045] refer to Figure 3dAfter forming multiple isolation layers, an etching process can be used to etch the multiple isolation layers to form multiple spaced isolation regions 308.

[0046] return Figure 2 After the isolation regions are fabricated, photodiodes with a double-layered interlaced structure can be formed in each isolation region.

[0047] Specifically, at step S205, the first interleaved structure can be formed on the insulating layer in each isolation region. The first interleaved structure includes an antimony (Sb) doped silicon material (hereinafter referred to as Si-Sb) layer and a plurality of phosphorus (P) doped silicon material (hereinafter referred to as Si-P) Si-P layers spaced apart in the Si-Sb layer.

[0048] refer to Figure 3e and Figure 3f ,like Figure 3e As shown, a first Si-Sb layer 309 can be deposited on the insulating layer 303 in each isolation region 308. Figure 3f As shown, the first Si-Sb layer 309 in each isolation region 308 can be etched to form multiple spaced grooves. Then, a first Si-P layer 310 is deposited in the multiple grooves. This completes the fabrication of the first interlaced structure. It should be noted that deposition methods can be used in the formation of both the first Si-Sb layer 309 and the first Si-P layer 310 to avoid lattice defects. It should be pointed out that this illustration uses Sb and P elements to form the Si-Sb and Si-P layers in the first interlaced structure; in practical applications, other Group VA elements can also be used to form this first interlaced structure.

[0049] return Figure 2 In step S206, an epitaxial layer can be formed above the first staggered structure of each isolation region.

[0050] refer to Figure 3g After the first interleaved structure is formed, an epitaxial layer 311 can be formed above the first interleaved structure in each isolation region. The epitaxial layer 311 can be formed using a silicon material doped with arsenic (As) (hereinafter referred to as Si-As) layer or other Group VA elements. This epitaxial layer 311 is provided to facilitate the subsequent formation of the second interleaved structure.

[0051] return Figure 2 In step S207, a second interleaved structure can be formed on the epitaxial layer in each isolation region. The first and second interleaved structures include a Si-Sb layer and a plurality of Si-P layers spaced apart in the Si-Sb layer.

[0052] refer to Figure 3h After forming the epitaxial layer 311, a second interleaved structure can be formed on the epitaxial layer 311 in each isolation region. Specifically, a second Si-Sb layer 312 can be deposited on the epitaxial layer 311 in each isolation region. Next, the second Si-Sb layer 312 in each isolation region can be etched to form multiple spaced grooves. Then, a second Si-P layer 313 is deposited in the multiple grooves. This completes the fabrication of the second interleaved structure. Both the second Si-Sb layer 312 and the second Si-P layer 313 can be formed using deposition methods to avoid lattice defects. It should be noted that this explanation uses Sb and P elements to form the Si-Sb and Si-P layers in the second interleaved structure as an example; in practical applications, other Group VA elements can also be used to form this first interleaved structure.

[0053] After the photodiodes are fabricated, a filter structure can be formed above the photodiodes in each isolation region. This filter structure may include a light-blocking region and a light-shielding sheet located within the light-blocking region.

[0054] Specifically, in step S208, multiple light-blocking layers can be formed above the photodiodes in each isolation region.

[0055] In some embodiments, the multilayer light-blocking layer may include a first light-blocking layer, a second light-blocking layer, and a third light-blocking layer. (See reference) Figure 3i After the photodiode is fabricated, a first light-blocking layer 314, a second light-blocking layer 315, and a third light-blocking layer 316 can be sequentially formed on top of the photodiode in each isolation region using a deposition process. The first light-blocking layer 314, the second light-blocking layer 315, and the third light-blocking layer 316 can all be formed by deposition, which effectively avoids lattice defects. In some embodiments, the first light-blocking layer can be made of tantalum oxide (Ta2O5), the second light-blocking layer 315 can be made of aluminum (Al), and the third light-blocking layer 316 can be made of titanium nitride (TiN). It should be noted that the description of the materials used for each light-blocking layer is merely illustrative, and the solution in this application is not limited thereto.

[0056] return Figure 2 In step S209, the aforementioned multi-layer light-blocking layer is etched to form spaced light-blocking areas.

[0057] refer to Figure 3j After forming multiple light-blocking layers (such as three light-blocking layers), an etching process can be used to etch the multiple light-blocking layers to form multiple spaced light-blocking areas 317.

[0058] return Figure 2 In step S210, a light-shielding sheet can be provided in each light-shielding area.

[0059] refer to Figure 3k After establishing the spaced-out shading zones, a shading sheet can be installed in each shading zone. For example... Figure 3k As shown, a first light-blocking plate 318, a second light-blocking plate 319, and a third light-blocking plate 320 of different colors can be set. This completes the fabrication of the image sensor.

[0060] An unexpected and beneficial technical effect of this application is that an insulating layer can be formed on a substrate, and after planarization of the substrate, the insulating layer is exposed. Then, multiple spaced isolation regions are formed on the exposed insulating layer, and a photodiode with a double-layered interlaced structure is formed within each isolation region. These photodiodes specifically include an epitaxial layer and a first interlaced structure and a second interlaced structure composed of a Si-Sb layer and multiple Si-P layers spaced apart within the Si-Sb layer. This double-layered interlaced structure facilitates the generation of more ions. The generation of more ions results in higher quantum efficiency, and higher quantum efficiency indicates a higher photoelectric conversion capability of the fabricated image sensor, higher photosensitivity, and more information provided by the image. This effectively improves the performance of the image sensor. Furthermore, the effective isolation of each fabricated photodiode by the isolation regions allows light incident on the image sensor to converge to the center of the photodiode region, thus reducing crosstalk. In addition, the use of deposition techniques to form multiple layers of isolation layers, individual layers within the photodiodes, and multiple light-blocking layers avoids lattice defects.

[0061] The present application also proposes an image sensor, comprising: a substrate having a shallow trench isolation structure formed thereon, an insulating layer formed above the shallow trench isolation structure; a plurality of photodiodes having a double-layered interleaved structure, wherein each photodiode is located in a plurality of spaced-apart isolation regions of the insulating layer, and each photodiode includes a first interleaved structure containing a group VA element, an epitaxial layer, and a second interleaved structure; and a filter structure located above the photodiodes in each isolation region.

[0062] Furthermore, the first interleaved structure is located on the insulating layer in each isolation region, the epitaxial layer is located above the first interleaved structure in each isolation region, and the second interleaved structure is located above the epitaxial layer in each isolation region. The first interleaved structure and the second interleaved structure include a Si-Sb layer and a plurality of Si-P layers spaced apart in the Si-Sb layer.

[0063] The structure of the image sensor includes, as follows: Figure 3kThe structures shown are the same, similar, or nearly identical. In practical applications, specific methods can be adopted as described above. Figures 1-3k The described fabrication method is used to fabricate the image sensor described above. It should be noted that the fabrication method for the image sensor having the above structure is not limited to... Figures 1-3k The fabrication method described can also be adapted to specific fabrication methods to obtain image sensors with the above-described structure, depending on actual application and design requirements.

[0064] In addition, adopting such Figure 1 or Figure 2 The image sensor fabricated by the described method, or an image sensor having the above structure, can be applied to various electronic devices. The specific category of electronic device is not limited here; it can include any device with image processing requirements.

[0065] It should be noted that although the operations of the method of this application are described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. On the contrary, the steps depicted in the flowchart can be performed in a different order. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0066] While numerous embodiments of this application have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many modifications, alterations, and alternatives will arise for those skilled in the art without departing from the spirit and intent of this application. It should be understood that various alternatives to the embodiments of this application described herein may be employed in the practice of this application. The appended claims are intended to define the scope of protection of this application and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A method for fabricating an image sensor, characterized in that, include: Provide a substrate having a shallow trench isolation structure; An insulating layer is formed above the shallow trench isolation structure; Multiple spaced isolation regions are formed on the insulating layer. Specifically, the substrate located on the back side of the insulating layer is planarized, and multiple isolation layers are sequentially deposited on the insulating layer. The multiple isolation layers are etched to form the multiple isolation regions. A photodiode with a double-layered interlaced structure is formed in each of the isolation regions, wherein the double-layered interlaced photodiode includes a first interlaced structure containing a group VA element, an epitaxial layer, and a second interlaced structure. as well as A filter structure is formed above the photodiode in each of the isolation regions; The photodiode having a double-layered interlaced structure in each of the isolation regions includes: The first interlaced structure is formed on the insulating layer in each of the isolated regions; The epitaxial layer is formed above the first staggered structure of each of the isolation regions; and The second interleaved structure is formed on the epitaxial layer in each of the isolation regions, wherein the first interleaved structure and the second interleaved structure include a Si-Sb layer and a plurality of Si-P layers spaced apart in the Si-Sb layer, and the bottom surface of the Si-P layer in the second interleaved structure is flush with the top surface of the epitaxial layer.

2. The method for fabricating an image sensor according to claim 1, characterized in that, The epitaxial layer includes a Si-As layer, and the first interlaced structure and the second interlaced structure are prepared by the following steps: A Si-Sb layer is deposited on the insulating layer and the Si-As layer in each of the isolation regions; The Si-Sb layer in each of the isolation regions is etched to form multiple grooves spaced apart. Si-P layers are deposited in the plurality of grooves.

3. The method for fabricating an image sensor according to claim 1, characterized in that, The sequential deposition of multiple insulating layers on the insulating layer includes: A first isolation layer, a second isolation layer, a third isolation layer, and a fourth isolation layer are sequentially formed on top of the insulating layer using a deposition process.

4. The method for fabricating an image sensor according to claim 1, characterized in that, Forming a filter structure above the photodiode in each of the isolation regions includes: Multiple light-blocking layers are formed above the photodiodes in each of the isolation regions; The multi-layer light-blocking layer is etched to form spaced light-blocking areas; A light-shielding sheet is provided in each of the aforementioned light-shielding areas.

5. The method for fabricating an image sensor according to claim 4, characterized in that, Depositing multiple light-blocking layers over the photodiode in each of the isolation regions includes: A first light-blocking layer, a second light-blocking layer, and a third light-blocking layer are sequentially formed above the photodiode in each of the isolation regions using a deposition process.

6. An image sensor, characterized in that, include: A substrate, wherein a shallow trench isolation structure is formed on the substrate, and an insulating layer is formed above the shallow trench isolation structure; Multiple photodiodes with a double-layered interleaved structure are provided, wherein each photodiode is located in multiple spaced-apart isolation regions of the insulating layer, and each photodiode includes a first interleaved structure containing a Group VA element, an epitaxial layer, and a second interleaved structure, wherein the first interleaved structure is located on the insulating layer in each isolation region, the epitaxial layer is located above the first interleaved structure in each isolation region, and the second interleaved structure is located above the epitaxial layer in each isolation region. The first interleaved structure and the second interleaved structure include a Si-Sb layer and multiple Si-P layers spaced apart in the Si-Sb layer, and the bottom surface of the Si-P layer in the second interleaved structure is flush with the top surface of the epitaxial layer. as well as A filter structure is located above the photodiode in each of the isolation regions.

7. An electronic device, characterized in that, include: An image sensor prepared by the method of any one of claims 1 to 5; or The image sensor as described in claim 6.

Images