Quantum bit state readout circuit and quantum computing system

Abstract

The application provides a quantum bit state reading circuit and a quantum computing system. The quantum bit state reading circuit comprises a low noise amplifier for receiving a multi-tone reflection signal of a quantum bit state reading resonant cavity and amplifying the multi-tone reflection signal; a first local oscillator generator for generating a first quadrature local oscillator signal required for first down-conversion of the multi-tone reflection signal; a first frequency mixer for receiving the amplified multi-tone reflection signal output by the low noise amplifier and performing first down-conversion operation on the amplified multi-tone reflection signal under the control of the first quadrature local oscillator signal to generate a first down-converted signal; a sampling clock generator for receiving a radio frequency local oscillator signal output by the first local oscillator generator and performing frequency division operation on the radio frequency local oscillator signal to generate a sampling clock signal; and a plurality of bit state detection links for ultimately obtaining state information of a plurality of quantum bits by using a multi-channel frequency division multiplexing technology based on the first down-converted signal and the sampling clock signal.

Description

Technical Field

[0001] This application relates to the fields of quantum computing and integrated circuit technology, and in particular to a quantum bit state readout circuit and a quantum computing system. Background Technology

[0002] A qubit is the fundamental unit of quantum computing. The biggest challenge facing large-scale quantum computing is further increasing the number of integrated qubits and reducing the size of the quantum computing platform. Currently, qubits in quantum computing platforms need to operate in ultra-low temperature environments, while the bulky qubit state control and readout devices need to operate at room temperature. Therefore, cross-temperature interconnects are required between the qubits and the qubit state control and readout devices to ensure their proper functioning. This further increases the space occupied by the quantum computing platform. Summary of the Invention

[0003] The purpose of this application is to provide a quantum bit state readout circuit and a quantum computing system that can solve at least one of the technical problems mentioned in the prior art.

[0004] One aspect of this application provides a quantum bit state readout circuit. The quantum bit state readout circuit includes a low-noise amplifier, a first local oscillator generator, a first mixer, a sampling clock generator, and multiple bit state detection links. The low-noise amplifier is used to receive the multi-tone reflection signal reflected from the multi-tone excitation signal via the quantum bit state readout resonant cavity, and amplify the multi-tone reflection signal; the first local oscillator generator is used to generate the first quadrature local oscillator signal required for the first down-conversion of the multi-tone reflection signal; the first mixer is connected to the low-noise amplifier and the first local oscillator generator, and is used to receive the amplified multi-tone reflection signal output by the low-noise amplifier, and under the control of the first quadrature local oscillator signal, perform the first down-conversion operation on the amplified multi-tone reflection signal to generate the first down-conversion signal; the sampling clock generator is connected to the first local oscillator generator, and is used to receive the radio frequency local oscillator signal output by the first local oscillator generator, and perform a frequency division operation on the radio frequency local oscillator signal to generate a sampling clock signal; the multiple bit state detection links are all connected to the first mixer and the sampling clock generator, and are used to ultimately obtain the state information of multiple quantum bits based on the first down-conversion signal and the sampling clock signal by using multi-channel frequency division multiplexing technology.

[0005] Furthermore, the multiple bit state detection links share a single FIR filter, and each bit state detection link includes a second local oscillator generator, a second mixer, a low-pass voltage-frequency conversion circuit, and a quantum bit state detector. The second local oscillator generator in each link generates a second quadrature local oscillator signal required for a second down-conversion of the first down-converted signal. The second mixer in each link is connected to the first mixer and the corresponding link's second local oscillator generator, and is used to perform a second down-conversion operation on the first down-converted signal under the control of the second quadrature local oscillator signal, generating a second down-converted signal. The FIR filter is connected to the sampling clock generator and the second mixer in each link, respectively, and is used to perform narrowband high-order filtering on the second down-converted signal under the control of the sampling clock signal, and output a low-pass filtered signal corresponding to the qubit of each link; the low-pass voltage-frequency conversion circuit in each link is used to receive the low-pass filtered signal of the corresponding link output by the FIR filter, and convert the low-pass filtered signal from the voltage domain to the frequency domain; the qubit state detector in each link is used to receive the frequency domain signal output by the low-pass voltage-frequency conversion circuit, and detect the qubit state of the link based on the frequency domain signal.

[0006] Furthermore, the frequencies of the second quadrature local oscillator signals generated by the second local oscillator generator in different bit states of the detection link are all different.

[0007] Furthermore, the frequency of the second orthogonal local oscillator signal of any link is equal to the frequency difference between the quantum bit state readout frequency of that link and the frequency of the first orthogonal local oscillator signal generated by the first local oscillator generator.

[0008] Further, the sampling clock signal includes a multi-phase sampling clock signal, and the FIR filter includes multiple tap circuits and a summer. Each tap circuit includes an input capacitor, a capacitor-to-analog converter, an output capacitor, and a transconductance amplifier. For any given link, the second down-conversion signal of that link is sequentially sampled onto the input capacitor of each tap circuit via the multi-phase sampling clock signal in chronological order. The charge stored on the input capacitor is multiplied by the corresponding tap coefficient through the capacitor-to-analog converter of the corresponding tap circuit. The output charge of the capacitor-to-analog converter of each tap circuit is stored on the output capacitor and converted into the output current of the corresponding tap circuit of that link through the transconductance amplifier of the corresponding tap circuit. The summer is used to synthesize and add the output currents of all tap circuits corresponding to each link, and output the synthesized current of each link. The low-pass filtered signal output by the FIR filter corresponding to the qubits of each link includes the synthesized current of each link output by the FIR filter.

[0009] Further, the tap circuit includes multiple input capacitors, multiple output capacitors, and multiple transconductance amplifiers corresponding to the multiple bit state detection links, wherein the number of multiple input capacitors, multiple output capacitors, and multiple transconductance amplifiers is equal to the number of multiple bit state detection links. The capacitor digital-to-analog converter includes a first capacitor digital-to-analog converter and a second capacitor digital-to-analog converter. The two ends of each input capacitor are connected to the second down-conversion signal of a link through a switch. The input terminals of the first capacitor digital-to-analog converter and the second capacitor digital-to-analog converter are respectively connected to the two ends of each input capacitor. The output terminals of the first capacitor digital-to-analog converter and the second capacitor digital-to-analog converter are respectively connected to the two ends of each output capacitor. The two ends of each output capacitor are connected to the two input terminals of a corresponding transconductance amplifier. The output terminal of each transconductance amplifier serves as the output terminal of the tap circuit corresponding to the link.

[0010] Furthermore, each of the tap circuits further includes a first driver, a second driver, a third driver, and a fourth driver. The two ends of each input capacitor are connected to the input terminals of the first capacitor-to-analog converter and the second capacitor-to-analog converter respectively through the first driver and the second driver, with the input terminal of the first driver short-circuited to its output terminal, and the input terminal of the second driver short-circuited to its output terminal. The output terminals of the first capacitor-to-analog converter and the second capacitor-to-analog converter are connected to the two ends of each output capacitor through the third driver and the fourth driver, with the input terminal of the third driver short-circuited to its output terminal, and the input terminal of the fourth driver short-circuited to its output terminal.

[0011] Furthermore, the low-noise amplifier includes a radio frequency inverter, a transformer, and an adjustable capacitor, wherein the radio frequency inverter is connected to the primary coil of the transformer, and the input terminal of the radio frequency inverter is connected to the multi-tone reflection signal; the secondary coil of the transformer is connected to the adjustable capacitor.

[0012] Furthermore, the low-pass voltage-frequency conversion circuit includes two low-pass voltage-frequency converters for the I-path and Q-path, each of which includes a first differential inverter, a second differential inverter, and a current mirror. The non-inverting input of the first differential inverter is connected to the non-inverting output of the second differential inverter; the inverting input of the first differential inverter is connected to the inverting output of the second differential inverter; the non-inverting output of the first differential inverter is connected to the inverting input of the second differential inverter; the inverting output of the first differential inverter is connected to the non-inverting input of the second differential inverter; the power supply terminals of both the first and second differential inverters are connected to a power supply voltage; the input of the current mirror is connected to the output of the FIR filter; and the first and second output terminals of the current mirror are respectively connected to the reference ground terminals of the first and second differential inverters.

[0013] Furthermore, the current mirror includes a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor, wherein the gates of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are connected together; the sources of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are all grounded; and the drains of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor serve as the input terminal, the first output terminal, and the second output terminal of the current mirror, respectively.

[0014] The quantum bit state readout circuit of this application can operate directly in an ultra-low temperature environment, and can realize the readout decision of the quantum bit state within the chip. It can minimize the number of room temperature devices and the number of interconnects across temperature zones required for quantum bit manipulation, and can effectively reduce the size of existing quantum computing systems.

[0015] Meanwhile, the qubit state readout circuit of this application can achieve simultaneous readout of multiple qubit states based on frequency division multiplexing of voltage-frequency conversion and time-domain qubit state detection, thereby shortening the qubit state readout time and reducing power consumption. The qubit state readout circuit of this application can contribute to the further development of integrated and large-scale quantum computing.

[0016] Another aspect of this application provides a quantum computing system. The quantum computing system includes an excitation signal generator, a qubit state readout resonant cavity, a qubit state readout circuit as described above, and a control terminal. The excitation signal generator is used to generate multi-tone excitation signals under the control of the control terminal; the qubit state readout resonant cavity is used to reflect the multi-tone excitation signals; the qubit state readout circuit is used to receive the multi-tone reflected signals from the qubit state readout resonant cavity, and read out the state information of multiple qubits based on the multi-tone reflected signals and output it to the control terminal.

[0017] Furthermore, the quantum computing system also includes a circulator having a first port, a second port, and a third port, wherein the output of the excitation signal generator is connected to the first port of the circulator, the qubit state readout resonant cavity is connected to the second port of the circulator, and the input of the qubit state readout circuit is connected to the third port of the circulator. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the circuit structure of a quantum computing system and a quantum bit state readout circuit according to an embodiment of this application.

[0019] Figure 2 This is a schematic diagram of the quantum bit state readout process of a quantum bit state readout circuit according to an embodiment of this application.

[0020] Figure 3 This is a schematic diagram of the circuit structure of a low-noise amplifier according to an embodiment of this application.

[0021] Figure 4 This is a schematic diagram of the circuit structure of an FIR filter according to an embodiment of this application.

[0022] Figure 5 This is a schematic diagram of the circuit structure of a low-pass voltage frequency converter according to an embodiment of this application. Detailed Implementation

[0023] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses consistent with some aspects of this application as detailed in the appended claims.

[0024] The quantum bit state readout circuit and quantum computing system of this application will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the features of the following embodiments and implementations can be combined with each other.

[0025] Figure 1 A schematic diagram of the circuit structure of a quantum computing system 200 and a quantum bit state readout circuit 100 according to an embodiment of this application is shown. Figure 1 As shown, a quantum computing system 200 according to one embodiment of this application includes an excitation signal generator 210, a quantum bit state readout resonant cavity 220, a quantum bit state readout circuit 100, and a control terminal 230.

[0026] The quantum bit state readout circuit 100 of this application can operate directly in an ultra-low temperature environment. The quantum bit state readout circuit 100 is connected to the excitation signal generator 210, the quantum bit state readout resonant cavity 220 and the control terminal 230 respectively. Under the control of the control terminal 230, the quantum bit state readout circuit 100 can realize the effective readout operation of multiple quantum bit states.

[0027] In some embodiments, the quantum computing system 200 of this application may further include a circulator 240. The qubit state readout circuit 100 is connected to the excitation signal generator 210 and the qubit state readout resonant cavity 220 respectively through the circulator 240. The circulator 240 can serve as an isolation device.

[0028] Specifically, the circulator 240 has a first port, a second port, and a third port. The output of the excitation signal generator 210 is connected to the first port of the circulator 240, the qubit state readout resonant cavity 220 is connected to the second port of the circulator 240, and the input of the qubit state readout circuit 100 is connected to the third port of the circulator 240.

[0029] The excitation signal generator 210 can generate an excitation signal under the control of the control terminal 230. Since the readout signal frequencies of different qubits are different, the excitation signal is a multi-tone excitation signal. Figure 2 A schematic diagram illustrating the quantum bit state readout process of a quantum bit state readout circuit 100 according to an embodiment of this application is shown. Figure 2 As shown, used for qubits <0> The frequency of the excitation signal read out is f q,<0> Used for qubits <n>The frequency of the excitation signal read out is f q, <n>< / n> .

[0030] The qubit state readout resonant cavity 220 is used to reflect the multi-tone excitation signal. The qubit state readout circuit 100 can receive the excitation signal reflected by the qubit state readout resonant cavity 220, i.e., the multi-tone reflection signal, and read out the state information of multiple qubits based on the multi-tone reflection signal and output it to the control terminal 230.

[0031] Because the different states of the qubits affect the reflection coefficient of the qubit state readout resonant cavity 220, the amplitude and phase characteristics of the reflected signal are changed. The state of the qubits can be detected by detecting the amplitude and phase characteristics of the reflected signal.

[0032] like Figure 1 As shown, the quantum bit state readout circuit 100 of this application includes a low-noise amplifier 110, a first local oscillator generator 120, a first mixer 130, a sampling clock generator 140, and multiple bit state detection links 150.

[0033] The low-noise amplifier 110 can receive the multi-tone reflection signal reflected by the multi-tone excitation signal via the quantum bit state readout resonant cavity 220, and amplify the multi-tone reflection signal.

[0034] The first local oscillator generator 120 can generate the first quadrature local oscillator signal required for the first down-conversion of the multi-tone reflection signal. The first local oscillator generator 120 is usually an on-chip phase-locked loop circuit.

[0035] The first mixer 130 is connected to the low-noise amplifier 110 and the first local oscillator generator 120. The first mixer 130 receives the amplified multi-tone reflection signal output from the low-noise amplifier 110 and, under the control of the first quadrature local oscillator signal, performs a first down-conversion operation on the amplified multi-tone reflection signal to generate a first down-converted signal. The frequency of the first quadrature local oscillator signal is... f LO The frequency of the first orthogonal local oscillator signal f LO Typically 6-7 GHz, with a default of 6.5 GHz, and below the quantum bit state readout signal frequency of approximately 200 MHz. The frequency range of the first down-conversion signal is, for example, 200-300 MHz.

[0036] The sampling clock generator 140 is connected to the first local oscillator generator 120. The sampling clock generator 140 can receive the radio frequency local oscillator signal output by the first local oscillator generator 120 and perform frequency division operation on the radio frequency local oscillator signal to generate a sampling clock signal.

[0037] Multiple bit state detection links 150 are all connected to the first mixer 130 and the sampling clock generator 140. The multiple bit state detection links 150 can ultimately obtain the state information of multiple qubits based on the first down-converted signal and the sampling clock signal by using multi-channel frequency division multiplexing technology.

[0038] In some embodiments, multiple bit state detection links 150 share a single FIR filter 153, and each bit state detection link 150 includes a second local oscillator generator 151, a second mixer 152, a low-pass voltage frequency conversion circuit, and a quantum bit state detector 155.

[0039] The bit state detection link 150 can perform further operations on the first down-converted signal, such as down-conversion, low-pass filtering, voltage-frequency domain conversion, and bit state detection operations, ultimately obtaining the state information of the qubit. The bit state detection link 150 features multi-channel frequency division multiplexing, enabling simultaneous readout of multiple qubit states. This supports scalable quantum computing systems, improves integration, and reduces power consumption. In the qubit state readout circuit 100 of this application, the bit state detection link 150 adopts an array layout, and the number of bit state detection links 150 (i.e., the number of channels) is consistent with the number of qubits in the quantum computing system 200.

[0040] The second local oscillator generator 151 in each link can generate the second quadrature local oscillator signal required for the second down-conversion of the first down-converted signal. The second local oscillator generator 151 is typically an on-chip phase-locked loop circuit.

[0041] The second mixer 152 in each link is connected to the first mixer 130 and the second local oscillator generator 151 of the corresponding link. Under the control of the second quadrature local oscillator signal, the second mixer 152 can perform a second down-conversion operation on the first down-converted signal to generate a second down-converted signal. The second mixer 152 can be, for example, a double-balanced Gilbert mixer.

[0042] The second orthogonal local oscillator signal generated by the second local oscillator generator 151 in the detection link 150 at different bit states has a different frequency, realizing down-conversion of the reflected signals of different qubits and achieving the purpose of frequency division multiplexing for multi-bit readout. The frequency of the second orthogonal local oscillator signal of any link is equal to the frequency difference between the qubit state readout frequency of that link and the frequency of the first orthogonal local oscillator signal generated by the first local oscillator generator 120. Figure 2 As shown, the first <0> The frequency of the second orthogonal local oscillator signal of the channel is f IF,<0> This frequency is the same as the corresponding qubit state readout frequency (i.e., the frequency used for qubits). <0> Read excitation signal frequency f q,<0> The frequency of the first orthogonal local oscillator signal and the frequency of the first orthogonal local oscillator signal f LO The frequency difference is equal, that is, it satisfies This causes the second down-conversion signal to be converted into a low-frequency DC signal. f BB,<0> Similarly, the first <n>The frequency of the second orthogonal local oscillator signal of the channel is f IF, <n>< / n> This frequency is the same as the corresponding qubit state readout frequency (i.e., the frequency used for qubits). <n>Read excitation signal frequency f q, <n>< / n> The frequency of the first orthogonal local oscillator signal and the frequency of the first orthogonal local oscill f LO The frequency difference is equal, that is, it satisfies This causes the second down-conversion signal to be converted into a low-frequency DC signal. f BB, <n>< / n> .

[0043] Since the second mixer 152 does not have ultra-narrow bandwidth filtering characteristics, the second down-converted signal still contains reflected signals from other qubits. To avoid interference, it is necessary to perform low-pass filtering to suppress the interference signals.

[0044] The FIR filter 153 is connected to the sampling clock generator 140 and the second mixer 152 in each link. Under the control of the sampling clock signal, the FIR filter 153 can realize high-order low-pass filtering characteristics, perform narrowband high-order filtering on the second down-converted signal, suppress out-of-band signals, and output low-pass filtered signals corresponding to the quantum bits of each link.

[0045] The low-pass voltage-frequency conversion circuit in each link is used to receive the low-pass filtered signal of the corresponding link output by the FIR filter 153, and to convert the low-pass filtered signal from the voltage domain to the frequency domain.

[0046] Each qubit state detector 155 in each link receives the frequency domain signal output from the low-pass voltage-frequency conversion circuit and detects the qubit state of its current link based on the frequency domain signal. Within a specific readout time, the qubit state detector 155 integrates and counts the frequency domain signal to obtain count values ​​representing the I / Q signal amplitude, i.e., it obtains constellation points representing the qubit state, such as... Figure 2 As shown. Within the I / Q counting plane, by selecting an appropriate decision threshold (i.e. Figure 2 The bit state detection threshold shown is used to determine the state of the qubit based on the distribution of the |1>, |0> state point set of the qubit. Finally, the qubit state is output to the control terminal 230 of the quantum computing system 200 to complete one state readout operation.

[0047] Figure 3 A schematic diagram of the circuit structure of a low-noise amplifier 110 according to an embodiment of this application is shown. Figure 3 As shown, in some embodiments, the low-noise amplifier 110 of this application includes a radio frequency inverter INV, a transformer T, and an adjustable capacitor Cx. The radio frequency inverter INV is connected to the primary coil of the transformer T, and the input terminal of the radio frequency inverter INV is connected to a multi-tone reflection signal LNA_IN; the secondary coil of the transformer T is connected to the adjustable capacitor Cx. The two ends of the adjustable capacitor Cx are the output terminals OUTP and OUTN of the low-noise amplifier 110.

[0048] The RF inverter INV enables a wide input frequency range while inverting the signal. By applying both forward and inverted signals to the primary winding of transformer T, noise cancellation is achieved. Simultaneously, an adjustable capacitor Cx is connected to the secondary winding of transformer T; adjusting the value of Cx allows for input matching. The advantages of this low-noise amplifier 110 are its extremely low noise figure (<1dB), easy input impedance matching, and simple structure, making it easy to design.

[0049] Figure 4 A schematic diagram of the circuit structure of an FIR filter 153 according to an embodiment of this application is shown. Figure 4 As shown, in some embodiments, the FIR filter 153 of this application includes multiple tap circuits 1530 and a summer (not shown). Accordingly, the sampling clock signal includes a multi-phase sampling clock signal. The frequency of the sampling clock signal is, for example, 100MHz. In the embodiment illustrated in this application, the FIR filter 153 includes 18 tap circuits 1530. Since the FIR filter 153 has 18 taps, the multi-phase sampling clock signal is an 18-phase non-overlapping sampling clock signal.

[0050] Each tap circuit 1530 includes an input capacitor C1, a capacitor-to-analog converter CDAC, an output capacitor C2, and a transconductance amplifier Gm.

[0051] For any given link, the second down-conversion signal of that link is sampled sequentially onto the input capacitor C1 of each tap circuit 1530 via a multi-phase sampling clock signal. The link implements an analog multiplier through a capacitor digital-to-analog converter (CDAC). The charge stored on the input capacitor C1 is multiplied by the corresponding tap coefficient through the capacitor digital-to-analog converter (CDAC) of the corresponding tap circuit 1530. The output charge of the capacitor digital-to-analog converter (CDAC) of each tap circuit 1530 is stored on the output capacitor C2 and converted into the output current Iout of the corresponding tap circuit 1530 through the transconductance amplifier Gm of the corresponding tap circuit 1530.

[0052] The summer can be used to combine the output currents Iout of all tap circuits 1530 corresponding to each link, and output the combined current Isum of each link to the subsequent low-pass voltage-frequency conversion circuit. The low-pass filtered signal output by the FIR filter 153, corresponding to the qubits of each link, includes the combined current Isum of each link output by the FIR filter 153.

[0053] like Figure 4 As shown, each tap circuit 1530 includes multiple input capacitors C1, multiple output capacitors C2, and multiple transconductance amplifiers Gm, each corresponding to a plurality of bit state detection links 150. The number of input capacitors C1, output capacitors C2, and transconductance amplifiers Gm is equal to the number of bit state detection links 150. It should be noted that... Figure 4 Only the input capacitor C1, output capacitor C2, and transconductance amplifier Gm corresponding to a single bit state detection link 150 (i.e., one channel) are shown.

[0054] The capacitor digital-to-analog converter (CDAC) includes a first capacitor digital-to-analog converter (CDAC1) and a second capacitor digital-to-analog converter (CDAC2).

[0055] Each input capacitor C1 is connected to the second down-conversion signal of a link via switch Φ1; the input terminals of the first capacitor digital-to-analog converter CDAC1 and the second capacitor digital-to-analog converter CDAC2 are respectively connected to the two ends of each input capacitor C1; the output terminals of the first capacitor digital-to-analog converter CDAC1 and the second capacitor digital-to-analog converter CDAC2 are respectively connected to the two ends of each output capacitor C2; the two ends of each output capacitor C2 are connected to the two input terminals of a corresponding transconductance amplifier Gm, and the output terminal of each transconductance amplifier Gm serves as the output terminal of the tap circuit 1530 corresponding to the link.

[0056] In some embodiments, each tap circuit 1530 further includes a first driver D1, a second driver D2, a third driver D3, and a fourth driver D4.

[0057] Each input capacitor C1 has its two ends connected to the input terminals of the first capacitor digital-to-analog converter CDAC1 and the second capacitor digital-to-analog converter CDAC2 via the first driver D1 and the second driver D2, respectively. The input terminal of the first driver D1 is short-circuited to the output terminal, and the input terminal of the second driver D2 is short-circuited to the output terminal.

[0058] The output terminals of the first capacitor digital-to-analog converter CDAC1 and the second capacitor digital-to-analog converter CDAC2 are connected to the two ends of each output capacitor C2 through the third driver D3 and the fourth driver D4, respectively. The input terminal of the third driver D3 is shorted to the output terminal, and the input terminal of the fourth driver D4 is shorted to the output terminal.

[0059] Return to reference Figure 1 In some embodiments, the low-pass voltage-frequency conversion circuit includes two low-pass voltage-frequency converters 154 for the I-path and Q-path. Figure 5 A schematic diagram of the circuit structure of a low-pass voltage-frequency converter 154 according to an embodiment of this application is shown. Figure 5 As shown, each low-pass voltage-frequency converter 154 includes a first differential inverter AMP1, a second differential inverter AMP2, and a current mirror 1540.

[0060] The non-inverting input terminal INP of the first differential inverter AMP1 is connected to the non-inverting output terminal OP of the second differential inverter AMP2; the inverting input terminal INN of the first differential inverter AMP1 is connected to the inverting output terminal ON of the second differential inverter AMP2; the non-inverting output terminal OP of the first differential inverter AMP1 is connected to the inverting input terminal INN of the second differential inverter AMP2; the inverting output terminal ON of the first differential inverter AMP1 is connected to the non-inverting input terminal INP of the second differential inverter AMP2; the power supply terminals of the first differential inverter AMP1 and the second differential inverter AMP2 are both connected to the power supply voltage VDD.

[0061] The input terminal of the current mirror 1540 is connected to the output terminal of the FIR filter 153 to receive the synthesized current Isum output by the FIR filter 153. The first and second output terminals of the current mirror 1540 are respectively connected to the reference ground terminals of the first differential inverter AMP1 and the second differential inverter AMP2.

[0062] In some embodiments, the current mirror 1540 may include a first NMOS transistor M1, a second NMOS transistor M2, and a third NMOS transistor M3.

[0063] The gates of the first NMOS transistor M1, the second NMOS transistor M2, and the third NMOS transistor M3 are connected together; the sources of the first NMOS transistor M1, the second NMOS transistor M2, and the third NMOS transistor M3 are all grounded; the drains of the first NMOS transistor M1, the second NMOS transistor M2, and the third NMOS transistor M3 serve as the input terminal, the first output terminal, and the second output terminal of the current mirror 1540, respectively.

[0064] The low-pass voltage-to-frequency converter 154 of this application is based on a two-stage differential ring oscillator. The synthesized current Isum output from the pre-stage FIR filter 153 is directly injected into the current mirror 1540. By properly designing the ratio of the current mirror 1540, a current-to-frequency conversion accuracy of 12 bits can be achieved. The frequency of the ring oscillator is positively correlated with the amplitude of the input signal (i.e., the injected synthesized current Isum). The larger the signal amplitude (i.e., the injected synthesized current Isum), the higher the oscillator frequency.

[0065] The quantum bit state readout circuit 100 of this application can operate directly in an ultra-low temperature environment, and can realize the readout decision of the quantum bit state within the chip. It can minimize the number of room temperature devices and the number of interconnects across temperature zones required for quantum bit manipulation, and can effectively reduce the size of the existing quantum computing system 200.

[0066] Meanwhile, the qubit state readout circuit 100 of this application can achieve simultaneous readout of multiple qubit states based on frequency division multiplexing of voltage-frequency conversion and time-domain qubit state detection, thereby shortening the qubit state readout time and reducing power consumption. The qubit state readout circuit 100 of this application can contribute to the further development of integrated and large-scale quantum computing.

[0067] The qubit state readout circuit and quantum computing system provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the qubit state readout circuit and quantum computing system of this application. The descriptions of the embodiments above are only for helping to understand the core ideas of this application and are not intended to limit this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the spirit and principles of this application, and all such improvements and modifications should fall within the protection scope of the appended claims.< / n> < / n> < / n>

Claims

1. A quantum bit state readout circuit, characterized in that, It includes a low-noise amplifier, a first local oscillator generator, a first mixer, a sampling clock generator, and multiple bit state detection links, among which, The low-noise amplifier is used to receive the multi-tone reflection signal reflected by the multi-tone excitation signal through the quantum bit state readout resonant cavity, and to amplify the multi-tone reflection signal; The first local oscillator generator is used to generate the first quadrature local oscillator signal required for the first down-conversion of the multi-tone reflection signal; The first mixer is connected to the low-noise amplifier and the first local oscillator generator, and is used to receive the amplified multi-tone reflection signal output by the low-noise amplifier, and under the control of the first quadrature local oscillator signal, perform the first down-conversion operation on the amplified multi-tone reflection signal to generate the first down-conversion signal. The sampling clock generator is connected to the first local oscillator generator and is used to receive the radio frequency local oscillator signal output by the first local oscillator generator and perform frequency division operation on the radio frequency local oscillator signal to generate a sampling clock signal. The multiple bit state detection links are all connected to the first mixer and the sampling clock generator, and are used to obtain the state information of multiple qubits based on the first down-conversion signal and the sampling clock signal by using multi-channel frequency division multiplexing technology.

2. The quantum bit state readout circuit as described in claim 1, characterized in that, The multiple bit state detection links share a single FIR filter, and each bit state detection link includes a second local oscillator generator, a second mixer, a low-pass voltage-frequency conversion circuit, and a quantum bit state detector. The second local oscillator generator in each link is used to generate the second quadrature local oscillator signal required for the second down-conversion of the first down-converted signal; The second mixer in each link is connected to the first mixer and the second local oscillator generator of the corresponding link, and is used to perform a second down-conversion operation on the first down-converted signal under the control of the second quadrature local oscillator signal to generate a second down-converted signal; The FIR filter is connected to the sampling clock generator and the second mixer in each link, respectively, and is used to perform narrowband high-order filtering on the second down-converted signal under the control of the sampling clock signal, and output a low-pass filter signal corresponding to each link quantum bit; The low-pass voltage-frequency conversion circuit in each link is used to receive the low-pass filtered signal of the corresponding link output by the FIR filter, and to convert the low-pass filtered signal from the voltage domain to the frequency domain. The qubit state detector in each link is used to receive the frequency domain signal output by the low-pass voltage frequency conversion circuit, and detect the qubit state of the link based on the frequency domain signal.

3. The quantum bit state readout circuit as described in claim 2, characterized in that, The frequencies of the second quadrature local oscillator signals generated by the second local oscillator generator in different bit states of the detection link are different.

4. The quantum bit state readout circuit as described in claim 3, characterized in that, The frequency of the second orthogonal local oscillator signal of any link is equal to the frequency difference between the quantum bit state readout frequency of that link and the frequency of the first orthogonal local oscillator signal generated by the first local oscillator generator.

5. The quantum bit state readout circuit as described in any one of claims 2 to 4, characterized in that, The sampling clock signal includes a multi-phase sampling clock signal, and the FIR filter includes multiple tap circuits and a summer. Each tap circuit includes an input capacitor, a capacitor-to-analog converter, an output capacitor, and a transconductance amplifier. For any given link, the second down-conversion signal of that link is sampled sequentially onto the input capacitor of each tap circuit through the multi-phase sampling clock signal in chronological order. The charge stored on the input capacitor is multiplied by the corresponding tap coefficient through the capacitor digital-to-analog converter of the corresponding tap circuit. The output charge of the capacitor digital-to-analog converter of each tap circuit is stored on the output capacitor and converted into the output current of the corresponding tap circuit of that link through the transconductance amplifier of the corresponding tap circuit. The summer is used to combine and add the output currents of all tap circuits corresponding to each link, and output the combined current of each link. The low-pass filtered signal output by the FIR filter, corresponding to each link qubit, includes the synthesized current of each link output by the FIR filter.

6. The quantum bit state readout circuit as described in claim 5, characterized in that, The tap circuit includes multiple input capacitors, multiple output capacitors, and multiple transconductance amplifiers, each corresponding to one of the multiple bit state detection links. The number of input capacitors, output capacitors, and transconductance amplifiers is equal to the number of the multiple bit state detection links. The capacitor-to-analog converter includes a first capacitor-to-analog converter and a second capacitor-to-analog converter. Each of the input capacitors is connected across its terminals to the second down-conversion signal of a link via a switch; The input terminals of the first capacitor-to-digital converter and the second capacitor-to-digital converter are respectively connected to the two ends of each input capacitor; The output terminals of the first capacitor digital-to-analog converter and the second capacitor digital-to-analog converter are respectively connected to the two ends of each output capacitor; Each of the output capacitors is connected to the two input terminals of a corresponding transconductance amplifier, and the output terminal of each transconductance amplifier serves as the output terminal of the tap circuit corresponding to the link.

7. The quantum bit state readout circuit as described in claim 6, characterized in that, Each of the aforementioned tap circuits further includes a first driver, a second driver, a third driver, and a fourth driver, wherein, Each input capacitor has its two ends connected to the input terminals of the first capacitor digital-to-analog converter and the second capacitor digital-to-analog converter respectively through the first driver and the second driver, and the input terminal of the first driver is short-circuited to the output terminal, and the input terminal of the second driver is short-circuited to the output terminal. The output terminals of the first capacitor digital-to-analog converter and the second capacitor digital-to-analog converter are respectively connected to the two ends of each output capacitor through the third driver and the fourth driver, and the input terminal of the third driver is short-circuited to the output terminal, and the input terminal of the fourth driver is short-circuited to the output terminal.

8. The quantum bit state readout circuit as described in any one of claims 1 to 4, characterized in that, The low-noise amplifier includes an RF inverter, a transformer, and an adjustable capacitor, wherein... The radio frequency inverter is connected to the primary coil of the transformer, and the input terminal of the radio frequency inverter is connected to the multi-tone reflection signal; The secondary coil of the transformer is connected to the adjustable capacitor.

9. The quantum bit state readout circuit as described in any one of claims 2 to 4, characterized in that, The low-pass voltage-frequency conversion circuit includes two low-pass voltage-frequency converters for the I-path and Q-path, each of which includes a first differential inverter, a second differential inverter, and a current mirror. The non-inverting input terminal of the first differential inverter is connected to the non-inverting output terminal of the second differential inverter; the inverting input terminal of the first differential inverter is connected to the inverting output terminal of the second differential inverter; the non-inverting output terminal of the first differential inverter is connected to the inverting input terminal of the second differential inverter; the inverting output terminal of the first differential inverter is connected to the non-inverting input terminal of the second differential inverter; both the power supply terminals of the first and second differential inverters are connected to a power supply voltage. The input terminal of the current mirror is connected to the output terminal of the FIR filter, and the first and second output terminals of the current mirror are respectively connected to the reference ground terminals of the first differential inverter and the second differential inverter.

10. The quantum bit state readout circuit as described in claim 9, characterized in that, The current mirror includes a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor, wherein... The gates of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are connected together; the sources of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are all grounded; the drains of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor serve as the input terminal, the first output terminal, and the second output terminal of the current mirror, respectively.

11. A quantum computing system, characterized in that, It includes an excitation signal generator, a qubit state readout resonant cavity, a qubit state readout circuit as described in any one of claims 1 to 10, and a control terminal, wherein, The excitation signal generator is used to generate multi-tone excitation signals under the control of the control terminal; The quantum bit state readout resonant cavity is used to reflect the multi-tone excitation signal; The quantum bit state readout circuit is used to receive the multi-tone reflection signal of the quantum bit state readout resonant cavity, and read out the state information of multiple quantum bits based on the multi-tone reflection signal and output it to the control terminal.

12. The quantum computing system as described in claim 11, characterized in that, It also includes a circulator having a first port, a second port, and a third port, wherein, The output of the excitation signal generator is connected to the first port of the circulator, the quantum bit state readout resonant cavity is connected to the second port of the circulator, and the input of the quantum bit state readout circuit is connected to the third port of the circulator.

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