Stress isolation structure and method of manufacture, semiconductor device and method of manufacture, and stress isolated wafer

Abstract

The application relates to a stress isolation structure and a preparation method, a semiconductor device and a preparation method and a stress isolation wafer, and comprises the following steps: providing a first wafer, the first wafer comprising a first surface and a second surface, the first surface being a bonding surface of a second wafer; forming an isolation groove and a through groove in the first wafer from the first surface side, the isolation groove and the through groove both extending from the first surface into the first wafer, the depth of the through groove being smaller than the depth of the isolation groove; forming an isolation cavity in the first wafer from the second surface side; the first wafer comprising a stress isolation area and a first dicing lane area surrounding the periphery of the stress isolation area, the stress isolation area corresponding to a chip area of the second wafer, the first dicing lane area corresponding to a second dicing lane area of the second wafer, the stress isolation area comprising a first isolation area and a second isolation area surrounding the periphery of the first isolation area, the isolation groove being formed in the second isolation area, the through groove extending to the isolation groove in the direction from the first dicing lane area to the first isolation area, and the isolation cavity being formed in the first isolation area.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a stress isolation structure and a preparation method thereof, a semiconductor device and a preparation method thereof, and a stress isolation wafer. BACKGROUND

[0002] The precision and stability of a chip under a high temperature difference environment (such as -40℃ to 120℃) and a complex mechanical working condition are key indicators for measuring the performance of the chip. However, there is an inevitable difference in the thermal expansion coefficient between the chip and the packaging material thereof, and the chip and the packaging material thereof will generate thermal stress due to the different volume changes in the temperature cycle process, and then cause the chip to deform. In addition to the temperature factor, mechanical vibration and impact in the assembly process and terminal application process of the chip will cause the PCB (Printed Circuit Board) to deform, and the mechanical stress generated by the deformation of the PCB will be conducted to the chip through the packaging tube shell, causing the chip to abnormally deform. When the chip deformation is serious, it will cause irreversible damage (such as micro-cracks, interface delamination or structure fracture) to the structure of the chip, resulting in failure of the chip function.

[0003] At present, the solutions in the field aiming at stress isolation mainly focus on the optimization at the level of the packaged die (chip), specifically introducing a stress isolation structure (such as a cantilever beam) in the chip packaging stage. However, the process precision requirement is high, the improvement cost is high, and the efficiency is low for designing a stress isolation structure for a single chip; and the stress isolation structure is introduced in the packaging process, and the chip has been affected by a certain mechanical stress, so that the performance of the chip decreases after packaging, and the improvement effect of the stress isolation structure is not good.

[0004] Therefore, how to better block the stress conduction to the chip and reduce the stress borne by the chip has become a problem to be solved in the field. SUMMARY

[0005] Therefore, the embodiments of the present application provide a stress isolation structure and a preparation method thereof, a semiconductor device and a preparation method thereof, and a stress isolation wafer to solve at least one problem in the background art.

[0006] In a first aspect, the embodiments of the present application provide a preparation method of a stress isolation structure, and the method comprises:

[0007] providing a first wafer, the first wafer comprising a first surface and a second surface opposite to each other, the first surface serving as a bonding surface for bonding with a second wafer, and the second wafer being a chip wafer;

[0008] forming an isolation groove and a through groove in the first wafer from the first surface side, the isolation groove and the through groove both extending from the first surface to the first wafer, and the depth of the through groove being less than the depth of the isolation groove;

[0009] forming an isolation cavity in the first wafer from the second surface side;

[0010] The first wafer comprises a stress isolation region and a first dicing lane region surrounding the stress isolation region, the stress isolation region corresponds to the position of the chip region on the second wafer, the first dicing lane region corresponds to the position of the second dicing lane region on the second wafer, the stress isolation region comprises a first isolation region and a second isolation region surrounding the first isolation region, the isolation groove is formed in the second isolation region, the through groove extends from the first dicing lane region to the first isolation region to communicate with the isolation groove, and the isolation cavity is formed in the first isolation region.

[0011] In an optional embodiment of the first aspect of the present application, the projection of the isolation groove along the thickness direction of the first wafer is annular around the outer periphery of the first isolation region, the projection of the through groove is annular around the outer periphery of the isolation groove, and the inner ring of the projection of the through groove overlaps the outer ring of the projection of the isolation groove.

[0012] In an optional embodiment of the first aspect of the present application, the depth of the isolation groove accounts for 40% to 60% of the thickness of the first wafer.

[0013] In an optional embodiment of the first aspect of the present application, after the isolation groove and the through groove are formed in the first wafer from the first surface side, the method further comprises:

[0014] The first wafer is etched through the isolation groove to form an expansion cavity; wherein the projection of the expansion cavity covers the projection of the isolation groove along the thickness direction of the first wafer, and the projection area of the expansion cavity is greater than the projection area of the isolation groove.

[0015] In an optional embodiment of the first aspect of the present application, the isolation cavity is formed in the first wafer from the second surface side, comprising:

[0016] A plurality of release holes are formed in the first wafer from the second surface side, and the plurality of release holes respectively extend from the second surface to the first wafer; wherein the plurality of release holes are formed in the first isolation region;

[0017] The first wafer is etched through the release hole to form the isolation cavity; wherein the projection of the plurality of release holes is located within the projection of the isolation cavity along the thickness direction of the first wafer.

[0018] In an optional embodiment of the first aspect of the present application, the depth of the release hole accounts for 40% to 60% of the thickness of the first wafer.

[0019] In an optional implementation of the first aspect of the present application, after the first wafer is etched through the release hole to form the isolation cavity, part of the remaining first wafer forms a first support structure, and the first support structure penetrates the isolation cavity.

[0020] In an optional implementation of the first aspect of the present application, after the first wafer is etched through the release hole to form the isolation cavity, part of the remaining first wafer forms a second support structure, and the second support structure is located between the isolation groove and the isolation cavity.

[0021] In an optional implementation of the first aspect of the present application, the isolation groove and the isolation cavity are in communication.

[0022] In an optional implementation of the first aspect of the present application, etching the first wafer through the isolation groove to form an expansion cavity comprises:

[0023] forming a first dielectric layer on all exposed surfaces of the first wafer;

[0024] removing part of the first dielectric layer covering the bottom wall of the isolation groove, and part of the first dielectric layer covering the side wall and the bottom wall of the through groove, the side wall of the isolation groove and the first surface are reserved to form a first mask;

[0025] etching the first wafer through the isolation groove to form the expansion cavity with the first mask as a mask.

[0026] In an optional implementation of the first aspect of the present application, etching the first wafer through the release hole to form the isolation cavity comprises:

[0027] forming a second dielectric layer on all exposed surfaces of the first wafer;

[0028] removing part of the second dielectric layer covering the bottom wall of the release hole, and part of the second dielectric layer covering the side wall of the release hole and the second surface are reserved to form a second mask;

[0029] etching the first wafer through the release hole to form the isolation cavity with the second mask as a mask.

[0030] In a second aspect, the embodiments of the present application provide a preparation method of a semiconductor device, the method comprising the steps in the preparation method of the stress isolation structure of the first aspect; further comprising:

[0031] providing a second wafer;

[0032] bonding the first wafer and the second wafer, the second wafer being located on the first surface side of the first wafer;

[0033] performing a scribing process to form a plurality of semiconductor devices;

[0034] wherein a portion of the second wafer located in the chip region forms a chip, and a portion of the first wafer located in the stress isolation region forms a stress isolation structure corresponding to the chip.

[0035] In a third aspect, an embodiment of the present application provides a stress isolation structure, comprising:

[0036] a first substrate comprising a first surface and a second surface opposite to each other, the first surface serving as a bonding surface for bonding with a chip;

[0037] an isolation groove extending from the first surface into the first substrate;

[0038] a through groove extending from the first surface into the first substrate, the through groove having a depth smaller than that of the isolation groove;

[0039] an isolation cavity located in the first substrate, an opening of the isolation cavity facing the second surface;

[0040] wherein the first substrate comprises a stress isolation region corresponding to a position of the chip, the stress isolation region comprising a first isolation region and a second isolation region surrounding an outer periphery of the first isolation region, the isolation groove being located in the second isolation region, the through groove extending from a side of the second isolation region away from the first isolation region to the first isolation region to communicate with the isolation groove, and the isolation cavity being located in the first isolation region.

[0041] In combination with the third aspect of the present application, in an optional embodiment, in a thickness direction of the first substrate, a projection of the isolation groove is annular around an outer periphery of the first isolation region, a projection of the through groove is annular around an outer periphery of the isolation groove, and an inner ring of the projection of the through groove overlaps an outer ring of the projection of the isolation groove.

[0042] In combination with the third aspect of the present application, in an optional embodiment, a ratio of the depth of the isolation groove to the thickness of the first substrate ranges from 40% to 60%.

[0043] In combination with the third aspect of the present application, in an optional embodiment, further comprising:

[0044] An expansion cavity is located in the first substrate and communicates with the isolation groove through an end of the isolation groove away from the first surface; wherein, along the thickness direction of the first substrate, the projection of the expansion cavity covers the projection of the isolation groove, and the projected area of the expansion cavity is greater than the projected area of the isolation groove.

[0045] In combination with the third aspect of the present application, in an optional implementation, the method further comprises:

[0046] A plurality of release holes extend from the second surface into the first substrate and communicate with the isolation cavity; wherein, the plurality of release holes are all located in the first isolation region, and along the thickness direction of the first substrate, the projections of the plurality of release holes are all located within the projection of the isolation cavity.

[0047] In combination with the third aspect of the present application, in an optional implementation, the depth of the release hole accounts for 40% to 60% of the thickness of the first substrate.

[0048] In combination with the third aspect of the present application, in an optional implementation, part of the first substrate constitutes a first support structure, and the first support structure penetrates the isolation cavity.

[0049] In combination with the third aspect of the present application, in an optional implementation, part of the first substrate constitutes a second support structure, and the second support structure is located between the isolation groove and the isolation cavity.

[0050] In combination with the third aspect of the present application, in an optional implementation, the isolation groove communicates with the isolation cavity.

[0051] In the fourth aspect, the embodiments of the present application provide a stress isolation wafer comprising a plurality of stress isolation structures as described in the third aspect.

[0052] In the fifth aspect, the embodiments of the present application provide a semiconductor device comprising a stress isolation structure as described in the third aspect and a chip; or, the semiconductor device is prepared by using the preparation method of the semiconductor device as described in the second aspect.

[0053] Compared with the prior art, the stress isolation structure and the preparation method, the semiconductor device and the preparation method, and the stress isolation wafer provided by the embodiments of the present application have the following beneficial effects:

[0054] In one aspect, a double stress isolation mechanism is formed by the isolation cavity, the isolation groove and the through groove. In the cooperative action of the three, the stress isolation structure can block stress from different directions and types from being conducted to the chip, and reduce the stress borne by the chip. Specifically, the isolation cavity is located in the first isolation area and has an opening facing outward, serving as a buffer zone below the chip. The isolation groove is located in the second isolation area on the periphery of the first isolation area. The through groove connects the isolation groove to outside the stress isolation area. The isolation groove and the through groove serve as buffer zones on the periphery of the chip. The isolation cavity, the isolation groove and the through groove provide space for elastic deformation of the stress isolation structure, effectively eliminate stress from all directions, avoid the stress from spreading inward to the chip, and make the external heat dissipate laterally in the longitudinal transmission process, thereby reducing heat transfer and thermal stress, and further reducing the stress borne by the chip.

[0055] In another aspect, the stress isolation structure is designed in the first wafer, and the first wafer is bonded with the chip wafer before dicing at the wafer level. Compared with designing the stress isolation structure for the single chip after dicing at the packaging stage, the stress isolation structure is prepared in the semiconductor front-end process in the embodiments of the present application, which is more efficient and lower in cost, and avoids the stress generated in packaging from being directly conducted to the chip when the stress isolation structure has not yet been formed, so as to reduce the stress borne by the chip.

[0056] Additional aspects and advantages of the present application will be made apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0057] The accompanying drawings, which are included to provide a further understanding of the present application and are incorporated in and constitute a part of this application, illustrate embodiments of the present application and together with the description serve to explain the present application. In the drawings:

[0058] Figure 1 A flowchart of a preparation method of the stress isolation structure provided in the embodiments of the present application is shown;

[0059] Figures 2 to 7 A cross-sectional structure schematic diagram of the stress isolation structure provided in the embodiments of the present application in the preparation process is shown;

[0060] Figure 8 A projection schematic diagram of the release hole along the thickness direction of the first wafer in a specific example is shown;

[0061] Figure 9 A projection schematic diagram of the first support structure along the thickness direction of the first wafer in a specific example is shown;

[0062] Figure 10 A projection schematic diagram of the release hole along the thickness direction of the first wafer in a specific example is shown;

[0063] Figure 11 A schematic view of a projection of the second support structure along the first wafer thickness direction in a specific example;

[0064] Figure 12 A schematic view of a projection of the release hole along the first wafer thickness direction in another specific example;

[0065] Figure 13 A schematic view of a projection of the second support structure along the first wafer thickness direction in another specific example;

[0066] Figure 14 A schematic view of a flow of a method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0067] Figures 15 to 17 A schematic view of a cross-sectional structure of a semiconductor device in a manufacturing process provided by an embodiment of the present application;

[0068] Figure 18 A schematic view of a cross-sectional structure of a stress isolation structure provided by an embodiment of the present application;

[0069] Figure 19 A schematic view of a projection of the first support structure along the first substrate thickness direction in a specific example;

[0070] Figure 20 A schematic view of a projection of the second support structure along the first substrate thickness direction in a specific example;

[0071] Figure 21 A schematic view of a projection of the second support structure along the first substrate thickness direction in another specific example.

[0072] Explanation of reference signs:

[0073] 100, first wafer; 101, first surface; 102, second surface; 110, stress isolation region; 111, first isolation region; 112, second isolation region; 120, first dicing lane region; 130, isolation groove; 131, through groove; 140, release hole; 150, first dielectric layer; 160, second dielectric layer; 151, first mask; 161, second mask; 170, isolation cavity; 180, expansion cavity; 191, first support structure; 192, second support structure; 200, second wafer; 210, chip region; 220, second dicing lane region; 230, interlayer dielectric layer; 240, first electrode layer; 250, conductive connection structure; 260, second electrode layer; 270, first bonding layer; 280, second bonding layer; 290, capping layer; 10, first substrate; 20, second substrate. DETAILED DESCRIPTION

[0074] Example embodiments of the present application will be described below in greater detail with reference to the accompanying drawings. While example embodiments of the present application are illustrated in the drawings, the present application can be embodied in various forms without being limited to specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present application to those skilled in the art.

[0075] In the drawings, the size of layers, regions, elements, and the relative sizes of the same can be exaggerated for clarity. Like reference numerals can denote like elements throughout the specification.

[0076] When an element or layer is referred to as being "on", "adjacent", or "connected" to another element or layer, it can be directly on, adjacent, or connected to the other element or layer, or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", or "directly connected" to another element or layer, there are no intervening elements or layers present. Although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these terms are not intended to denote a particular order or sequence, but are merely used to distinguish one element, component, region, layer or section from another. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an overly literal or overly formal sense unless expressly so defined herein.

[0077] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, the exemplary terms "below" and "under" can encompass both an orientation of above and below. The apparatus can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0078] The singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0079] The terms "comprises", "comprising", "includes", "including" and the like can be used herein to generally describe the presence of the stated features, integers, steps, operations, elements, and / or components, but not to the exclusion of the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0080] In order to thoroughly understand the present application, detailed steps and structures will be presented in the following description. The preferred embodiments of the present application are described in detail as follows, however, the present application can have other embodiments in addition to these detailed descriptions.

[0081] Figure 1A flowchart of a preparation method of a stress isolation structure provided by an embodiment of the present application is shown in the figure. The method comprises the following steps:

[0082] Step S1: providing a first wafer, the first wafer comprising a first surface and a second surface opposite to each other, the first surface serving as a bonding surface for bonding with a second wafer, the second wafer being a chip wafer;

[0083] Step S2: forming an isolation groove and a through groove in the first wafer from the first surface side, both the isolation groove and the through groove extending from the first surface to the first wafer, the depth of the through groove being smaller than that of the isolation groove;

[0084] Step S3: forming an isolation cavity in the first wafer from the second surface side.

[0085] In the embodiment, the first wafer comprises a stress isolation region and a first dicing lane region surrounding the periphery of the stress isolation region, the stress isolation region corresponding in position to a chip region on the second wafer, and the first dicing lane region corresponding in position to a second dicing lane region on the second wafer. The stress isolation region comprises a first isolation region and a second isolation region surrounding the periphery of the first isolation region. The isolation groove is formed in the second isolation region, and the through groove extends from the first dicing lane region to the first isolation region to communicate with the isolation groove. The isolation cavity is formed in the first isolation region.

[0086] It can be understood that the current solutions for stress isolation in the field mainly focus on chip-level improvement. Specifically, after the chip wafer is diced to form a plurality of chips, a corresponding stress isolation structure is set for each chip during packaging. However, this solution has several problems. Firstly, the chip is in the packaging stage at this time and has already been affected by the stress caused by packaging. Secondly, the stress isolation structure is prepared in the packaging stage of the semiconductor back-end process, which has lower maturity and precision than the semiconductor front-end process, and it is more difficult to prepare the stress isolation structure. Moreover, it is necessary to make great changes to the traditional packaging process, which is more difficult and costly to improve. Thirdly, the stress isolation structure is prepared for each chip separately, which is less efficient and more costly. As can be seen, the improvement effect of this solution is not ideal, and it is inefficient, costly, and difficult, which is not conducive to mass production. Therefore, the embodiment of the present application processes the stress isolation structure on the first wafer, realizes wafer-level bonding of the first wafer and the chip wafer before dicing, and prepares the stress isolation structure in the semiconductor front-end process, which is more efficient and less costly. Moreover, the stress isolation structure is set before the chip enters the packaging stage, so as to avoid the stress caused by packaging directly conducting to the chip before the stress isolation structure is formed. Thus, the stress can be effectively blocked from conducting to the chip, a better stress isolation effect can be achieved, the existing packaging process can be compatible, the improvement difficulty is low, and it is conducive to mass production.

[0087] It can be understood that it is a common means in the art to encapsulate a chip by a package shell, and the chip is fixedly connected with the package shell through the substrate inside the chip. Since there is usually a certain difference in the thermal expansion coefficient between the chip and the package shell, when the temperature changes, thermal stress will be generated between the chip and the package shell under the influence of the mismatched thermal expansion coefficient, and the thermal stress specifically presents as a force in the vertical direction. Under the action of the thermal stress, the chip will be convex upward or concave downward. The package shell usually also has a filler arranged therein, which is filled between the chip and the package shell and surrounds the chip. The filler and the chip also have a difference in the thermal expansion coefficient, and thermal stress will also be generated between the chip and the filler, which specifically presents as a force in the horizontal direction. Under the action of the thermal stress, the chip will be compressed inward or stretched outward. Therefore, the chip can be affected by thermal stress from different directions. In addition, temperature is an important factor affecting the size of the thermal stress.

[0088] The stress borne by the chip includes not only the thermal stress caused by the temperature change and the mismatched thermal expansion coefficient, but also the mechanical stress conducted by the deformation of the PCB (Printed Circuit Board). The encapsulated chip needs to be welded to the PCB to realize system-level connection with other chips. The PCB with the chip welded thereon can participate in the assembly and application of terminal devices, and in this process, mechanical vibration and mechanical impact can be generated, thereby causing the deformation of the PCB, which specifically presents as bending, twisting or delamination. The mechanical stress generated by the deformation of the PCB can be in various directions, and the mechanical stress will be conducted to the chip through the package shell, causing the chip to bend, twist, break and other abnormal deformations.

[0089] Therefore, in the face of the stress that the chip can bear from different directions and types, the embodiments of the present application set up a double stress isolation mechanism composed of an isolation cavity, an isolation groove and a through groove, and under the synergistic action of the three, the stress from different directions and types is effectively blocked from being conducted to the chip, and the stress borne by the chip is reduced. Specifically, the isolation cavity with an opening facing outward is formed in the first isolation area as a buffer area below the chip, the isolation groove is formed in the second isolation area, and the through groove connects the isolation groove to the outside of the stress isolation area. The isolation groove and the through groove serve as buffer areas around the chip, and a stress isolation structure with the isolation cavity, the isolation groove and the through groove is formed. The stress from the outside needs to be conducted to the chip through the stress isolation structure. When the stress is conducted to the stress isolation structure, the stress isolation structure deforms elastically, and the isolation cavity, the isolation groove and the through groove provide space for the elastic deformation of the stress isolation structure. The stress conducted from various directions is dissipated by the isolation cavity, the isolation groove and the through groove, so that the part of the first isolation area bonded with the chip deforms small, and the stress is effectively blocked from being conducted to the chip. The isolation cavity also serves as a heat dissipation cavity, so that the external heat is dissipated laterally in the longitudinal transmission process, the heat transmission is reduced, and the thermal stress is reduced in size. Therefore, the stress conducted to the chip can be better blocked, and the stress borne by the chip is reduced.

[0090] First, refer to Figure 2 and Figure 15 , execute step S1, provide a first wafer 100, the first wafer 100 includes a first surface 101 and a second surface 102 opposite to each other, the first surface 101 as a bonding surface bonded with a second wafer, and the second wafer is a chip wafer. The first wafer 100 includes a stress isolation region 110 and a first dicing lane region 120 surrounding the outer periphery of the stress isolation region 110, the stress isolation region 110 corresponds to the position of the chip region on the second wafer, the first dicing lane region 120 corresponds to the position of the second dicing lane region on the second wafer, and the stress isolation region 110 includes a first isolation region 111 and a second isolation region 112 surrounding the outer periphery of the first isolation region 111.

[0091] It can be understood that, compared to designing a stress isolation structure for a single chip after dicing in the packaging stage, the embodiments of the present application subsequently process the isolation groove 130, the through groove 131 and the isolation cavity 170 on the first wafer 100, and the first wafer 100 and the chip wafer before dicing realize wafer-level bonding, and the stress isolation structure is prepared in the semiconductor front-end process, which is more efficient and lower in cost, and the stress isolation structure is set before the chip enters the packaging stage, avoiding the stress generated by packaging directly conducting to the chip when the stress isolation structure has not been formed. Therefore, the stress conduction to the chip can be better blocked, and the stress borne by the chip can be reduced.

[0092] In some embodiments, the thermal expansion coefficient of the first wafer 100 matches the thermal expansion coefficient of the second wafer. Thus, the stress isolation structure formed by the first wafer 100 and the chip formed by the second wafer can avoid generating thermal stress due to the mismatch of the thermal expansion coefficient when the temperature changes, so as to reduce the stress borne by the chip. Those skilled in the art can select any suitable first wafer according to the material of the second wafer, and the embodiments of the present application do not limit the material of the first wafer 100.

[0093] Next, continue to refer to Figure 2, execute step S2 to form the isolation groove 130 and the through groove 131 in the first wafer 100 from the first surface 101 side, the isolation groove 130 and the through groove 131 both extend from the first surface 101 to the first wafer 100, the depth of the through groove 131 is less than the depth of the isolation groove 130. The isolation groove 130 is formed in the second isolation region 112, the through groove 131 extends to the isolation groove 130 from the first cutting track region 120 to the first isolation region 111. It can be understood that the through groove 131 extends to the isolation groove 130 from the first cutting track region 120 to the first isolation region 111, the through groove 131 connects the isolation groove 130 to the outside of the stress isolation region 110, after dicing, the through groove 131 connects the isolation groove 130 to the outside, the part of the stress isolation structure outside the isolation groove 130 is arranged apart from the chip through the through groove 131, the chip is bonded only with the part of the stress isolation structure inside the isolation groove 130, the outside of the isolation groove 130 is the side of the isolation groove 130 away from the first isolation region 111, the inside of the isolation groove 130 is the side of the isolation groove 130 close to the first isolation region 111, thereby making the isolation groove 130 provide space for the elastic deformation of the stress isolation structure, avoiding the chip being bonded with the part of the stress isolation structure on both sides of the isolation groove 130, making it difficult for the isolation groove 130 to accommodate deformation, and blocking stress conduction to the chip.

[0094] It should be noted that, Figure 2 Only the case that the through groove 131 extends from the side of the first cutting track region 120 close to the second isolation region 112 to the first isolation region 111 is shown, and the present application does not exclude the case that the through groove 131 extends from the inside of the first cutting track region 120 to the first isolation region 111, and the case that the through groove 131 extends from the side of the first cutting track region 120 away from the second isolation region 112 to the first isolation region 111.

[0095] In some embodiments, along the thickness direction of the first wafer 100, the projection of the isolation groove 130 is an annular shape surrounding the outer periphery of the first isolation region 111, the projection of the through groove 131 is an annular shape surrounding the outer periphery of the isolation groove 130, and the inner ring of the projection of the through groove 131 overlaps the outer ring of the projection of the isolation groove 130. Thus, it is beneficial to block stress conduction in various directions and reduce the stress borne by the chip. It should be noted that in this embodiment, the projection of the isolation groove 130 surrounds the projection of the first isolation region 111, and the present application does not exclude the case that the projection of the isolation groove 130 is located outside the outer periphery of the projection of the first isolation region 111. In a specific example, along the thickness direction of the first wafer 100, the projection of the first isolation region 111 is a rectangular shape, and the projection of the isolation groove 130 is adjacent to two sides of the projection of the first isolation region 111. Further, the two sides of the projection of the first isolation region 111 are two sides symmetrical to each other.

[0096] In some embodiments, forming the isolation groove 130 in the first wafer 100 can be achieved by a photolithography-etching process. Specifically, forming the isolation groove 130 in the first wafer 100 from the first surface 101 side can include: forming a first photoresist layer (not shown in the figure) covering the first surface 101; performing an exposure process and a developing process to form a patterned first photoresist layer; etching the first wafer 100 with the patterned first photoresist layer as a mask to form the isolation groove 130. In the present embodiment, the process of forming the through groove 131 is the same as that of forming the isolation groove 130. It should be noted that the present embodiment does not limit the order of preparation of the isolation groove 130 and the through groove 131.

[0097] Optionally, the depth of the through groove 131 accounts for less than or equal to 10% of the thickness of the first wafer 100. It can be understood that the through groove 131 is used to communicate the isolation groove 130 with the outside world, and the part of the stress isolation structure located outside the isolation groove 130 is arranged apart from the chip through the through groove 131, and the chip is bonded only with the part of the stress isolation structure located inside the isolation groove 130, the outside of the isolation groove 130 is the side of the isolation groove 130 away from the first isolation region 111, and the inside of the isolation groove 130 is the side of the isolation groove 130 close to the first isolation region 111, thereby enabling the isolation groove 130 to provide space for elastic deformation of the stress isolation structure and avoiding the chip being bonded with the parts of the stress isolation structure located on both sides of the isolation groove 130. If the depth of the through groove 131 is too large, the thickness of the remaining first wafer 100 below the through groove 131 will be too small, resulting in reduced mechanical strength, thereby more favorably ensuring the stress isolation effect.

[0098] Optionally, the depth of the isolation groove 130 accounts for 40% to 60% of the thickness of the first wafer 100. It can be understood that if the depth of the isolation groove 130 accounts for too small a proportion of the thickness of the first wafer 100, the space for elastic deformation provided by the isolation groove 130 is insufficient, which will reduce the stress isolation effect of the isolation groove 130; if the depth of the isolation groove 130 accounts for too large a proportion of the thickness of the first wafer 100, the depth of the isolation groove 130 is too large, the thickness of the remaining first wafer 100 below the isolation groove 130 is too small, resulting in reduced mechanical strength, which may, when the stress conducted from the outside world is too large, cause structural rupture, and the etching time is long, affecting production efficiency. Therefore, controlling the depth of the isolation groove 130 to account for a proportion of the thickness of the first wafer 100 within this range is favorable for ensuring the stress isolation effect.

[0099] Further, the depth of the isolation groove 130 accounts for 50% of the thickness of the first wafer 100. This is more favorable for ensuring the stress isolation effect.

[0100] In some embodiments, please refer to Figure 6After the isolation groove 130 and the through groove 131 are formed in the first wafer 100 from the first surface 101 side, the method can further include: etching the first wafer 100 through the isolation groove 130 to form an expansion cavity 180; wherein, in the thickness direction of the first wafer 100, the projection of the expansion cavity 180 covers the projection of the isolation groove 130, and the projection area of the expansion cavity 180 is greater than the projection area of the isolation groove 130. Thus, the expansion cavity 180 is formed in communication with the isolation groove 130, which provides more space for the elastic deformation of the stress isolation structure, better resolves the stress, and is more conducive to blocking the stress conduction to the chip and reducing the stress borne by the chip.

[0101] Optionally, the depth of the expansion cavity 180 accounts for 25% to 30% of the thickness of the first wafer 100. Understandably, if the depth of the expansion cavity 180 is too small, the stress isolation effect is poor; if the depth of the expansion cavity 180 is too large, the mechanical strength of the first wafer 100 is reduced, and warping is prone to occur. Therefore, controlling the proportion of the depth of the expansion cavity 180 to the thickness of the first wafer 100 within this range is conducive to guaranteeing the stress isolation effect.

[0102] In some embodiments, referring to Figures 4 to 6 The etching of the first wafer 100 through the isolation groove 130 to form the expansion cavity 180 can include: forming a first dielectric layer 150 on all exposed surfaces of the first wafer 100; removing the part of the first dielectric layer 150 covering the bottom wall of the isolation groove 130, and the part of the first dielectric layer 150 covering the side wall and bottom wall of the through groove 131, the side wall of the isolation groove 130 and the first surface 101 are retained to form a first mask 151; taking the first mask 151 as a mask, etching the first wafer 100 through the isolation groove 130 to form the expansion cavity 180. By forming a first dielectric layer 150 on all exposed surfaces of the first wafer 100, damage to other positions of the first wafer 100 during etching of the first wafer 100 can be avoided; when the first dielectric layer 150 is formed, the thickness of the first dielectric layer 150 formed on the bottom wall of the isolation groove 130 is small, so that, in the same process, the first dielectric layer 150 on the bottom wall of the isolation groove 130 is removed first, and the first dielectric layer 150 on other positions is only partially removed to form the first mask 151, without the need for additional mask plates to prepare the first mask 151.

[0103] The material of the first dielectric layer 150 can include an oxidation material or a nitridation material.

[0104] The process of forming a first dielectric layer 150 on all exposed surfaces of the first wafer 100 can include a thermal oxidation process or a nitridation process.

[0105] In some embodiments, after the first dielectric layer 150 is formed on all exposed surfaces of the first wafer 100, the method can further include: forming a third dielectric layer (not shown in the figure) covering the sidewalls and bottom wall of the through slot 131, the sidewalls and bottom wall of the isolation slot 130, and the first surface 101, the third dielectric layer and the first dielectric layer 150 being of the same material;

[0106] The part of the first dielectric layer 150 covering the bottom wall of the isolation slot 130 is removed, and the part of the first dielectric layer 150 and the third dielectric layer covering the sidewalls and bottom wall of the through slot 131, the sidewalls of the isolation slot 130, and the first surface 101 is retained to form the first mask 151.

[0107] It can be understood that, when the third dielectric layer is formed, the thickness of the third dielectric layer formed on the bottom wall of the isolation slot 130 is small, and therefore, in the same process, the third dielectric layer on the bottom wall of the isolation slot 130 is removed first, and the third dielectric layer on other positions of the first wafer 100 is only partially removed, and can be formed into the first mask 151 together with the remaining first dielectric layer 150, without the need of an additional mask plate to prepare the first mask 151; the third dielectric layer increases the thickness of the first mask 151, which is conducive to guaranteeing the shielding effect of the first mask 151.

[0108] In a specific example, the thickness of the first dielectric layer 150 is 0.5 μm, and the thickness of the third dielectric layer is 2 μm.

[0109] The process of forming the third dielectric layer can include a deposition process.

[0110] Next, referring to Figure 6 , step S3 is performed to form the isolation cavity 170 in the first wafer 100 from the second surface 102 side. The isolation cavity 170 is formed in the first isolation region 111. It can be understood that the first isolation region 111 corresponds to the chip region, and the isolation cavity 170 is formed in the first isolation region 111. After dicing, the isolation cavity 170 serves as a stress buffer zone and a heat release zone below the chip, which not only provides space for the elastic deformation of the stress isolation structure, but also promotes the lateral dissipation of heat in the process of longitudinal heat transfer, reduces heat transfer, and in turn reduces thermal stress; so as to better block the stress from being conducted to the chip and reduce the stress borne by the chip. The isolation cavity 170, the isolation slot 130, and the through slot 131 constitute a double stress isolation mechanism, which blocks stress from all directions and reduces the stress borne by the chip under the synergistic action of the three.

[0111] It should be noted that, althoughFigure 1 The arrow in the figure shows that step S2 is performed before step S3, but the present application does not exclude the case that step S3 is performed before step S2.

[0112] In some embodiments, forming the isolation cavity 170 in the first wafer 100 from the second surface 102 side can include: forming a second photoresist layer (not shown in the figure) covering the second surface 102; performing an exposure process and a development process to form a patterned second photoresist layer; etching the first wafer 100 with the patterned second photoresist layer as a mask to form the isolation cavity 170.

[0113] The projected area of the isolation cavity 170 along the thickness direction of the first wafer 100 is greater than or equal to 50% of the projected area of the stress isolation region 110. Thus, it is beneficial to provide sufficient elastic deformation space for the stress isolation structure.

[0114] In some embodiments, please refer to Figures 3 to 6 In some embodiments, forming the isolation cavity 170 in the first wafer 100 from the second surface 102 side can include: forming a plurality of release holes 140 in the first wafer 100 from the second surface 102 side, the plurality of release holes 140 respectively extending from the second surface 102 to the first wafer 100; wherein the plurality of release holes 140 are all formed in the first isolation region 111; etching the first wafer 100 through the release holes 140 to form the isolation cavity 170; wherein the projections of the plurality of release holes 140 along the thickness direction of the first wafer 100 are all located within the projection range of the isolation cavity 170. Thus, it is beneficial to strengthen the mechanical strength of the stress isolation structure; and compared with directly etching the first wafer 100 from the second surface 102, the etching amount of the first wafer 100 in this embodiment is relatively small, and the production efficiency is higher.

[0115] The etching process of the first wafer 100 can include a wet etching process. Compared with a dry etching process, the wet etching process is more efficient.

[0116] Optionally, the proportion of the depth of the release hole 140 to the thickness of the first wafer 100 ranges from 40% to 60%. It can be understood that if the proportion of the depth of the release hole 140 to the thickness of the first wafer 100 is too small, after the isolation cavity 170 is formed, the remaining thickness of the first wafer 100 below the isolation cavity 170 is too small, the mechanical strength is reduced, and when the externally transmitted stress is too large, it is easy to break; if the proportion of the depth of the release hole 140 to the thickness of the first wafer 100 is too large, after the isolation cavity 170 is formed, the remaining thickness of the first wafer 100 between the isolation cavity 170 and the chip is too small, the blocking effect of heat is reduced, and the etching time is long, the production efficiency is low. Therefore, controlling the proportion of the depth of the release hole 140 to the thickness of the first wafer 100 within this range is beneficial to guarantee the stress isolation effect.

[0117] Further, the depth of the release hole 140 accounts for 50% of the thickness of the first wafer 100. Thus, the stress isolation effect is further ensured.

[0118] Optionally, the depth of the isolation cavity 170 accounts for 25%-30% of the thickness of the first wafer 100. It can be understood that if the depth of the isolation cavity 170 is too small, the isolation effect is poor; if the depth of the isolation cavity 170 is too large, the mechanical strength of the first wafer 100 is reduced, and warping is prone to occur. Therefore, controlling the depth of the isolation cavity 170 to account for 25%-30% of the thickness of the first wafer 100 is beneficial to ensure the stress isolation effect.

[0119] In some embodiments, referring to Figure 9 After etching the first wafer 100 through the release hole 140 to form the isolation cavity 170, part of the remaining first wafer 100 constitutes a first support structure 191, and the first support structure 191 penetrates the isolation cavity 170. Thus, the first support structure 191 connects the remaining first wafer 100 on the upper and lower sides of the isolation cavity 170, thereby strengthening the mechanical strength and avoiding the remaining first wafer 100 below the isolation cavity 170 from breaking.

[0120] The number of the first support structure 191 can be one. In some embodiments, the projection of the first support structure 191 along the thickness direction of the first wafer 100 is located at the center of the projection of the isolation cavity 170. Thus, the first support structure 191 is more evenly stressed, and the support effect is better.

[0121] The number of the first support structure 191 can be multiple. In some embodiments, the projections of the first support structures 191 along the thickness direction of the first wafer 100 are centrally symmetric with the center of the projection of the isolation cavity 170. Thus, the multiple first support structures 191 are more evenly stressed, and the support effect is better.

[0122] It can be understood that, referring to Figure 8 In actual production, the positions of the first support structures 191 can be set by setting the distribution mode of the multiple release holes 140. Specifically, no release hole 140 can be set at part of the positions of the first isolation region 111, and the positions will be reserved in the subsequent etching process to form the first support structure 191.

[0123] In some embodiments, referring to Figure 6After the first wafer 100 is etched by the release holes 140 to form the isolation cavities 170, the remaining first wafer 100 at the second support structures 192 between the isolation grooves 130 and the isolation cavities 170 forms the second support structures 192. Thus, the remaining first wafer 100 on both sides of the isolation cavities 170 is connected by the second support structures 192, which strengthens the mechanical strength and avoids the remaining first wafer 100 under the isolation cavities 170 from breaking.

[0124] The number of the second support structures 192 can be multiple. In some embodiments, the projection of the second support structures 192 along the thickness direction of the first wafer 100 is centrally symmetric to the center of the projection of the isolation cavities 170. Thus, the multiple second support structures 192 are more evenly stressed and have better support effect.

[0125] For example, Figure 11 In a specific example, the projection of the isolation grooves 130 along the thickness direction of the first wafer 100 is a rectangular ring, and the projection of the second support structures 192 is adjacent to the four corners of the projection of the isolation grooves 130.

[0126] For example, Figure 13 In another specific example, the projection of the isolation grooves 130 along the thickness direction of the first wafer 100 is a rectangular ring, and the projection of the second support structures 192 is adjacent to the opposite two corners of the projection of the isolation grooves 130.

[0127] It should be noted that Figures 10 to 13 The number of the second support structures 192 is specifically shown as 2 and 4, and the number of the second support structures 192 can also be 1, 3, 5, etc.

[0128] It can be understood that Figure 10 and Figure 12 In actual production, the positions of the second support structures 192 can be set by setting the distribution of the multiple release holes 140. Specifically, no release hole 140 can be set at some positions of the first isolation region 111, which will be reserved in the subsequent etching process to form the second support structures 192.

[0129] In some embodiments, for example Figures 4 to 6The etching the first wafer 100 through the release hole 140 to form the isolation cavity 170 can include: forming a second dielectric layer 160 on all exposed surfaces of the first wafer 100; removing the part of the second dielectric layer 160 covering the bottom wall of the release hole 140, and the part of the second dielectric layer 160 covering the sidewall of the release hole 140 and the second surface 102 are reserved to form a second mask 161; etching the first wafer 100 through the release hole 140 with the second mask 161 as a mask to form the isolation cavity 170. By forming a second dielectric layer 160 on all exposed surfaces of the first wafer 100, damage to other positions of the first wafer 100 in the subsequent etching process can be avoided; when the second dielectric layer 160 is formed, the thickness of the second dielectric layer 160 formed on the bottom wall of the release hole 140 is smaller, so that in the same process, the second dielectric layer 160 on the bottom wall of the release hole 140 is removed first, and the second dielectric layer 160 on other positions of the first wafer 100 is only partially removed to form the second mask 161, without the need to additionally set a mask plate to prepare the second mask 161.

[0130] The material of the second dielectric layer 160 can include an oxidation material or a nitridation material.

[0131] The process of forming a second dielectric layer 160 on all exposed surfaces of the first wafer 100 can include a thermal oxidation process or a nitridation process.

[0132] In some embodiments, after the second dielectric layer 160 is formed on all exposed surfaces of the first wafer 100, the method can further include: forming a fourth dielectric layer (not shown in the figure) covering the sidewall and the bottom wall of the release hole 140 and the second surface 102, the material of the fourth dielectric layer being the same as that of the second dielectric layer 160;

[0133] The removing the part of the second dielectric layer 160 covering the bottom wall of the release hole 140, and the part of the second dielectric layer 160 covering the sidewall of the release hole 140 and the second surface 102 are reserved to form the second mask 161 can include: removing the part of the second dielectric layer 160 and the fourth dielectric layer covering the bottom wall of the release hole 140, and the part of the second dielectric layer 160 and the fourth dielectric layer covering the sidewall of the release hole 140 and the second surface 102 are reserved to form the second mask 161.

[0134] It can be understood that, when the fourth dielectric layer is formed, the thickness of the fourth dielectric layer formed on the bottom wall of the release hole 140 is small, so that, in the same process, the fourth dielectric layer on the bottom wall of the release hole 140 is removed first, and the fourth dielectric layer at other positions is only partially removed, and can be formed into the second mask 161 together with the remaining second dielectric layer 160, without the need to additionally set a mask plate to prepare the second mask 161; the fourth dielectric layer increases the thickness of the second mask 161, and guarantees the shielding effect of the second mask 161.

[0135] In a specific example, the thickness of the second dielectric layer 160 is 0.5 μm, and the thickness of the fourth dielectric layer is 2 μm.

[0136] The process of forming the fourth dielectric layer can include a deposition process.

[0137] In some embodiments, the first dielectric layer 150 and the second dielectric layer 160 are the same material layer formed by the same process. In a specific example, a thermal oxidation process can be performed to form an oxide layer on all exposed surfaces of the first wafer 100. The oxide layer can be used as the first dielectric layer 150 for forming the first mask 151, and can also be used as the second dielectric layer 160 for forming the second mask 161.

[0138] It should be noted that, Figures 4 to 6 Only a part of the first wafer 100 is shown, and it should be understood that the part of the first dielectric layer 150 (the second dielectric layer 160) located outside the second isolation area 112 covers the sidewall of the entire first wafer 100.

[0139] In some embodiments, the isolation cavity 170 and the expansion cavity 180 are prepared in the same process. The process of forming the isolation cavity 170 and the expansion cavity 180 can include a wet etching process. The etchant of the wet etching process can include XeF2 and / or phosphorus nitric acid.

[0140] Optionally, the isolation groove 130 communicates with the isolation cavity 170. In this way, the isolation groove 130 can also act as a heat dissipation groove, and the external heat transferred to the isolation cavity 170 can be further conducted through the isolation groove 130, which is more conducive to reducing thermal stress.

[0141] Optionally, the isolation groove 130 communicates with the isolation cavity 170 through the expansion cavity 180.

[0142] In some embodiments, the bottom wall of the isolation cavity 170 and the top wall of the expansion cavity 180 are in the same plane, and the top wall of the isolation cavity 170 and the bottom wall of the expansion cavity 180 are in the same plane.

[0143] Please refer to Figure 7 , the method further comprises: removing the first mask 151 and the second mask 161.

[0144] The application further provides a preparation method of a semiconductor device, please refer to Figure 14 , the method comprises the steps in the preparation method of the stress isolation structure in the above embodiments; further comprising:

[0145] Step S4: providing a second wafer;

[0146] Step S5: bonding the first wafer and the second wafer, the second wafer is located on the first surface side of the first wafer;

[0147] Step S6: performing a dicing process to form a plurality of semiconductor devices.

[0148] Wherein, the part of the second wafer located in the chip area forms a chip, and the part of the first wafer located in the stress isolation area is formed as a stress isolation structure corresponding to the chip.

[0149] Therefore, compared with designing a stress isolation structure for a single chip after dicing in the packaging stage, the stress isolation structure is designed in the first wafer in the embodiments of the application, and the first wafer is bonded with the chip wafer before dicing at the wafer level, the stress isolation structure is prepared in the semiconductor front-end process, the production efficiency is higher, the cost is lower, and the stress generated by packaging is directly conducted to the chip before the stress isolation structure is formed; The double stress isolation mechanism is composed of the isolation cavity, the isolation groove and the through groove, and under the synergistic action of the three, the stress isolation structure can block the stress from different directions and types from conducting to the chip, reduce the stress borne by the chip, specifically, the isolation cavity is located in the first isolation area and the opening faces outward, as a buffer area below the chip, the isolation groove is located in the second isolation area, and the through groove extends from the first cutting channel area to communicate with the isolation groove, the isolation groove and the through groove serve as a buffer area outside the chip, the isolation cavity, the isolation groove and the through groove provide space for the elastic deformation of the stress isolation structure, effectively eliminate the stress from each direction, avoid the stress from diffusing inward to the chip, and the isolation cavity also serves as a heat dissipation cavity, so that the external heat is dissipated laterally in the longitudinal transmission process, reducing heat transmission, and in turn reducing thermal stress. Therefore, the stress can be better blocked from conducting to the chip, the stress borne by the chip can be reduced, and the performance of the semiconductor device can be improved.

[0150] First, please refer to Figure 15 , step S4 is performed to provide a second wafer 200. The second wafer 200 is a chip wafer, which comprises a plurality of chip areas 210 and a second cutting channel area 220 located outside the chip areas 210. Figure 15 Only one chip area 210 of the second wafer 200 is shown exemplarily.

[0151] In some embodiments, please refer to Figure 15The chip region 210 is formed with a chip structure layer, and the chip structure layer includes an interlayer dielectric layer 230, a first electrode layer 240, a conductive connection structure 250, a second electrode layer 260, a first bonding layer 270, a second bonding layer 280, and a capping layer 290 which are sequentially stacked. The first electrode layer 240 and the second electrode layer 260 are spaced apart and conductively connected through the conductive connection structure 250. The second electrode layer 260 and the capping layer 290 are bonded through the first bonding layer 270 and the second bonding layer 280. It can be understood that Figure 15 The chip wafer is exemplarily shown as a MEMS (Micro-Electro-Mechanical System) chip wafer, and the chip wafer can be other chip wafers known to those skilled in the art, which are not limited in the present application.

[0152] Next, referring to Figure 16 , a step S5 is performed to bond the first wafer 100 and the second wafer 200, and the second wafer 200 is located on the side of the first surface 101 of the first wafer 100. The first surface 101 of the first wafer 100 serves as a bonding surface for bonding with the second wafer 200. It can be understood that, compared to designing a stress isolation structure for a single chip after dicing in the packaging stage, the embodiment of the present application realizes wafer-level bonding of the first wafer 100 and the chip wafer before dicing, and the stress isolation structure is prepared in the semiconductor front-end process, which is more efficient and lower in cost. In addition, the stress isolation structure is provided before the chip enters the packaging stage, so as to avoid the stress generated in packaging from being directly transmitted to the chip when the stress isolation structure has not yet been formed. Thus, the stress transmission to the chip can be better blocked, and the stress borne by the chip can be reduced.

[0153] In some embodiments, the thermal expansion coefficient of the first wafer 100 matches the thermal expansion coefficient of the second wafer 200. Thus, the stress isolation structure formed by the first wafer 100 and the chip formed by the second wafer 200 can avoid generating thermal stress due to mismatch of thermal expansion coefficients when the temperature changes, so as to reduce the stress borne by the chip. Those skilled in the art can select any suitable first wafer 100 according to the material of the second wafer 200, and the material of the first wafer 100 is not limited in the embodiment of the present application.

[0154] In a specific example, the material of the first wafer 100 includes silicon, the material of the second wafer 200 includes silicon, and the first wafer 100 and the second wafer 200 realize silicon-silicon bonding.

[0155] Finally, referring to Figure 17After step S5, step S6 is performed to perform a dicing process to form a plurality of semiconductor devices. In actual manufacturing process, dicing is performed through the first dicing groove region 120 and the second dicing groove region 220. The part of the second wafer 200 located in the chip region 210 forms a chip, and the part of the first wafer 100 located in the stress isolation region 110 forms a stress isolation structure corresponding to the chip.

[0156] Therefore, the double stress isolation mechanism is formed by the isolation cavity 170, the isolation groove 130 and the through groove 131. Under the synergistic effect of the three, the stress isolation structure can block the stress from different directions and types from being conducted to the chip, reduce the stress borne by the chip, and specifically, the isolation cavity 170 can act as a buffer zone below the chip, the isolation groove 130 and the through groove 131 can act as a buffer zone outside the chip, the isolation cavity 170, the isolation groove 130 and the through groove 131 provide space for elastic deformation of the stress isolation structure, effectively eliminate the stress from each direction, avoid the stress from diffusing inward to the chip, and the isolation cavity 170 also acts as a heat dissipation cavity, so that the external heat is dissipated laterally in the longitudinal transmission process, reducing heat transmission and in turn reducing thermal stress. Therefore, the stress can be better blocked from being conducted to the chip, the stress borne by the chip can be reduced, and the performance of the semiconductor device can be improved.

[0157] The embodiment of the present application also provides a stress isolation structure, please refer to Figure 18 , comprising:

[0158] A first substrate 10, comprising a first surface 101 and a second surface 102 opposite to each other, the first surface 101 as a bonding surface bonded with a chip;

[0159] An isolation groove 130 extending from the first surface 101 into the first substrate 10;

[0160] A through groove 131 extending from the first surface 101 into the first substrate 10, the depth of the through groove 131 being less than the depth of the isolation groove 130;

[0161] An isolation cavity 170 located in the first substrate 10, the opening of the isolation cavity 170 facing the second surface 102;

[0162] Wherein, the first substrate 10 comprises a stress isolation region 110 corresponding to the position of the chip, the stress isolation region 110 comprises a first isolation region 111 and a second isolation region 112 surrounding the outer periphery of the first isolation region 111, the isolation groove 130 is located in the second isolation region 112, the through groove 131 extends from the side of the second isolation region 112 away from the first isolation region 111 to the first isolation region 111 to communicate with the isolation groove 130, and the isolation cavity 170 is located in the first isolation region 111.

[0163] The stress isolation structure can block stress from different directions and types from being conducted to the chip, and reduce the stress borne by the chip. Specifically, the isolation cavity 170 is located in the first isolation area 111 and has an opening facing outward, serving as a buffer area below the chip. The isolation groove 130 is located in the second isolation area 112 on the periphery of the first isolation area 111. The through groove 131 extends from a side of the second isolation area 112 away from the first isolation area 111 to the isolation groove 130. The isolation groove 130 and the through groove 131 serve as buffer areas on the periphery of the chip. The isolation cavity 170, the isolation groove 130, and the through groove 131 provide space for elastic deformation of the stress isolation structure, effectively eliminate stress conducted from various directions, and avoid the stress from spreading inward to the chip. The isolation cavity 170 also serves as a heat dissipation cavity, so that external heat is dissipated laterally in the longitudinal transmission process, reducing heat transmission and in turn reducing thermal stress. Thus, stress can be better blocked from being conducted to the chip, and the stress borne by the chip can be reduced.

[0164] In some embodiments, the chip includes a second substrate 20, and the first substrate 10 is bonded to the second substrate 20. The coefficient of thermal expansion of the first substrate 10 matches the coefficient of thermal expansion of the second substrate 20. Thus, the stress isolation structure and the chip are avoided from generating thermal stress due to mismatch of the coefficients of thermal expansion when the temperature changes, so as to reduce the stress borne by the chip. A person skilled in the art can select any suitable first substrate 10 according to the material of the second substrate 20, and embodiments of the present application do not limit the material of the first substrate 10.

[0165] In some embodiments, in the thickness direction of the first substrate 10, the projection of the isolation groove 130 is annular around the periphery of the first isolation area 111, the projection of the through groove 131 is annular around the periphery of the isolation groove 130, and the inner ring of the projection of the through groove 131 overlaps the outer ring of the projection of the isolation groove 130. Thus, it is beneficial to block stress conducted from various directions and reduce the stress borne by the chip.

[0166] In some embodiments, the depth of the through groove 131 accounts for less than or equal to 10% of the thickness of the first substrate 10. It can be understood that the through groove 131 is used to communicate the isolation groove 130 with the outside world, the part of the stress isolation structure located outside the isolation groove 130 is spaced apart from the chip through the through groove 131, and the chip is bonded only with the part of the stress isolation structure located inside the isolation groove 130. The outside of the isolation groove 130 is the side of the isolation groove 130 away from the first isolation area 111, and the inside of the isolation groove 130 is the side of the isolation groove 130 close to the first isolation area 111, thereby enabling the isolation groove 130 to provide space for elastic deformation of the stress isolation structure and avoiding the chip being bonded with the part of the stress isolation structure located on both sides of the isolation groove 130. If the depth of the through groove 131 is too large, the thickness of the remaining first wafer 100 below the through groove 131 will be too small, and the mechanical strength will be reduced, thereby more favorably ensuring the stress isolation effect.

[0167] In some embodiments, the depth of the isolation groove 130 accounts for 40% to 60% of the thickness of the first substrate 10. It can be understood that if the depth of the isolation groove 130 accounts for too small a proportion of the thickness of the first substrate 10, the space for elastic deformation provided by the isolation groove 130 is insufficient, which will reduce the stress isolation effect of the isolation groove 130; if the depth of the isolation groove 130 accounts for too large a proportion of the thickness of the first substrate 10, the depth of the isolation groove 130 is too large, the thickness of the remaining first substrate 10 below the isolation groove 130 is too small, the mechanical strength is reduced, and when the stress conducted from the outside world is too large, the structure may be broken, and the etching time is long, which affects the production efficiency. Therefore, controlling the proportion of the depth of the isolation groove 130 to the thickness of the first substrate 10 within this range is more favorable to ensure the stress isolation effect.

[0168] Further, the depth of the isolation groove 130 accounts for 50% of the thickness of the first substrate 10. This is more favorable to the stress isolation effect.

[0169] In some embodiments, the stress isolation structure can further include an expansion cavity 180 located in the first substrate 10 and communicating with the isolation groove 130 through the end of the isolation groove 130 away from the first surface 101; wherein the projection of the expansion cavity 180 covers the projection of the isolation groove 130 along the thickness direction of the first substrate 10, and the projection area of the expansion cavity 180 is greater than the projection area of the isolation groove 130. Thus, the expansion cavity 180 communicating with the isolation groove 130 is formed to provide more space for elastic deformation of the stress isolation structure, so as to better dissipate stress and more favorably block the stress from being conducted to the chip and reduce the stress borne by the chip.

[0170] In some embodiments, the isolation cavity 170 extends from the second surface 102 into the first substrate 10.

[0171] In some embodiments, the stress isolation structure can further include: a plurality of release holes 140 extending from the second surface 102 into the first substrate 10 and in communication with the isolation cavity 170; wherein each of the plurality of release holes 140 is located in the first isolation region 111, and a projection of each of the plurality of release holes 140 along the thickness direction of the first substrate 10 is located within a projection of the isolation cavity 170. This is advantageous for strengthening the mechanical strength of the stress isolation structure, and can improve production efficiency in actual production.

[0172] Optionally, the depth of the release hole 140 accounts for 40% to 60% of the thickness of the first substrate 10. Understandably, if the depth of the release hole 140 accounts for too small a proportion of the thickness of the first substrate 10, the remaining thickness of the first substrate 10 below the isolation cavity 170 is too small after the isolation cavity 170 is formed, and the mechanical strength is reduced, and when the stress conducted from the outside is too large, the first substrate 10 is prone to rupture. If the depth of the release hole 140 accounts for too large a proportion of the thickness of the first substrate 10, the remaining thickness of the first substrate 10 between the isolation cavity 170 and the chip is too small after the isolation cavity 170 is formed, the blocking effect of heat is reduced, and the etching time is long, and the production efficiency is low. Therefore, controlling the depth of the release hole 140 to account for a proportion of the thickness of the first substrate 10 within this range is advantageous for guaranteeing the stress isolation effect of the isolation cavity 170.

[0173] Further, the depth of the release hole 140 accounts for 50% of the thickness of the first wafer 100. This is more advantageous for guaranteeing the stress isolation effect of the isolation cavity 170.

[0174] In some embodiments, referring to Figure 19 , part of the first substrate 10 constitutes a first support structure 191, and the first support structure 191 penetrates the isolation cavity 170. In this way, the first support structure 191 connects the first substrate 10 on the upper and lower sides of the isolation cavity 170, strengthens the mechanical strength, and avoids the rupture of part of the first substrate 10 below the isolation cavity 170.

[0175] The number of the first support structure 191 can be one. In some embodiments, a projection of the first support structure 191 along the thickness direction of the first substrate 10 is located at the center of a projection of the isolation cavity 170. In this way, the first support structure 191 is more evenly stressed, and the support effect is better.

[0176] The number of the first support structure 191 can be multiple. In some embodiments, a projection of the first support structure 191 along the thickness direction of the first substrate 10 is centrally symmetric with the center of a projection of the isolation cavity 170. In this way, the multiple first support structures 191 are more evenly stressed, and the support effect is better.

[0177] In some embodiments, part of the first substrate 10 constitutes a second support structure 192, which is located between the isolation groove 130 and the isolation cavity 170. Thus, the first substrate 10 on both sides of the isolation cavity 170 is connected by the second support structure 192, which strengthens the mechanical strength and avoids the breakage of the part of the first substrate 10 below the isolation cavity 170.

[0178] The number of the second support structure 192 can be multiple. In some embodiments, the projection of the second support structure 192 along the thickness direction of the first wafer 100 is centrally symmetric to the center of the projection of the isolation cavity 170. Thus, the multiple second support structures 192 are more evenly stressed and have better support effect.

[0179] For reference Figure 20 In a specific example, the projection of the isolation groove 130 along the thickness direction of the first substrate 10 is a rectangular ring, and the projection of the second support structure 192 is adjacent to the four corners of the projection of the isolation groove 130.

[0180] For reference Figure 21 In another specific example, the projection of the isolation groove 130 along the thickness direction of the first substrate 10 is a rectangular ring, and the projection of the second support structure 192 is adjacent to the opposite two corners of the projection of the isolation groove 130.

[0181] It should be noted that Figure 20 and Figure 21 The number of the second support structure 192 is specifically shown as 2 and 4, but the number of the second support structure 192 can also be 1, 3, 5, etc.

[0182] Optionally, the isolation groove 130 is in communication with the isolation cavity 170. Thus, the isolation groove 130 can also serve as a heat dissipation groove, and the external heat transferred to the isolation cavity 170 can be further conducted through the isolation groove 130, which is more conducive to reducing thermal stress.

[0183] Optionally, the isolation groove 130 is in communication with the isolation cavity 170 through the expansion cavity 180. In some embodiments, the bottom wall of the isolation cavity 170 and the top wall of the expansion cavity 180 are in the same plane, and the top wall of the isolation cavity 170 and the bottom wall of the expansion cavity 180 are in the same plane.

[0184] The embodiments of the present application also provide a stress isolation wafer comprising a plurality of stress isolation structures as described above.

[0185] The stress isolation wafer can be bonded with the chip wafer before dicing to promote stress isolation from the chip level to the wafer level, which is more efficient and lower in cost. The stress isolation structure can block stress from different directions and types from being transmitted to the chip and reduce the stress borne by the chip through a double stress isolation mechanism composed of the isolation cavity, the isolation groove and the through groove. Specifically, the isolation cavity is located in the first isolation area and has an opening facing outward, serving as a buffer zone below the chip. The isolation groove is located in the second isolation area outside the periphery of the first isolation area. The through groove connects the isolation groove to the outside of the stress isolation area. The isolation groove and the through groove serve as buffer zones outside the periphery of the chip. The isolation cavity, the isolation groove and the through groove provide space for elastic deformation of the stress isolation structure, effectively eliminate stress transmitted from different directions, and avoid the stress from spreading inward to the chip. The isolation cavity also serves as a heat dissipation cavity, allowing external heat to dissipate laterally in the longitudinal transmission process, reducing heat transmission, and in turn reducing thermal stress. Thus, stress can be better blocked from being transmitted to the chip, and the stress borne by the chip can be reduced.

[0186] The application also provides a semiconductor device comprising the stress isolation structure and the chip in the above embodiments, or prepared by the preparation method of the semiconductor device in the above embodiments.

[0187] Thus, the stress isolation structure can block stress from different directions and types from being transmitted to the chip and reduce the stress borne by the chip through a double stress isolation mechanism composed of the isolation cavity, the isolation groove and the through groove. Specifically, the isolation cavity is located in the first isolation area and has an opening facing outward, serving as a buffer zone below the chip. The isolation groove is located in the second isolation area outside the periphery of the first isolation area. The through groove connects the isolation groove to the outside of the stress isolation area. The isolation groove and the through groove serve as buffer zones outside the periphery of the chip. The isolation cavity, the isolation groove and the through groove provide space for elastic deformation of the stress isolation structure, effectively eliminate stress transmitted from different directions, and avoid the stress from spreading inward to the chip. The isolation cavity also serves as a heat dissipation cavity, allowing external heat to dissipate laterally in the longitudinal transmission process, reducing heat transmission, and in turn reducing thermal stress. Thus, stress can be better blocked from being transmitted to the chip, and the stress borne by the chip can be reduced, improving the performance of the semiconductor device.

[0188] It should be noted that the stress isolation structure preparation method, the semiconductor device preparation method, the stress isolation structure, the stress isolation wafer and the semiconductor device provided in the embodiments of the present application belong to the same concept. The technical features of the technical solutions recorded in each embodiment can be combined arbitrarily without conflict. However, it should be further noted that the combination of the technical features of the stress isolation structure provided in the embodiments of the present application can already solve the technical problems to be solved by the present application. Therefore, the stress isolation structure provided in the embodiments of the present application can not be limited by the stress isolation structure preparation method provided in the embodiments of the present application, and any stress isolation structure prepared by a stress isolation structure preparation method capable of forming the stress isolation structure provided in the embodiments of the present application is within the scope of protection of the present application.

[0189] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations. Various modifications and changes can also be made to the above embodiments without departing from the scope of the present application. Similarly, any combination of the technical features of the above embodiments can be made to form additional embodiments of the present application that can not be explicitly described. The above embodiments only express several implementations of the present application and do not limit the protection scope of the present application.

Claims

1. A method of fabricating a stress isolation structure, comprising: The method comprises: providing a first wafer, the first wafer comprising a first surface and a second surface opposite to each other, the first surface serving as a bonding surface for bonding with a second wafer, the second wafer being a chip wafer; forming an isolation groove and a through groove in the first wafer from the first surface side, both the isolation groove and the through groove extending from the first surface to the first wafer, the depth of the through groove being smaller than the depth of the isolation groove; forming an isolation cavity in the first wafer from the second surface side; wherein the first wafer comprises a stress isolation region and a first scribe lane region surrounding the periphery of the stress isolation region, the stress isolation region corresponding to the position of a chip region on the second wafer, the first scribe lane region corresponding to the position of a second scribe lane region on the second wafer, the stress isolation region comprising a first isolation region and a second isolation region surrounding the periphery of the first isolation region, the isolation groove being formed in the second isolation region, the through groove extending from the first scribe lane region to the first isolation region to communicate with the isolation groove, and the isolation cavity being formed in the first isolation region.

2. The method of claim 1, wherein: in the thickness direction of the first wafer, the projection of the isolation groove is annular around the periphery of the first isolation region, the projection of the through groove is annular around the periphery of the isolation groove, and the inner ring of the projection of the through groove overlaps the outer ring of the projection of the isolation groove.

3. The method of claim 1, wherein: the depth of the isolation groove accounts for 40% to 60% of the thickness of the first wafer.

4. The method of claim 1, wherein After forming the isolation groove and the through groove in the first wafer from the first surface side, the method further comprises: etching the first wafer through the isolation groove to form an expansion cavity, wherein in the thickness direction of the first wafer, the projection of the expansion cavity covers the projection of the isolation groove, and the projection area of the expansion cavity is larger than the projection area of the isolation groove.

5. The method of claim 1, wherein The forming of the isolation cavity in the first wafer from the second surface side comprises: forming a plurality of release holes in the first wafer from the second surface side, each of the plurality of release holes extending from the second surface to the first wafer, wherein each of the plurality of release holes is formed in the first isolation region; etching the first wafer through the release holes to form the isolation cavity, wherein in the thickness direction of the first wafer, the projection of each of the plurality of release holes is located within the projection of the isolation cavity.

6. The method of claim 5, wherein: the depth of the release hole accounts for 40% to 60% of the thickness of the first wafer.

7. The method of claim 5, wherein: after etching the first wafer through the release holes to form the isolation cavity, part of the remaining first wafer constitutes a first support structure, and the first support structure penetrates the isolation cavity.

8. The method of claim 5, wherein, after the first wafer is etched through the release hole to form the isolation cavity, a portion of the first wafer remaining forms a second support structure between the isolation trench and the isolation cavity.

9. The method of claim 1 or 8, wherein, the isolation trench is in communication with the isolation cavity, and the etching of the first wafer through the isolation trench to form the expansion cavity comprises: forming a first dielectric layer on all exposed surfaces of the first wafer; removing a portion of the first dielectric layer covering a bottom wall of the isolation trench, while leaving a portion of the first dielectric layer covering side walls and the bottom wall of the through trench, side walls of the isolation trench, and the first surface to form a first mask; and etching the first wafer through the isolation trench to form the expansion cavity using the first mask as a mask. the etching of the first wafer through the release hole to form the isolation cavity comprises: forming a second dielectric layer on all exposed surfaces of the first wafer; removing a portion of the second dielectric layer covering a bottom wall of the release hole, while leaving a portion of the second dielectric layer covering side walls of the release hole and the second surface to form a second mask; and etching the first wafer through the release hole to form the isolation cavity using the second mask as a mask. the method further comprises: providing a second wafer; bonding the first wafer and the second wafer, with the second wafer on a first surface side of the first wafer; performing a dicing process to form a plurality of semiconductor devices; and wherein a portion of the second wafer in the die area forms a die, and a portion of the first wafer in the stress isolation area forms a stress isolation structure corresponding to the die.

10. The method of claim 4, wherein: the stress isolation structure comprises: a first substrate comprising a first surface and a second surface opposite to each other, the first surface serving as a bonding surface for bonding with a die; an isolation trench extending from the first surface into the first substrate; a through trench extending from the first surface into the first substrate, the through trench having a depth less than a depth of the isolation trench; and an isolation cavity in the first substrate, an opening of the isolation cavity facing the second surface; wherein the first substrate comprises a stress isolation area corresponding to a position of the die, the stress isolation area comprising a first isolation area and a second isolation area surrounding an outer periphery of the first isolation area, the isolation trench being in the second isolation area, the through trench extending from a side of the second isolation area away from the first isolation area to the first isolation area to communicate with the isolation trench, and the isolation cavity being in the first isolation area.

14. The stress isolation structure of claim 13, wherein, ​ ​ 11. The method of claim 5, wherein: ​ ​ ​ ​ 12. A method of manufacturing a semiconductor device, characterized by, ​ ​ ​ ​ ​ 13. A stress isolation structure, characterized by, ​ ​ ​ ​ ​ ​ ​ In the thickness direction of the first substrate, a projection of the isolation groove is an annulus surrounding the outer periphery of the first isolation region, a projection of the through groove is an annulus surrounding the outer periphery of the isolation groove, and an inner annulus of the projection of the through groove overlaps with an outer annulus of the projection of the isolation groove.

15. The stress isolation structure of claim 13, wherein, The depth of the isolation groove accounts for 40% to 60% of the thickness of the first substrate.

16. The stress isolation structure of claim 13, wherein, Further comprising: An expansion cavity is located in the first substrate and communicates with the isolation groove through an end of the isolation groove away from the first surface; wherein, in the thickness direction of the first substrate, a projection of the expansion cavity covers a projection of the isolation groove, and the projection area of the expansion cavity is greater than the projection area of the isolation groove.

17. The stress isolation structure of claim 13, wherein, Further comprising: A plurality of release holes extend from the second surface into the first substrate and communicate with the isolation cavity; wherein, the plurality of release holes are all located in the first isolation region, and in the thickness direction of the first substrate, projections of the plurality of release holes are all located within the projection of the isolation cavity.

18. The stress isolation structure of claim 17, wherein, The depth of the release hole accounts for 40% to 60% of the thickness of the first substrate.

19. The stress isolation structure of claim 17, wherein, Part of the first substrate constitutes a first support structure, and the first support structure penetrates the isolation cavity.

20. The stress isolation structure of claim 17, wherein, Part of the first substrate constitutes a second support structure, and the second support structure is located between the isolation groove and the isolation cavity.

21. The stress isolation structure of claim 13 or 20, wherein, The isolation groove communicates with the isolation cavity.

22. A stress isolated wafer, characterized by A plurality of stress isolation structures as claimed in any one of claims 13 to 21 are included.

23. A semiconductor device, characterized by comprising: A semiconductor device including a stress isolation structure as claimed in any one of claims 13 to 21 and a chip; or, prepared by the preparation method of the semiconductor device as claimed in claim 12.

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