Constant on-time control system

Abstract

The invention discloses a constant turn-on time control system, which comprises an upper tube turn-on time control module used for sending an upper tube turn-off instruction and receiving a feedback signal of a lower-stage module; the superaudio frequency control module is used for receiving an instruction sent by the upper tube conduction time control module, sending an instruction for controlling a lower tube to be opened or closed and feeding back the instruction to the upper tube conduction time control module; and the feedback module is used for receiving a feedback signal of the output voltage of the control system and sending an upper tube opening instruction to the superaudio frequency control module. The output voltage is discharged in advance in the lower tube driving operation, and the upper tube conduction time is dynamically adjusted, so that the upper tube conduction time of each period is gradually reduced, the power conversion efficiency is effectively optimized on the premise of keeping stable operation and output voltage precision, the steady-state operation of the system is ensured, and the power conversion efficiency is improved. And output voltage ripples under light-load and no-load conditions are obviously reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits and relates to a constant on-time control system. Background Art

[0002] Traditional buck (BUCK) circuits based on the COT (Constant On-Time) architecture exhibit significant technical drawbacks under light-load conditions: their switching frequency can drop sharply into the audio-sensitive range (20Hz-20kHz), causing audible noise in inductive or capacitive components. The core mechanism of this phenomenon stems from the interaction between the inherent characteristics of the COT control mode and light-load operation. When the load current is too low, the energy supply required to maintain the output voltage is sharply reduced. At this point, the COT controller triggers a pulse skipping mode, directly causing the switching frequency to drop to several kilohertz or even lower. Compared to voltage-mode or current-mode circuits, which maintain a minimum frequency through a fixed clock reference, the traditional COT architecture lacks a mandatory lower frequency limit, and its switching cycle is completely subject to the transient response of real-time load fluctuations and ripple voltage.

[0003] In conventional technical solutions, in order to prevent the switching frequency from dropping to audio frequency under light load or no-load conditions, a strategy is usually adopted to pre-apply a forced conduction drive signal to the lower tube before the upper tube is turned on and maintain a preset pulse width. This forced conduction stage enables the power circuit to form an effective discharge path, and the excess charge accumulated in the output capacitor can be quickly discharged through the conduction circuit. When the load current drops to the critical threshold, the system switches the upper tube turn-on timing to a fixed-width modulation mode with a fixed frequency above 20kHz. However, this rigid switching mechanism is prone to periodic fluctuations in the output voltage. If the forced conduction control of the lower tube is simply applied without the dynamic adjustment of the upper tube turn-on time, the ripple amplitude of the system output voltage will increase significantly, and the system efficiency will be significantly reduced. Summary of the Invention

[0004] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a constant on-time control system. Under light-load or no-load conditions, the system pre-discharges the output voltage during the lower tube driving operation and dynamically adjusts the on-time of the upper tube. By periodically shortening the on-time of the upper tube of the power device, it is ensured that the on-pulse width decreases according to a predetermined ratio after each number of switching cycles. While maintaining stable operation and output voltage accuracy, the power conversion efficiency is effectively optimized, which not only ensures the steady-state operation of the system, but also significantly reduces the output voltage ripple under light-load and no-load conditions.

[0005] To achieve the above object, the present invention is implemented by adopting the following technical solutions: A constant on-time control system, comprising an upper tube, a lower tube, an inductor, and an output capacitor, wherein one end of the inductor is connected between the source of the upper tube and the drain of the lower tube, and the other end of the inductor is connected to the output capacitor. The system also includes a feedback module, an upper tube on-time control module, and an ultrasonic frequency control module. The feedback module is used to monitor the output voltage of the control system; when the feedback voltage used to monitor the output voltage is lower than the reference voltage, the feedback module outputs a control signal to turn on the upper tube to the super audio control module; the feedback module is connected to the output capacitor and the super audio control module respectively; The super-audio control module is used to process and output a control signal from the upper tube conduction time control module to drive the upper tube to be turned on or off, delay the output of a control signal to drive the lower tube to be turned on, and output a control signal to drive the lower tube to be turned off, and feed back the output control signal of the upper tube, the control signal of the lower tube, or a state representation signal to the upper tube conduction time control module; when the feedback voltage is continuously higher than the reference voltage for a preset time period, output a control signal to drive the lower tube to be turned on; when the voltage at the end of the inductor element is greater than a preset voltage, or when the feedback voltage is lower than the reference voltage, output a control signal to drive the lower tube to be turned off; the super-audio control module is connected to the upper tube conduction time control module, and the super-audio control module is externally connected to a zero-crossing detector; The upper tube on-time control module is used to receive and process the upper tube or lower tube drive state feedback signal and the voltage signal from the end of the inductor element to control the on-time of the upper tube within the switching cycle. When the feedback voltage is higher than the reference voltage, the upper tube on-time control module receives and processes the signal, and after processing, outputs a control signal to shut down the upper tube to the super audio control module; the upper tube on-time control module is connected to the inductor element.

[0006] Optionally, a power tube control module is further included, which is used to process the control signal from the super audio control module, output the driving signal for turning on or off the upper tube and the lower tube, and feed back the driving signal for turning on or off the lower tube to the upper tube conduction time control module; the super audio control module is respectively connected to the upper tube and the lower tube through the power tube control module, and the power tube control module is connected to the upper tube conduction time control module.

[0007] Optionally, the power tube control module includes a first NAND gate, a second NAND gate, a fifth inverter, a sixth inverter and a gate drive circuit, the super audio control module is respectively connected to the input end of the first NAND gate, the input end of the fifth inverter and one input end of the second NAND gate, the output end of the first NAND gate is connected to the other input end of the second NAND gate, the input end of the sixth inverter is connected to the output end of the second NAND gate, the output end of the sixth inverter and the output end of the fifth inverter are respectively connected to the input end of the gate drive circuit, the output end of the gate drive circuit is respectively connected to the gate of the upper tube and the gate of the lower tube, and the upper tube conduction time control module is respectively connected to the output end of the sixth inverter and the output end of the fifth inverter.

[0008] Optionally, the upper tube conduction time control module includes a sampling filter circuit, an upper tube conduction time reference voltage generating circuit, a first comparator, a first capacitor, a first current source, and a first transistor. The sampling filter circuit is connected to the upper tube conduction time reference voltage generating circuit, the upper tube conduction time reference voltage generating circuit is connected to the inverting input terminal of the first comparator, the drain of the first transistor is respectively connected to the non-inverting input terminal of the first comparator, the first current source and one end of the first capacitor, and the source of the first transistor and the other end of the first capacitor are grounded.

[0009] Optionally, the sampling filter circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fourth capacitor and a fifth capacitor, one end of the first resistor is respectively connected to the source of the upper tube, the drain of the lower tube and the inductor element, the other end of the first resistor is respectively connected to one end of the second resistor and the third resistor, the other end of the third resistor is respectively connected to one end of the fourth capacitor and the fourth resistor, and the other end of the fourth resistor is connected to the fifth capacitor.

[0010] Optionally, the upper tube conduction time reference voltage generating circuit includes a seventh inverter, an eighth inverter, a ninth inverter, a tenth inverter, a third D flip-flop, a first AND gate, a fifth resistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a counter, and a sixth resistor. The input end of the seventh inverter is connected to the power tube control module, the output end of the seventh inverter is respectively connected to the input end of the eighth inverter, the sixth capacitor, and the tenth capacitor. The output end of the eighth inverter is respectively connected to the gate of the sixth transistor, the gate of the fourth transistor, and the reset end of the third D flip-flop. The data input end of the third D flip-flop is externally connected to a positive power supply voltage. The clock input end of the third D flip-flop is connected to the super audio control module. The output end of the third D flip-flop is connected to the input end of the ninth inverter. The output end of the ninth inverter is connected to an input end of the first AND gate. The other input end of the first AND gate is connected to the power tube control module, the output end of the first AND gate is connected to the gate of the fifth transistor, one end of the fifth resistor is connected to the fourth resistor and the fifth capacitor respectively, the other end of the fifth resistor is connected to the source of the fourth transistor, the drain of the fourth transistor is connected to the sixth capacitor, the seventh capacitor and the source of the fifth transistor respectively, the drain of the fifth transistor is connected to the eighth capacitor, the inverting input end of the first comparator and the drain of the seventh transistor respectively, the input end of the tenth inverter is connected to the super audio control module, the output end of the tenth inverter is connected to one end of the counter, the other end of the counter is connected to the gate of the seventh transistor, one end of the sixth resistor is connected to an external reference voltage, the other end of the sixth resistor is connected to the ninth capacitor and the source of the sixth transistor respectively, and the drain of the sixth transistor is connected to the tenth capacitor, the eleventh capacitor and the source of the seventh transistor respectively.

[0011] Optionally, the super audio control module includes a first D flip-flop, a first NOR gate, a second NOR gate, a first inverter and a delay circuit for delaying signal transmission, the reset end of the first D flip-flop is connected to the upper tube conduction time control module, the clock input end of the first D flip-flop is connected to the feedback module, the data input end of the first D flip-flop is externally connected to a positive power supply voltage, the output end of the first D flip-flop is respectively connected to the upper tube conduction time control module, the input end of the first inverter and the power tube control module, the output end of the first inverter is connected to an input end of the second NOR gate, the other input end of the second NOR gate is connected to the output end of the first NOR gate, one input end of the first NOR gate is externally connected to a zero-crossing detection, the output end of the second NOR gate is respectively connected to the other input end of the first NOR gate, the input end of the delay circuit and the power tube control module, and the output end of the delay circuit is connected to the power tube control module.

[0012] Optionally, the delay circuit includes a second inverter, a first buffer, a third inverter, a delay unit, a second D flip-flop and a fourth inverter, the output end of the second NOR gate is connected to the input end of the second inverter, the output end of the second inverter is respectively connected to the reset end of the delay unit and the second D flip-flop, the input end of the first buffer is connected to the delay unit, the output end of the first buffer is respectively connected to the upper tube conduction time control module and the input end of the third inverter, the output end of the third inverter is connected to the delay unit, the data input end of the second D flip-flop is externally connected to the positive power supply voltage, the clock input end of the second D flip-flop is connected to the delay unit, the output end of the second D flip-flop is connected to the input end of the fourth inverter, and the output end of the fourth inverter is connected to the power tube control module.

[0013] Optionally, the delay time of the delay unit is 28μs~50μs; The delay unit includes a first delay unit and a second delay unit, the first delay unit includes a second transistor, a second current source and a second capacitor, the second current source is connected to the drain of the second transistor and one end of the second capacitor respectively, and the source of the second transistor and the other end of the second capacitor are grounded; The second delay unit includes a third transistor, a third current source and a third capacitor. The gate of the third transistor is connected to the output end of the third inverter, the drain of the third transistor is respectively connected to the third current source, one end of the third capacitor and the clock input end of the second D flip-flop, and the source of the third transistor and the other end of the third capacitor are grounded.

[0014] Optionally, the feedback module includes a feedback circuit and a second comparator, the input end of the feedback circuit is connected to the output end of the control system, the output end of the feedback circuit is connected to the inverting input end of the second comparator, the non-inverting input end of the second comparator is externally connected to a reference voltage, and the output end of the second comparator is connected to the ultrasonic control module.

[0015] Compared with the prior art, the present invention has the following beneficial effects: The present invention provides a constant on-time control system. An upper tube on-time control module is connected to an inductor element and is used to issue an upper tube off instruction and receive feedback signals from a lower-level module. The upper tube on-time control module generates a gate drive signal to cause the upper tube on-time to exhibit an intermittent periodic reduction characteristic, thereby effectively improving the stability of the output voltage, reducing the output voltage ripple, and improving the system's operating efficiency. The super-audio control module establishes connections with the upper tube conduction time control module and the zero-crossing detection unit. By receiving the drive instructions from the upper tube conduction time control module, this module generates the lower tube opening and closing control instructions and feeds back the instruction status to the upper tube conduction time control module. This module can avoid audio interference and force the drive activation signal of the lower tube to turn on, accurately triggering the output voltage circuit for rapid discharge. The feedback module is electrically connected to the capacitor element and the super audio control module respectively. The module triggers the upper tube conduction control instruction to the super audio control module by collecting the feedback signal of the control system output voltage in real time; This invention effectively optimizes the operating characteristics of a step-down (BUCK) circuit based on a constant on-time (COT) architecture under light-load and no-load conditions. It activates the lower tube to dissipate excess energy, while employing a progressive on-time reduction strategy to dynamically stabilize the system switching frequency above the audio frequency, effectively preventing the switching frequency from dropping into the audio range. The invention achieves continuous attenuation of the output ripple amplitude by proportionally reducing the on-time of the upper tube during each cycle. Furthermore, the linear reduction mechanism for the upper tube's conduction loss significantly improves overall system efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic diagram of a constant on-time control system according to an embodiment of the present invention; Figure 2 A schematic diagram of an upper tube on-time control module of a constant on-time control system according to an embodiment of the present invention; Figure 3 A schematic diagram of a sampling filter circuit and an upper tube on-time reference voltage generating circuit of a constant on-time control system according to an embodiment of the present invention; Figure 4 A schematic diagram of an ultrasonic audio control module of a constant on-time control system according to an embodiment of the present invention; Figure 5 A schematic diagram of a delay circuit of a constant on-time control system according to an embodiment of the present invention; Figure 6 A schematic diagram of a power tube control module of a constant on-time control system according to an embodiment of the present invention; Figure 7 Schematic diagram of a constant on-time control system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0017] The present invention will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present invention.

[0018] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, features defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0019] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances. Example 1

[0020] like Figures 1 to 7As shown, a constant on-time control system includes an upper tube MUP, a lower tube MDOWN, an inductor L1, and an output capacitor C0. One end of the inductor L1 is connected to the source of the upper tube MUP and the drain of the lower tube MDOWN, respectively. The source of the upper tube MUP generates a voltage signal PHASE, the drain of the upper tube MUP is connected to a power supply, and the source of the lower tube MDOWN is grounded. The other end of the inductor L1 is connected to the output capacitor C0, and an output voltage VOUT is output. The control system also includes an upper tube on-time control module, an ultrasonic audio control module, a power tube control module, and a feedback module.

[0021] The feedback module is used to monitor the output voltage VOUT of the control system. When the feedback voltage FB used to monitor the output voltage VOUT is lower than the reference voltage VREF, the feedback module outputs a control signal to turn on the upper tube MUP to the super audio control module. The feedback module is connected to the output capacitor C0 and the super audio control module respectively.

[0022] The feedback module includes a feedback circuit and a second comparator PWM_COMP. The feedback circuit is a prior art and will not be described in detail here. The feedback voltage FB output by the feedback circuit is a divided voltage of the output voltage VOUT. The input end of the feedback circuit is connected to the output voltage VOUT of the output end of the control system. The output end of the feedback circuit outputs the feedback voltage FB and is connected to the inverting input end of the second comparator PWM_COMP. The non-inverting input end of the second comparator PWM_COMP is externally connected to the reference voltage VREF. The output end of the second comparator PWM_COMP outputs a signal PWM and is connected to the clock input end CP of the first D flip-flop DFF1.

[0023] The upper tube on-time control module is used to receive and process the upper tube MUP or lower tube MDOWN drive state feedback signal and the voltage signal PHASE from the end of the inductor element L1 to control the on-time of the upper tube MUP during the switching cycle. When the feedback voltage FB is higher than the reference voltage VREF, the upper tube on-time control module receives and processes the signal and, after processing, outputs a control signal to shut down the upper tube MUP to the super audio control module. The upper tube on-time control module is connected to the left end of the inductor element L1.

[0024] The upper tube on-time control module includes a sampling and filtering circuit, an upper tube on-time reference voltage generating circuit, a first comparator TON_COMP, a first capacitor C1, a first current source I_VIN, and a first transistor MN1. The output end of the sampling and filtering circuit is connected to the input end of the upper tube on-time reference voltage generating circuit, and the output end signal VREF_TON of the upper tube on-time reference voltage generating circuit is connected to the inverting input end of the first comparator TON_COMP. The drain of the first transistor MN1 is respectively connected to the non-inverting input end of the first comparator TON_COMP, the first current source I_VIN and one end of the first capacitor C1. The source of the first transistor MN1 and the other end of the first capacitor C1 are grounded. The signal received by the non-inverting input end of the first comparator TON_COMP is VRAMP, and the output end of the first comparator TON_COMP outputs the TON_CLK signal.

[0025] The sampling filter circuit includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fourth capacitor C4, and a fifth capacitor C5. One end of the first resistor R1 is connected to the source of the upper tube MUP, the drain of the lower tube MDOWN, and the inductor L1, respectively. One end of the first resistor R1 receives a feedback signal PHASE. The other end of the first resistor R1 is connected to one end of the second resistor R2 and one end of the third resistor R3, respectively. The other end of the second resistor R2 is grounded. The other end of the third resistor R3 is connected to one end of the fourth capacitor C4 and one end of the fourth resistor R4, respectively. The other end of the fourth resistor R4 is connected to one end of the fifth capacitor C5. The other ends of the fourth capacitor C4 and the fifth capacitor C5 are grounded.

[0026] The upper tube conduction time reference voltage generating circuit includes a seventh inverter INV7, an eighth inverter INV8, a ninth inverter INV9, a tenth inverter INV10, a third D flip-flop DFF3, a first AND gate AND1, a fifth resistor R5, a fourth transistor MN4, a fifth transistor MN5, a sixth transistor MN6, a seventh transistor MN7, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, an eleventh capacitor C11, a counter 8-DIV and a sixth resistor R6.The input end of the seventh inverter INV7 is connected to the CLK_LG signal output by the power tube control module, and the output end of the seventh inverter INV7 is respectively connected to the input end of the eighth inverter INV8, the sixth capacitor C6 and the tenth capacitor C10; the output end of the eighth inverter INV8 is respectively connected to the gate of the sixth transistor MN6, the gate of the fourth transistor MN4 and the reset end CLR of the third D flip-flop DFF3, the data input end D of the third D flip-flop DFF3 is externally connected to the positive power supply voltage VCC, the clock input end CP of the third D flip-flop DFF3 is connected to the SKIPD signal of the super audio control module, and the output end Q of the third D flip-flop DFF3 is connected to the ninth inverter The input end of the ninth inverter INV9 is connected to the input end of the first AND gate AND1, the other input end of the first AND gate AND1 is connected to the CLK_UG signal output by the power tube control module, and the output end of the first AND gate AND1 is connected to the gate of the fifth transistor MN5; one end of the fifth resistor R5 is connected to the fourth resistor R4 and the fifth capacitor C5 respectively, the other end of the fifth resistor R5 is connected to the source of the fourth transistor MN4, the drain of the fourth transistor MN4 is connected to the sixth capacitor C6, the seventh capacitor C7 and the source of the fifth transistor MN5 respectively, and the seventh capacitor C7 is grounded; the drain of the fifth transistor MN5 is connected to the eighth capacitor C6 and the eighth capacitor C7 respectively. 8. The inverting input terminal of the first comparator TON_COMP is connected to the drain of the seventh transistor MN7, the eighth capacitor C8 is grounded, and the eighth capacitor C8 is connected to the output terminal VREF_TON signal of the upper tube conduction time reference voltage generating circuit; the input terminal of the tenth inverter INV10 is connected to the SONIC signal output by the super audio control module, the output terminal of the tenth inverter INV10 is connected to one end of the counter 8-DIV, and the other end of the counter 8-DIV is connected to the gate of the seventh transistor MN7. Four SONIC signals will turn on the MN7 tube once; one end of the sixth resistor R6 is connected to the external reference voltage VREF_MIN, and the other end of the sixth resistor R6 is respectively connected to the reference voltage VREF_MIN. The ninth capacitor C9 is connected to the source of the sixth transistor MN6, and the ninth capacitor C9 is grounded; the drain of the sixth transistor MN6 is respectively connected to the tenth capacitor C10, the eleventh capacitor C11 and the source of the seventh transistor MN7; the high-side tube on-time (Ton) reference voltage generation circuit implements an automatic switching mechanism between two operating modes: a standard Ton reference mode under normal working conditions; and an adaptive Ton reference mode with a slowly decreasing high-side tube on-time when the ultra-high frequency protection mechanism is triggered; by gradually reducing the high-side tube on-time reference voltage, that is, the VREF_TON signal, the rising edge of TON_CLK arrives earlier, thereby gradually shortening the high-side tube on-time.

[0027] The super audio frequency control module is used to process and output the control signal for driving the upper tube MUP to turn on or off from the upper tube conduction time control module, delay the output of the control signal for driving the lower tube MDOWN to turn on, and output the control signal for driving the lower tube MDOWN to turn off, and feed back the output control signal of the upper tube MUP, the control signal of the lower tube MDOWN or the state characterization signal to the upper tube conduction time control module; when the feedback voltage FB is continuously higher than the reference voltage VREF for a preset time, the control signal for driving the lower tube MDOWN to turn on is output, and the preset time is the delay time in the super audio frequency control module; when the voltage at the end of the inductor element L1 is -2mV, or when the feedback voltage FB is lower than the reference voltage VREF, the control signal for driving the lower tube MDOWN to turn off is output. The super-audio control module is connected to the upper tube conduction time control module. The super-audio control module is externally connected to zero-crossing detection. Zero-crossing detection is an existing technology and will not be described in detail here. The super-audio control module can generate a super-audio avoidance signal (SONIC), which realizes a controlled discharge operation of the output voltage VOUT by forcibly turning on the lower tube MDOWN drive circuit.

[0028] The super audio logic control circuit includes a first D flip-flop DFF1, a first NOR gate NOR1, a second NOR gate NOR2, a first inverter INV1, and a delay circuit for delaying signal transmission. The reset terminal CLR of the first D flip-flop DFF1 is connected to the TON_CLK signal emitted by the first comparator TON_COMP. The clock input terminal CP of the first D flip-flop DFF1 is connected to the PWM signal fed back by the feedback module. The data input terminal D of the first D flip-flop DFF1 is externally connected to the positive power supply voltage VDD. The output terminal Q‾ of the first D flip-flop DFF1 outputs the G_CTRL signal respectively connected to the G_CTRL signal of the first transistor MN1. The gate is connected, the input end of the first inverter INV1 is connected to the power tube control module; the output end of the first inverter INV1 is connected to one input end of the second NOR gate NOR2, and the other input end of the second NOR gate NOR2 is connected to the output end of the first NOR gate NOR1; one input end of the first NOR gate NOR1 is externally connected to the zero-crossing detection output signal ZCD_OUT, and the output end of the second NOR gate NOR2 outputs a SKIP signal which is respectively connected to the other input end of the first NOR gate NOR1, the input end of the delay circuit, and the power tube control module; the output end of the delay circuit outputs a SONIC signal which is connected to the power tube control module.

[0029] The delay circuit includes a second inverter INV2, a first buffer BUF1, a third inverter INV3, a delay unit, a second D flip-flop DFF2, and a fourth inverter INV4. The output of the second NOR gate NOR2 outputs a SKIP signal connected to the input of the second inverter INV2. The output of the second inverter INV2 is connected to the reset terminal CLR of the delay unit and the second D flip-flop DFF2, respectively. A first delay unit is provided between the second inverter INV2 and the first buffer BUF1, and a second delay unit is provided between the third inverter INV3 and the second D flip-flop DFF2. The first delay unit includes a second transistor MN2, a second current source I2 and a second capacitor C2, and the second delay unit includes a third transistor MN3, a third current source I3 and a third capacitor C3. The first delay unit and the second delay unit are respectively set to a delay of 14 μs; the gate of the second transistor MN2 is connected to the output end of the second inverter INV2, the second current source I2 is respectively connected to the drain of the second transistor MN2, the input end of the first buffer BUF1 and one end of the second capacitor C2, the source of the second transistor MN2 is grounded, and the other end of the second capacitor C2 is grounded, the output end of the first buffer BUF1 outputs a SKIPD signal which is respectively connected to the clock input end CP of the third D flip-flop and the input end of the third inverter INV3, and the output of the third inverter INV3 The first terminal is connected to the gate of the third transistor MN3, the drain of the third transistor MN3 is respectively connected to the third current source I3, one end of the third capacitor C3 and the clock input terminal CP of the second D-type flip-flop DFF2, the source of the third transistor MN3 and the other end of the third capacitor C3 are grounded, the data input terminal D of the second D-type flip-flop DFF2 is externally connected to the positive power supply voltage VCC, the output terminal Q of the second D-type flip-flop DFF2 is connected to the input terminal of the fourth inverter INV4, the output terminal of the fourth inverter INV4 outputs the SONIC signal and is connected to the power tube control module; the input signal of the delay circuit is SKIP, and the output signal is SONIC. When SKIP flips from a low level to a high level, the rising edge of SKIPD will be delayed by 14μs compared to the rising edge of SKIP, and the falling edge of SONIC will be delayed by 28μs compared to the rising edge of SKIP. The delay circuit has a simple structure and can generate a relatively fixed delay time.

[0030] The power tube control module is used to process the control signal from the super audio control module, output the driving signal for turning on or off the upper tube MUP and the lower tube MDOWN, and feed back the driving signal for turning on or off the lower tube MDOWN to the upper tube conduction time control module; the super audio control module is connected to the upper tube MUP and the lower tube MDOWN respectively through the power tube control module, and the power tube control module is connected to the upper tube conduction time control module.

[0031] The power tube control module includes a first NAND gate NAND1, a second NAND gate NAND2, a fifth inverter INV5, a sixth inverter INV6 and a gate drive circuit. The gate drive circuit is a prior art and will not be described in detail here. One end of the first NAND gate NAND1 is connected to the output end of the fourth inverter INV4 to output the SONIC signal, the other end of the first NAND gate NAND1 is connected to the output end of the second NOR gate NOR2 to output the SKIP signal, the input end of the fifth inverter INV5 and one input end of the second NAND gate NAND2 are respectively connected to the G_CTRL signal outputted by the output end Q‾ of the first D flip-flop, the output end of the first NAND gate NAND1 is connected to the other end of the second NAND gate NAND2 The input end of the sixth inverter INV6 is connected to the output end of the second NAND gate NAND2, the output end output CLK_LG signal of the sixth inverter INV6 and the output end output CLK_UG signal of the fifth inverter INV5 are respectively connected to the input end of the gate drive circuit, the other input end of the first AND gate AND1 is connected to the output end output CLK_UG signal of the fifth inverter INV5, the input end of the seventh inverter INV7 is connected to the output end output CLK_LG signal of the sixth inverter INV6, the output end of the gate drive circuit outputs the UGATE signal connected to the gate of the upper tube MUP, and the output end of the gate drive circuit outputs the LGATE signal connected to the gate of the lower tube MDOWN. Example 2

[0032] like Figures 1 to 7 As shown, based on the first embodiment, this embodiment provides a constant on-time control system, in which the first delay unit and the second delay unit are respectively set to a delay of 25μs; the input signal of the delay circuit is SKIP, and the output signal is SONIC. When SKIP flips from a low level to a high level, the rising edge of SKIPD will be delayed by 25μs compared to the rising edge of SKIP, and the falling edge of SONIC will be delayed by 50μs compared to the rising edge of SKIP. The delay circuit has a simple structure and can generate a relatively fixed delay time. Example 3

[0033] like Figures 1 to 7 As shown, based on the first embodiment, this embodiment provides a constant on-time control system, in which the first delay unit and the second delay unit are respectively set to a delay of 15μs; the input signal of the delay circuit is SKIP, and the output signal is SONIC. When SKIP flips from a low level to a high level, the rising edge of SKIPD will be delayed by 15μs compared to the rising edge of SKIP, and the falling edge of SONIC will be delayed by 30μs compared to the rising edge of SKIP. The delay circuit has a simple structure and can generate a relatively fixed delay time.

[0034] The working method of this embodiment is as follows: When the load is light and the super audio function is not triggered, the upper tube MUP turns on: When the feedback voltage FB of the feedback circuit is lower than the VREF voltage, the output signal PWM of the second comparator PWM_COMP is high. After passing through the first D-type flip-flop DFF1, the output signal G_CTRL of the output terminal Q‾ is low. The G_CTRL signal passes through the fifth inverter INV5, causing the CLK_UG signal to be high. Then, through the gate drive circuit, the UGATE signal is high, turning on the upper tube MUP. At the same time, the G_CTRL signal passes through the first inverter INV1 and the second NOR gate NOR2, causing the SKIP signal to be low. After the upper tube MUP turns on, it connects to the power supply and begins to replenish energy for the output voltage VOUT. When the FB signal voltage exceeds the VREF voltage, the PWM signal is low. The high-side switch MUP turns off and the low-side switch MDOWN turns on: When the FB voltage is higher than the VREF voltage, the PWM signal is low. In the previous phase, after the G_CTRL signal is low, the first transistor MN1 in the high-side switch on-time control circuit turns off. The first current source I_VIN, which is positively correlated with the power supply voltage at the high-side switch MUP, charges the first capacitor C1. When the voltage on the first capacitor C1 exceeds VREF_TON (the formula for the high-side switch MUP on-time is: t = (C1*VREF_TON) / I_VIN, where C1 is the capacitance of the first capacitor, VREF_TON is the output level of the high-side switch on-time reference voltage generation circuit, and I_VIN is the output current of the first current source), the output signal TON_CLK of the first comparator TON_COMP goes high. The first trigger DFF1 drives the G_CTRL signal high, turning on the first transistor MN1. This rapidly discharges the first capacitor C1, pulling the VRAMP voltage down and causing the TON_CLK signal to go low. After the G_CTRL signal is high, it passes through the fifth inverter INV5, making CLK_UG low, UGATE low, and the upper tube MUP off. At the same time, the G_CTRL signal passes through the second NAND gate NAND2 and the sixth inverter INV6, making CLK_LG high, LGATE high, and the lower tube MDOWN on. Turning off the lower transistor MDOWN: When the lower transistor MDOWN turns on, the current in the inductor L1 continues to flow through the lower transistor MDOWN. The voltage at the feedback signal PHASE terminal gradually increases from a negative voltage and approaches 0V. When it approaches 0V (-2mV), the zero-crossing detection output signal ZCD_OUT is high. At this time, because G_CTRL is low, the zero-crossing detection output signal ZCD_OUT is high. After passing through the first NOR gate NOR1 and the second NOR gate NOR2, the SKIP signal is high. The SKIP signal passes through the first NAND gate NAND1, the second NAND gate NAND2, and the sixth inverter INV6, causing the CLK_LG signal to go low. The LGATE signal is also low, turning off the lower transistor MDOWN. The current in the inductor L1 continues to flow through the body diode of the lower transistor MDOWN.

[0035] When the super audio function is triggered under extremely light load or no load, the upper tube MUP is turned on: when the FB signal voltage is less than VREF, the PWM signal output by the comparator is high, the G_CTRL signal is low, the CLK_LG signal is low, the CLK_UG signal is high, the SKIP signal is low, and SONIC is controlled to a high level by the SKIP signal. The first current source I_VIN starts to charge the first capacitor C1. At this time, the UGATE signal is controlled by the CLK_UG signal, so that the UGATE signal is high and the upper tube MUP is turned on; The upper tube MUP is turned off and the lower tube MDOWN is turned on for the first time: When the FB signal voltage is less than the VREF voltage, the PWM signal is low. The G_CTRL signal is low, and the first current source I_VIN charges the first capacitor C1. When the voltage on the first capacitor C1 exceeds the VREF_TON signal (the upper tube MUP turn-on time formula is: t = (C1 * VREF_TON) / I_VIN, where C1 is the capacitance of the first capacitor, VREF_TON is the output voltage of the upper tube on-time reference voltage generation circuit, and I_VIN is the output current of the first current source), the TON_CLK signal is high, the G_CTRL signal is high, the CLK_UG signal is low, the CLK_LG signal is high, the UGATE signal is low, and the LGATE signal is high). At this time, the upper tube MUP is turned off and the lower tube MDOWN is turned on for the first time.

[0036] The first time the lower MDOWN is turned off: When the lower MDOWN is turned on, the current in the inductor L1 continues to flow through the lower MDOWN. The voltage at the feedback signal PHASE terminal gradually increases from negative to approaching 0V. When PHASE approaches 0V (-2mV), the ZCD_OUT signal is high. At this time, because the G_CTRL signal is low, the high ZCD_OUT signal causes the SKIP signal to be high, the CLK_LG signal to be low, and the LGATE signal to be low. The lower MDOWN is turned off, and the current in the inductor L1 continues to flow through the body diode of the lower MDOWN.

[0037] The second turn-on of the lower tube MDOWN: When the zero-crossing detection function is triggered and the lower tube MDOWN is turned off for the first time, the SKIP signal is high. Since the load is extremely light, the output voltage VOUT discharges very slowly, the FB signal voltage continues to be higher than VREF, the PWM signal continues to be high, and the upper tube MUP is always in the cut-off state. When the zero-crossing detection tube MDOWN is triggered to turn off, the SKIP signal is at a high level. The SKIP signal turns off the second transistor MN2 through the second inverter INV2, and the second current source I2 charges the second capacitor C2. (Delay time t=(C2*V2) / I2, where V2 is the flip level of the first buffer BUF1. After a delay of 15μs, the SKIPD signal is at a high level. The SKIPD signal turns off the third transistor MN3 through the third inverter INV3, and the third current source I3 charges the third capacitor C3. After a delay of 15μs, the SONIC signal is at a low level through the second D flip-flop DFF2 and the fourth inverter INV4. The SONIC signal is connected to the first NAND gate NAND1 and the second NAND gate NAND2. The sixth inverter INV6 drives the LGATE signal high, forcing the lower transistor MDOWN to turn on, discharging the output voltage VOUT and rapidly dropping the FB voltage below VREF. After a 30μs (15μs + 15μs) delay, the lower transistor MDOWN is forced on, discharging the output voltage VOUT and rapidly dropping the FB voltage below VREF. This 30μs delay determines the system's minimum operating frequency to approximately 30kHz (frequency f = 1 / T, where T is the switching period of the upper transistor MUP). The delay time parameter can be adjusted adaptively within a reasonable range, but the system operating frequency must be strictly maintained above 20kHz to avoid audible noise and below the 35kHz threshold to prevent chip efficiency degradation.

[0038] The second shutdown of the lower tube MDOWN: When the lower tube MDOWN is turned on for the second time to discharge the output voltage VOUT, the FB voltage gradually decreases. When the FB voltage is lower than VREF, the PWM signal output by the comparator is high, the G_CTRL signal is low, the CLK_LG signal is low, and the CLK_UG signal is high. At this time, the lower tube MDOWN is turned off and the upper tube MUP is turned on.

[0039] When the super audio frequency SONIC function is not triggered, the VREF_TON voltage is generated: In the high-side transistor on-time control module, when the SONIC function is not triggered, the CLK_LG, SKIPD, and CLK_UG signals, controlled by the combinatorial logic of the seventh inverter INV7, the eighth inverter INV8, the ninth inverter INV9, the first AND gate AND1, and the third D-type flip-flop DFF3, keep the fifth transistor MN5 in the on state. The voltage at the PHASE terminal is divided by the first resistor R1 and the second resistor R2, and then passes through two stages of RC filtering (third resistor R3, fourth capacitor C4 and fourth resistor R4, fifth capacitor C5). Finally, it passes through the fourth transistor MN4 and the fifth transistor MN5 to output the VREF_TON signal.

[0040] When the super audio frequency SONIC is triggered, the VREF_TON voltage decreases: When the SONIC function is triggered, the CLK_LG, SKIPD, and CLK_UG signals, under the combined logic control of the seventh inverter INV7, the eighth inverter INV8, the ninth inverter INV9, the first AND gate AND1, and the third D-flip-flop DFF3, keep the fifth transistor MN5 permanently off. The SONIC signal, passing through the tenth inverter INV10 and the counter 8-DIV, periodically turns on the seventh transistor MN7. (The SONIC signal turns on the seventh transistor MN7 once every 4 to 16 times. In this embodiment, the SONIC signal turns on once every 8 times. If the SONIC signal turns on once less than 4 times, the upper transistor's on-time decreases too quickly, affecting the stability of the output voltage VOUT. If the SONIC signal turns on once every 16 times, the upper transistor's on-time reference voltage decreases too slowly, resulting in long-term large ripple in the output voltage VOUT and slowing system efficiency improvement.) Simultaneously, CLK_LG discharges the eleventh capacitor C11 through the tenth capacitor C10. As the SONIC function continues to be triggered, the charge stored on the eighth capacitor C8 gradually decreases, and the VREF_TON voltage gradually decreases. As VREF_TON gradually decreases, the first current source I_VIN charges the first capacitor C1, and the generated voltage VRAMP will reach the VREF_TON voltage value in a shorter time, making TON_CLK a high level. Therefore, the conduction time of the upper tube gradually decreases.

[0041] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A constant on-time control system, comprising an upper tube, a lower tube, an inductor, and an output capacitor, wherein one end of the inductor is connected between the source of the upper tube and the drain of the lower tube, and the other end of the inductor is connected to the output capacitor, characterized in that: include: An upper tube conduction time control module, used to control the conduction time of the upper tube within a switching cycle; Outputting a control signal for shutting down the upper tube according to a driving state feedback signal of the upper tube or the lower tube received from a downstream module and a voltage signal from an end of the inductor element; A feedback module is used to monitor the output voltage of the control system; and output a control signal for turning on the upper tube according to the feedback of the monitored output voltage; The super audio frequency control module is used to receive and process the shutdown control signal from the upper tube conduction time control module and the conduction control signal from the feedback module, and output a control signal to drive the upper tube and the lower tube to be turned on or off, so that the conduction states of the upper tube and the lower tube are mutually exclusive.

2. The constant on-time control system according to claim 1, characterized in that: It also includes a power tube control module for processing the control signal from the super audio control module, outputting the driving signal for turning on or off the upper tube and the lower tube, and feeding back the driving signal for turning on or off the lower tube to the upper tube conduction time control module.

3. The constant on-time control system according to claim 2, characterized in that: The power tube control module includes a first NAND gate, a second NAND gate, a fifth inverter, a sixth inverter and a gate drive circuit. The super audio control module is respectively connected to the input end of the first NAND gate, the input end of the fifth inverter and one input end of the second NAND gate. The output end of the first NAND gate is connected to the other input end of the second NAND gate. The input end of the sixth inverter is connected to the output end of the second NAND gate. The output end of the sixth inverter and the output end of the fifth inverter are respectively connected to the input end of the gate drive circuit. The output end of the gate drive circuit is respectively connected to the gate of the upper tube and the gate of the lower tube. The upper tube conduction time control module is respectively connected to the output end of the sixth inverter and the output end of the fifth inverter.

4. The constant on-time control system according to claim 2, characterized in that: The upper tube conduction time control module includes a sampling and filtering circuit, an upper tube conduction time reference voltage generating circuit, a first comparator, a first capacitor, a first current source, and a first transistor. The sampling and filtering circuit is connected to the upper tube conduction time reference voltage generating circuit, the upper tube conduction time reference voltage generating circuit is connected to the inverting input terminal of the first comparator, the drain of the first transistor is respectively connected to the non-inverting input terminal of the first comparator, the first current source, and one end of the first capacitor, and the source of the first transistor and the other end of the first capacitor are grounded.

5. The constant on-time control system according to claim 4, characterized in that: The sampling filter circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fourth capacitor, and a fifth capacitor. One end of the first resistor is respectively connected to the source of the upper tube, the drain of the lower tube, and the inductor element. The other end of the first resistor is respectively connected to one end of the second resistor and the third resistor. The other end of the third resistor is respectively connected to one end of the fourth capacitor and the fourth resistor. The other end of the fourth resistor is connected to the fifth capacitor.

6. The constant on-time control system according to claim 5, characterized in that: The upper tube conduction time reference voltage generating circuit includes a seventh inverter, an eighth inverter, a ninth inverter, a tenth inverter, a third D flip-flop, a first AND gate, a fifth resistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a counter and a sixth resistor. The input end of the seventh inverter is connected to the power tube control module, the output end of the seventh inverter is respectively connected to the input end of the eighth inverter, the sixth capacitor and the tenth capacitor, the output end of the eighth inverter is respectively connected to the gate of the sixth transistor, the gate of the fourth transistor and the reset end of the third D flip-flop, the data input end of the third D flip-flop is externally connected to a positive power supply voltage, the clock input end of the third D flip-flop is connected to the super audio control module, the output end of the third D flip-flop is connected to the input end of the ninth inverter, the output end of the ninth inverter is connected to an input end of the first AND gate, and the The other input end of the first AND gate is connected to the power tube control module, the output end of the first AND gate is connected to the gate of the fifth transistor, one end of the fifth resistor is connected to the fourth resistor and the fifth capacitor respectively, the other end of the fifth resistor is connected to the source of the fourth transistor, the drain of the fourth transistor is connected to the sixth capacitor, the seventh capacitor and the source of the fifth transistor respectively, the drain of the fifth transistor is connected to the eighth capacitor, the inverting input end of the first comparator and the drain of the seventh transistor respectively, the input end of the tenth inverter is connected to the super audio control module, the output end of the tenth inverter is connected to one end of the counter, the other end of the counter is connected to the gate of the seventh transistor, one end of the sixth resistor is connected to an external reference voltage, the other end of the sixth resistor is connected to the ninth capacitor and the source of the sixth transistor respectively, and the drain of the sixth transistor is connected to the tenth capacitor, the eleventh capacitor and the source of the seventh transistor respectively.

7. The constant on-time control system according to claim 2, characterized in that: The super-audio control module is externally connected to a zero-crossing detection device. The super-audio control module includes a first D-type flip-flop, a first NOR gate, a second NOR gate, a first inverter, and a delay circuit for delaying signal transmission. The reset terminal of the first D-type flip-flop is connected to the upper tube conduction time control module, the clock input terminal of the first D-type flip-flop is connected to the feedback module, the data input terminal of the first D-type flip-flop is externally connected to a positive power supply voltage, the output terminal of the first D-type flip-flop is respectively connected to the upper tube conduction time control module, the input terminal of the first inverter, and the power tube control module, the output terminal of the first inverter is connected to one input terminal of the second NOR gate, the other input terminal of the second NOR gate is connected to the output terminal of the first NOR gate, one input terminal of the first NOR gate is externally connected to a zero-crossing detection device, the output terminal of the second NOR gate is respectively connected to the other input terminal of the first NOR gate, the input terminal of the delay circuit, and the power tube control module, and the output terminal of the delay circuit is connected to the power tube control module.

8. The constant on-time control system according to claim 7, characterized in that: The delay circuit includes a second inverter, a first buffer, a third inverter, a delay unit, a second D flip-flop and a fourth inverter. The output end of the second NOR gate is connected to the input end of the second inverter, the output end of the second inverter is respectively connected to the reset end of the delay unit and the second D flip-flop, the input end of the first buffer is connected to the delay unit, the output end of the first buffer is respectively connected to the input end of the upper tube conduction time control module and the third inverter, the output end of the third inverter is connected to the delay unit, the data input end of the second D flip-flop is externally connected to the positive power supply voltage, the clock input end of the second D flip-flop is connected to the delay unit, the output end of the second D flip-flop is connected to the input end of the fourth inverter, and the output end of the fourth inverter is connected to the power tube control module.

9. The constant on-time control system according to claim 8, characterized in that: The delay time of the delay unit is 28μs~50μs; The delay unit includes a first delay unit and a second delay unit, the first delay unit includes a second transistor, a second current source and a second capacitor, the second current source is connected to the drain of the second transistor and one end of the second capacitor respectively, and the source of the second transistor and the other end of the second capacitor are grounded; The second delay unit includes a third transistor, a third current source and a third capacitor. The gate of the third transistor is connected to the output end of the third inverter, the drain of the third transistor is respectively connected to the third current source, one end of the third capacitor and the clock input end of the second D flip-flop, and the source of the third transistor and the other end of the third capacitor are grounded.

10. The constant on-time control system according to claim 1, characterized in that: The feedback module includes a feedback circuit and a second comparator, the input end of the feedback circuit is connected to the output end of the control system, the output end of the feedback circuit is connected to the inverting input end of the second comparator, the non-inverting input end of the second comparator is externally connected to a reference voltage, and the output end of the second comparator is connected to the ultrasonic control module.

Images