High electron mobility transistor device
By arranging the source field plate contact portion in the active region in a high electron mobility transistor device, the problem of terminal region area limitation is solved, the length of the source bus and the drain bus is increased, and the on-resistance is reduced.
Patent Information
- Application Number
- CN202510941792.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-09
- Publication Date
- 2025-10-03
AI Technical Summary
In the prior art high electron mobility transistor devices, the active region area is limited due to the provision of contacts in the terminal region, resulting in a high on-resistance.
The source field plate contact portion is arranged in the active region, eliminating the need to reserve an area in the terminal region for the contact portion, increasing the active region area to extend the length of the source bus and the drain bus.
The active region area is effectively utilized to reduce the on-resistance of the high electron mobility transistor device.
Smart Images
Figure CN120751727A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a high electron mobility transistor (HEMT) device, and more particularly to a HEMT device in which a source field plate contact is disposed in an active region, thereby increasing the lengths of the source bus and drain bus of the HEMT device, thereby reducing the on-resistance of the HEMT device. Background Art
[0002] Please refer to FIG1 , which illustrates a top view of an embodiment of a prior art high electron mobility transistor (HEMT) device layout. To balance the withstand voltage and current requirements of the HEMT device, the HEMT device utilizes a source field plate design to improve the internal electric field within the HEMT device. As shown in FIG1 , the prior art HEMT device 100 includes an active region AA' and a termination region TA'. A first source field plate 110 and a second source field plate 120 are electrically connected to a source bus 130 at and adjacent to the termination region TA' via at least one contact 141, 142, 143 and an upper metal layer (not shown). Because area must be reserved in and adjacent to the termination region TA' for the contacts 141, 142, 143, the active region AA' area of the prior art HEMT device 100 is limited, resulting in a higher on-resistance. Therefore, improvements are necessary. Summary of the Invention
[0003] The main purpose of the present invention is to provide a high electron mobility transistor device in which a source field plate contact portion is disposed in an active region, thereby increasing the active region area of the high electron mobility transistor device and reducing on-resistance.
[0004] To achieve the above-mentioned objectives, the high electron mobility transistor device of the present invention includes an active region, two gate buses, a source bus, a first source field plate, a plurality of source contacts, a second source field plate, a top metal layer, and a second source field plate contact. The two gate buses are located in the active region and extend along a first direction. The source bus is located in the active region and is disposed between the two gate buses. The first source field plate is located in the active region and at least partially overlaps the two gate buses. The second source field plate is located in the active region and is disposed above the first source field plate. The top metal layer is located above the second source field plate. A plurality of source contacts are disposed on the source bus and electrically connected to the top metal layer. The second source field plate contact is located in the active region and electrically connects the second source field plate and the top metal layer, such that the second source field plate is electrically connected to the source bus.
[0005] The present invention further provides a high electron mobility transistor device comprising an active region, two gate buses, a source bus, a first source field plate, a first source field plate contact, a second source field plate, a top metal layer, a plurality of source contacts, and a second source field plate contact. The two gate buses are located in the active region and extend along a first direction. The source bus is located in the active region and disposed between the two gate buses. The first source field plate is located in the active region and includes a first field plate bus, a second field plate bus, and a first connecting portion. The first field plate bus and the second field plate bus each partially overlap the two gate buses, and the first connecting portion connects the first field plate bus and the second field plate bus. The first source field plate contact is located in the first connecting portion. The second source field plate is located in the active region and includes a third field plate bus, a fourth field plate bus, and a second connecting portion. The third field plate bus at least partially overlaps the first field plate bus, the fourth field plate bus at least partially overlaps the second field plate bus, and the second connecting portion connects the third field plate bus and the fourth field plate bus. The top metal layer is located above the second source field plate. A plurality of source contacts are disposed on the source bus and electrically connected to the top metal layer. A second source field plate contact contacts the second connection portion, wherein the first source field plate is electrically connected to the top metal layer via the first source field plate contact, and the second source field plate is electrically connected to the top metal layer via the second source field plate contact.
[0006] The high electron mobility transistor device of the present invention disposes the source field plate contact portion in the active region, thereby eliminating the trouble of reserving area in the terminal region for setting the contact portion in the prior art. As a result, the active region of the high electron mobility transistor device of the present invention can be more effectively utilized, thereby increasing the length of the source bus and drain bus of the high electron mobility transistor device of the present invention, thereby reducing the on-resistance of the high electron mobility transistor device of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] FIG1 is a top view schematically illustrating an embodiment of a high electron mobility transistor device layout according to the prior art;
[0008] Figure 2A is a top view schematically illustrating a high electron mobility transistor (HEMT) device of the present invention;
[0009] Figure 2B yes Figure 2A An enlarged schematic diagram of a high electron mobility transistor device after removing the top metal layer;
[0010] Figure 3 is a partial top view schematic diagram of a first embodiment of a source bus line and layout of a high electron mobility transistor device of the present invention;
[0011] Figure 4A yes Figure 3Schematic cross-section of line segment AA';
[0012] Figure 4B yes Figure 3 Schematic cross-section of line segment BB';
[0013] Figure 5 is a partial top view schematic diagram of a second embodiment of a source bus line and layout of a high electron mobility transistor device of the present invention;
[0014] Figure 6A yes Figure 5 Schematic cross-section of line segment AA';
[0015] Figure 6B yes Figure 5 Schematic cross-section of line segment BB';
[0016] Figure 7 is a partial top view schematically illustrating a third embodiment of a source bus line and layout of a high electron mobility transistor device according to the present invention;
[0017] Figure 8A yes Figure 7 Schematic cross-section of line segment AA';
[0018] Figure 8B yes Figure 7 Schematic cross-section of line segment BB';
[0019] Figure 9 is a partial top view schematically illustrating a fourth embodiment of a source bus line and layout of a high electron mobility transistor device according to the present invention;
[0020] Figure 10A yes Figure 9 Schematic cross-section of line segment BB';
[0021] Figure 10B yes Figure 9 Schematic cross-section of line segment AA';
[0022] Figure 11 is a partial top view schematically illustrating a fifth embodiment of a source bus line and layout of a high electron mobility transistor device according to the present invention;
[0023] Figure 12A yes Figure 11 Schematic cross-section of line segment BB';
[0024] Figure 12B yes Figure 11 Schematic cross-section of line segment AA'.
[0025]
Explanation of symbols
[0026] High electron mobility transistor devices 1, 1a, 1b, 1c, 1d, 1e, 100
[0027] Active area AA', AA
[0028] First sub-source bus line 311
[0029] Source electrodes 12, 12a
[0030] Gate electrodes 13 and 13a
[0031] Drain bus lines 14, 150
[0032] The second sub-source bus line 312
[0033] Drain bus length L', L
[0034] Source contact 71
[0035] Gate bus lines 21, 21a, 22, 22a
[0036] Gate connecting portions 23, 23a
[0037] Source bus line 130
[0038] Source bus lines 31 and 32
[0039] First source field plates 40 , 110
[0040] First field board bus 41
[0041] Second field board bus 42
[0042] First connecting portion 43
[0043] First source field plate contact 50
[0044] Second source field plate contact 70
[0045] Second source field plates 60 , 120
[0046] The third field board bus 61
[0047] Fourth field board bus 62
[0048] Second connecting portion 63
[0049] The third connecting portion 44
[0050] Fourth connecting portion 64
[0051] Source metal layer 80
[0052] Epitaxial layer 90
[0053] First direction D1
[0054] Second direction D2
[0055] Contact parts 141, 142, 143
[0056] Terminal area TA', TA
[0057] Area A
[0058] Area B
[0059] Gap GP
[0060] Top metal layer 88 DETAILED DESCRIPTION
[0061] In order to better understand the technical content of the present invention, the preferred specific embodiments are described below. Figure 2A and Figure 2B A top view of a high electron mobility transistor (HEMT) device according to the present invention and Figure 2A An enlarged schematic diagram of a high electron mobility transistor device after removing the top metal layer.
[0062] like Figure 2A and Figure 2B As shown, in this embodiment, the high electron mobility transistor device 1 of the present invention includes an active area AA, a termination area TA, a plurality of gate bus lines 21, 21a, 22, 22a, a plurality of gate connections 23, 23a, a plurality of source bus lines 31, 32, a plurality of drain bus lines 14, 15, a first source field plate 40, a first source field plate contact 50, a second source field plate 60, a second source field plate contact 70, a plurality of source contacts 71, and a top metal layer 88. The gate bus lines 21, 21a, 22 extend along a first direction D1 to the termination area TA and are connected in the termination area TA by the gate connection 23 to form a closed gate ring surrounding the drain bus line 14. The top metal layer 88 is located above the entire structure of the high electron mobility transistor device 1. In other words, the plurality of source bus lines 31, 32 and the plurality of source contacts 71 are all located below the top metal layer 88.
[0063] The source bus line 31 is located in the active area AA and is disposed between the gate bus lines 21 and 22. The source bus line 32 is located in the active area AA and is disposed between the gate bus lines 21a and 22a. Figure 2BAs shown, the first source field plate 40 is located in the active area AA and extends along the second direction D2 to at least partially overlap the gate bus lines 21 and 22 and at least partially overlap the source bus line 31, wherein the first source field plate 40 is electrically connected to the source bus line 31 via a first source field plate contact 50. In the present invention, overlap means that one component is located above another object without the two objects being in direct contact. In this embodiment, the first direction D1 is perpendicular to the second direction D2, thereby allowing the first source field plate 40 to partially overlap the gate bus lines 21 and 22 and the source bus line 31. However, the present invention is not limited to this embodiment. As long as the first source field plate 40 can achieve the effect of partially overlapping the gate bus lines 21 and 22 and the source bus line 31, the first direction D1 does not necessarily need to be perpendicular to the second direction D2.
[0064] like Figure 2B As shown, the second source field plate 60 is located in the active area AA and above the first source field plate 40. The second source field plate 60 is electrically connected to the source bus 31 through the second source field plate contact 70. In addition, the first source field plate contact 50 and the second source field plate contact 70 of the present invention are both located in the active area AA. In other words, it can be considered that the first source field plate contact 50 and the second source field plate contact 70 are both located in the active area AA and are respectively located between any two source contacts 71.
[0065] like Figure 2A and Figure 2B As shown, the first source field plate 40 of this embodiment further includes a first field plate bus 41, a second field plate bus 42, a first connecting portion 43, and a third connecting portion 44. The first field plate bus 41 and the second field plate bus 42 extend along a first direction D1 and partially overlap the gate bus lines 21 and 22, respectively. The first field plate bus 41 and the second field plate bus 42 are connected by the third connecting portion 44 in the active area AA adjacent to the terminal area TA. Specifically, the third connecting portion 44 is located near the end points of the first field plate bus 41 and the second field plate bus 42. Thus, the first field plate bus 41, the third connecting portion 44, and the second field plate bus 42 form a ring that surrounds the source bus line 31. In addition, the first connection portion 43 is located in the active area AA and extends along the second direction D2. The first connection portion 43 overlaps a portion of the source bus 31. The two ends of the first connection portion 43 are respectively connected to the first field plate bus 41 and the second field plate bus 42. A first source field plate contact portion 50 is provided on the first connection portion 43. The first source field plate 40 can be electrically connected to the source bus 31 through the first source field plate contact portion 50 and the top metal layer 88.
[0066] like Figure 2A and Figure 2BAs shown, the second source field plate 60 of this embodiment further includes a third field plate bus 61, a fourth field plate bus 62, a second connection portion 63, and a fourth connection portion 64. The third field plate bus 61 and the fourth field plate bus 62 both extend along the first direction D1. The third field plate bus 61 partially overlaps the first field plate bus 41, and the fourth field plate bus 62 partially overlaps the second field plate bus 42. The third field plate bus 61 and the fourth field plate bus 62 are connected in the active area AA adjacent to the termination area TA via the fourth connection portion 64. Specifically, the fourth connection portion 64 is located near the end points of the third and fourth field plate buses 61 and 62. Consequently, the third field plate bus 61, the fourth connection portion 64, and the fourth field plate bus 62 form a ring that surrounds the source bus 31. Furthermore, the second connecting portion 63 extends along the second direction D2 and overlaps a portion of the source bus line 31. Two ends of the second connecting portion 63 are respectively connected to the third field plate bus line 61 and the fourth field plate bus line 62. The second source field plate contact portion 70 is located on the second connecting portion 63. Thus, the second source field plate 60 can be electrically connected to the source bus line 31 via the second source field plate contact portion 70.
[0067] In this embodiment, the material used for the source contact portion 71, the first source field plate contact portion 50 and the second source field plate contact portion 70 can be conductive tungsten (W). The position where the first connection portion 43 contacts the first source field plate contact portion 50, and the position where the second connection portion 63 contacts the second source field plate contact portion 70 can be changed depending on the internal component layout of the high electron mobility transistor device 1, and is not limited to this embodiment. As long as the first source field plate contact portion 50 and the second source field plate contact portion 70 are both located in the active area AA, the present invention is applicable. Furthermore, because the first source field plate contact portion 50 and the second source field plate contact portion 70 are both located in the active area AA, the problem in the prior art of requiring an area to be reserved in the terminal area to set up the contact portion, resulting in a reduction in the available area of the active area, is solved. Figure 2A It can be seen that the length of the active region AA of the high electron mobility transistor device 1 of the present invention is longer than the length of the active region AA' of the prior art in FIG1 , the drain bus length L' is also longer than the drain bus length L of the prior art in FIG1 , and the length of the terminal region TA of the high electron mobility transistor device 1 of the present invention is also shorter than the length of the terminal region TA' of the prior art in FIG1 . This allows for more efficient utilization of the active region AA of the high electron mobility transistor device 1 of the present invention, thereby reducing the on-resistance of the high electron mobility transistor device 1 of the present invention. It should be noted here that since the first source field plate 40, the first source field plate contact 50, the second source field plate 60, and the second source field plate contact 70 are all located inside the high electron mobility transistor device 1, Figure 2A and Figure 2BThe top views shown are only for simplified description. The structures of the first source field plate 40 , the first source field plate contact 50 , the second source field plate 60 , and the second source field plate contact 70 in each embodiment of the HEMT device 1 will be described in detail later.
[0068] Please refer to the following Figure 3 、 Figure 4A and Figure 4B ,in Figure 3 is a partial top view schematic diagram of a first embodiment of a source bus and layout of a high electron mobility transistor device of the present invention, Figure 4A yes Figure 3 Schematic diagram of the cross section of line segment AA', and Figure 4B yes Figure 3 Schematic cross-section of line segment BB'.
[0069] Figure 3 show Figure 2B A partial top view of area A in the middle. Figure 3 Specifically, a partially enlarged top view of the gate bus lines 21 and 22, the first sub-source bus line 311, the first field plate bus line 41, the second field plate bus line 42, the third field plate bus line 61, the fourth field plate bus line 62, the second connecting portion 63, the second source field plate contact portion 70, and the source contact portion 71 in the high electron mobility transistor device 1a of the first embodiment is shown. In this embodiment, as shown in FIG. Figure 3 、 Figure 4A and Figure 4B As shown, the third field plate bus 61 is located above the first field plate bus 41 and partially overlaps the first field plate bus 41, the fourth field plate bus 62 is located above the second field plate bus 42 and partially overlaps the second field plate bus 42, and the second connecting portion 63 connects the third field plate bus 61 and the fourth field plate bus 62 at both ends and partially overlaps the first sub-source bus 311, that is, the second connecting portion 63 spans the source 12 and the gate 13, 13a, and the gate buses 21, 22 are partially overlapped by the first field plate bus 41 and the second field plate bus 42 respectively. In this embodiment, one end of the second source field plate contact portion 70 passes through the second connecting portion 63 and is electrically connected to the source 12 located on the epitaxial layer 90, and the top metal layer 88 is electrically connected to the second source field plate 60 through the other end of the second source field plate contact portion 70 at the second connecting portion 63. Figure 4A and Figure 4B As shown, the first field plate bus 41 is located above the gate 13, and the second field plate bus 42 is located above the gate 13a. In this embodiment, no first connecting portion 43 is provided between the first field plate bus 41 and the second field plate bus 42. Figure 3 A partial top view after removing the top metal layer 88 is shown. In order to clearly illustrate the electrical connection between the top metal layer 88 and the second source field plate 60, Figure 4Aand Figure 4B The top metal layer 88 is shown only in dashed lines and is represented by Figure 2A As described above, the top metal layer 88 is located above the second source field plate contact portion 70 .
[0070] Please refer to the following Figure 5 、 Figure 6A and Figure 6B ,in Figure 5 is a partial top view schematic diagram of a second embodiment of the source bus and layout of a high electron mobility transistor device of the present invention, Figure 6A yes Figure 5 Schematic diagram of the cross section of line segment AA', and Figure 6B yes Figure 5 Schematic cross-section of line segment BB'.
[0071] Same as the first embodiment, Figure 4A The high electron mobility transistor device 1a shown is Figure 6A The difference of the HEMT device 1b of the second embodiment shown is that Figure 6A As shown, in the high electron mobility transistor device 1b, one end of the second source field plate contact portion 70 contacts and does not pass through the second connecting portion 63, and the top metal layer 88 is electrically connected to the second source field plate 60 at the second connecting portion 63 through the other end of the second source field plate contact portion 70. Therefore, the second source field plate contact portion 70 of the high electron mobility transistor device 1b of the second embodiment does not contact the source 12.
[0072] Please refer to the following Figure 7 、 Figure 8A and Figure 8B ,in Figure 7 1 is a partial top view of a third embodiment of the source bus and layout of a high electron mobility transistor of the present invention. Figure 8A yes Figure 7 Schematic diagram of the cross section of line segment AA', and Figure 8B yes Figure 7 Schematic cross-section of line segment BB'.
[0073] like Figure 7FIG. 1 shows a partially enlarged top view of the gate bus lines 21 and 22, the first sub-source bus line 311, the second sub-source bus line 312, the first field plate bus line 41, the second field plate bus line 42, the first connector 43, the third field plate bus line 61, the fourth field plate bus line 62, the first source field plate contact 50, and the source contact 71 in a high electron mobility transistor device 1 c. In this embodiment, the first source field plate 40 includes the first field plate bus line 41, the second field plate bus line 42, and the first connector 43. The first field plate bus line 41 and the second field plate bus line 42 overlap portions of the gate bus lines 21 and 22, respectively. The first connector 43 connects the first field plate bus line 41 and the second field plate bus line 42 at both ends. The first source field plate contact 50 is disposed on the first connector 43, which is located above the gap GP between the first sub-source bus line 311 and the second sub-source bus line 312. The third field plate bus 61 partially overlaps the first field plate bus 41 , and the fourth field plate bus 62 partially overlaps the second field plate bus 42 .
[0074] like Figure 7 、 Figure 8A and Figure 8B As shown, the high electron mobility transistor device 1c of this embodiment has a plurality of source electrodes 12, 12a, and the source electrodes 12, 12a are located on the epitaxial layer 90 and extend along the first direction D1 and are dispersedly disposed in the active area AA. Figure 8A As shown, the first connection portion 43 spans the gates 13 and 13a, the third field plate bus 61 is located above the first field plate bus 41, and the fourth field plate bus 62 is located above the second field plate bus 42. In this embodiment, no second connection portion 63 is provided between the third field plate bus 61 and the fourth field plate bus 62. At the same time, the first source field plate contact portion 50 contacts and does not pass through the first connection portion 43, and as shown in FIG. Figure 8B As shown, the first connection portion 43 in contact with the first source field plate contact portion 50 is located between any two source electrodes 12 , 12 a.
[0075] Please refer to the following Figure 9 、 Figure 10A and Figure 10B ,in Figure 9 is a partial top view of a fourth embodiment of the source bus and layout of a high electron mobility transistor device of the present invention, Figure 10A yes Figure 9 Schematic diagram of the cross section of line segment BB', and Figure 10B yes Figure 9 Schematic cross-section of line segment AA'.
[0076] In the high electron mobility transistor device 1d of this embodiment and the high electron mobility transistor device 1a of the first embodiment, the third field plate bus 61 is located above the first field plate bus 41 and partially overlaps the first field plate bus 41, the fourth field plate bus 62 is located above the second field plate bus 42 and partially overlaps the second field plate bus 42, and the second connecting portion 63 connects the third field plate bus 61 and the fourth field plate bus 62 at both ends and spans the source 12 and the gates 13 and 13a. The differences between the two embodiments are as follows: Figure 9 、 Figure 10A and Figure 10B As shown, the high electron mobility transistor device 1d further includes a source metal layer 80, wherein the source metal layer 80 is located between the third field plate bus 61 and the first field plate bus 41, and between the fourth field plate bus 62 and the second field plate bus 42. Figure 9 、 Figure 10A and Figure 10B As shown, the second source field plate contact portion 70 contacts the second connecting portion 63 but does not pass through the second connecting portion 63 . Therefore, the second source field plate contact portion 70 of the HEMT device 1 d of the fourth embodiment does not contact the source 12 .
[0077] Please refer to the following Figure 11 、 Figure 12A and Figure 12B ,in Figure 11 is a partial top view of a fifth embodiment of the source bus and layout of a high electron mobility transistor device of the present invention, Figure 12A yes Figure 11 Schematic diagram of the cross section of line segment BB', and Figure 12B yes Figure 11 Schematic cross-section of line segment AA'.
[0078] Figure 11 The high electron mobility transistor device 1e shown is Figure 12A The difference of the high electron mobility transistor device 1d of the fourth embodiment shown is that Figure 12A As shown, in the HEMT device 1 e , the second source field plate contact portion 70 passes through the second connecting portion 63 and is electrically connected to the source 12 located on the epitaxial layer 90 .
[0079] The following table shows the measured data of the improved on-resistance of the HEMT device 1 after the first source field plate contact 50 and the second source field plate 60 are both disposed in the active area AA.
[0080]
[0081] Table 1. Measurement data of high electron mobility transistor device on-resistance
[0082] As can be seen from the above table, the high electron mobility transistor devices 1, 1a, 1b, 1c, 1d, and 1e of the present invention can make more effective use of the active region area of the high electron mobility transistor devices 1, 1a, 1b, 1c, 1d, and 1e by arranging the first source field plate contact portion 50 and the second source field plate contact portion 70 in the active region, so that the length of the source bus 31 and the drain bus 14 of the high electron mobility transistor devices 1, 1a, 1b, 1c, 1d, and 1e can be increased, thereby reducing the on-resistance of the high electron mobility transistor devices 1, 1a, 1b, 1c, 1d, and 1e.
[0083] It should be noted that the above embodiments are merely examples for the purpose of illustration, and the scope of rights claimed by the present invention should be based on the claims, and is not limited to the above embodiments.
Claims
1. A high electron mobility transistor device, characterized in that include: an active zone; Two gate bus lines are located in the active region and extend along a first direction; a source bus located in the active region and disposed between the two gate bus lines; a first source field plate located in the active region and at least partially overlapping the two gate bus lines; a second source field plate located in the active region and disposed above the first source field plate; a top metal layer located above the second source field plate; A plurality of source contacts are disposed on the source bus and electrically connected to the top metal layer; as well as A second source field plate contact portion is located in the active region and electrically connects the second source field plate and the top metal layer, so that the second source field plate is electrically connected to the source bus.
2. The high electron mobility transistor device according to claim 1, wherein The device also includes a first source field plate contact portion located in the active region and electrically connecting the first source field plate and the top metal layer.
3. The high electron mobility transistor device according to claim 2, wherein: The source bus further includes a first sub-source bus and a second sub-source bus. A gap is defined between the first sub-source bus and the second sub-source bus. The first source field plate contact portion is located above the gap.
4. The high electron mobility transistor device according to claim 2, wherein: The first source field plate contact portion contacts the first source field plate but does not pass through the first source field plate.
5. The high electron mobility transistor device according to claim 4, wherein: The first source field plate includes a first field plate bus, a second field plate bus, and a first connecting portion, wherein the first field plate bus and the second field plate bus respectively overlap the two gate buses, the two ends of the first connecting portion are respectively connected to the first field plate bus and the second field plate bus, and the first connecting portion is located above the gap, wherein the first source field plate contact portion contacts and does not pass through the first connecting portion.
6. The high electron mobility transistor device according to claim 1, wherein: The first source field plate includes a first field plate bus and a second field plate bus, wherein the first field plate bus and the second field plate bus respectively overlap portions of the two gate bus lines.
7. The high electron mobility transistor device according to claim 6, wherein: The high electron mobility transistor device has an epitaxial layer and a source. The source is located in the active region and is disposed on the epitaxial layer. The second source field plate includes a third field plate bus, a fourth field plate bus, and a second connecting portion. The third field plate bus at least partially overlaps the first field plate bus, the fourth field plate bus at least partially overlaps the second field plate bus, the second connecting portion overlaps the source bus, two ends of the second connecting portion are respectively connected to the third field plate bus and the fourth field plate bus, and the second source field plate contact portion contacts the second connecting portion.
8. The high electron mobility transistor device according to claim 1, wherein: The device has an epitaxial layer and a source. The source is located in the active region and is disposed on the epitaxial layer. The second source field plate contact portion passes through the second source field plate and contacts the source.
9. The high electron mobility transistor device according to claim 1, wherein: The second source field plate contact portion contacts the second source field plate but does not pass through the second source field plate.
10. A high electron mobility transistor device, characterized in that: include: an active zone; Two gate bus lines are located in the active region and extend along a first direction; a source bus located in the active region and extending along the first direction, and disposed between the two gate busses; a first source field plate located in the active region, wherein the first source field plate includes a first field plate bus, a second field plate bus, and a first connecting portion, wherein the first field plate bus and the second field plate bus partially overlap the two gate buses, respectively, and the first connecting portion connects the first field plate bus and the second field plate bus; a first source field plate contact portion, disposed at the first connecting portion; a second source field plate located in the active region, wherein the second source field plate includes a third field plate bus, a fourth field plate bus, and a second connecting portion, the third field plate bus at least partially overlapping the first field plate bus, the fourth field plate bus at least partially overlapping the second field plate bus, and the second connecting portion connecting the third field plate bus and the fourth field plate bus; a top metal layer located above the second source field plate; A plurality of source contacts are disposed on the source bus and electrically connected to the top metal layer; as well as A second source field plate contact portion contacts the second connection portion, wherein the first source field plate is electrically connected to the top metal layer through the first source field plate contact portion, and the second source field plate is electrically connected to the top metal layer through the second source field plate contact portion.
11. The high electron mobility transistor device according to claim 10, wherein: The invention also includes a second source bus located in the active region and extending along the first direction and disposed between the two gate buses. There is a gap between the source bus and the second source bus, and the first connecting portion is located above the gap.
12. The high electron mobility transistor device according to claim 10, wherein: The second connecting portion partially overlaps the source bus line.
13. The high electron mobility transistor device according to claim 10, wherein: The first source field plate further includes a third connecting portion located in the active region and at an extension end of the first field plate bus and the second field plate bus, and the third connecting portion connects the first field plate bus and the second field plate bus.
14. The high electron mobility transistor device according to claim 10, wherein: The second source field plate further includes a fourth connecting portion located in the active region and at an extension end of the third field plate bus and the fourth field plate bus, and the fourth connecting portion connects the third field plate bus and the fourth field plate bus.
15. The high electron mobility transistor device according to claim 10, wherein: The first source field plate contact portion and the second source field plate contact portion are respectively located between any two of the plurality of source contact portions.