Laterally diffused metal oxide semiconductor element and manufacturing method thereof

Abstract

The invention discloses a laterally diffused metal oxide semiconductor element and a manufacturing method thereof, and the method for manufacturing the laterally diffused metal oxide semiconductor element comprises the steps: firstly, forming a first fin-shaped structure and a second fin-shaped structure on a substrate, then forming a shallow trench isolation between the first fin-shaped structure and the second fin-shaped structure, the method includes forming a first fin-shaped structure, forming a first gate structure on the first fin-shaped structure and a second gate structure on the second fin-shaped structure, forming a source region on the first fin-shaped structure on one side of the first gate structure, forming a drain region on the second fin-shaped structure on one side of the second gate structure, and forming a contact field plate right above the shallow trench isolation.

Description

[0001] This application is a divisional application of the Chinese invention patent application (application number: 202110388841.4, application date: April 12, 2021, invention name: Laterally diffused metal oxide semiconductor element and its manufacturing method). Technical Field

[0002] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for integrating a lateral diffused metal oxide semiconductor (LDMOS) device with a fin structure. Background Art

[0003] Laterally diffused metal oxide semiconductor (LDMOS) devices, due to their high operating bandwidth and efficiency, as well as their planar structure that facilitates integration with other integrated circuits, are now widely used in high-voltage operating environments, such as CPU power supplies, power management systems, DC / DC converters, and high-power or high-frequency power amplifiers.

[0004] Furthermore, as device dimensions continue to shrink, the development of existing planar field-effect transistors (FETs) is facing process limitations. To overcome these limitations, replacing planar transistors with non-planar FETs, such as fin field-effect transistors (Fin FETs), has become a mainstream development trend. Because the three-dimensional structure of Fin FETs increases the contact area between the gate and the fin structure, the gate's control over the carrier channel region can be further enhanced, thereby reducing the drain-induced barrier lowering (DIBL) effect faced by small-sized devices and suppressing the short channel effect (SCE). Furthermore, because Fin FETs have a wider channel width at the same gate length, they can achieve double the drain drive current. Furthermore, the transistor's threshold voltage can be controlled by adjusting the gate's work function.

[0005] However, as device dimensions continue to shrink, the integration of existing LDMOS devices and fin structures still faces many challenges, such as controlling leakage current and breakdown voltage. Therefore, improving the existing high-voltage device architecture is a key issue today. Summary of the Invention

[0006] One embodiment of the present invention discloses a method for fabricating a laterally diffused metal oxide semiconductor (LDMOS) device. The method includes forming a first fin structure and a second fin structure on a substrate, forming a shallow trench isolation between the first and second fin structures, forming a first gate structure on the first fin structure and a second gate structure on the second fin structure, forming a source region on the first fin structure on one side of the first gate structure, forming a drain region on the second fin structure on one side of the second gate structure, and forming a contact field plate directly above the shallow trench isolation.

[0007] Another embodiment of the present invention discloses a laterally diffused metal oxide semiconductor device, which mainly includes a first fin structure arranged on a substrate, a shallow trench isolation arranged next to the first fin structure, a first gate structure arranged on the first fin structure, and a contact field plate arranged directly above the shallow trench isolation next to the first gate structure.

[0008] Another embodiment of the present invention discloses a laterally diffused metal oxide semiconductor element, which mainly includes a first fin structure arranged on a substrate, a shallow trench isolation arranged next to the first fin structure, a first gate structure arranged on the first fin structure and the shallow trench isolation, and a contact field plate arranged directly above the shallow trench isolation next to the first gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1 to 4 A schematic diagram of a method for manufacturing a laterally diffused metal oxide semiconductor device according to an embodiment of the present invention;

[0010] Figure 5 A schematic structural diagram of a laterally diffused metal oxide semiconductor device according to an embodiment of the present invention;

[0011] Figure 6 FIG. 1 is a schematic structural diagram of a laterally diffused metal oxide semiconductor device according to an embodiment of the present invention.

[0012] Description of main component symbols

[0013] 12: Base

[0014] 14: First fin structure

[0015] 16: Second fin structure

[0016] 18:P well

[0017] 20:N well

[0018] 22: Shallow Trench Isolation

[0019] 24: Gate structure

[0020] 26: Gate structure

[0021] 28: Gate structure

[0022] 30: Gate structure

[0023] 32: Gate dielectric layer

[0024] 34: Gate material layer

[0025] 36: gap wall

[0026] 38: Source region

[0027] 40: Drain region

[0028] 42: interlayer dielectric layer

[0029] 44: dielectric layer

[0030] 46: High dielectric constant dielectric layer

[0031] 48: Work function metal layer

[0032] 50: low impedance metal layer

[0033] 52: Hard mask

[0034] 54: interlayer dielectric layer

[0035] 56: Contact plug

[0036] 58: Contact plug

[0037] 60: Contact field plate DETAILED DESCRIPTION

[0038] Please refer to Figures 1 to 4 , Figures 1 to 4 Schematic diagram of a method for manufacturing a laterally diffused metal oxide semiconductor device according to an embodiment of the present invention, wherein Figure 1 A top view of a LDMOS device according to an embodiment of the present invention is shown. Figures 2 to 4 Then Figure 1 Schematic diagram of the cross section of the lateral diffused metal oxide semiconductor device along the tangent line AA'. Figures 1 to 2As shown, a substrate 12 is first provided, and then a plurality of fin structures, such as a first fin structure 14 and a second fin structure 16, are formed on the substrate 12. A first well region (e.g., a P-well 18) and a second well region (e.g., an N-well 20) are formed within the first fin structure 14 and the second fin structure 16. A shallow trench isolation (STI) 22 is then formed between the first fin structure 14 and the second fin structure 20, with the upper surface of the STI 22 being slightly lower than the upper surfaces of the first fin structure 14 and the second fin structure 16. The first well region (e.g., the P-well 18) is completely located within the first fin structure 14, while the second well region (e.g., the N-well 20) is located within the second fin structure 16 and the first fin structure 14. Furthermore, the contact STI 22 is completely located within the second well region (e.g., the N-well 20).

[0039] In this embodiment, the substrate 12 is preferably made of a semiconductor material, such as a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate or a silicon-on-insulator (SOI) substrate, and the shallow trench isolation 22 is preferably made of silicon oxide, but is not limited thereto. Figure 1 Although the top view takes seven first fin structures 14 and seven second fin structures 16 extending along the Y direction formed on the substrate 12 as an example, the number of the fin structures is not limited thereto and can be adjusted according to the manufacturing process or product requirements.

[0040] According to a preferred embodiment of the present invention, the fin structure includes a first fin structure 14 and a second fin structure 16, which are preferably manufactured by sidewall pattern transfer (SIT) and other technologies. The procedure generally includes: providing a layout pattern to a computer system, and defining the corresponding pattern in a photomask through appropriate calculations. Subsequently, a plurality of equidistant and equal-width patterned sacrificial layers can be formed on the substrate through photolithography and etching processes, so that their individual appearances are strip-shaped. Thereafter, deposition and etching processes are sequentially performed to form spacers on each sidewall of the patterned sacrificial layer. The patterned sacrificial layer is then removed, and an etching process is performed under the coverage of the spacers, so that the pattern formed by the spacers is transferred to the substrate, and then the desired patterned structure, such as a strip-shaped patterned fin structure, is obtained by a fin structure cutting process (fin cut).

[0041] In addition, the fin structure can be formed by first forming a patterned mask (not shown) on the substrate 12, and then performing an etching process to transfer the pattern of the patterned mask into the substrate 12 to form the first fin structure 14 and the second fin structure 16. Alternatively, the fin structure can be formed by first forming a patterned hard mask layer (not shown) on the substrate 12, and then using an epitaxial process to grow a semiconductor layer, such as silicon germanium, on the substrate 12 exposed by the patterned hard mask layer. This semiconductor layer can serve as the corresponding first fin structure 14 and second fin structure 16. These embodiments of forming the fin structure are all within the scope of the present invention.

[0042] Next, a gate structure 24 is formed on the first fin structure 14, a gate structure 26 is formed on the first fin structure 14 to the left of the gate structure 24, and gate structures 28 and 30 are formed on the second fin structure 16. In this embodiment, the gate structures can be fabricated using a gate-first process, a gate-last process (high-k first), or a gate-last process (high-k last) depending on the fabrication process requirements. Taking the high-k dielectric layer fabrication process of the present embodiment as an example, a gate dielectric layer 32 or dielectric layer composed of silicon oxide, a gate material layer 34 composed of polysilicon, and a selective hard mask (not shown) can be sequentially formed on the substrate 12. A pattern transfer process is then performed using a patterned photoresist (not shown) as a mask. A portion of the gate material layer 34 and the gate dielectric layer 32 are removed by a single etching or successive etching steps. The patterned photoresist is then stripped to form gate structures 24, 26, 28, and 30 composed of the patterned gate dielectric layer 32 and the patterned gate material layer 34 on the substrate 12.

[0043] Then, at least one spacer 36 is formed on the sidewalls of each gate structure 24, 26, 28, and 30, and a source region 38 composed of, for example, an N+ region is formed in the first fin structure 14 on one side of the gate structure 24, and a drain region 40 composed of, for example, an N+ region is formed in the second fin structure 16 on one side of the gate structure 28. In this embodiment, the spacer 36 can be a single spacer or a composite spacer, for example, it can include an offset spacer and a main spacer in detail. The offset spacer and the main spacer can include the same or different materials, and both can be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride. The source region 38 and the drain region 40 can include different dopants depending on the conductivity type of the transistor to be provided, for example, they can include P-type dopants or N-type dopants.

[0044] like Figure 3 As shown, an interlayer dielectric layer 42 may then be formed over the gate structures 24, 26, 28, 30 and the shallow trench isolation 22. A planarization process may then be performed, such as chemical mechanical polishing (CMP), to remove a portion of the interlayer dielectric layer 42 and expose the gate material layer 34 made of polysilicon material, so that the top surface of each gate material layer 34 is flush with the top surface of the interlayer dielectric layer 42. A metal gate replacement process may then be performed to convert the gate structure 24 into a metal gate. For example, a patterned mask (not shown) may be selectively formed to cover the gate structures 26, 28, 30. A selective dry or wet etching process may then be performed, such as using an etching solution such as ammonium hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH), to remove the gate material layer 34 and even the gate dielectric layer 32 in the gate structure 24, thereby forming a recess (not shown) in the interlayer dielectric layer 42. Then, a dielectric layer 44, a high-k dielectric layer 46, and a conductive layer including at least a work function metal layer 48 and a low-resistance metal layer 50 are sequentially formed in the groove, and a planarization process is then performed to make the surfaces of the U-shaped high-k dielectric layer 46, the U-shaped work function metal layer 48, and the low-resistance metal layer 50 flush with the surface of the interlayer dielectric layer 42.

[0045] In the present embodiment, the high-k dielectric layer 46 includes a dielectric material having a dielectric constant greater than 4, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalum oxide (SrTiO3), and strontium bismuth tantalum oxide (SrTiO3). tantalate,SrBi2Ta2O9,SBT), lead zirconate titanate (leadzirconate titanate,PbZrx Ti 1-x O3, PZT), barium strontium titanate (barium strontium titanate, Ba x Sr 1- x TiO3, BST), or a combination thereof.

[0046] The work function metal layer 48 is preferably used to adjust the work function of the metal gate so that it is suitable for an N-type transistor (NMOS) or a P-type transistor (PMOS). If the transistor is an N-type transistor, the work function metal layer 48 can be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3 eV, such as, but not limited to, titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or TiAlC (titanium aluminum carbide). If the transistor is a P-type transistor, the work function metal layer 48 can be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as, but not limited to, titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC). Another barrier layer (not shown) may be included between the work function metal layer 48 and the low resistance metal layer 50, wherein the material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc. The low resistance metal layer 50 may be selected from low resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., or a combination thereof. Since converting a dummy gate into a metal gate based on a metal gate replacement process is a well-known technology in this field, it will not be described in detail here. Then, a portion of the high dielectric constant dielectric layer 46, a portion of the work function metal layer 48, and a portion of the low resistance metal layer 50 may be removed to form a groove (not shown), and then a hard mask 52 is filled in the groove and made flush with the surface of the interlayer dielectric layer 42. The hard mask 52 may be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride.

[0047] like Figure 4As shown, another interlayer dielectric layer 54 may then be optionally formed on the gate structure 24 and the interlayer dielectric layer 42 formed by the metal gate, and a pattern transfer process may be performed. For example, a patterned mask may be used to remove portions of the interlayer dielectric layers 42 and 54 adjacent to the gate structures 24, 26, 28, and 30 to form a plurality of contact holes (not shown) and expose the source region 38, the drain region 40, and the shallow trench isolation 22. The contact holes are then filled with a desired conductive material, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN), and a low-resistance metal layer selected from a low-resistance material such as tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), or a combination thereof. A planarization process is then performed, such as chemical mechanical polishing, to remove a portion of the conductive material to form contact plugs 56 that contact and electrically connect to the source region 38, contact plugs 58 that contact and electrically connect to the drain region 40, and contact field plates 60 on the shallow trench isolation 22. This completes the fabrication of the semiconductor device according to the preferred embodiment of the present invention.

[0048] Please refer to Figure 4 , Figure 4 FIG. 1 is a schematic structural diagram of a laterally diffused metal oxide semiconductor device according to an embodiment of the present invention. Figure 4 As shown, the LDMOS device mainly includes a first fin structure 14 and a second fin structure 16 disposed on a substrate 12, a shallow trench isolation 22 disposed between the first fin structure 14 and the second fin structure 16, a gate structure 24 disposed on the first fin structure 14, a gate structure 28 disposed on the second fin structure 16, a source region 38 disposed on the first fin structure 14 on one side of the gate structure 24, a drain region 40 disposed on the second fin structure 16 on one side of the gate structure 28, interlayer dielectric layers 42 and 54 surrounding the gate structures 24 and 28, a contact plug 56 disposed on the source region 38, a contact plug 58 disposed on the drain region 40, and a contact field plate 60 disposed directly above the shallow trench isolation 22 between the gate structures 24 and 28 and contacting the shallow trench isolation 22. Figure 1 As shown in FIG, the first fin structure 14 and the second fin structure 16 preferably extend along a first direction, such as the X direction, while the contact plug 56 , the contact plug 56 and the contact field plate 60 extend along a second direction, such as the Y direction, on the substrate 12 .

[0049] It should be noted that since the contact field plate 60 and the contact plugs 56 and 58 are fabricated in the same process, they are preferably made of the same material. Furthermore, from a structural perspective, the gate structures 26, 28, and 30 are preferably dummy gate structures, and their widths are preferably smaller than the width of the gate structure 24. Since the bottom of the contact field plate 60 contacts the surface of the shallow trench isolation 22, its bottom surface is preferably lower than the bottom surfaces of the contact plugs 56 and 58. However, the top surface of the contact field plate 60 is preferably flush with the top surfaces of the contact plugs 56 and 58. In other words, the overall height of the contact field plate 60 is preferably greater than the heights of the contact plug 56 connected to the source region 38 and the contact plug 58 connected to the drain region 40.

[0050] Please continue to refer to Figure 5 , Figure 5 FIG. 1 is a schematic structural diagram of a laterally diffused metal oxide semiconductor device according to an embodiment of the present invention. Figure 5 As shown, compared with the aforementioned embodiment in which only the gate structure 24 is converted into a metal gate, according to other embodiments of the present invention, the aforementioned patterned mask setting can be omitted during the metal gate replacement manufacturing process and the gate structures 24, 26, 28, and 30 can be converted into metal gates at the same time. That is, each gate structure 24, 26, 28, and 30 includes metal gate materials such as a dielectric layer 44, a high-k dielectric layer 46, a work function metal layer 48, and a low-resistance metal layer 50. This variation also falls within the scope of the present invention.

[0051] Please continue to refer to Figure 6 , Figure 6 FIG. 1 is a schematic structural diagram of a laterally diffused metal oxide semiconductor device according to an embodiment of the present invention. Figure 6 As shown, the LDMOS device mainly includes a first fin structure 14 and a second fin structure 16 disposed on a substrate 12, a shallow trench isolation 22 disposed between the first fin structure 14 and the second fin structure 16, a gate structure 24 disposed on the first fin structure 14, a gate structure 28 disposed on the second fin structure 16, a source region 38 disposed on the first fin structure 14 on one side of the gate structure 24, a drain region 40 disposed on the second fin structure 16 on one side of the gate structure 28, interlayer dielectric layers 42 and 54 surrounding the gate structures 24 and 28, a contact plug 56 disposed on the source region 38, a contact plug 58 disposed on the drain region 40, and a contact field plate 60 disposed directly above the shallow trench isolation 22 between the gate structures 24 and 28 and contacting the shallow trench isolation 22.

[0052] Compared to the gate structure 24 in the previous embodiment, which is only provided on the first fin structure 14 but does not extend to the top of the shallow trench isolation 22 or the side of the gate structure 24, the spacer 36 is aligned with the sidewall of the first fin structure 14. In this embodiment, the gate structure 24, 26, 28, and 30 can be formed by the aforementioned patterning process, so that the gate structure 24 is extended to the right and crosses over the shallow trench isolation 22. Figure 3 A metal gate replacement process and a contact plug process are performed to convert the gate structure 24 into a metal gate and form a contact field plate 60 next to the gate structure 24. In this embodiment, the gate structure 24 and the contact field plate 60 are preferably simultaneously disposed on and contact the shallow trench isolation 22. The bottom surface of the gate structure 24 disposed on the shallow trench isolation 22 is preferably flush with the bottom surface of the contact field plate 60 and lower than the top surfaces of the first fin structure 14 and the second fin structure 16.

[0053] As in the aforementioned embodiment, since the contact field plate 60 and the contact plugs 56 and 58 are completed from the same manufacturing process, the contact field plate 60 and the contact plugs 56 and 58 preferably include the same material composition. From a structural point of view, the gate structure 28 provided between the contact field plate 60 and the drain region 40 is preferably a virtual gate structure and its width is preferably smaller than the width of the gate structure 24. Since the bottom of the contact field plate 60 contacts the surface of the shallow trench isolation 22, its bottom surface is preferably lower than the bottom surface of the contact plugs 56 and 58, but the top surface of the contact field plate 60 is preferably flush with the top surface of the contact plugs 56 and 58. In other words, the overall height of the contact field plate 60 is preferably greater than the height of the contact plug 56 connected to the source region 38 and the contact plug 58 connected to the drain region 40. In addition, although this embodiment Figure 4 In the embodiment, the gate structure 24 includes a metal gate and the gate structures 26, 28, and 30 include polysilicon gates. However, the present invention is not limited thereto. According to other embodiments of the present invention, the extended gate structure 24 can be applied to Figure 5 In the embodiment, the gate structures 24, 26, 28, and 30 are all formed by metal gates, and this variation also falls within the scope of the present invention.

[0054] Generally speaking, the gate structure or gate electrode of the existing laterally diffused metal oxide semiconductor element usually extends outward to form a field plate to achieve a higher breakdown voltage. In order to improve the existing design without adding extra costs and complicating the manufacturing process, the present invention mainly forms another contact plug as a contact field plate directly above the shallow trench isolation when forming a contact plug connecting the source region and the drain region, so that the laterally diffused metal oxide semiconductor element can use the coupling effect between the contact field plate 60, the interlayer dielectric layer 42, 54 and the gate structure 24 to improve the breakdown voltage of the element. According to different embodiments of the present invention, in addition to forming a contact field plate, the gate structure of the diffused metal oxide semiconductor element can be based on product requirements such as Figure 4 and Figure 5 Generally does not extend to shallow trench isolation or Figure 6 Generally, the gate structure and the contact field plate are extended to the shallow trench isolation so that both the gate structure and the contact field plate are in contact with each other and stand on the shallow trench isolation. These variations are all within the scope of the present invention.

[0055] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A laterally diffused metal oxide semiconductor device, characterized in that: Include: a first fin-shaped structure disposed on the substrate; Shallow trench isolation, provided beside the first fin structure; a first gate structure disposed on the first fin structure; A first spacer is disposed on a sidewall of the first gate structure, wherein an edge of the first spacer is aligned with a sidewall of the first fin structure; as well as A contact field plate is disposed just above the shallow trench isolation next to the first gate structure.

2. The LDMOS device according to claim 1, further comprising: a second fin-shaped structure disposed adjacent to the first fin-shaped structure, wherein the shallow trench isolation is disposed between the first fin-shaped structure and the second fin-shaped structure; A second gate structure is disposed on the second fin structure; and The second spacer is disposed on the sidewall of the second gate structure, wherein an edge of the second spacer is aligned with the sidewall of the second fin structure. The sidewall of the first fin structure and the sidewall of the second fin structure are opposite to each other. 3 . The LDMOS device as claimed in claim 1 , wherein the first gate structure and the second gate structure are both metal gates.

4. The LDMOS device according to claim 2, further comprising: a source region disposed on the first fin structure on one side of the first gate structure; a drain region disposed on the second fin structure on one side of the second gate structure; an interlayer dielectric layer surrounding the first gate structure and the second gate structure; and A first contact plug is disposed on the source region, and a second contact plug is disposed on the drain region. 5 . The LDMOS device as claimed in claim 2 , wherein the contact field plate is disposed between the first gate structure and the second gate structure. 6 . The LDMOS device as claimed in claim 2 , wherein a width of the second gate structure is smaller than a width of the first gate structure. 7 . The LDMOS device as claimed in claim 2 , wherein the contact field plate and the first contact plug comprise the same material. 8 . The LDMOS device as claimed in claim 2 , wherein a bottom surface of the contact field plate is lower than a bottom surface of the first contact plug. 9 . The LDMOS device as claimed in claim 2 , wherein a top surface of the contact field plate is flush with a top surface of the first contact plug.

10. A laterally diffused metal oxide semiconductor device, characterized in that: Include: a first fin-shaped structure disposed on the substrate; Shallow trench isolation, provided beside the first fin structure; A first gate structure is provided on the first fin structure and the shallow trench isolation; as well as A contact field plate is provided directly above the shallow trench isolation next to the first gate structure, The bottom surface of the gate structure disposed on the shallow trench isolation is aligned with the bottom surface of the contact field plate and is lower than the top surface of the first fin structure.

11. The LDMOS device according to claim 10, further comprising: a second fin-shaped structure disposed adjacent to the first fin-shaped structure, wherein the shallow trench isolation is disposed between the first fin-shaped structure and the second fin-shaped structure; a second gate structure disposed on the second fin structure; a source region disposed on the first fin structure on one side of the first gate structure; a drain region disposed on the second fin structure on one side of the second gate structure; an interlayer dielectric layer surrounding the first gate structure and the second gate structure; and A first contact plug is disposed on the source region and a second contact plug is disposed on the drain region. 12 . The LDMOS device of claim 11 , wherein the contact field plate is disposed between the first gate structure and the second gate structure. 13 . The LDMOS device of claim 11 , wherein the contact field plate and the first contact plug comprise the same material. 14 . The LDMOS device as claimed in claim 11 , wherein a bottom surface of the contact field plate is lower than a bottom surface of the first contact plug. 15 . The LDMOS device of claim 11 , wherein a top surface of the contact field plate is flush with a top surface of the first contact plug.

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