Surface emitting laser

Abstract

A surface emitting laser according to one embodiment of the present disclosure includes a first DBR layer, a second DBR layer, an active layer, a first spacer layer, a second spacer layer, a tunnel junction layer, a first electrode layer, and a second electrode layer. The first electrode layer is electrically connected to the first spacer layer without passing through the first DBR layer. The second electrode layer is electrically connected to the second spacer layer without passing through the second DBR layer. The first spacer layer has a flat exposed surface in a region not facing the tunnel junction layer. The first electrode layer is formed in contact with a portion of the first spacer layer deeper than the exposed surface.

Description

Technical Field

[0001] The present disclosure relates to surface emitting lasers. Background Art

[0002] For example, surface emitting lasers are disclosed in Patent Documents 1 and 2.

[0003] Reference List

[0004] Patent Literature

[0005] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2007-315883

[0006] Patent Document 2: Japanese Unexamined Patent Application Publication No. H9-27671 Summary of the Invention

[0007] In order to release the laser into space, it is necessary to consider sufficient safety for the retina of the human eye (eye safety). Therefore, surface-emitting lasers that are eye-safe have been developed in recent years. For surface-emitting lasers that are eye-safe, high efficiency and low power consumption are required. It is desirable to provide a surface-emitting laser that can achieve high efficiency and low voltage.

[0008] A surface emitting laser according to an embodiment of the present disclosure includes a first DBR layer, a second DBR layer, an active layer, a first spacer layer, a second spacer layer, a tunnel junction layer, a first electrode layer, and a second electrode layer. The active layer is disposed between the first DBR layer and the second DBR layer. The first spacer layer is disposed between the active layer and the first DBR layer. The second spacer layer is disposed between the active layer and the second DBR layer. The tunnel junction layer is disposed between the active layer and the second DBR layer. The first electrode layer is electrically coupled to the first spacer layer without passing through the first DBR layer. The second electrode layer is electrically coupled to the second spacer layer without passing through the second DBR layer. The first spacer layer has a flat exposed surface in a region not opposite the tunnel junction layer. The first electrode layer is formed to contact a portion of the first spacer layer that is deeper than the exposed surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] [ Figure 1 ] Figure 1 is a diagram showing an example of a cross-sectional configuration of a surface emitting laser according to the first embodiment of the present disclosure.

[0010] [ Figure 2 ] Figure 2 It shows Figure 1 FIG. 1 is a diagram of an embodiment of an upper surface configuration of a surface emitting laser.

[0011] [ Figure 3 ] Figure 3 It shows Figure 1FIG. 1 is a diagram illustrating an embodiment of a method for manufacturing a surface emitting laser.

[0012] [ Figure 4 ] Figure 4 It shows Figure 3 Schematic diagram of an embodiment of the subsequent manufacturing process.

[0013] [ Figure 5 ] Figure 5 It shows Figure 4 Schematic diagram of an embodiment of the subsequent manufacturing process.

[0014] [ Figure 6 ] Figure 6 It shows Figure 5 Schematic diagram of an embodiment of the subsequent manufacturing process.

[0015] [ Figure 7 ] Figure 7 It shows Figure 6 Schematic diagram of an embodiment of the subsequent manufacturing process.

[0016] [ Figure 8 ] Figure 8 It shows Figure 7 Schematic diagram of an embodiment of the subsequent manufacturing process.

[0017] [ Figure 9 ] Figure 9 It shows Figure 8 Schematic diagram of an embodiment of the subsequent manufacturing process.

[0018] [ Figure 10 ] Figure 10 It shows Figure 9 Schematic diagram of an embodiment of the subsequent manufacturing process.

[0019] [ Figure 11 ] Figure 11 It shows Figure 10 Schematic diagram of an embodiment of the subsequent manufacturing process.

[0020] [ Figure 12 ] Figure 12 is a diagram illustrating an example of a cross-sectional configuration of a surface emitting laser according to a comparative example.

[0021] [ Figure 13 ] Figure 13 is a diagram showing an example of the relationship between carrier concentration and sheet resistance.

[0022] [ Figure 14 ] Figure 14 : is a graph showing examples of IV characteristics of surface emitting lasers according to the embodiment and comparative examples.

[0023] [ Figure 15 ] Figure 15 It shows Figure 1 FIG. 1 is a diagram showing a modified example of the cross-sectional configuration of a surface emitting laser.

[0024] [ Figure 16 ] Figure 16 It shows Figure 1 FIG. 1 is a diagram showing a modified example of the cross-sectional configuration of a surface emitting laser.

[0025] [ Figure 17 ] Figure 17 It shows Figure 1 FIG. 1 is a diagram showing a modified example of the cross-sectional configuration of a surface emitting laser.

[0026] [ Figure 18 ] Figure 18 It shows Figure 1 FIG. 1 is a diagram showing a modified example of the cross-sectional configuration of a surface emitting laser.

[0027] [ Figure 19 ] Figure 19 It shows Figure 1 FIG. 1 is a diagram showing a modified example of the cross-sectional configuration of a surface emitting laser.

[0028] [ Figure 20 ] Figure 20 It shows Figure 19 FIG. 1 is a diagram of an embodiment of an upper surface configuration of a surface emitting laser.

[0029] [ Figure 21 ] Figure 21 It shows Figure 1 FIG. 1 is a diagram showing a modified example of the cross-sectional configuration of a surface emitting laser.

[0030] [ Figure 22 ] Figure 22 It shows Figure 1 FIG. 1 is a diagram showing a modified example of the cross-sectional configuration of a surface emitting laser.

[0031] [ Figure 23 ] Figure 23 It shows Figure 1 FIG. 1 is a diagram showing a modified example of the cross-sectional configuration of a surface emitting laser.

[0032] [ Figure 24 ] Figure 24 It shows Figure 1 FIG. 1 is a diagram showing a modified example of the cross-sectional configuration of a surface emitting laser.

[0033] [ Figure 25 ] Figure 25 It shows Figure 1 FIG. 1 is a diagram showing a modified example of the cross-sectional configuration of a surface emitting laser.

[0034] [ Figure 26 ] Figure 26 It shows Figure 1 FIG. 1 is a diagram showing a modified example of the cross-sectional configuration of a surface emitting laser.

[0035] [ Figure 27 ] Figure 27 It shows Figure 1 FIG. 1 is a diagram showing a modified example of the cross-sectional configuration of a surface emitting laser.

[0036] [ Figure 28 ] Figure 28 It shows Figure 1 FIG. 1 is a diagram showing a modified example of the cross-sectional configuration of a surface emitting laser.

[0037] [ Figure 29 ] Figure 29 It shows Figure 1 FIG. 1 is a diagram showing a modified example of the cross-sectional configuration of a surface emitting laser.

[0038] [ Figure 30 ] Figure 30 It shows Figure 1 FIG. 1 is a diagram showing a modified example of the cross-sectional configuration of a surface emitting laser.

[0039] [ Figure 31 ] Figure 31 It shows Figure 1 FIG. 1 is a diagram showing a modified example of the cross-sectional configuration of a surface emitting laser.

[0040] [ Figure 32 ] Figure 32 is a diagram illustrating an example of a cross-sectional configuration of a surface emitting laser according to a second embodiment of the present disclosure.

[0041] [ Figure 33 ] Figure 33 It shows Figure 32 FIG. 1 is a diagram of an embodiment of an upper surface configuration of a surface emitting laser.

[0042] [ Figure 34 ] Figure 34 It shows Figure 32 FIG. 1 is a diagram showing a modified example of the cross-sectional configuration of a surface emitting laser. DETAILED DESCRIPTION

[0043] Hereinafter, embodiments for practicing the present disclosure will be described in detail with reference to the accompanying drawings. The following description is a specific embodiment of the present disclosure, and the present disclosure is not limited to the following embodiments. In addition, the present disclosure is not limited to the arrangement, size, size ratio, etc. of the corresponding components shown in the accompanying drawings. Note that the description is given in the following order.

[0044] 1. First embodiment: Figures 1 to 14

[0045] Embodiments of the lower electrode embedded in the semiconductor layer

[0046] 2. Modification of the First Embodiment

[0047] Modification A: Example where the lower electrode includes a metal layer and a plating layer ( Figure 15 )

[0048] Modification B: An embodiment in which the lower electrode includes a diffused metal region and an alloy metal layer ( Figure 16 )

[0049] Modification C: An embodiment in which the lower electrode includes a diffused metal region, an alloy metal layer, and a metal layer ( Figure 17 )

[0050] Modification D: An embodiment in which the lower electrode is formed at the interface between the active layer and the semiconductor layer in contact with the active layer ( Figure 18 );

[0051] Modification E: An embodiment in which the annular lower electrode is arranged around the table ( Figure 19 and Figure 20 )

[0052] Modification F: An embodiment in which the embedded portion of the lower electrode has a cross-sectional shape tapering forward ( Figure 21 )

[0053] Modification G: Example in which the embedded portion of the lower electrode has a conical shape ( Figure 22 )

[0054] Modification H: Example of forming a tunnel junction using ion implantation ( Figure 23 )

[0055] Modification I: An embodiment in which a transparent conductive layer is provided between the semiconductor layer and the upper DBR layer ( Figure 24 )

[0056] Modification J: Embodiment in which the lower DBR layer comprises a dielectric ( Figure 25 )

[0057] Modification K: An embodiment in which the lower reflector includes a dielectric DBR layer and a reflective metal layer ( Figure 26 )

[0058] Modification L: Example in which the lower DBR layer comprises a GaAs semiconductor ( Figure 27 )

[0059] Modification M: In a back-emitting surface emitting laser, an embodiment in which the lower electrode is embedded in the semiconductor layer ( Figure 28 )

[0060] Modification N: In a back-emitting surface-emitting laser, an embodiment in which the lower DBR layer includes a dielectric ( Figure 29 )

[0061] Modification O: In a back-emitting surface-emitting laser, an embodiment in which the lower DBR layer comprises a GaAs semiconductor ( Figure 30 )

[0062] Modification P: In a back-emitting surface emitting laser, an embodiment in which the upper reflecting mirror includes a dielectric DBR layer and a reflective metal layer ( Figure 31 ).

[0063] 3. Second embodiment

[0064] An embodiment in which the lower electrode is disposed on the bottom surface of the groove ( Figure 32 and Figure 33 )

[0065] 4. Modification of the Second Embodiment

[0066] Modification Q: In a back-emitting surface emitting laser, an embodiment in which the lower electrode is embedded in the semiconductor layer ( Figure 34 )

[0067] 1. First Implementation

[0068] [Configuration]

[0069] A surface emitting laser 1 according to a first embodiment of the present disclosure will be described. Figure 1 An example of a cross-sectional configuration of the surface emitting laser 1 is shown. Figure 2 An example of an upper surface configuration of the surface emitting laser 1 is shown.

[0070] The surface emitting laser 1 includes a vertical resonator structure 20 on a substrate 10. The substrate 10 is a crystal growth substrate for epitaxial crystal growth of the vertical resonator structure 20. In the surface emitting laser 1, the substrate 10 may be omitted.

[0071] The vertical resonator structure 20 includes a semiconductor distributed Bragg reflector (DBR) layer 21, a dielectric DBR layer 26, and a cavity layer disposed between the semiconductor DBR layer 21 and the dielectric DBR layer 26. The cavity layer is designed based on the oscillation wavelength λ0 and the application. The cavity layer includes, for example, an active layer 23, a spacer layer 22 located between the active layer 23 and the semiconductor DBR layer 21, spacer layers 24 and 25 disposed between the active layer 23 and the dielectric DBR layer 26, and a tunnel junction layer disposed between the active layer 23 and the dielectric DBR layer 26.

[0072] The spacer layer 24 is provided on the active layer 23 side, and the spacer layer 25 is provided on the dielectric DBR layer 26 side. Figure 1 As shown, the tunnel junction layer is surrounded by spacer layers 24 and 25. Spacer layer 24 contacts the bottom surface of the tunnel junction layer, and spacer layer 25 contacts the top and side surfaces of the tunnel junction layer. Figure 1 As shown, the tunnel junction layer includes a high-concentration p-layer 28 and a high-concentration n-layer 29, which are stacked one on top of the other. Spacer layer 24 is in contact with the bottom surface of high-concentration p-layer 28, and spacer layer 25 is in contact with the side surfaces of high-concentration p-layer 28. High-concentration p-layer 28 is in contact with the bottom surface of high-concentration n-layer 29, and spacer layer 25 is in contact with the top and side surfaces of high-concentration n-layer 29.

[0073] The tunnel junction layer forms a current-confining structure via a tunnel junction. In the tunnel junction layer, at the boundary between high-concentration p-layer 28 and high-concentration n-layer 29, the conduction band of high-concentration p-layer 28 and the valence band of high-concentration n-layer 29 approach each other, forming a tunnel junction between high-concentration p-layer 28 and high-concentration n-layer 29. As a result, current flows from high-concentration n-layer 29 to high-concentration p-layer 28 in the tunnel junction layer.

[0074] The surface-emitting laser 1 is configured so that laser light L having an oscillation wavelength λ0 is emitted from the dielectric DBR layer 26 side. Specifically, in the vertical resonator structure 20, the number of pairs and reflectivity of the reflective mirrors on the semiconductor DBR layer 21 side, and the number of pairs and reflectivity of the reflective mirrors on the dielectric DBR layer 26 side are configured so that laser light L having an oscillation wavelength λ0 is emitted from the dielectric DBR layer 26 side. Therefore, the surface-emitting laser 1 is an upper surface-emitting laser that emits laser light L from a light-emitting surface 1S provided on the dielectric DBR layer 26 side.

[0075] In the vertical resonator structure 20 , at least the active layer 23 , the spacer layer 24 , the tunnel junction layer, the spacer layer 25 , and the dielectric DBR layer 26 constitute a columnar mesa portion 20A extending in the normal direction of the substrate 10 . Figure 1 The embodiment of the mesa portion 20A is shown, which includes a portion of the spacer layer 22, an active layer 23, a spacer layer 24, a tunnel junction layer, a spacer layer 25, and a dielectric DBR layer 26. The mesa portion 20A has, for example, a circular shape when viewed from above. Considering the position of the mesa portion 20A, the semiconductor DBR layer 21 is provided in a region on the substrate 10 side.

[0076] The tunnel junction layer is provided in the center of the mesa portion 20A when viewed from above. The tunnel junction layer has, for example, a circular shape when viewed from above. The tunnel junction layer is provided on the opposite side of the active layer 23 from the substrate 10 (i.e., on the light-emitting surface 1S side). A protrusion is formed on the upper surface of the spacer layer 25 at a portion opposite the tunnel junction layer. The shape of the protrusion corresponds to the shape of the tunnel junction layer. The protrusion is provided in the center of the mesa portion 20A when viewed from above and has, for example, a circular shape when viewed from above.

[0077] The dielectric DBR layer 26 is in contact with the upper surface of the spacer layer 25 , for example, in contact with the upper surface of the aforementioned protrusion. Figure 1 In the embodiment shown, the dielectric DBR layer 26 contacts the upper surface of the spacer layer 25. Specifically, the dielectric DBR layer 26 contacts not only the upper surface of the protrusion but also the side surface and bottom edge portion of the protrusion. The portion of the dielectric DBR layer 26 that contacts the side surface and bottom edge portion of the protrusion does not contribute to laser oscillation.

[0078] For example, Figure 1 and Figure 2 As shown, the surface emitting laser 1 further includes a contact layer 27 and an electrode layer 32 as an upper electrode above the mesa portion 20A. The contact layer 27 is in contact with the spacer layer 25 and the electrode layer 32. For example, Figure 1 As shown, the contact layer 27 is in contact with the bottom edge portion of the protrusion of the spacer layer 25 and has, for example, a ring shape surrounding the protrusion of the spacer layer 25 when viewed from above. The contact layer 27 is a layer that makes ohmic contact between the spacer layer 25 and the electrode layer 32. The electrode layer 32 is in contact with the contact layer 27 and is electrically coupled to the spacer layer 25 not via the dielectric DBR layer 26 but via the contact layer 27. For example, Figure 1 and Figure 2 As shown, the electrode layer 32 has a protruding annular shape surrounding the spacer layer 25 in a plan view.

[0079] For example, Figure 1 As shown, the surface emitting laser 1 further includes an electrode layer 31 as a lower electrode at a portion corresponding to the bottom edge of the mesa portion 20A. Figure 1 and Figure 2 As shown, a portion of the spacer layer 22 is exposed at a portion corresponding to the bottom edge of the mesa portion 20A. Hereinafter, the portion of the spacer layer 22 corresponding to the bottom edge of the mesa portion 20A is referred to as an exposed surface 22S. The exposed surface 22S is a flat surface. For example, the exposed surface 22S is a flat surface parallel to the stacking plane of the semiconductor DBR layer 21. The electrode layer 31 is formed so as to contact the portion of the exposed surface 22S and also contact a portion of the spacer layer 22 that is deeper than the exposed surface 22S. The spacer layer 22 has a recess 22A in the exposed surface 22S, which has a depth that does not reach the semiconductor DBR layer 21. The electrode layer 31 is formed so as to fill the recess 22A and contact the spacer layer 22 at the inner surface of the recess 22A. The electrode layer 31 is electrically coupled to the spacer layer 22 without passing through the semiconductor DBR layer 21. Therefore, in the surface emitting laser 1, the current path formed by the electrode layer 31 and the electrode layer 32 is provided in such a manner as not to pass through the semiconductor DBR layer 21 and the dielectric DBR layer 26 ( Figure 1 dotted line in the figure).

[0080] Next, the material of each component of the surface emitting laser 1 will be described.

[0081] The substrate 10 is an n-type InP substrate, which contains, for example, silicon (Si) as an n-type impurity.

[0082] The semiconductor DBR layer 21 is an undoped semiconductor DBR layer. It is formed by alternately stacking low-refractive-index semiconductor layers containing undoped InP and high-refractive-index semiconductor layers containing undoped AlGaInAs. The optical thickness of each of the low-refractive-index semiconductor layer and the high-refractive-index semiconductor layer is, for example, λ0×1 / 4.

[0083] Spacer layers 22, 24, and 25 comprise an InP-based semiconductor. Spacer layer 22 comprises, for example, n-type InP. The n-type InP contains, for example, silicon (Si) as an n-type impurity. Spacer layer 24 comprises, for example, p-type InP. The p-type InP contains, for example, carbon (C), zinc (Zn), magnesium (Mg), or beryllium (Be) as a p-type impurity. Spacer layer 25 comprises, for example, n-type InP. The n-type InP contains, for example, silicon (Si) as an n-type impurity.

[0084] The dielectric DBR layer 26 is formed by alternately stacking low-refractive-index dielectric layers composed of a first dielectric material and high-refractive-index dielectric layers composed of a second dielectric material. The optical thickness of each of the low-refractive-index dielectric layer and the high-refractive-index dielectric layer is, for example, λ0×1 / 4. The low-refractive-index dielectric layer comprises, for example, SiO2. The high-refractive-index dielectric layer comprises, for example, Ta2O5. The material of the dielectric DBR layer 26 is not limited to the aforementioned dielectric materials.

[0085] Contact layer 27 includes, for example, n-type InGaAs containing n-type impurities at a higher concentration than the n-type impurities of spacer layer 25. The n-type InGaAs contains the same impurities as those contained in spacer layer 25 as n-type impurities. Electrode layer 31 has a structure in which Ti, Pt, and Au are stacked in this order from the inner surface side of recess 22A of spacer layer 22. Ti, Pt, and Au are formed, for example, by sputtering or vapor deposition. Electrode layer 32 has a structure in which Ti, Pt, and Au, or AuGe, Ni, and Au, are stacked in this order from the contact layer 27 side. The material of electrode layer 32 is not limited to the aforementioned materials.

[0086] High-concentration p-layer 28 includes p-type AlGaInAs containing a p-type impurity at a higher concentration than the p-type impurity concentration of spacer layer 24. For example, p-type AlGaInAs contains, as a p-type impurity, the same impurity as the p-type impurity contained in spacer layer 24. High-concentration n-layer 29 includes n-type InP containing an n-type impurity at a higher concentration than the n-type impurity concentration of spacer layer 25. For example, n-type InP contains, as an n-type impurity, the same impurity as the n-type impurity contained in spacer layer 25.

[0087] [Manufacturing method]

[0088] Next, a method of manufacturing the surface emitting laser 1 according to the present embodiment will be described.

[0089] To manufacture the surface-emitting laser 1, a compound semiconductor is formed on a substrate 10 containing, for example, InP by an epitaxial crystal growth method such as metal organic chemical vapor deposition (MOCVD). In this process, for example, a methyl-based organometallic gas (such as trimethylaluminum (TMAl), trimethylgallium (TMGa), or trimethylindium (TMIn)), phosphine (PH3) gas, or arsine (AsH3) gas is used as a raw material for the compound semiconductor. For example, disilane (Si2H6) is used as a raw material for the donor impurity, and for example, tetrabromide (CBr4) is used as a raw material for the acceptor impurity.

[0090] First, for example, a semiconductor DBR layer 21, a spacer layer 22, an active layer 23, a spacer layer 24, a high concentration p layer 28, and a high concentration n layer 29 are formed on a substrate 10 by an epitaxial crystal growth method such as an MOCVD method. Figure 3 ). Next, for example, a circular resist layer (not shown) is formed in a plan view, and then the high concentration p layer 28 and the high concentration n layer 29 are selectively etched using the resist layer as a mask. As a result, the high concentration p layer 28 and the high concentration n layer 29 are formed into a circular shape in a plan view ( Figure 4 ). The resist layer is then removed.

[0091] Next, for example, a spacer layer 25 and a contact layer 27 are formed on the surface including the surface of the circular high concentration p layer 28 and the circular high concentration n layer 29 by an epitaxial crystal growth method such as an MOCVD method. Figure 5 At this time, in the isolation layer 25 and the contact layer 27 , a stepped structure portion having a shape simulating the circular high-concentration p layer 28 and the circular high-concentration n layer 29 is formed in a region facing the circular high-concentration p layer 28 and the circular high-concentration n layer 29 .

[0092] Next, for example, a circular resist layer (not shown) is formed that covers a predetermined area centered around the circular high-concentration p layer 28 and the circular high-concentration n layer 29 when viewed from above. Using this resist layer as a mask, the semiconductor layer such as the contact layer 27 is selectively etched to a depth that reaches the spacer layer 22. At this time, it is preferable to use reactive ion etching (RIE) using, for example, a Cl-based gas. In this way, the columnar mesa portion 20A ( Figure 6 ). At this time, the spacer layer 22 is exposed at the bottom edge of the mesa portion 20A. In other words, the exposed surface 22S is formed at the bottom edge of the mesa portion 20A. The resist layer is then removed.

[0093] Next, the electrode layer 32 ( Figure 7 ). Then, for example, a resist layer (not shown) is formed that covers the electrode layer 32 and the mesa portion 20A and has an opening only at a predetermined portion of the exposed surface 22S. Using this resist layer as a mask, the spacer layer 22 is selectively etched, and the spacer layer 22 is etched to a depth that does not reach the semiconductor DBR layer 21. At this time, it is preferable to use RIE using, for example, a Cl-based gas. In this way, the recessed portion 22A is formed in the exposed surface 22S ( Figure 8 ). The resist layer is then removed.

[0094] Next, the electrode layer 31 is formed so as to fill the recess 22A ( Figure 9 ). As a result, the electrode layer 31 contacts the portion in the exposed surface 22S and also contacts the portion of the spacer layer 22 deeper than the exposed surface 22S (specifically, the inner surface of the recessed portion 22A). Next, a resist layer (not shown) having an opening only at the portion in the upper surface of the mesa portion 20A surrounded by the electrode layer 32 is formed. The contact layer 27 is selectively etched using this resist layer as a mask. In this way, the protrusions ( Figure 10 ). The resist layer is then removed.

[0095] Then, a dielectric DBR layer 26 ( ) is formed on the entire surface including the surface of the protrusion of the spacer layer 25 using, for example, a vacuum evaporation method. Figure 11 ). Then, the formed dielectric DBR layer 26 is selectively removed except for the portion surrounded by the electrode layer 32. In this way, the surface emitting laser 1 is manufactured.

[0096] [operate]

[0097] In the surface-emitting laser 1 having this configuration, when a predetermined voltage is applied between the electrode layer 31 electrically coupled to the spacer layer 22 and the electrode layer 32 electrically coupled to the contact layer 27, a current confined by the tunnel junction layer formed by the high-concentration p-layer 28 and the high-concentration n-layer 29 is injected into the active layer 23. This results in light emission due to the recombination of electrons and holes. At this time, the tunnel junction layer confines the light generated in the active layer 23 in the in-plane direction of the stacking plane. As a result, laser oscillation at an oscillation wavelength λ0 is generated due to the vertical resonator structure 20. Light leaking from the dielectric DBR layer 26 becomes a beam of laser light L and is output externally from the light-emitting surface 1S.

[0098] [Effect]

[0099] Next, the effects of the surface emitting laser 1 of the present embodiment will be described.

[0100] In order to release laser light into space, it is necessary to consider sufficient safety for the human retina (eye safety). Therefore, eye-safe surface-emitting lasers have been developed in recent years. For eye-safe surface-emitting lasers, high efficiency and low power consumption are required.

[0101] On the other hand, according to the present embodiment, the spacer layer 22 provided between the active layer 23 and the semiconductor DBR layer 21 has a flat exposed surface 22S in a region not facing the tunnel junction layer. The electrode layer 31 is formed so as to be in contact with a portion of the spacer layer 22 that is deeper than the exposed surface 22S. As a result, with, for example Figure 12 Compared to the comparative example in which the electrode layer 131 is provided only on the exposed surface 22S in the surface emitting laser 100 , the density of the current flowing laterally in the spacer layer 22 is reduced and the operating voltage is also reduced.

[0102] For example, Figure 13 As shown, the sheet resistance of the surface emitting laser 1 according to the present embodiment can be significantly reduced compared to the sheet resistance of the surface emitting laser 100 according to the comparative example. Figure 14 As shown, the operating voltage of the surface emitting laser 1 according to the present embodiment can be significantly reduced (by about 0.2 V) compared to the operating voltage of the surface emitting laser 100 according to the comparative example.

[0103] Furthermore, according to this embodiment, the current path formed by the electrode layer 31 and the electrode layer 32 is arranged so as not to pass through the semiconductor DBR layer 21 and the dielectric DBR layer 26. Neither the semiconductor DBR layer 21 nor the dielectric DBR layer 26 need to contain an impurity-doped semiconductor. As a result, losses due to free-carrier absorption in the semiconductor DBR layer 21 and the dielectric DBR layer 26 can be reduced. Furthermore, since the impurity concentration of the spacer layer 22 itself can be reduced, losses due to free-carrier absorption in the spacer layer 22 can also be reduced. Consequently, higher efficiency and lower voltage can be achieved.

[0104] Furthermore, this embodiment can improve oscillation efficiency by reducing losses due to free-carrier absorption. The reduced operating voltage can reduce power consumption in the surface-emitting laser 1 and keep the temperature rise in the surface-emitting laser 1 low. Consequently, the reliability of the surface-emitting laser 1 can be enhanced. Furthermore, the reduced operating voltage allows for the implementation of an array of surface-emitting lasers 1.

[0105] According to this embodiment, recess 22A is formed in exposed surface 22S of spacer layer 22, and electrode layer 31 is formed to fill recess 22A. As a result, electrode layer 31 contacts a portion of spacer layer 22 that is deeper than exposed surface 22S. Compared to a case where electrodes are provided only on exposed surface 22S, the density of current flowing laterally in spacer layer 22 is reduced, and the operating voltage is also reduced. Furthermore, since the current path formed by electrode layer 31 and electrode layer 32 is provided without passing through semiconductor DBR layer 21 and dielectric DBR layer 26, neither semiconductor DBR layer 21 nor dielectric DBR layer 26 need to contain an impurity-doped semiconductor. As a result, losses caused by free carrier absorption in semiconductor DBR layer 21 and dielectric DBR layer 26 can be reduced. Consequently, higher efficiency and lower voltage can be achieved.

[0106] According to this embodiment, the electrode layer 31 is formed so as to contact a portion of the exposed surface 22S and also contact a portion of the spacer layer 22 deeper than the exposed surface 22S. Compared to a case where the electrode is provided only on the exposed surface 22S, the density of the current flowing laterally in the spacer layer 22 is reduced, and the operating voltage is also reduced. Furthermore, since the current path formed by the electrode layer 31 and the electrode layer 32 is provided so as not to pass through the semiconductor DBR layer 21 and the dielectric DBR layer 26, neither the semiconductor DBR layer 21 nor the dielectric DBR layer 26 need to contain an impurity-doped semiconductor. As a result, losses caused by free carrier absorption in the semiconductor DBR layer 21 and the dielectric DBR layer 26 can be reduced. Consequently, higher efficiency and lower voltage can be achieved.

[0107] According to this embodiment, electrode layer 31 has a structure in which Ti, Pt, and Au are stacked in this order from the inner surface side of recess 22A. Ti contacts the inner surface of recess 22A and forms ohmic contact with the inner surface of recess 22A (spacer layer 22). Pt prevents impurities contained in spacer layer 22 from diffusing into Au. Au strengthens the bond between electrode layer 31 and the solder, thereby enabling lower voltages to be achieved.

[0108] According to this embodiment, spacer layers 22, 24, and 25 include an InP-based semiconductor, semiconductor DBR layer 21 includes an undoped semiconductor, and dielectric DBR layer 26 includes a dielectric. This reduces losses due to free carrier absorption in semiconductor DBR layer 21 and dielectric DBR layer 26. Consequently, higher efficiency can be achieved.

[0109] According to the present embodiment, the semiconductor DBR layer 21 and the dielectric DBR layer 26 are configured so that the laser light L can be emitted from the side of the dielectric DBR layer 26. This enables realization of a top surface emitting laser.

[0110] According to the present embodiment, the mesa portion 20A is provided. This allows the electrode layer 31 to be formed near the tunnel junction layer. As a result, a lower voltage can be achieved.

[0111] 2. Modification of the First Embodiment

[0112] [Variation A]

[0113] According to the aforementioned embodiment, for example, Figure 15 As shown, the electrode layer 31 may include a metal layer 31a and a plating layer 31b formed on the metal layer 31a, in which Ti, Pt, and Au are stacked in this order from the inner surface side of the recess 22A. This configuration allows the turnaround time (TAT) of the electrode layer 31 to be shortened compared to a case where the electrode layer 31 is entirely composed of the metal layer 31a.

[0114] [Variation B]

[0115] According to the aforementioned embodiment, for example, Figure 16As shown, the electrode layer 31 may have a diffusion metal region 31c and an alloy metal layer 31d. The alloy metal layer 31d is in contact with the exposed surface 22S and is, for example, a layer in which AuGe, Ni, and Au are stacked in sequence from the exposed surface 22S side. The alloy metal layer 31d may be, for example, a layer in which Pd and Ge are stacked in sequence from the exposed surface 22S side. The diffusion metal region 31c is provided at a portion of the spacer layer 22 that is deeper than the exposed surface 22S and is in contact with the alloy metal layer 31d. The diffusion metal region 31c is formed, for example, by heating the alloy metal layer 31d formed on the exposed surface 22S at a predetermined temperature and diffusing Ge contained in the alloy metal layer 31d to a portion of the spacer layer 22 that is deeper than the exposed surface 22S. Such a structure makes it possible to reduce the operating voltage without etching the spacer layer 22 to form the recess 22A. As a result, a lower voltage can be achieved.

[0116] [Variant C]

[0117] According to the aforementioned modification B, for example, Figure 17 As shown, the electrode layer 31 may further include a metal layer 31e. The metal layer 31e is formed on the alloy metal layer 31d and includes a material different from that of the alloy metal layer 31d. The metal layer 31e is, for example, a stack of Ti, Pt, and Au in the order from the alloy metal layer 31d. This configuration enables a lower voltage to be achieved.

[0118] [Variant D]

[0119] According to the aforementioned embodiment and its modified example, the exposed surface 22S can be formed in the same plane as the interface between the active layer 23 and the spacer layer 22. According to this modified example, for example, Figure 18 As shown, the exposed surface 22S is formed in the same plane as the interface between the active layer 23 and the spacer layer 22. In such a configuration, the distance of the current path can be shortened compared to the aforementioned embodiment, and thus a lower voltage can be achieved.

[0120] [Variation E]

[0121] According to the aforementioned embodiment and its modified example, the electrode layer 31 can be formed in an annular region surrounding the electrode layer 32 in a plan view. According to this modified example, for example, Figure 19 and Figure 20 As shown, the electrode layer 31 has a ring shape surrounding the electrode layer 32 in a plan view. Figure 19 is a diagram showing an example of a cross-sectional configuration of a surface emitting laser 1 according to the present modification. Figure 20 express Figure 19The embodiment of the upper surface configuration of the surface emitting laser 1 described in . Compared with the aforementioned embodiment, the density of the current flowing laterally in the spacer layer 22 is further reduced, and the operating voltage is also further reduced. As a result, the voltage can be further reduced.

[0122] [Variant F]

[0123] According to the aforementioned embodiment and its modified example, the recess 22A may have a cross-sectional shape that tapers forward in the stacking direction. According to this modified example, for example, Figure 21 As shown, the cross-sectional shape of recess 22A in the stacking direction can be a shape that tapers forward. In this case, the portion of electrode layer 31 embedded in recess 22A has a shape that is the opposite of the shape of recess 22A. Even in this case, as in the aforementioned embodiment and its variations, the density of the current flowing laterally in spacer layer 22 is reduced, and the operating voltage is also reduced. As a result, a lower voltage can be achieved.

[0124] [Variant G]

[0125] According to the aforementioned embodiment and its modified example, the shape of the recess 22A may be conical. According to this modified example, for example, Figure 22 As shown, recess 22A may have a conical shape. In this case, the portion of electrode layer 31 embedded in recess 22A has a shape opposite to that of recess 22A. Even in this case, as in the aforementioned embodiment and its variations, the density of the current flowing laterally in spacer layer 22 decreases, and the operating voltage also decreases. As a result, a lower voltage can be achieved.

[0126] [Variation H]

[0127] According to the aforementioned embodiment and its modified example, the tunnel junction layer can be formed in a region surrounded by a region having high resistance by ion implantation into the vertical resonator structure 20 in a plan view. According to this modified example, for example, Figure 23 As shown, the tunnel junction layer TJ may be formed in a region surrounded by a region 33 having high resistance due to ion implantation into the vertical resonator structure 20 (the high-concentration p layer 28 and the high-concentration n layer 29 ) in a plan view.

[0128] In region 33, the tunnel junction formed by high-concentration p-layer 28 and high-concentration n-layer 29 is degraded due to the reduction in carrier concentration through ion implantation. As a result, the resistance of region 33 is greater than the resistance of tunnel junction layer TJ. The ions to be implanted into region 33 can specifically include O, N, B, H, and He ions. Of these, O ions are particularly suitable because they can oxidize region 33.

[0129] Therefore, according to this modification, the current confinement structure is formed by ion implantation. Such a structure allows the omission of etching of the high-concentration p layer 28 and the high-concentration n layer 29 according to the aforementioned embodiment.

[0130] [Modification 1]

[0131] According to the aforementioned modification H, the region 33 may be formed in a region extending from the upper surface of the spacer layer 25 to the spacer layer 22. According to the aforementioned modification H, for example, Figure 24 As shown, the region 33 may be formed in a region that reaches the spacer layer 22 from the upper surface of the spacer layer 25. In this case, a transparent conductive layer 34 may be provided instead of the contact layer 27. The transparent conductive layer 34 is provided between the dielectric DBR layer 26 and the spacer layer 25, and is in contact with the portion of the upper surface of the spacer layer 25 surrounded by the region 33 and the electrode layer 32. The transparent conductive layer 34 is electrically coupled to the spacer layer 25 and the electrode layer 32, and constitutes a portion of the current path in the surface emitting laser 1.

[0132] The transparent conductive layer 34 includes, for example, an indium-based transparent conductive material, a tin-based transparent conductive material, or a zinc-based transparent conductive material. Examples of indium-based transparent conductive materials include indium tin oxide (ITO) (including Sn-doped In2O3, crystalline ITO, and amorphous ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium-doped gallium zinc oxide (IGZO and In-GaZnO4), IFO (F-doped In2O3), ITiO (Ti-doped In2O3), and InSn or InSnZnO. Examples of tin-based transparent conductive materials include tin oxide (SnO2), ATO (Sb-doped SnO2), or FTO (F-doped SnO2). Examples of zinc-based transparent conductive materials include zinc oxide (ZnO) (including Al-doped ZnO (AZO) and B-doped ZnO), gallium-doped zinc oxide (GZO), and AlMgZnO (aluminum oxide and magnesium oxide doped zinc oxide).

[0133] Therefore, according to this modification, a transparent conductive layer 34 is provided that is electrically coupled to the spacer layer 25 and the electrode layer 32. As a result, even when the region 33 is formed in the region reaching the spacer layer 22 from the upper surface of the spacer layer 25, current can be injected into the surface emitting laser 1.

[0134] [Variation J]

[0135] According to the aforementioned embodiment and its modified examples, for example, Figure 25 As shown, a dielectric DBR layer 35 may be provided instead of the semiconductor DBR layer 21 .

[0136] The dielectric DBR layer 35 is formed by alternately stacking low-refractive-index dielectric layers composed of a first dielectric material and high-refractive-index dielectric layers composed of a second dielectric material. The optical thickness of each of the low-refractive-index dielectric layer and the high-refractive-index dielectric layer is, for example, λ0×1 / 4. The low-refractive-index dielectric layer may comprise, for example, SiO2. The high-refractive-index dielectric layer may comprise, for example, Ta2O5. The material of the dielectric DBR layer 35 is not limited to the aforementioned dielectric materials. The material of the dielectric DBR layer 35 may be a different material from that of the dielectric DBR layer 26 or a common material with the dielectric DBR layer 26.

[0137] Therefore, according to this modification, the dielectric DBR layer 35 is provided. This can reduce the loss due to free carrier absorption in the dielectric DBR layer 35. As a result, higher efficiency and lower voltage can be achieved.

[0138] [Variation K]

[0139] According to the aforementioned modification J, for example, Figure 26 As shown, the reflective metal layer 36 may be provided in contact with the dielectric DBR layer 35 on the side opposite to the active layer 23. As viewed from the active layer 23, the reflective metal layer 36 acts as the end portion of the reflector on the dielectric DBR layer 35 side. The reflective metal layer 36 assists the function of the dielectric DBR layer 35 and helps reduce the number of pairs of the dielectric DBR layer 35. The reflective metal layer 36 includes, for example, gold (Au), silver (Ag), or aluminum (Al). The thickness of the reflective metal layer 36 is, for example, 20 nm or greater.

[0140] Therefore, according to this modification, the reflective metal layer 36 is provided. Since the number of pairs of the dielectric DBR layer 35 can be reduced, the turnaround time (TAT) of the surface emitting laser 1 can be shortened compared to the case where the reflective metal layer 36 is not provided.

[0141] [Variation L]

[0142] According to the aforementioned embodiment and its modifications A to I, for example, Figure 27 As shown, a substrate 40 and a semiconductor DBR layer 41 may be provided instead of the substrate 10 and the semiconductor DBR layer 21, respectively.

[0143] The substrate 40 is a crystal growth substrate for epitaxial crystal growth of the semiconductor DBR layer 41. According to this modification, the substrate 40 can be omitted. The substrate 40 is an n-type GaAs substrate. The n-type GaAs substrate contains, for example, silicon (Si) as an n-type impurity. The semiconductor DBR layer 41 is an undoped GaAs semiconductor DBR layer. The semiconductor DBR layer 41 is formed by alternately stacking low-refractive-index semiconductor layers containing undoped AlAs and high-refractive-index semiconductor layers containing undoped GaAs. The optical thickness of each of the low-refractive-index semiconductor layer and the high-refractive-index semiconductor layer is, for example, λ0×1 / 4.

[0144] According to this modification, the substrate 40 having the semiconductor DBR layer 41 formed thereon is attached to the semiconductor DBR layer 41 so that the surface of the substrate 40 on the semiconductor DBR layer 41 side faces the spacer layer 22. Here, the semiconductor DBR layer 41 is not included in the current path. Therefore, the semiconductor DBR layer 41 can be attached depending on the value of the oscillation wavelength λ0 and the application.

[0145] [Variation M]

[0146] According to the aforementioned embodiment and its modifications A to J and L, the surface emitting laser 1 may be a back-emitting laser having a rear surface on which the light emitting surface 1S is provided. Figure 28 As shown, the surface emitting laser 1 can be configured so that laser light L having an oscillation wavelength λ0 is emitted from the semiconductor DBR layer 21 side. Specifically, in the vertical resonator structure 20, the number of pairs and reflectivity of the reflective mirrors on the semiconductor DBR layer 21 side and the number of pairs and reflectivity of the reflective mirrors on the dielectric DBR layer 26 side can be set so that laser light L having an oscillation wavelength λ0 is emitted from the semiconductor DBR layer 21 side. This configuration can produce effects similar to those produced in the aforementioned embodiment and its modifications A to J and L.

[0147] [Variant N]

[0148] According to the aforementioned modification M, for example, Figure 29 As shown, a dielectric DBR layer 35 may be provided instead of the substrate 10 and the semiconductor DBR layer 21. This configuration can produce effects similar to those produced according to the aforementioned modification M.

[0149] [Variation O]

[0150] According to the aforementioned modification M, for example, Figure 30 As shown, a semiconductor DBR layer 41 may be provided instead of the substrate 10 and the semiconductor DBR layer 21. This configuration can produce effects similar to those produced according to the aforementioned modification M.

[0151] [Variation P]

[0152] In the aforementioned embodiment and its modifications A to J and L to O, for example, Figure 31 As shown, a reflective metal layer 37 may be provided in contact with the side of the dielectric DBR layer 26 opposite the active layer 23. As viewed from the active layer 23, the reflective metal layer 37 acts as the end portion of the reflector on the dielectric DBR layer 26 side. The reflective metal layer 37 assists the function of the dielectric DBR layer 26 and helps reduce the number of pairs of the dielectric DBR layer 26. The reflective metal layer 37 includes, for example, gold (Au), silver (Ag), or aluminum (Al). The thickness of the reflective metal layer 37 is, for example, 20 nm or greater.

[0153] Therefore, according to the present modification, the reflective metal layer 37 is provided. Since the number of pairs of the dielectric DBR layer 26 can be reduced, the heat dissipation performance of the surface emitting laser 1 can be enhanced compared to the case where the reflective metal layer 37 is not provided.

[0154] 3. Second embodiment

[0155] [Configuration]

[0156] A surface emitting laser 2 according to a second embodiment of the present disclosure will be described. Figure 32 is a diagram showing an example of a cross-sectional configuration of the surface emitting laser 2 . Figure 33 is a diagram showing an example of the upper surface configuration of the surface emitting laser 2 .

[0157] According to this embodiment, in the vertical resonator structure 20 of the first embodiment and its modifications A to L, a groove 20B is provided instead of the mesa portion 20A. An exposed surface 22S is formed at the bottom of the groove 20B. This configuration can produce effects similar to those produced in the first embodiment and its modifications A to L described above.

[0158] 4. Modification of the Second Embodiment

[0159] [Variant Q]

[0160] According to the aforementioned second embodiment, the surface emitting laser 2 may be a back-emitting laser having a rear surface on which the light emitting surface 1S is provided. Figure 34 As shown, the surface emitting laser 2 may be configured so that laser light L having an oscillation wavelength λ0 is emitted from the side of the semiconductor DBR layer 21. This configuration can produce effects similar to those produced in the aforementioned second embodiment.

[0161] Although the present disclosure has been described with reference to a plurality of embodiments and variations, the present disclosure is not limited to the aforementioned embodiments, etc., and various modifications are possible. Note that the effects described in this specification are merely exemplary. The effects of the present disclosure are not limited to the effects described herein. The present disclosure may have effects other than those described herein.

[0162] Furthermore, for example, the present disclosure can also be configured as follows. (1)

[0164] A surface emitting laser comprising:

[0165] First DBR (distributed Bragg reflector) layer;

[0166] Second DBR layer;

[0167] An active layer is provided between the first DBR layer and the second BDR layer;

[0168] a first spacer layer of a first conductivity type, disposed between the active layer and the first DBR layer;

[0169] a second spacer layer of the second conductivity type, disposed between the active layer and the second DBR layer;

[0170] a tunnel junction layer, disposed between the active layer and the second DBR layer;

[0171] a first electrode layer electrically coupled to the first spacer layer without passing through the first DBR layer; and

[0172] The second electrode layer is electrically coupled to the second spacer layer without passing through the second DBR layer, wherein

[0173] The first spacer layer has a flat exposed surface in a region not opposite to the tunnel junction layer, and

[0174] The first electrode layer is formed so as to be in contact with a portion of the first spacer layer that is deeper than the exposed surface. (2)

[0176] The surface emitting laser according to (1), wherein

[0177] The first spacer layer has a recess in the exposed surface, and

[0178] The first electrode layer is formed to fill the recess. (3)

[0180] The surface emitting laser according to (1) or (2), wherein the first electrode layer is formed in contact with a portion in the exposed surface and a portion of the first spacer layer deeper than the exposed surface. (4)

[0182] The surface emitting laser according to (2), wherein the first electrode layer has a structure in which Ti, Pt, and Au are stacked in this order from the inner surface side of the recess. (5)

[0184] The surface emitting laser according to (2), wherein the first electrode layer includes a metal layer containing Ti, Pt, and Au stacked in this order from the inner surface side of the recess, and a plating layer formed on the metal layer. (6)

[0186] The surface emitting laser according to (1) or (3), wherein the first electrode layer includes an alloy metal layer and a diffusion metal region, the alloy metal layer being in contact with the exposed surface, the diffusion metal region being located in a portion of the first spacer layer deeper than the exposed surface and in contact with the alloy metal layer. (7)

[0188] The surface emitting laser according to (6), wherein the first electrode layer further includes a metal layer formed on the alloy metal layer and containing a material different from that of the alloy metal layer. (8)

[0190] The surface emitting laser according to any one of (1) to (7), wherein the exposed surface is formed in the same plane as an interface between the active layer and the first spacer layer. (9)

[0192] The surface emitting laser according to any one of (1) to (8), wherein the first electrode layer is formed in an annular region surrounding the second electrode layer in a plan view. (10)

[0194] The surface emitting laser according to (2), wherein the recess has a cross-sectional shape tapering forward in the stacking direction. (11)

[0196] The surface emitting laser according to (2), wherein the recess is conical in shape. (12)

[0198] The surface emitting laser according to any one of (1) to (11), comprising:

[0199] The stacked structure comprises a first spacer layer, an active layer, a tunnel junction layer and a second spacer layer, wherein:

[0200] The tunnel junction layer is formed in a region surrounded by a region having high resistance due to ion implantation into the stacked structure in a plan view. (13)

[0202] The surface emitting laser according to any one of (1) to (12), further comprising:

[0203] The transparent conductive layer is disposed between the second spacer layer and the second DBR layer and is electrically coupled to the second electrode. (14)

[0205] The surface emitting laser according to any one of (1) to (13), wherein

[0206] The first spacer layer and the second spacer layer include an InP-based semiconductor,

[0207] The first DBR layer includes an undoped semiconductor DBR layer, and

[0208] The second DBR layer includes a dielectric DBR layer. (15)

[0210] The surface emitting laser according to any one of (1) to (13), wherein

[0211] The first spacer layer and the second spacer layer include an InP-based semiconductor, and

[0212] The first DBR layer and the second DBR layer include dielectric DBR layers. (16)

[0214] The surface emitting laser according to (15), further comprising:

[0215] a reflective metal layer in contact with the opposite side of the first DBR layer relative to the active layer, wherein

[0216] The reflective metal layer corresponds to the end portion of the reflective mirror on the first DBR layer side when viewed from the active layer. (17)

[0218] The surface emitting laser according to any one of (1) to (13), wherein

[0219] The first spacer layer and the second spacer layer include an InP-based semiconductor,

[0220] The first DBR layer includes an undoped GaAs semiconductor DBR layer, and

[0221] The second DBR layer includes a dielectric DBR layer. (18)

[0223] The surface emitting laser according to any one of (1) to (17), wherein the first DBR layer and the second DBR layer are configured so that laser light is emitted from the second DBR layer side. (19)

[0225] The surface emitting laser according to any one of (1) to (17), further comprising:

[0226] a reflective metal layer in contact with the opposite side of the second DBR layer relative to the active layer, wherein

[0227] The reflective metal layer corresponds to the end portion of the reflective mirror on the second DBR layer side when viewed from the active layer. (20)

[0229] The surface emitting laser according to any one of (1) to (19), comprising: a mesa portion including at least an active layer, a tunnel junction layer, and a second spacer layer. (twenty one)

[0231] The surface emitting laser according to any one of (1) to (19), comprising:

[0232] The stacked structure comprises a first DBR layer, a first spacer layer, an active layer, a tunnel junction layer, a second spacer layer and a second DBR layer, wherein:

[0233] The stack structure further includes a groove having an exposed surface as a bottom surface, and

[0234] The first electrode layer is formed to contact a portion of the first spacer layer deeper than the exposed surface within the groove.

[0235] In a surface-emitting laser according to an embodiment of the present disclosure, a first spacer layer disposed between the active layer and the first DBR layer has a flat exposed surface in an area not facing the tunnel junction layer. The first electrode layer is formed to contact a portion of the first spacer layer that is deeper than the exposed surface. As a result, the density of current flowing laterally in the first spacer layer is reduced, and the operating voltage is also reduced, compared to a case where the first electrode is disposed only on the exposed surface. Furthermore, because the current path formed by the first and second electrode layers is provided without passing through the first and second DBR layers, for example, neither the first and second DBR layers need to include an impurity-doped semiconductor. For example, both the first and second DBR layers can include an undoped semiconductor or a dielectric. For example, the first DBR layer can include an undoped semiconductor, while the second DBR layer can include a dielectric. As a result, losses due to free carrier absorption in the first and second DBR layers can be reduced. Consequently, higher efficiency and lower voltage can be achieved.

[0236] This application claims the benefit of Japanese Priority Patent Application JP 2023-032514 filed with the Japan Patent Office on March 3, 2023, the entire contents of which are incorporated herein by reference.

[0237] It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.

Claims

1. A surface emitting laser comprising: First DBR (distributed Bragg reflector) layer; Second DBR layer; an active layer, disposed between the first DBR layer and the second BDR layer; a first spacer layer of a first conductivity type, disposed between the active layer and the first DBR layer; a second spacer layer of a second conductivity type, disposed between the active layer and the second DBR layer; a tunnel junction layer, disposed between the active layer and the second DBR layer; a first electrode layer electrically coupled to the first spacer layer without passing through the first DBR layer; as well as a second electrode layer electrically coupled to the second spacer layer without passing through the second DBR layer, wherein The first spacer layer has a flat exposed surface in a region not opposite to the tunnel junction layer, and The first electrode layer is formed to be in contact with a portion of the first spacer layer that is deeper than the exposed surface.

2. The surface emitting laser according to claim 1, wherein The first spacer layer has a recess in the exposed surface, and The first electrode layer is formed to fill the recess.

3. The surface emitting laser according to claim 1, wherein The first electrode layer is formed to contact a portion in the exposed surface and a portion of the first spacer layer deeper than the exposed surface.

4. The surface emitting laser according to claim 2, wherein The first electrode layer has a structure in which Ti, Pt, and Au are stacked in this order from the inner surface side of the recess.

5. The surface emitting laser according to claim 2, wherein The first electrode layer includes a metal layer including Ti, Pt, and Au stacked in this order from the inner surface side of the recess, and a plating layer formed on the metal layer.

6. The surface emitting laser according to claim 1, wherein The first electrode layer includes an alloy metal layer in contact with the exposed surface and a diffusion metal region located in a portion of the first spacer layer deeper than the exposed surface and in contact with the alloy metal layer.

7. The surface emitting laser according to claim 6, wherein The first electrode layer further includes a metal layer formed on the alloy metal layer and including a material different from that of the alloy metal layer.

8. The surface emitting laser according to claim 1, wherein The exposed surface is formed in the same plane as an interface between the active layer and the first spacer layer.

9. The surface emitting laser according to claim 1, wherein The first electrode layer is formed in an annular region surrounding the second electrode layer in a plan view.

10. The surface emitting laser according to claim 2, wherein The recess has a cross-sectional shape that tapers forward in the stacking direction.

11. The surface emitting laser according to claim 2, wherein The recess is conical in shape.

12. The surface emitting laser according to claim 1, comprising: A stacked structure comprising the first spacer layer, the active layer, the tunnel junction layer and the second spacer layer, wherein: The tunnel junction layer is formed in a region surrounded by a region having high resistance due to ion implantation into the stacked structure in a plan view.

13. The surface emitting laser according to claim 1, further comprising: A transparent conductive layer is disposed between the second spacer layer and the second DBR layer and is electrically coupled to the second electrode.

14. The surface emitting laser according to claim 1, wherein The first spacer layer and the second spacer layer include InP-based semiconductors, The first DBR layer includes an undoped semiconductor DBR layer, and The second DBR layer includes a dielectric DBR layer.

15. The surface emitting laser according to claim 1, wherein The first and second spacer layers include an InP-based semiconductor, and the first and second DBR layers include a dielectric DBR layer.

16. The surface emitting laser according to claim 15, further comprising: a reflective metal layer in contact with the opposite side of the first DBR layer relative to the active layer, wherein The reflective metal layer corresponds to a terminal end portion of the reflective mirror on the first DBR layer side when viewed from the active layer.

17. The surface emitting laser according to claim 1, wherein The first spacer layer and the second spacer layer include InP-based semiconductors, The first DBR layer includes an undoped GaAs semiconductor DBR layer, and the second DBR layer includes a dielectric DBR layer.

18. The surface emitting laser according to claim 1, wherein The first DBR layer and the second DBR layer are configured so that laser light is emitted from the second DBR layer side.

19. The surface emitting laser according to claim 1, further comprising: a reflective metal layer in contact with the opposite side of the second DBR layer relative to the active layer, wherein The reflective metal layer corresponds to a terminal end portion of the reflective mirror on the second DBR layer side when viewed from the active layer.

20. The surface emitting laser according to claim 1, comprising: The mesa portion at least includes the active layer, the tunnel junction layer and the second spacer layer.

21. The surface emitting laser according to claim 1, comprising: A stacked structure comprising the first DBR layer, the first spacer layer, the active layer, the tunnel junction layer, the second spacer layer and the second DBR layer, wherein: The stack structure further includes a groove having the exposed surface as a bottom surface, and The first electrode layer is formed to contact a portion of the first spacer layer that is deeper than the exposed surface in the groove.

Images