Photolithography repair method and semiconductor process equipment

Abstract

The present application relates to the technical field of semiconductor, in particular to a photoetching rework method and a semiconductor process equipment.The photoetching rework method comprises: a plasma burning step, process gas is introduced into a process chamber and plasma is generated by excitation, so that the plasma reacts with residual substances in the process chamber; a waferless cleaning step, process gas is introduced into the process chamber and plasma is generated by excitation; a removing step, a defective wafer is placed in the process chamber, process gas is introduced into the process chamber and plasma is generated by excitation, so that the plasma reacts with a soft mask layer on the defective wafer, the wafer after removing the soft mask layer is taken out from the process chamber, and the waferless cleaning step is executed again.The photoetching rework method and the semiconductor process equipment provided by the present application are beneficial to reduce the line width difference of the hard mask layer before and after rework, improve the stability and yield of products, and can be applied to a metal hard mask layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a photolithography rework method and semiconductor process equipment. Background Technology

[0002] In semiconductor manufacturing, hard metal masks (especially titanium nitride layers) serve as crucial intermediate layers for pattern transfer. Their high hardness and excellent chemical stability make them widely used in advanced processes. The photolithography process preceding the etching of the hard metal mask is a core step in semiconductor manufacturing. It utilizes the chemical reaction of photoresist to transfer and replicate circuit patterns, playing a decisive role in device performance and precision.

[0003] However, as semiconductor manufacturing processes continue to shrink, the requirements for photolithography are becoming increasingly stringent. Due to the complexity of the photolithography process and its susceptibility to various factors, problems such as underexposure, development defects, pattern distortion, and other process deviations can occur, causing the product's critical dimension (CD) to fail to meet design requirements, thus resulting in products that do not meet quality standards. In such cases, performing photolithography rework before etching the metal hard mask layer can reduce defects and is an important means of salvaging defective wafers and improving semiconductor manufacturing efficiency and yield. However, photolithography rework processes in related technologies can easily cause significant changes in product linewidth, leading to a lower final wafer yield. Summary of the Invention

[0004] The purpose of this invention is to provide a photolithography rework method and semiconductor process equipment to alleviate the technical problem in the prior art that easily leads to large changes in product linewidth, resulting in a low final wafer yield.

[0005] The photolithography rework method provided by this invention includes:

[0006] The plasma ablation step involves introducing process gas into the process chamber and exciting it to generate plasma, so that the plasma reacts with the residual substances in the process chamber.

[0007] In the fabless cleaning step, process gas is introduced into the process chamber and plasma is generated to allow the plasma to react with residual substances in the process chamber.

[0008] In the removal step, the defective wafer is placed in the process chamber, process gas is introduced into the process chamber and plasma is generated, so that the plasma reacts with the soft mask layer on the defective wafer. The wafer after removing the soft mask layer is taken out of the process chamber and returned to perform the waferless cleaning step.

[0009] Preferably, as one possible implementation, the plasma ablation step includes:

[0010] In the cleaning step, process gas is introduced into the process chamber, the process pressure is set to 60~65mT, the upper electrode power is set to 1000~1200W, the upper electrode coil current ratio is set to 0.4~0.6, the lower electrode power is set to 0, and the process duration is set to 1800~1900s.

[0011] Preferably, as one possible implementation, the plasma ablation step further includes, prior to the cleaning step:

[0012] In the calcination stabilization step, process gas is introduced into the process chamber, the process pressure is set to 60~65mT, the upper electrode power and lower electrode power are set to 0, and the process duration is set to 5~7s.

[0013] Preferably, as one possible implementation, the fabless cleaning step includes:

[0014] In the conversion step, process gas is introduced into the process chamber, the process pressure is set to 60~65mT, the upper electrode power is set to 1000~1200W, the upper electrode coil current ratio is set to 0.4~0.6, the lower electrode power is set to 0, and the process duration is set to 3~4s.

[0015] Preferably, as one possible implementation, after the conversion step, the fabless cleaning step further includes:

[0016] In the high-pressure cleaning step, process gas is introduced into the process chamber, the process pressure is set to 115~120mT, the upper electrode power is set to 1000~1200W, the upper electrode coil current ratio is set to 0.4~0.6, the lower electrode power is set to 0, and the process duration is set to 15~17s.

[0017] In the low-pressure cleaning step, process gas is introduced into the process chamber, the process pressure is set to 8~15mT, the upper electrode power is set to 1000~1200W, the upper electrode coil current ratio is set to 0.4~0.6, the lower electrode power is set to 0, and the process duration is set to 15~17s.

[0018] Preferably, as one possible implementation, prior to the conversion step, the waferless cleaning step further includes:

[0019] Without wafer stabilization, process gas is introduced into the process chamber, the process pressure is set to 8~15mT, the upper electrode power and lower electrode power are set to 0, and the process duration is set to 3~4s.

[0020] Preferably, as one possible implementation, in the plasma ablation step, the process gas includes O2 or NF3, and the flow rate of O2 or NF3 is 300~400 sccm;

[0021] And / or, in the waferless cleaning step, the process gas includes O2 or NF3, and the flow rate of O2 or NF3 is 300~400 sccm.

[0022] Preferably, as one possible implementation, between the plasma ablation step and the fabless cleaning step, the method further includes:

[0023] In the pyrolysis and purging step, inert gas is introduced into the process chamber at a flow rate of 480-500 sccm, the process pressure is set to 8-15 mT, the upper electrode power and lower electrode power are set to 0, and the process duration is set to 5-7 s.

[0024] And / or, between the waferless cleaning step and the removal step, the method further includes:

[0025] In the wafer-free purging step, an inert gas is introduced into the process chamber at a flow rate of 480-500 sccm. The process pressure is set to 8-15 mT, the upper electrode power and lower electrode power are set to 0, and the process duration is set to 10-12 s.

[0026] Preferably, as one possible implementation, in the ignition purging step, the inert gas includes Ar or N2;

[0027] And / or, in the waferless purging step, the inert gas includes Ar or N2.

[0028] Preferably, as one possible implementation, the method further includes:

[0029] Set the upper and lower power supply frequencies to 13.56MHz, and set the upper electrode power application mode and the lower electrode power application mode to continuous wave;

[0030] And / or, the temperature of the electrostatic chuck used to carry the wafer is set to 40~60℃, the helium pressure on the back of the wafer is set to 6~10T, and the temperature of the process chamber is set to 200~300℃.

[0031] The semiconductor process equipment provided by the present invention includes a process chamber, an air intake assembly, an upper electrode assembly, a lower electrode assembly, and a controller. The controller is characterized in that it includes at least one processor and at least one memory, wherein the memory stores a computer program, and the computer program is executed by the processor to implement the above-mentioned photolithography rework method.

[0032] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0033] The photolithography rework method provided by this invention removes the soft mask layer on the defective wafer using plasma in the removal step. Compared to acid cleaning, this method is more adaptable, especially for metal hard mask layers. Before removing the soft mask layer, plasma can be generated by exciting the process gas. The plasma reacts with and consumes the residual material in the chamber, thereby reducing the amount of impurity plasma generated by the voltage excitation of residual material in the chamber during the removal step. This reduces the additional etching caused by these impurity plasmas on the hard mask layer, which helps to reduce the linewidth difference of the hard mask layer before and after rework, improving product stability and yield. It should be noted that when reworking a batch of defective wafers, only one plasma ablation step is performed at the very beginning, and a waferless cleaning step is performed before removing the soft mask layer from each defective wafer. This achieves a balance between a clean chamber and ensuring production efficiency.

[0034] It should be noted that the photolithography rework method provided by this invention only requires a plasma ablation step before formally reworking several defective wafers to preliminarily remove residual materials in the process chamber, eliminating the "chamber pretreatment" step in related technologies. Therefore, it avoids the risk of changes in the chemical properties or physical structure of the polymer material on the chamber sidewalls caused by "chamber pretreatment," resulting in a stable chamber environment. Consequently, during the subsequent formal rework process, it can improve the etching uniformity and stability of the hard mask layer, further reducing the linewidth deviation of the metal hard mask layer before and after rework, and avoiding the introduction of new defects. This, in turn, ensures the performance and reliability of semiconductor devices and improves the final yield. In addition, the simplified process flow can effectively improve overall production efficiency.

[0035] The semiconductor process equipment provided by this invention has the same technical features as the above-mentioned photolithography rework method, so it can also solve the same technical problems and achieve the same technical effects. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0037] Figure 1 This is a schematic diagram of the wafer mask layer before rework;

[0038] Figure 2This is a schematic diagram of the structure of the wafer mask layer after rework;

[0039] Figure 3 This is a schematic flowchart illustrating the rework process in related technologies;

[0040] Figure 4 This is a first schematic flowchart of the photolithography rework process provided in an embodiment of the present invention;

[0041] Figure 5 This is a second schematic flowchart of the photolithography rework process provided in an embodiment of the present invention;

[0042] Figure 6 This is a comparison chart showing the linewidth difference before and after reworking a defective wafer using different process methods.

[0043] Figure 7 This is a comparison chart showing the yield of defective wafers after rework using different process methods;

[0044] Figure 8 This is a schematic diagram of the structure of a semiconductor process equipment provided in an embodiment of the present invention. Detailed Implementation

[0045] Typical wafer mask layer structure before rework is as follows: Figure 1 As shown, rework is usually caused by a deviation in the formation of the top photoresist layer. The top photoresist layer can be removed using chemical reagents via wet etching. However, other layers (including the silicon anti-reflective layer and the SOC layer) typically require plasma etching to remove them in preparation for subsequent recoating. The reworked wafer mask layer structure is shown below. Figure 2 As shown. However, in previous etching processes, etching gases such as chloride ions are usually used. After etching, some etching gas remains in the chamber. This causes the residual gas in the etching process to form impurity plasma due to voltage excitation in the chamber during the process of using plasma to remove the upper film layers (including silicon anti-reflection layer and SOC layer). This impurity plasma continues to react with various materials on the metal hard mask layer, causing additional etching to the metal hard mask layer. This results in a change in the linewidth of the metal hard mask layer. This change in linewidth leads to a difference in linewidth before and after rework, which in turn affects the stability and yield of the product.

[0046] One photolithography rework method in related technologies is as follows: First, a semiconductor with a passivation protective layer and a photoresist layer is provided for rework to remove photoresist. Next, the semiconductor surface is subjected to dry photoresist removal treatment under preset temperature conditions. Subsequently, acid cleaning is used to remove the oxide layer formed on the passivation protective layer surface during the dry process. Finally, a wet process is used to remove the remaining photoresist. Although this method can reduce the linewidth difference of the semiconductor before and after rework, it still has an approximately 10% linewidth difference, making it difficult to meet the process requirements of advanced manufacturing processes. Furthermore, the use of acid cleaning in this process makes it unsuitable for metal hard mask layers (such as titanium nitride), resulting in poor adaptability.

[0047] In related technologies, such as Figure 3 As shown, before formal rework (removal of the soft mask layer), the cavity needs to be pre-treated. While this cavity pre-treatment can eliminate some impurities and residues, it can also adversely affect the stability and uniformity of the cavity. Specifically, traditional cavity pre-treatment may alter the chemical properties or physical structure of the polymer material on the cavity sidewalls. This unstable cavity environment may affect the etching uniformity and stability of the metal hard mask layer during subsequent formal rework, leading to deviations in the linewidth of the reworked metal hard mask layer, and even introducing new defects. Consequently, this problem not only affects the performance and reliability of semiconductor devices but also significantly reduces the final yield.

[0048] Based on this, the present invention proposes a novel photolithography rework method. By optimizing the process steps and the operating parameters and conditions of each step, it effectively removes the soft mask layer (including the photoresist layer, silicon anti-reflective layer, and SOC layer) while minimizing damage to the hard mask layer and semiconductor surface. This ensures the linewidth accuracy and stability of the metal hard mask layer and significantly reduces the wafer scrap rate caused by rework due to photolithography defects. Through this innovative process flow, the present invention can not only significantly improve the yield in the semiconductor manufacturing process but also effectively reduce production costs, increase production efficiency, and enhance the stability and reliability of the entire semiconductor manufacturing process.

[0049] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0050] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings.

[0051] Figure 4 A schematic flowchart of a photolithography rework method provided in one embodiment of the present invention, the method comprising:

[0052] S102, Plasma ablation step: process gas is introduced into the process chamber and plasma is generated so that the plasma reacts with the residual substances in the process chamber.

[0053] S104, waferless cleaning step, introduces process gas into the process chamber and generates plasma so that the plasma reacts with the residual substances in the process chamber.

[0054] S106, Removal Step: Place the defective wafer in the process chamber, introduce process gas into the process chamber and generate plasma, so that the plasma reacts with the soft mask layer on the defective wafer, remove the wafer after removing the soft mask layer from the process chamber, and return to perform the waferless cleaning step.

[0055] The photolithography rework method provided in this embodiment removes the soft mask layer on the defective wafer using plasma in the removal step. Compared to acid cleaning, this method is more adaptable, especially for metal hard mask layers. Before removing the soft mask layer, plasma can be generated by exciting the process gas. The plasma reacts with and consumes the residual material in the chamber, thereby reducing the amount of impurity plasma generated by the voltage excitation of residual material in the chamber during the removal step. This reduces the additional etching caused by these impurity plasmas on the hard mask layer, which helps to reduce the linewidth difference of the hard mask layer before and after rework, improving product stability and yield. It should be noted that when reworking a batch of defective wafers, only one plasma ablation step is performed at the very beginning, and a waferless cleaning step is performed before removing the soft mask layer from each defective wafer. This achieves a balance between a clean chamber and ensuring production efficiency.

[0056] It should be noted that the photolithography rework method provided in this embodiment only requires a plasma ablation step before formally reworking several defective wafers to preliminarily remove residual materials in the process chamber. This eliminates the "chamber pretreatment" step in related technologies. Therefore, it avoids the risk of changes in the chemical properties or physical structure of the polymer material on the chamber sidewalls caused by "chamber pretreatment," resulting in a stable chamber environment. Consequently, during the subsequent formal rework process, it can improve the etching uniformity and stability of the hard mask layer, further reducing the linewidth deviation of the metal hard mask layer before and after rework, and avoiding the introduction of new defects. This, in turn, ensures the performance and reliability of semiconductor devices and improves the final yield. In addition, the simplified process flow can effectively improve overall production efficiency.

[0057] The aforementioned plasma ablation step may specifically include a cleaning step, in which process gas is introduced into the process chamber, the process pressure is set to 60~65mT, the upper electrode power is set to 1000~1200W, the upper electrode coil current ratio is set to 0.4~0.6, the lower electrode power is set to 0, and the process duration is set to 1800~1900s. Under these process conditions, substances remaining in the chamber from the previous etching process can be effectively removed, resulting in excellent cleaning. The coil current ratio is the ratio of the inner coil current to the sum of the inner and outer coil currents.

[0058] Before the cleaning step, the plasma ablation step may also include an ablation stabilization step, in which process gas is introduced into the process chamber, the process pressure is set to 60~65mT, the upper electrode power and the lower electrode power are set to 0, and the process duration is set to 5~7s. This step can achieve the initial stabilization effect on the chamber environment.

[0059] The aforementioned fabless cleaning step may specifically include: a conversion step, in which process gas is introduced into the process chamber, the process pressure is set to 60~65mT, the upper electrode power is set to 1000~1200W, the upper electrode coil current ratio is set to 0.4~0.6, the lower electrode power is set to 0, and the process duration is set to 3~4s. Under these process conditions, substances remaining in the chamber from the previous etching process or substances remaining in the chamber from the previous rework can be further removed, which can significantly improve the cleanliness of the chamber and reduce the impurity plasma generated by the voltage excitation in the chamber during the removal step. This is beneficial to reduce the linewidth difference of the hard mask layer before and after rework.

[0060] Following the conversion step, the aforementioned fabless cleaning step may further include:

[0061] In the high-pressure cleaning step, process gas is introduced into the process chamber, the process pressure is set to 115~120mT, the upper electrode power is set to 1000~1200W, the upper electrode coil current ratio is set to 0.4~0.6, the lower electrode power is set to 0, and the process duration is set to 15~17s.

[0062] In the low-pressure cleaning step, process gas is introduced into the process chamber, and the process pressure is set to 8~15mT, the upper electrode power is set to 1000~1200W, the upper electrode coil current ratio is set to 0.4~0.6, the lower electrode power is set to 0, and the process duration is set to 15~17s.

[0063] It should be noted that the process pressure in the high-pressure cleaning step is relatively high, while the process pressure in the low-pressure cleaning step is relatively low. This creates an alternating high- and low-pressure purging effect, which effectively removes residual impurity ions in the chamber and stabilizes the chamber environment. In addition, it can avoid problems such as incomplete or excessive purging caused by constant pressure, thereby ensuring the stability of the chamber environment and providing a reliable environmental basis for the subsequent process of removing the soft mask layer.

[0064] The aforementioned fabless cleaning step may also include a fabless stabilization step, in which process gas is introduced into the process chamber, the process pressure is set to 8~15mT, the upper electrode power and the lower electrode power are set to 0, and the process duration is set to 3~4s. This step can achieve a preliminary stabilization effect on the chamber environment.

[0065] In the plasma ablation step described above, the process gas may include O2 or NF3. The flow rate of O2 or NF3 is set to 300~400 sccm. Both O2 and NF3 can react with residual substances (such as chloride ions) in the process chamber, thereby effectively cleaning the process chamber.

[0066] In the above-mentioned fabless cleaning step, the process gas may include O2 or NF3. The flow rate of O2 or NF3 is set to 300~400 sccm. Both O2 and NF3 can react with residual substances (such as chloride ions) in the process chamber, thereby effectively cleaning the process chamber.

[0067] Figure 5 This is a schematic flowchart of a photolithography rework method provided in an embodiment of the present invention. In this method, O2 is used as the process gas in the plasma ablation step and the fabless cleaning step. The method includes: oxygen plasma ablation, oxygen fabless cleaning, and removal of the soft mask layer. The oxygen fabless cleaning step and the soft mask layer removal step are performed on each rework wafer (and defective wafer).

[0068] Between the plasma ablation step and the fabless cleaning step described above, the method provided in this embodiment may further include: an ablation purging step, in which an inert gas is introduced into the process chamber, the flow rate of the inert gas is set to 480~500 sccm, the process pressure is set to 8~15 mT, the upper electrode power and lower electrode power are set to 0, and the process duration is set to 5~7 s. In this way, ions and other impurities in the process chamber can be effectively removed by purging with the inert gas, improving the cleanliness of the chamber. The inert gas is preferably Ar, but N2 or other inert gases can also be used.

[0069] Between the aforementioned fabless cleaning step and the aforementioned removal step, the method provided in this embodiment further includes a fabless purging step, in which an inert gas is introduced into the process chamber. The inert gas flow rate is set to 480~500 sccm, the process pressure is set to 8~15 mT, the coil current ratio of the upper electrode is 0.4~0.6, the power of the lower electrode is set to 0, and the process duration is set to 10~12 s. In this way, ions and other impurities in the process chamber can be effectively removed by purging with inert gas, thereby improving the cleanliness of the chamber. The inert gas is preferably Ar, but N2 or other inert gases can also be used.

[0070] Furthermore, the method provided in this embodiment may also include setting the upper and lower power supply frequencies to 13.56MHz, and setting the upper and lower electrode power application methods to continuous wave, thereby achieving better chamber cleaning results. Additionally, the temperature of the electrostatic chuck used to support the wafer may be set to 40~60℃, the helium pressure on the back side of the wafer to 6~10T, and the temperature of the process chamber to 200~300℃ to achieve better rework results.

[0071] In practice, the removal step is carried out immediately after the wafer-free purging step to reduce changes in chamber conditions caused by time delays or other interference factors.

[0072] This invention achieves a dual effect by continuously implementing plasma ablation and waferless cleaning steps: on the one hand, it uses chemical reactions to consume residual materials that may interfere with subsequent rework in advance; on the other hand, it uses high and low pressure alternating purging technology to thoroughly clean the chamber, effectively avoiding changes in the linewidth of the metal hard mask layer caused by environmental instability. Figure 6 The figures show a comparison of the linewidth difference test results after photolithography rework of defective wafers using the photolithography rework method provided in this embodiment of the invention and the conventional method. When using the conventional method to rework defective wafers numbered 1-30, the average linewidth difference before and after rework is 1.161 nm. However, when using the photolithography rework method of this invention to rework defective wafers numbered 31-60, the average linewidth difference before and after rework is significantly reduced to 0.8775 nm, greatly minimizing the average linewidth difference before and after rework.

[0073] This invention significantly improves product yield by reducing the difference in line width before and after rework. Figure 7The diagram shows a comparison of the yield of defective wafers after reworking using traditional rework processes and the photolithography rework method provided in this embodiment of the invention. The average yield of defective wafers numbered 1-30 after reworking using traditional rework processes is 72.79%, while the average yield of defective wafers numbered 31-60 after reworking using the photolithography rework method proposed in this embodiment of the invention is significantly improved to 90.42%, resulting in a substantial increase in yield.

[0074] Figure 8 A semiconductor process apparatus provided according to one embodiment of the present invention includes a process chamber 20, an inlet assembly 20A, an upper electrode assembly 20B, a lower electrode assembly 20C, and a controller (shown). The controller includes at least one processor and at least one memory, the memory storing a computer program that, when executed by the processor, implements the method of any of the above embodiments.

[0075] For example, the controller can be a host computer or a slave computer. The controller can open the valve of the air inlet assembly 20A to introduce the corresponding process gas into the process chamber 20; the controller can also control the flow rate of the process gas by controlling the opening and closing degree of the valve of the air inlet assembly 20A. The controller can also control the evacuation assembly 20D to evacuate the process chamber 20, thereby controlling the gas pressure inside the process chamber 20 and removing reaction byproducts.

[0076] The upper electrode assembly 20B includes an RF coil 21, an upper RF power supply 23, and an upper matching unit 25. The controller is also used to control the upper RF power supply 23 to provide upper electrode power to the RF coil 21 through the upper matching unit 25, so that the RF coil 21 excites the process gas inside the process chamber 20 to generate plasma.

[0077] The lower electrode assembly 20C includes a wafer carrier 22, a lower RF power supply 24, and a lower matching unit 26. The controller further controls the lower RF power supply 24 to provide lower electrode power to the lower electrode of the wafer carrier 22 through the lower matching unit 26. The wafer carrier 22 includes an electrostatic chuck.

[0078] The semiconductor process equipment 200 in this application embodiment can be an inductively coupled plasma (ICP) etching device or a capacitively coupled plasma (CCP) etching device. This application embodiment does not limit the type of semiconductor process equipment 200.

[0079] The semiconductor process equipment provided in this embodiment of the invention has the same technical features as the photolithography rework method provided in the above embodiment, so it can also solve the same technical problems and achieve the same technical effects.

[0080] This embodiment also provides a machine-readable storage medium storing machine-executable instructions. When the machine-executable instructions are called and executed by a processor, the machine-executable instructions cause the processor to implement the above-described photolithography rework method.

[0081] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the above-described equipment and apparatus can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0082] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes: USB flash drives, portable hard drives, and read-only memory (ROM). Various media that can store program code, such as random access memory (RAM), magnetic disks, or optical disks.

[0083] In the description of this invention, it should be noted that the terms "upper", "lower", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0084] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A lithographic repair method characterized by, include: The plasma ablation step involves introducing process gas into the process chamber and exciting it to generate plasma, so that the plasma reacts with the residual substances in the process chamber. In the fabless cleaning step, process gas is introduced into the process chamber and plasma is generated to allow the plasma to react with residual substances in the process chamber. In the removal step, the defective wafer is placed in the process chamber, process gas is introduced into the process chamber and plasma is generated, so that the plasma reacts with the soft mask layer on the defective wafer. The wafer after removing the soft mask layer is taken out from the process chamber and returned to perform the waferless cleaning step.

2. The photo-lithographic rework method of claim 1, wherein, The plasma ablation step includes: In the cleaning step, process gas is introduced into the process chamber, the process pressure is set to 60~65mT, the upper electrode power is set to 1000~1200W, the upper electrode coil current ratio is set to 0.4~0.6, the lower electrode power is set to 0, and the process duration is set to 1800~1900s.

3. The photo-lithographic rework method of claim 2, wherein, Prior to the cleaning step, the plasma ablation step further includes: In the calcination stabilization step, process gas is introduced into the process chamber, the process pressure is set to 60~65mT, the upper electrode power and lower electrode power are set to 0, and the process duration is set to 5~7s.

4. The photoresist rework method of claim 1, wherein The fabless cleaning step includes: In the conversion step, process gas is introduced into the process chamber, the process pressure is set to 60~65mT, the upper electrode power is set to 1000~1200W, the upper electrode coil current ratio is set to 0.4~0.6, the lower electrode power is set to 0, and the process duration is set to 3~4s.

5. The photolithography rework method of claim 4, wherein, Following the conversion step, the fabless cleaning step further includes: In the high-pressure cleaning step, process gas is introduced into the process chamber, the process pressure is set to 115~120mT, the upper electrode power is set to 1000~1200W, the upper electrode coil current ratio is set to 0.4~0.6, the lower electrode power is set to 0, and the process duration is set to 15~17s. In the low-pressure cleaning step, process gas is introduced into the process chamber, the process pressure is set to 8~15mT, the upper electrode power is set to 1000~1200W, the upper electrode coil current ratio is set to 0.4~0.6, the lower electrode power is set to 0, and the process duration is set to 15~17s.

6. The photolithography rework method according to claim 4, characterized in that, Prior to the conversion step, the fabless cleaning step further includes: Without wafer stabilization, process gas is introduced into the process chamber, the process pressure is set to 8~15mT, the upper electrode power and lower electrode power are set to 0, and the process duration is set to 3~4s.

7. The lithographic rework method according to any of claims 1-6, wherein In the plasma ablation step, the process gas includes O2 or NF3, and the flow rate of O2 or NF3 is 300~400 sccm. And / or, in the waferless cleaning step, the process gas includes O2 or NF3, and the flow rate of O2 or NF3 is 300~400 sccm.

8. The photolithography rework method according to any one of claims 1-6, wherein, Between the plasma ablation step and the fabless cleaning step, the method further includes: In the pyrolysis and purging step, inert gas is introduced into the process chamber at a flow rate of 480-500 sccm, the process pressure is set to 8-15 mT, the upper electrode power and lower electrode power are set to 0, and the process duration is set to 5-7 s. And / or, between the waferless cleaning step and the removal step, the method further includes: In the wafer-free purging step, an inert gas is introduced into the process chamber at a flow rate of 480-500 sccm. The process pressure is set to 8-15 mT, the upper electrode power and lower electrode power are set to 0, and the process duration is set to 10-12 s.

9. The photolithography rework method of claim 8, wherein, In the burning and purging step, the inert gas includes Ar or N2; And / or, in the waferless purging step, the inert gas includes Ar or N2.

10. The photolithography rework method according to any one of claims 1-6, wherein, The method further includes: Set the upper and lower power supply frequencies to 13.56MHz, and set the upper electrode power application mode and the lower electrode power application mode to continuous wave; And / or, the temperature of the electrostatic chuck used to carry the wafer is set to 40~60℃, the helium pressure on the back of the wafer is set to 6~10T, and the temperature of the process chamber is set to 200~300℃.

11. A semiconductor process apparatus comprising a process chamber, a gas inlet assembly, an upper electrode assembly, a lower electrode assembly, and a controller, wherein, The controller includes at least one processor and at least one memory, the memory storing a computer program that, when executed by the processor, implements the lithography rework method as described in any one of claims 1-10.

Images