Power device packaging structure and power device packaging module

Abstract

The embodiment of the invention discloses a power device packaging structure and a power device packaging module. The power device packaging structure comprises a heat dissipation substrate; the chip comprises a first electrode, a second electrode and a third electrode; a plurality of bonding pads are arranged on the circuit carrier; the vertical projection of the chip on the heat dissipation substrate is located in the vertical projection of the circuit carrier on the heat dissipation substrate and does not coincide with the vertical projection. A first lead connected to the first pad and serving as an external electrode of the first electrode; a second lead connected to the second pad and serving as an external electrode of a second electrode; one end of the conductive wire is connected with the first electrode, and the other end is connected with the third pad; one end of the first conductive band is connected with the second electrode, and the other end is connected with the fourth pad; an endless belt structure; the vertical projection of the circuit carrier on the heat dissipation substrate is located in the vertical projection of the annular belt structure on the heat dissipation substrate and does not coincide with the vertical projection of the annular belt structure. The vertical projection of the annular belt structure on the heat dissipation substrate is located in the heat dissipation substrate and does not coincide with the heat dissipation substrate. According to the technical scheme of the embodiment of the invention, the assembly cost can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a power device packaging structure and a power device packaging module. Background Art

[0002] Current power control modules integrating metal oxide semiconductor field effect transistors (MOSFETs) are primarily assembled by directly soldering multiple MOSFETs onto a shared heat sink. During the soldering process, the stacked MOSFETs, along with a heat sink and solder sheet (or solder paste), require specialized soldering fixtures for positioning. The soldering assembly is then completed through heating and cooling in a high-temperature tunnel furnace.

[0003] However, during electrical performance testing after soldering, if a MOSFET on a heat sink exhibits electrical performance degradation, the entire power module must be discarded, increasing assembly costs. For power modules integrating multiple MOSFETs, the leakage limit is higher than the defined range for a single MOSFET due to the series and parallel connection of the MOSFETs. Also, because the shared heat sink has a large thermal capacity, applying electrical energy pulses to a single MOSFET does not easily heat it to the higher MOSFET case temperature. This makes it difficult to achieve stringent screening conditions, making it difficult to detect MOSFETs with minor defects, thereby reducing the accuracy of electrical performance testing of power devices. Summary of the Invention

[0004] The present invention provides a power device packaging structure and a power device packaging module to solve the problems of high assembly cost and low accuracy in testing the electrical performance of power devices.

[0005] According to one aspect of the present invention, a power device packaging structure is provided, the power device packaging structure comprising:

[0006] heat dissipation substrate;

[0007] The chip is located on one side of the heat dissipation substrate; the chip includes a first electrode, a second electrode, and a third electrode; the heat dissipation substrate serves as an external electrode of the third electrode;

[0008] The circuit carrier is located on a side of the chip away from the heat dissipation substrate; a plurality of pads are provided on the circuit carrier; a vertical projection of the chip on the heat dissipation substrate is located within the vertical projection of the circuit carrier on the heat dissipation substrate and does not overlap;

[0009] A first lead; the first lead is connected to the first pad; the first lead serves as an external electrode of the first electrode;

[0010] a second lead; the second lead is connected to the second pad; the second lead serves as an external electrode of the second electrode; the first pad and the second pad are arranged opposite to each other on the circuit carrier;

[0011] A conductive wire; one end of the conductive wire is connected to the first electrode; the other end of the conductive wire is connected to the third pad; the first pad is connected to the third pad;

[0012] a first conductive strip; one end of the first conductive strip is connected to the second electrode; the other end of the first conductive strip is connected to the fourth pad; the second pad is connected to the fourth pad;

[0013] An annular belt structure; the annular belt structure is located on one side of the heat dissipation substrate, and the vertical projection of the circuit carrier on the heat dissipation substrate is located within the vertical projection of the annular belt structure on the heat dissipation substrate and does not overlap; the vertical projection of the annular belt structure on the heat dissipation substrate is located within the heat dissipation substrate and does not overlap.

[0014] Optionally, the circuit carrier includes a ceramic circuit board;

[0015] The vertical projection shape of the ceramic circuit board on the heat dissipation substrate includes a circular ring or a square ring.

[0016] Optionally, the shape of the heat dissipation substrate includes a cylindrical shape; and the outer cylindrical surface of the heat dissipation substrate is provided with tooth-shaped knurling.

[0017] Optionally, the power device packaging structure further includes: a sealing unit;

[0018] The sealing unit is arranged in a space formed by the annular structure and the heat dissipation substrate.

[0019] Optionally, the diameter of the second lead is greater than or equal to the diameter of the first lead.

[0020] Optionally, the power device packaging structure further includes: a second conductive strip; one end of the second conductive strip is connected to the second electrode; the other end of the second conductive strip is connected to the fifth pad; and the second pad is connected to the fifth pad.

[0021] Optionally, the first conductive tape and the second conductive tape include aluminum tapes; and the conductive wire includes aluminum wire.

[0022] Optionally, the power device packaging structure further includes: a transient suppression unit; the transient suppression unit is arranged on the circuit carrier;

[0023] One end of the transient suppression unit is connected to the second electrode, and the other end of the transient suppression unit is connected to the third electrode.

[0024] Optionally, the material of the heat dissipation substrate includes copper; and / or the ring belt structure includes a plastic ring belt.

[0025] According to another aspect of the present invention, a power device packaging module is provided, which includes: the above-mentioned power device packaging structure and a heat sink; a plurality of the above-mentioned power device packaging structures are arrayed on one side of the heat sink.

[0026] The technical solution of the embodiment of the present invention combines a single chip with a single heat sink, which has a small spatial size. The same number of chips and the corresponding heat sink together are relatively smaller than the volume of a shared heat sink and multiple chips together. In the same time, high-temperature welding equipment (such as a chain welding furnace) can complete the welding of a larger number of chip and heat sink combinations, thereby improving the efficiency of batch welding in high-temperature welding equipment. In addition, compared with scrapping a shared heat sink and multiple other intact chips welded thereon, the technical solution of the embodiment of the present invention can reduce the scrapping cost of the power module. If a chip fails after welding, only one chip and the heat sink are discarded, reducing the loss cost. At the same time, after the chip is welded on the heat sink, more stringent electrical parameters (such as forward or reverse electric pulse energy or increasing the temperature of the chip) can be applied to the single chip welded on the heat sink, and more stringent leakage limits can be adopted, so that small defects existing inside the chip after welding and in the chip and welding bonding layer are easier to detect, thereby improving the quality of the power module.

[0027] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 This is a schematic top view of a power device packaging structure provided according to an embodiment of the present invention;

[0030] Figure 2 This is a schematic side view of a power device packaging structure provided according to an embodiment of the present invention;

[0031] Figure 3 This is a schematic diagram of a circuit carrier in a square ring shape according to an embodiment of the present invention;

[0032] Figure 4 is a schematic top view of a portion of another power device packaging structure provided according to an embodiment of the present invention;

[0033] Figure 5 is a schematic top view of a portion of a structure in another power device packaging structure provided by an embodiment of the present invention;

[0034] Figure 6 The figure is a schematic top view of the structure of a power device packaging module provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0035] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0036] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0037] Figure 1 1 is a schematic top view of a power device packaging structure provided according to an embodiment of the present invention. Figure 2 FIG. 1 is a schematic side view of a power device packaging structure provided according to an embodiment of the present invention. Figure 1 and Figure 2As shown, the power device package structure comprises a heat dissipation substrate 10; a chip 20; the chip 20 is located on one side of the heat dissipation substrate 10; the chip 20 comprises a first electrode, a second electrode and a third electrode; the heat dissipation substrate 10 serves as an external electrode of the third electrode; a circuit carrier 30; the circuit carrier 30 is located on a side of the chip 20 away from the heat dissipation substrate 10; the circuit carrier 30 is provided with a plurality of pads; a vertical projection of the chip 20 on the heat dissipation substrate 10 is located within and does not coincide with a vertical projection of the circuit carrier 30 on the heat dissipation substrate 10; a first lead 40; the first lead 40 is connected with a first pad 301; the first lead 40 serves as an external electrode of the first electrode; a second lead 50; the second lead 50 is connected with a second pad 302; the second lead 50 serves as an external electrode of the second electrode; the first pad 301 and the second pad 302 are oppositely arranged on the circuit carrier 30; a conductive wire 60; one end of the conductive wire 60 is connected with the first electrode; the other end of the conductive wire 60 is connected with a third pad 303; the first pad 301 is connected with the third pad 303; a first conductive strip 70; one end of the first conductive strip 70 is connected with the second electrode; the other end of the first conductive strip 70 is connected with a fourth pad 304; the second pad 302 is connected with the fourth pad 304; a ring strip structure 80; the ring strip structure 80 is located on one side of the heat dissipation substrate 10, and a vertical projection of the circuit carrier 30 on the heat dissipation substrate 10 is located within and does not coincide with a vertical projection of the ring strip structure 80 on the heat dissipation substrate 10; a vertical projection of the ring strip structure 80 on the heat dissipation substrate 10 is located within and does not coincide with the heat dissipation substrate 10.

[0038] In the embodiment of the present application, the heat dissipation substrate 10 can be a cylindrical bottom shell. The material of the heat dissipation substrate 10 can be copper or aluminum. In the optional embodiment of the present application, the material of the heat dissipation substrate 10 can be copper. Copper is selected as the material of the heat dissipation substrate 10 because the heat dissipation performance and the thermal expansion coefficient of copper are superior to those of aluminum. The chip 20 can be a MOSFET power device. The heat dissipation substrate 10 can serve as a heat sink of the chip 20, or as an external electrode of the source of the MOSFET. The heat dissipation substrate 10 and the chip 20 can be combined together by soldering. The circuit carrier 30 can be a circuit board. The shape of the circuit carrier 30 can be a circular ring or a square ring, which is not limited herein. The vertical projection of the chip 20 on the heat dissipation substrate 10 is located within and does not coincide with the vertical projection of the circuit carrier 30 on the heat dissipation substrate 10, which can avoid the mutual interference between the chip 20 and the circuit carrier 30, and improve the reliability of the power device package structure. The heat dissipation substrate 10 is also used to support the circuit carrier 30.

[0039] The first electrode can be the gate of the MOSFET, the second electrode can be the drain of the MOSFET, and the third electrode can be the source of the MOSFET. The first lead 40 serves as the external electrode of the gate of the MOSFET. The second lead 50 serves as the external electrode of the drain of the MOSFET. A plurality of pads are provided on the circuit carrier 30. For example, in the embodiment of the present invention, the number of pads is four, including a first pad 301, a second pad 302, a third pad 303, and a fourth pad 304. Two of the pads are used for soldering external leads, and the other two pads are used for soldering internal conductive wires. The first lead 40 is connected to the first pad 301 by soldering, and the second lead 50 is connected to the second pad 302 by soldering, thereby combining the first lead 40 with the second lead 50 and the circuit carrier 30. The circuit carrier 30 and the heat dissipation substrate 10 can be bonded together by colloid.

[0040] Conductive wire 60 is ultrasonically welded to third pad 303 to form a solder joint. Conductive wire 60 is used to connect the gate of the MOSFET to third pad 303, which is then connected to first pad 301. First pad 301 is connected to first lead 40, and thus the gate of the MOSFET is connected to first lead 40. A first conductive ribbon 70 is ultrasonically welded to fourth pad 304 to form a solder joint. First conductive ribbon 70 is used to connect the drain of the MOSFET to fourth pad 304, which is then connected to second pad 302. Second pad 302 is connected to second lead 50, and thus the drain of the MOSFET is connected to second lead 50. Because the current flowing through the drain of a MOSFET is generally greater than the current flowing through the gate of a MOSFET, a conductive ribbon is used to connect the drain of the MOSFET, and a conductive wire is used to connect the gate of the MOSFET. The ring structure 80 and heat dissipation substrate 10 together form a container. The ring structure 80 can be made of materials such as plastic, rubber, or carbon fiber. In an optional embodiment of the present invention, the ring structure 80 comprises a plastic ring. The ring structure 80 is made of plastic material, which has the characteristics of being lightweight, corrosion-resistant, having good insulation performance and low cost.

[0041] The technical solution of the embodiment of the present invention combines a single chip with a single heat sink, which has a small spatial size. The same number of chips and the corresponding heat sink together are relatively smaller than the volume of a shared heat sink and multiple chips together. In the same time, high-temperature welding equipment (such as a chain welding furnace) can complete the welding of a larger number of chip and heat sink combinations, thereby improving the efficiency of batch welding in high-temperature welding equipment. In addition, compared with scrapping a shared heat sink and multiple other intact chips welded thereon, the technical solution of the embodiment of the present invention can reduce the scrapping cost of the power module. If a chip fails after welding, only one chip and the heat sink are discarded, reducing the loss cost. At the same time, after the chip is welded on the heat sink, more stringent electrical parameters (such as forward or reverse electric pulse energy or increasing the temperature of the chip) can be applied to the single chip welded on the heat sink, and more stringent leakage limits can be adopted, so that small defects existing inside the chip after welding and in the chip and welding bonding layer are easier to detect, thereby improving the quality of the power module.

[0042] Figure 3 1 is a schematic diagram of a circuit carrier in a square ring shape according to an embodiment of the present invention. Figure 1 and Figure 3 The circuit carrier 30 includes a ceramic circuit board; the vertical projection shape of the ceramic circuit board on the heat dissipation substrate 10 includes a circular ring or a square ring.

[0043] In an embodiment of the present invention, the ceramic circuit board has excellent electrical insulation, high thermal conductivity, and mechanical strength. Ceramic materials commonly used are aluminum oxide (Al2O3), aluminum nitride (AlN), or silicon nitride (Si3N4). The vertical projection shape of the ceramic circuit board on the heat dissipation substrate 10 can be a circular ring or a square ring. The projection is a hollow structure with no circuit wiring in the middle area. The middle area is used to solder the chip 20 to the heat dissipation substrate 10. The annular structure or square structure of the ceramic circuit board is provided with a circuit path to improve the heat dissipation efficiency of the power device packaging structure.

[0044] In an optional embodiment of the present invention, reference Figure 1 and Figure 2 The shape of the heat dissipation substrate 10 includes a cylindrical shape; the outer cylindrical surface of the heat dissipation substrate 10 is provided with a tooth-shaped knurling.

[0045] In an embodiment of the present invention, the heat dissipation substrate 10 is cylindrical in shape, which can reduce the size of the power device packaging structure and facilitate axial heat dissipation. The outer cylindrical surface of the heat dissipation substrate 10 is provided with a toothed knurling, and is installed by press-fitting onto an external heat sink having mounting holes. The toothed knurling on the outer cylindrical surface of the heat dissipation substrate 10 forms a tight mechanical engagement with the external heat sink, improving heat conduction efficiency, preventing relative rotation between the heat dissipation substrate 10 and the external heat sink, enhancing friction, and preventing loosening.

[0046] In an optional embodiment of the present invention, reference Figure 1 and Figure 2 The power device packaging structure further includes: a sealing unit 90 ; the sealing unit 90 is disposed in a space formed by the annular structure 80 and the heat dissipation substrate 10 .

[0047] In an embodiment of the present invention, sealing unit 90 may be a sealant. Sealing unit 90 is disposed within the container formed by the annular structure 80 and the heat dissipation substrate 10. Sealing unit 90 is used to protect chip 20 and corresponding solder joints, reducing contamination from external moisture, dust, and smoke, ensuring the insulation properties within the power device package structure, and improving the reliability of the power device package structure.

[0048] In an optional embodiment of the present invention, reference Figure 1 and Figure 2 , the diameter of the second lead 50 is greater than or equal to the diameter of the first lead 40 .

[0049] In this embodiment of the present invention, the second lead 50 is connected to the drain of the MOSFET and serves as the external electrode of the MOSFET drain. The first lead 40 is connected to the gate of the MOSFET and serves as the external electrode of the MOSFET gate. Therefore, the current flowing through the second lead 50 is greater than the current flowing through the first lead 40. Therefore, the diameter of the second lead 50 is set to be greater than or equal to the diameter of the first lead 40 to improve the reliability of the power device packaging structure. For example, the diameter of the second lead 50 can be set to 1.3 mm, and the diameter of the first lead 40 can be set to 1 mm.

[0050] Figure 4 FIG. 1 is a schematic top view of a portion of another power device packaging structure provided according to an embodiment of the present invention. Figure 1 and Figure 4 The power device packaging structure further includes: a second conductive tape 100; one end of the second conductive tape 100 is connected to the second electrode; the other end of the second conductive tape 100 is connected to the fifth pad 305; and the second pad 302 is connected to the fifth pad 305.

[0051] In the embodiment of the present invention, the second conductive strip 100 and the first conductive strip 70 are both connected to the drain of the MOSFET, which can reduce the internal resistance of the connection link and improve the performance of the power device packaging structure.

[0052] In an optional embodiment of the present invention, reference Figure 1 and Figure 4 The first conductive tape 70 and the second conductive tape 100 include aluminum tapes; and the conductive wire 60 includes aluminum wire.

[0053] In the embodiment of the present application, the first conductive strip 70 and the second conductive strip 100 are both made of aluminum strips. Since the aluminum surface can form a dense oxide film, it can resist the corrosion of humid or weak acid environment and prolong the service life of the conductive strip. The first conductive strip 70, the second conductive strip 100 and the conductive wire 60 are all made of aluminum material, which can improve the conductive performance.

[0054] Figure 5 is a top view schematic diagram of part of a power device packaging structure according to an embodiment of the present application. In an optional embodiment of the present application, referring to Figure 1 and Figure 5 , the power device packaging structure further comprises: a transient suppression unit 200; the transient suppression unit 200 is arranged on the circuit carrier 30; one end of the transient suppression unit 200 is connected with the second electrode, and the other end of the transient suppression unit 200 is connected with the third electrode.

[0055] In the embodiment of the present application, the transient suppression unit 200 can be a transient voltage suppression diode (TVS). The TVS is a high-efficiency transient overvoltage protection device. Through the PN junction reverse breakdown mechanism, it can clamp the transient pulse voltage in the circuit within a safe range, and protect sensitive electronic components from overvoltage damage such as surges, static electricity or lightning strikes. The overvoltage transient pulse suppression component TVS is connected in parallel between the source and the drain of the MOSFET, which is used to protect the MOSFET from breakdown caused by overvoltage. The TVS has the characteristics of extremely fast response speed (nanosecond level, ≤1 ns) and can suppress transient pulses in time. The clamping voltage of the TVS is stable, which can limit the overvoltage below the safe working voltage of the device. Moreover, the TVS has high surge absorption capacity (peak power can reach hundreds to thousands of watts). By integrating the transient suppression unit 200 in the power device packaging structure, the chip 20 can be protected from breakdown caused by overvoltage, and the performance and reliability of the power device packaging structure can be improved.

[0056] Figure 6 is a top view structural schematic diagram of a power device packaging module according to an embodiment of the present application. As shown in Figure 6 , the power device packaging module 400 comprises the power device packaging structure 300 of any embodiment of the present application and a heat sink 500; a plurality of power device packaging structures 300 are arranged in an array on one side of the heat sink 500.

[0057] Specifically, the power device packaging module 400 includes a power device packaging structure 300 and a heat sink 500 according to any embodiment of the present invention. Multiple power device packaging structures 300 are arranged in an array on one side of the heat sink 500. Chips already soldered to a heat sink substrate are assembled on the heat sink 500, enhancing heat dissipation within the power device packaging structure 300 and improving power density and heat dissipation efficiency. Furthermore, the outer cylindrical surface of the heat sink substrate in the power device packaging structure 300 can be provided with tooth-shaped knurling, and mounting holes adapted thereto can be provided on the heat sink 500. The tooth-shaped knurling on the outer cylindrical surface of the heat sink substrate engages with the mounting holes on the heat sink 500, thereby more firmly bonding the power device packaging structure 300 and the heat sink 500 together and enhancing the reliability of the resulting power device packaging module 400.

[0058] It should be noted that Figure 6 3 shows three arrays of power device packaging structures 300 arranged on one side of the heat sink 500. The embodiment of the present invention does not impose a specific limit on the number of power device packaging structures 300 arranged on one side of the heat sink 500, and can be set according to actual needs.

[0059] The technical solution of an embodiment of the present invention provides a power device packaging module, comprising a power device packaging structure according to any embodiment of the present invention and a heat sink, wherein multiple power device packaging structures are arrayed on one side of the heat sink, and chips soldered to a heat sink substrate are assembled on the heat sink, thereby enhancing heat dissipation of the chips within the power device packaging structure and improving power density and heat dissipation efficiency. Furthermore, the outer cylindrical surface of the heat sink substrate in the power device packaging structure can be provided with a toothed knurling pattern, and mounting holes adapted thereto can be provided on the heat sink. The toothed knurling pattern on the outer cylindrical surface of the heat sink substrate engages with the mounting holes on the heat sink, thereby more firmly combining the power device packaging structure and the heat sink, thereby enhancing the reliability of the resulting power device packaging module.

[0060] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0061] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A power device packaging structure, characterized in that: include: heat dissipation substrate; Chip; the chip is located on one side of the heat dissipation substrate; the chip includes a first electrode, a second electrode and a third electrode; The heat dissipation substrate serves as an external electrode of the third electrode; A circuit carrier; the circuit carrier is located on a side of the chip away from the heat dissipation substrate; a plurality of pads are provided on the circuit carrier; a vertical projection of the chip on the heat dissipation substrate is located within the vertical projection of the circuit carrier on the heat dissipation substrate and does not overlap; a first lead; the first lead is connected to the first pad; the first lead serves as an external electrode of the first electrode; a second lead; the second lead is connected to a second pad; the second lead serves as an external electrode of the second electrode; the first pad and the second pad are arranged opposite to each other on the circuit carrier; A conductive wire; one end of the conductive wire is connected to the first electrode; the other end of the conductive wire is connected to the third pad; the first pad is connected to the third pad; a first conductive strip; one end of the first conductive strip is connected to the second electrode; the other end of the first conductive strip is connected to the fourth pad; the second pad is connected to the fourth pad; An annular belt structure; the annular belt structure is located on one side of the heat dissipation substrate, and the vertical projection of the circuit carrier on the heat dissipation substrate is located within the vertical projection of the annular belt structure on the heat dissipation substrate and do not overlap; the vertical projection of the annular belt structure on the heat dissipation substrate is located within the heat dissipation substrate and do not overlap.

2. The power device packaging structure according to claim 1, wherein: The circuit carrier includes a ceramic circuit board; The vertical projection shape of the ceramic circuit board on the heat dissipation substrate includes a circular ring or a square ring.

3. The power device packaging structure according to claim 1, wherein: The shape of the heat dissipation substrate includes a cylindrical shape; the outer cylindrical surface of the heat dissipation substrate is provided with tooth-shaped knurling.

4. The power device packaging structure according to claim 1, wherein: Also includes: Sealing unit; The sealing unit is arranged in a space formed by the annular structure and the heat dissipation substrate.

5. The power device packaging structure according to claim 1, wherein: The diameter of the second lead is greater than or equal to the diameter of the first lead.

6. The power device packaging structure according to claim 1, wherein: Also includes: a second conductive strip; one end of the second conductive strip is connected to the second electrode; the other end of the second conductive strip is connected to the fifth pad; and the second pad is connected to the fifth pad.

7. The power device packaging structure according to claim 6, characterized in that: The first conductive tape and the second conductive tape include aluminum tapes; and the conductive wire includes aluminum wire.

8. The power device packaging structure according to claim 1, wherein: Also includes: transient suppression unit; The transient suppression unit is arranged on the circuit carrier; One end of the transient suppression unit is connected to the second electrode, and the other end of the transient suppression unit is connected to the third electrode.

9. The power device packaging structure according to claim 1, wherein: The material of the heat dissipation substrate includes copper; and / or the ring belt structure includes a plastic ring belt.

10. A power device packaging module, characterized in that: It comprises the power device packaging structure according to any one of claims 1 to 9 and a heat sink; a plurality of power device packaging structures according to any one of claims 1 to 9 are arrayed on one side of the heat sink.

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