High-gain diamond logic phase inverter and preparation method thereof

Abstract

The invention discloses a high-gain diamond logic phase inverter and a preparation method thereof, and aims to solve the problem that the voltage gain of an existing logic phase inverter is relatively small. According to the high-gain diamond logic inverter, a diamond substrate is subjected to hydrotreating through hydrogen plasma to form the diamond substrate with a hydrogen terminal, a conducting channel is formed after the surface of the hydrogen terminal is in contact with air, and a first source electrode, a first drain electrode, a second source electrode and a second drain electrode are arranged on the diamond substrate. A first ferroelectric medium layer and a second ferroelectric medium layer are deposited on a diamond substrate, a first grid electrode is arranged on the first ferroelectric medium layer, and a second grid electrode is arranged on the second ferroelectric medium layer. According to the invention, an electron beam evaporation process is adopted to form an orthorhombic phase on a ferroelectric material deposited at a low temperature, the ferroelectric material has convertible ferroelectric characteristics, and ultra-steep sub-threshold swing is realized; the surface conductivity can be regulated and controlled by treating the surface of the hydrogen terminal diamond through the oxygen plasma, current matching is achieved, and the logic inverter works in a deep subthreshold region.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor devices, and in particular relates to a high-gain diamond logic inverter and a preparation method thereof. Background Art

[0002] As an ultra-wide bandgap (5.5 eV) semiconductor, diamond stands out for its low dielectric constant and high thermal conductivity. More importantly, dangling hydrogen bonds on the diamond surface can undergo a transfer doping effect, generating a two-dimensional hole gas, resulting in excellent p-type conductivity at ultrathin scales. Consequently, diamond is considered a highly promising channel material for the next generation of transistors and logic circuits in the post-Moore era. To meet the high reliability, high speed, and high interference immunity requirements of integrated circuits for signal propagation and logic operations, the basic unit of logic circuits, the inverter, must have high voltage gain. This requires transistors with a high on / off ratio and fast switching speed (low subthreshold swing). Furthermore, the driver and load transistor structures must be designed with current matching to enable the logic inverter to operate in the deep subthreshold region.

[0003] However, the Boltzmann limit defines the thermodynamic limit of the subthreshold swing, and new transistor device structures are urgently needed to achieve lower subthreshold swings. Negative capacitance field-effect transistors offer a potential solution, exploiting the negative capacitance effect generated by ferroelectric dielectrics during ferroelectric transitions to amplify the surface potential of the channel, thus breaking the Boltzmann limit. However, diamond negative capacitance field-effect transistors have not yet been reported. In addition, there is a lack of a reliable method to treat the surface of hydrogen-terminated diamond to regulate its conductivity and achieve current matching between the driver transistor and the load transistor. Therefore, the voltage gain of current diamond-based logic inverters is still relatively small, which cannot meet the requirements of high-density integrated circuits.

[0004] In view of the above problems, it is necessary to develop a preparation method for a diamond logic inverter based on a negative capacitance diamond field-effect transistor, as well as a reliable hydrogen-terminated diamond surface conductivity control process, so as to realize a high voltage gain diamond logic inverter. Summary of the Invention

[0005] The purpose of the present invention is to solve the problem that the voltage gain of the existing logic inverter is small and cannot meet the requirements of high-density and high-performance integrated circuits, and to provide a high-voltage-gain diamond logic inverter.

[0006] The high-gain diamond logic inverter comprises a diamond substrate, a first source electrode, a first drain electrode, a second source electrode, a second drain electrode, a first ferroelectric dielectric layer, a second ferroelectric dielectric layer, a first gate electrode and a second gate electrode, the diamond substrate is subjected to hydrogenation treatment by hydrogen plasma to form a diamond substrate with a hydrogen termination, a conductive channel is formed on the surface of the hydrogen termination after the hydrogen termination is contacted with air, the first source electrode, the first drain electrode, the second source electrode and the second drain electrode are arranged on the diamond substrate with the hydrogen termination, the first ferroelectric dielectric layer and the second ferroelectric dielectric layer are deposited on the diamond substrate with the hydrogen termination at low temperature by an electron beam evaporation process, the first ferroelectric dielectric layer is located between the first source electrode and the first drain electrode, the second ferroelectric dielectric layer is located between the second source electrode and the second drain electrode, the first gate electrode is arranged on the first ferroelectric dielectric layer, and the second gate electrode is arranged on the second ferroelectric dielectric layer, and part of the second gate electrode is connected with the second source electrode.

[0007] In the present application, the diamond substrate, the conductive channel, the first source electrode, the first drain electrode, the first ferroelectric dielectric layer and the first gate electrode constitute a driving transistor in the logic inverter, and the diamond substrate, the conductive channel, the second source electrode, the second drain electrode, the second ferroelectric dielectric layer and the second gate electrode constitute a load transistor in the logic inverter.

[0008] The preparation method of the high-gain diamond logic inverter is realized according to the following steps:

[0009] I. The diamond substrate is pretreated and cleaned to obtain a pretreated diamond substrate.

[0010] II. The pretreated diamond substrate is placed into a microwave plasma chemical vapor deposition device, and the diamond substrate is subjected to hydrogenation treatment by hydrogen plasma, and a conductive channel is formed after being contacted with air, thereby obtaining a diamond substrate with a conductive channel.

[0011] III. The patterns of the first source electrode, the first drain electrode, the second source electrode and the second drain electrode are formed on the conductive channel of the diamond substrate by a photolithography process, and then metal electrodes are deposited, and the first source electrode, the first drain electrode, the second source electrode and the second drain electrode are formed on the conductive channel by a stripping process, the first drain electrode and the second source electrode are arranged in close proximity (contact), thereby obtaining a diamond substrate with source electrodes and drain electrodes.

[0012] IV. A photoresist protective layer is formed on the conductive channel between the first source electrode and the first drain electrode by a photolithography process, and the conductive channel between the second source electrode and the second drain electrode is treated by oxygen plasma, the hydrogen termination coverage of the diamond surface is controlled by adjusting the treatment time and power of the oxygen plasma, and the conductivity of the conductive channel is reduced to realize current matching.

[0013] 5. Depositing a first ferroelectric layer and a second ferroelectric layer between the first source and the first drain, and between the second source and the second drain, by an electron beam evaporation process at a low temperature of 150° to 350°, wherein the first ferroelectric layer is located between the first source and the first drain, and the second ferroelectric layer is located between the second source and the second drain, to obtain a device with a ferroelectric layer;

[0014] 6. forming a first gate pattern on the first ferroelectric dielectric layer by a photolithography process, and depositing the first gate;

[0015] 7. Using a photolithography process, a second gate pattern is formed on the second ferroelectric dielectric layer, and a second gate is deposited. Part of the second gate is connected to the second source, thereby obtaining a high-gain diamond logic inverter.

[0016] The high-gain diamond logic inverter and its preparation method of the present invention have the following beneficial effects:

[0017] The present invention uses electron beam evaporation to form an orthorhombic phase (O-phase) in a low-temperature deposited ferroelectric material. This process exhibits excellent switchable ferroelectric properties and achieves an ultra-steep subthreshold swing in transistors. This low-temperature process, which does not require high-temperature post-annealing, is compatible with standard CMOS processes at advanced technology nodes and can meet the thermal budget for chip integrated circuit fabrication. Furthermore, oxygen plasma treatment of the hydrogen-terminated diamond surface reliably regulates surface conductivity, achieving current matching and enabling logic inverters to operate in the deep subthreshold region. The diamond logic inverter fabricated by the present invention can operate in the deep subthreshold region with an ultra-steep subthreshold swing, thereby achieving ultra-high voltage gain. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 1 is a schematic structural diagram of a high-gain diamond logic inverter according to the present invention;

[0019] Figure 2 This is a process flow chart of a method for preparing a high-gain diamond logic inverter according to the present invention;

[0020] Figure 3 1 is a phase transition diagram and amplitude diagram of a piezoelectric force microscope of a ferroelectric dielectric layer deposited in an embodiment;

[0021] Figure 4 is a transfer curve diagram of a driving transistor in a high-gain diamond logic inverter according to an embodiment;

[0022] Figure 5 is a voltage transfer curve diagram of a high-gain diamond logic inverter in an embodiment;

[0023] Figure 6 is a voltage gain diagram of a high-gain diamond logic inverter in an embodiment;

[0024] Figure 7 1 is an output curve diagram of the driving transistor and the load transistor in the high-gain diamond logic inverter in an embodiment. DETAILED DESCRIPTION

[0025] The following is a further detailed description of the embodiments of the present invention in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the embodiments of the present invention and are not intended to limit the embodiments of the present invention. It should also be noted that, for ease of description, the accompanying drawings only illustrate portions of the embodiments of the present invention, rather than all structures.

[0026] Furthermore, the terms "first," "second," "third," etc., in the specification and claims are used solely for descriptive purposes to distinguish between identical technical features. They are not to be construed as indicating or implying relative importance, or as implicitly specifying the number of technical features, nor do they necessarily describe a sequential or chronological order. The terms are interchangeable where appropriate. Thus, a feature specified as "first" or "second" may explicitly or implicitly include at least one of those features.

[0027] Specific embodiment 1: The high-gain diamond logic inverter of this embodiment includes a diamond substrate 1, a first source 3, a first drain 4, a second source 5, a second drain 6, a first ferroelectric dielectric layer 7-1, a second ferroelectric dielectric layer 7-2, a first gate 8 and a second gate 9. The diamond substrate 1 is hydrogenated by hydrogen plasma to form a diamond substrate 1 with a hydrogen terminal. The surface of the hydrogen terminal is exposed to air to form a conductive channel 2. The first source 3, the first drain 4, the second gate 8 and the second gate 9 are provided on the diamond substrate 1 with a hydrogen terminal. There are two source electrodes 5 and a second drain electrode 6. A first ferroelectric dielectric layer 7-1 and a second ferroelectric dielectric layer 7-2 are deposited at low temperature on a diamond substrate 1 with a hydrogen terminal using an electron beam evaporation process. The first ferroelectric dielectric layer 7-1 is located between the first source electrode 3 and the first drain electrode 4, and the second ferroelectric dielectric layer 7-2 is located between the second source electrode 5 and the second drain electrode 6. A first gate electrode 8 is provided on the first ferroelectric dielectric layer 7-1, and a second gate electrode 9 is provided on the second ferroelectric dielectric layer 7-2. Part of the second gate electrode 9 is connected to the second source electrode 5.

[0028] In this embodiment, the source and drain are arranged at both ends of the conductive channel; and the ferroelectric dielectric layer is located between the source and drain.

[0029] The root mean square surface roughness of the diamond substrate in this embodiment is less than 0.5 nm, and the Raman half-peak width is less than 2 cm -1 The XRD rocking curve half-peak width is less than 0.1°. The appropriate diamond substrate is selected to meet the requirements of ultra-wide bandgap and high breakdown field strength, and is conducive to the formation of hydrogen termination surface.

[0030] The ferroelectric dielectric deposited at low temperature and without the need for high-temperature post-annealing in this embodiment is compatible with standard CMOS processes at advanced technology nodes, meeting the thermal budget for chip integrated circuit fabrication. It also exhibits excellent switchable ferroelectricity, enabling ultra-steep subthreshold swings. Oxygen plasma treatment of the hydrogen-terminated diamond surface reliably modulates surface conductivity, achieving current matching and enabling logic inverters to operate in the deep subthreshold region. This combination improves the voltage gain of the logic inverter.

[0031] Specific embodiment 2: The difference between this embodiment and specific embodiment 1 is that the hole density of the conductive channel 2 is 1×10 12 -1×10 14 cm -2 , with a mobility of 50-200 cm 2 / (V·s).

[0032] Specific embodiment three: This embodiment is different from specific embodiments one or two in that the material of the first ferroelectric dielectric layer 7-1 and the second ferroelectric dielectric layer 7-2 is ZrO2 or HfO2.

[0033] Specific embodiment 4: This embodiment is different from any one of specific embodiments 1 to 3 in that the thickness of the first ferroelectric dielectric layer 7 - 1 and the second ferroelectric dielectric layer 7 - 2 is 30-100 nm.

[0034] Specific embodiment 5: The preparation method of the high-gain diamond logic inverter of this embodiment is implemented according to the following steps:

[0035] 1. Pre-treating and cleaning the diamond substrate 1 to obtain a pre-treated diamond substrate;

[0036] 2. Placing the pretreated diamond substrate into a microwave plasma chemical vapor deposition device, hydrogenating the diamond substrate using hydrogen plasma, and then forming a conductive channel 2 after contacting the diamond substrate with air, thereby obtaining a diamond substrate with a conductive channel;

[0037] 3. A pattern of a first source electrode 3, a first drain electrode 4, a second source electrode 5, and a second drain electrode 6 is formed on the conductive channel 2 of the diamond substrate using a photolithography process, and then a metal electrode is deposited. A first source electrode 3, a first drain electrode 4, a second source electrode 5, and a second drain electrode 6 are respectively formed on the conductive channel 2 using a lift-off process. The first drain electrode 4 and the second source electrode 5 are arranged adjacent to each other, thereby obtaining a diamond substrate with source and drain electrodes;

[0038] Fourth, a photoresist protective layer is formed on the conductive channel between the first source electrode 3 and the first drain electrode 4 using a photolithography process, and the conductive channel between the second source electrode 5 and the second drain electrode 6 is treated with oxygen plasma. By adjusting the oxygen plasma treatment time and power, the hydrogen terminal coverage of the diamond surface is adjusted to reduce the conductivity of the conductive channel to achieve current matching;

[0039] 5. Depositing a first ferroelectric layer 7-1 and a second ferroelectric layer 7-2 between the first source electrode 3 and the first drain electrode 4, and between the second source electrode 5 and the second drain electrode 6 by an electron beam evaporation process at a low temperature of 150° to 350°, wherein the first ferroelectric layer 7-1 is located between the first source electrode 3 and the first drain electrode 4, and the second ferroelectric layer 7-2 is located between the second source electrode 5 and the second drain electrode 6, thereby obtaining a device having a ferroelectric layer;

[0040] 6. Forming a first gate pattern on the first ferroelectric dielectric layer 7 - 1 by a photolithography process and depositing a first gate 8 ;

[0041] 7. A second gate pattern is formed on the second ferroelectric dielectric layer 7 - 2 using a photolithography process, and a second gate 9 is deposited. Part of the second gate 9 is connected to the second source 5 , thereby obtaining a high-gain diamond logic inverter.

[0042] Specific embodiment 6: The difference between this embodiment and specific embodiment 5 is that the pretreatment of the diamond substrate in step 1 is to place the diamond substrate in a mixed solution of concentrated H2SO4 and concentrated HNO3, heat it to boiling, and treat it for 0.5 to 2 hours.

[0043] Specific embodiment seven: The difference between this embodiment and specific embodiment five or six is ​​that in step two, the pretreated diamond substrate is placed in a microwave plasma chemical vapor deposition device, the hydrogen flow rate is controlled to 200-400sccm, the treatment temperature is 650-850°C, the treatment time is 10-60 min, and then cooled to room temperature in a hydrogen atmosphere to complete the hydrogenation treatment.

[0044] Specific embodiment eight: This embodiment differs from any one of specific embodiments five to seven in that the process of forming the source and drain in step three is as follows:

[0045] Photoresist is spin-coated on the conductive channel of the diamond substrate and dried. A photolithography machine is used to expose the preset positions of the source and drain electrodes. The electrodes are developed in a developer to form source and drain patterns. The electrodes are then placed in an electron beam evaporation device to deposit the source and drain electrodes. After deposition, the electrodes are immersed in acetone, taken out after immersion, and the source and drain electrodes in the unexposed areas are peeled off using ultrasound, thereby forming the source and drain electrodes on the conductive channel.

[0046] Specific implementation nine: the difference between this implementation and one of the specific implementations five to eight is that the material of the first source electrode 3, the first drain electrode 4, the second source electrode 5 and the second drain electrode 6 in step three is gold, palladium or iridium.

[0047] Specific implementation ten: the difference between this implementation and one of the specific implementations five to nine is that the first gate pattern is formed on the first ferroelectric dielectric layer 7-1 by using a photolithography process in step seven, and the process of depositing the first gate 8 is as follows:

[0048] The photoresist is spin-coated on the first ferroelectric dielectric layer 7-1 and dried, the first gate is exposed at the preset position by using a photoetching machine, developed in the developing solution, and the first gate pattern is formed, and then placed in an electron beam evaporation device to deposit the first gate 8.

[0049] After the deposition of this implementation is completed, it is soaked in acetone, taken out after soaking, and the gate material in the unexposed area is ultrasonically stripped.

[0050] Specific implementation eleven: the difference between this implementation and one of the specific implementations five to ten is that the material of the first gate 8 and the second gate 9 is aluminum, titanium, platinum, zirconium, tungsten, nickel, yttrium, bismuth, indium or scandium.

[0051] Embodiment: the preparation method of the low-power-consumption diamond transistor in this embodiment is implemented according to the following steps:

[0052] Step S1: the diamond substrate 1 is pretreated and cleaned, and the specific process is as follows:

[0053] The diamond substrate 1 with a thickness of 300 μm is placed in a mixed solution of concentrated H2SO4 and concentrated HNO3 (the mass concentration of concentrated H2SO4 is 98%, and the mass concentration of concentrated HNO3 is 68%), the diamond substrate is obtained by microwave plasma chemical vapor deposition, the volume ratio of concentrated H2SO4 to concentrated HNO3 is 1:1, heated to boiling, treated for 1 hour, the impurities on the surface of the diamond are removed and an oxygen terminal surface is formed, then sequentially placed in acetone, deionized water and anhydrous ethanol for ultrasonic cleaning for 30 minutes respectively, and the pretreated diamond substrate is obtained after cleaning, the root mean square surface roughness of the diamond substrate is less than 0.5 nm, the Raman half-peak width is less than 2 cm -1 , and the XRD rocking curve half-peak width is less than 0.1°.

[0054] Step S2: the pretreated diamond substrate is placed in a microwave plasma chemical vapor deposition device, and the diamond substrate is hydrogenated by using hydrogen plasma, and a conductive channel 2 is formed after being exposed to air, and the specific process is as follows:

[0055] The pretreated diamond substrate 1 was placed in a microwave plasma chemical vapor deposition device and hydrogenated using hydrogen plasma. The hydrogen flow rate was maintained at 300 sccm. The chamber pressure and microwave power were adjusted to maintain the temperature at 650°C for 30 minutes. The substrate was then cooled to room temperature in a hydrogen atmosphere, thereby forming a hydrogen-terminated surface on the diamond substrate 1. A conductive channel 2 was formed after contact with air.

[0056] Step S3: Using a photolithography process to form patterns of a first source electrode 3, a first drain electrode 4, a second source electrode 5, and a second drain electrode 6 on the conductive channel 2 of the diamond substrate, and then depositing metal electrodes. Using a lift-off process, the first source electrode 3, the first drain electrode 4, the second source electrode 5, and the second drain electrode 6 are respectively formed on the conductive channel 2, and the first drain electrode 4 is connected to the second source electrode 5, to obtain a diamond substrate with source and drain electrodes. The specific process is as follows:

[0057] A layer of AZ5214E ​​photoresist was spin-coated on the surface of the diamond substrate with a conductive channel and dried at 95°C for 90 seconds. An ultraviolet photolithography machine was used to expose the preset positions of the first source electrode 3 and the first drain electrode 4 as well as the second source electrode 5 and the second drain electrode 6 through a mask. After developing in a developer for 45 seconds, a source electrode pattern and a drain electrode pattern were formed. The substrate was then placed in an electron beam evaporation device and 100 nm of gold was deposited according to the source electrode pattern and the drain electrode pattern. After the deposition was completed, the substrate was immersed in acetone for 30 minutes, taken out after soaking, and the gold in the unexposed area was stripped off by ultrasound to form the first source electrode 3 and the first drain electrode 4 as well as the second source electrode 5 and the second drain electrode 6 on the conductive channel 2.

[0058] Step S4: using a photolithography process to form a photoresist protection layer on the conductive channel between the first source electrode 3 and the first drain electrode 4, and using oxygen plasma to treat the conductive channel between the second source electrode 5 and the second drain electrode 6. By adjusting the treatment time, the conductivity of the conductive channel is adjusted to achieve current matching. The specific process is as follows:

[0059] A layer of AZ6112 photoresist protective layer was spin-coated on the surface of the diamond substrate with the conductive channel 2 and dried at 105°C for 90 seconds. The region of the conductive channel 2 between the second source electrode 5 and the second drain electrode 6 was exposed using a UV photolithography machine. After developing in a developer for 60 seconds, a photoresist protective layer of the conductive channel was formed. The exposed surface of the diamond substrate 1 was treated with oxygen plasma for 3 seconds to achieve current matching. The photoresist protective layer was then removed with acetone.

[0060] Step S5: Depositing a ferroelectric dielectric layer between the first source electrode 3 and the first drain electrode 4 and the second source electrode 5 and the second drain electrode 6 at low temperature by using an electron beam evaporation process. The specific process is as follows:

[0061] The first ferroelectric dielectric layer 7-1 and the second ferroelectric dielectric layer 7-2 are deposited on the surface of the device after electrical isolation at 350 ℃ by using an electron beam evaporation process, and the electron beam evaporation process parameters are as follows: vacuum degree is 8*10 -4 The evaporation voltage is 6 kV, and the evaporation beam current is 0.55 A, so as to obtain the first ferroelectric dielectric layer 7-1 and the second ferroelectric dielectric layer 7-2.

[0062] Step S6: A first gate pattern is formed on the ferroelectric dielectric layer by using a photolithography process, and a first gate 8 is deposited, and the specific process is as follows:

[0063] An AZ5214E photoresist is spin-coated on the surface of the device with the ferroelectric dielectric layer, and is baked at 95 ℃ for 90 seconds, and is exposed at the preset position of the gate 8 by using an ultraviolet photolithography machine, and is developed in a developing solution for 45 seconds to form a gate pattern, and then is placed in an electron beam evaporation device to deposit gate metal aluminum, and after depositing 100 nm of aluminum, is taken out, is soaked in acetone for 30 minutes, and then is taken out, and the gate material in the unexposed area is stripped by using ultrasonic stripping to obtain the first gate 8.

[0064] Step S7: A second gate pattern is formed on the ferroelectric dielectric layer by using a photolithography process, a second gate 9 is deposited, and is connected to the second source electrode, and the specific process is as follows:

[0065] An AZ5214E photoresist is spin-coated on the surface of the device with the ferroelectric dielectric layer, and is baked at 95 ℃ for 90 seconds, and is exposed at the preset position of the gate 9 by using an ultraviolet photolithography machine, and is developed in a developing solution for 45 seconds to form a gate pattern, and then is placed in an electron beam evaporation device to deposit gate metal aluminum, and after depositing 100 nm of aluminum, is taken out, is soaked in acetone for 30 minutes, and then is taken out, and the gate material in the unexposed area is stripped by using ultrasonic stripping to obtain the second gate 9, thereby obtaining the high-gain diamond logic inverter.

[0066] The embodiment provides a preparation method of a high-gain diamond logic inverter, Figure 11 is a schematic structural diagram of a high-gain diamond logic inverter, which includes a diamond substrate 1, a first source 3, a first drain 4, a second source 5, a second drain 6, a first ferroelectric layer 7-1, a second ferroelectric layer 7-2, a first gate 8, and a second gate 9. The diamond substrate 1 is hydrogenated by hydrogen plasma to form a hydrogen-terminated surface on the diamond substrate 1. The hydrogen-terminated surface forms a conductive channel 2 after contact with air. The first source 3, the first drain 4, the second source 5, and the second drain 6 are provided on the diamond substrate 1 with the hydrogen terminal. The first ferroelectric layer 7-1 and the second ferroelectric layer 7-2 are deposited at room temperature on the diamond substrate 1 with the hydrogen terminal by electron beam evaporation. The first gate 8 and the second gate 9 are respectively provided on the first ferroelectric layer 7-1 and the second ferroelectric layer 7-2. The diamond substrate 1, the conductive channel 2, the first source 3, the first drain 4, the first ferroelectric layer 7-1 and the first gate 8 constitute the driving transistor in the logic inverter; the diamond substrate 1, the conductive channel 2, the first source 5, the first drain 6, the second ferroelectric layer 7-2 and the second gate 9 constitute the load transistor in the logic inverter. Figure 2 This is a schematic diagram of the preparation method of high-gain diamond logic inverter, please refer to Figure 1-2 .

[0067] Figure 3 The phase transition and amplitude diagrams of the ferroelectric layer are shown. The low-temperature deposited ferroelectric layer exhibits an ideal butterfly curve and a 180° phase transition, indicating excellent switchable ferroelectricity.

[0068] Figure 4 The transfer curve of the driver transistor in the high-gain diamond logic inverter of the embodiment is shown, indicating that the subthreshold swing of the driver transistor is 13 mV / dec, which is much smaller than the Boltzmann limit of 60 mV / dec. This is mainly because the deposited ferroelectric dielectric layer has excellent ferroelectric properties, which causes a negative capacitance effect when the polarization is flipped, thereby amplifying the surface potential, thereby enabling the transistor to achieve an ultra-steep subthreshold swing and break the Boltzmann limit.

[0069] Figure 5 The voltage transfer curve of the high-gain diamond logic inverter in the embodiment is shown, indicating that the prepared diamond logic inverter can realize the function of a NOT gate and has the characteristic of near-rail-to-rail operation.

[0070] Figure 6The voltage gain diagram of the high-gain diamond logic inverter in the embodiment is shown, demonstrating that the fabricated diamond logic inverter has an ultra-high voltage gain exceeding 400. The high voltage gain is primarily due to two factors: first, the fast current conversion speed enabled by the ultra-steep subthreshold swing, and second, current matching that enables the inverter to operate in the deep subthreshold region.

[0071] Figure 7 The output curves of the driving transistor and the load transistor in the high-gain diamond logic inverter in the embodiment are shown, reflecting the working state of the logic inverter.

Claims

1. A high-gain diamond logic inverter, characterized in that The high-gain diamond logic inverter comprises a diamond substrate (1), a first source (3), a first drain (4), a second source (5), a second drain (6), a first ferroelectric dielectric layer (7-1), a second ferroelectric dielectric layer (7-2), a first gate (8) and a second gate (9). The diamond substrate (1) is hydrogenated by hydrogen plasma to form a diamond substrate (1) with a hydrogen terminal. The surface of the hydrogen terminal is exposed to air to form a conductive channel (2). The first source (3), the first drain (4), the second source (5) and the second gate (9) are provided on the diamond substrate (1) with the hydrogen terminal. The invention relates to a second drain electrode (6), wherein a first ferroelectric dielectric layer (7-1) and a second ferroelectric dielectric layer (7-2) are deposited at low temperature on a diamond substrate (1) with a hydrogen terminal by an electron beam evaporation process, wherein the first ferroelectric dielectric layer (7-1) is located between the first source electrode (3) and the first drain electrode (4), and the second ferroelectric dielectric layer (7-2) is located between the second source electrode (5) and the second drain electrode (6). A first gate electrode (8) is provided on the first ferroelectric dielectric layer (7-1), and a second gate electrode (9) is provided on the second ferroelectric dielectric layer (7-2), and a portion of the second gate electrode (9) is connected to the second source electrode (5).

2. The high-gain diamond logic inverter according to claim 1, characterized in that The hole density of the conductive channel (2) is 1×10 12 -1×10 14 cm -2 , with a mobility of 50-200 cm 2 / (V·s).

3. The high-gain diamond logic inverter according to claim 1, characterized in that The material of the first ferroelectric dielectric layer (7-1) and the second ferroelectric dielectric layer (7-2) is ZrO2 or HfO2.

4. The high-gain diamond logic inverter according to claim 1, characterized in that The thickness of the first ferroelectric dielectric layer (7-1) and the second ferroelectric dielectric layer (7-2) is 30-100 nm.

5. The method for preparing a high-gain diamond logic inverter according to claim 1, characterized in that The preparation method of the high-gain diamond logic inverter is implemented according to the following steps:

1. Pre-treating and cleaning the diamond substrate (1) to obtain a pre-treated diamond substrate; 2. Placing the pretreated diamond substrate into a microwave plasma chemical vapor deposition device, hydrogenating the diamond substrate using hydrogen plasma, and then forming a conductive channel (2) after contacting the diamond substrate with air, thereby obtaining a diamond substrate with a conductive channel; 3. forming patterns of a first source electrode (3), a first drain electrode (4), a second source electrode (5) and a second drain electrode (6) on the conductive channel (2) of the diamond substrate by using a photolithography process, then depositing metal electrodes, and forming the first source electrode (3), the first drain electrode (4), the second source electrode (5) and the second drain electrode (6) on the conductive channel (2) by using a lift-off process, wherein the first drain electrode (4) and the second source electrode (5) are arranged adjacent to each other, thereby obtaining a diamond substrate with source and drain electrodes; 4. forming a photoresist protective layer on the conductive channel between the first source electrode (3) and the first drain electrode (4) by using a photolithography process, treating the conductive channel between the second source electrode (5) and the second drain electrode (6) with oxygen plasma, and regulating the hydrogen terminal coverage of the diamond surface by adjusting the oxygen plasma treatment time and power to reduce the conductivity of the conductive channel to achieve current matching; 5. Depositing a first ferroelectric dielectric layer (7-1) and a second ferroelectric dielectric layer (7-2) between the first source (3) and the first drain (4), and between the second source (5) and the second drain (6) by an electron beam evaporation process at a low temperature of 150° to 350°, wherein the first ferroelectric dielectric layer (7-1) is located between the first source (3) and the first drain (4), and the second ferroelectric dielectric layer (7-2) is located between the second source (5) and the second drain (6), thereby obtaining a device with a ferroelectric dielectric layer; 6. forming a first gate pattern on the first ferroelectric dielectric layer (7-1) by using a photolithography process, and depositing a first gate (8); 7. Using a photolithography process to form a second gate pattern on the second ferroelectric dielectric layer (7-2), depositing a second gate (9), and connecting a portion of the second gate (9) to the second source (5), thereby obtaining a high-gain diamond logic inverter.

6. The method for preparing a high-gain diamond logic inverter according to claim 5, characterized in that In step 1, the diamond substrate is pretreated by placing the diamond substrate in a mixed solution of concentrated H2SO4 and concentrated HNO3, heating it to boiling, and treating it for 0.5 to 2 hours.

7. The method for preparing a high-gain diamond logic inverter according to claim 5, characterized in that In step 2, the pretreated diamond substrate is placed in a microwave plasma chemical vapor deposition device, the hydrogen flow rate is controlled to 200-400 sccm, the treatment temperature is 650-850 ° C, the treatment time is 10-60 min, and then cooled to room temperature in a hydrogen atmosphere to complete the hydrogenation treatment.

8. The method for preparing a high-gain diamond logic inverter according to claim 5, characterized in that In step three, the first source electrode (3), the first drain electrode (4), the second source electrode (5) and the second drain electrode (6) are made of gold, palladium or iridium.

9. The method for preparing a high-gain diamond logic inverter according to claim 5, characterized in that In step seven, a first gate pattern is formed on the first ferroelectric dielectric layer (7-1) using a photolithography process. The process of depositing the first gate (8) is as follows: A photoresist is spin-coated on the first ferroelectric dielectric layer (7-1) and dried, and exposed at a preset position of the first gate using a photolithography machine, developed in a developer to form a first gate pattern, and then placed in an electron beam evaporation device to deposit the first gate (8).

10. The method for preparing a high-gain diamond logic inverter according to claim 5, characterized in that The first gate (8) and the second gate (9) are made of aluminum, titanium, platinum, zirconium, tungsten, nickel, yttrium, bismuth, indium or scandium.

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