Judgment circuit for output power of flyback topological structure

Abstract

The invention discloses a flyback topological structure output power judgment circuit which comprises a detection end connected with a synchronous rectification mos tube SR end through a low end of a resistor R1, a resistor R2 is connected between the detection end and the resistor R1 in parallel, and the detection end comprises a diode clamping circuit composed of a diode D1 and a bias voltage source VB and a low connection current mirror composed of a triode Q1 and a triode Q2. The triode Q2 is connected with dynamic voltage; the low connection current mirror transmits a detection current mirror image to a resistor R3; the voltage comparator T1 outputs a detection signal based on the detection current and the resistor R3, and the rising edge counter J1 measures the rising edge frequency of the detection signal and outputs a judgment result. Therefore, only one resistor needs to be additionally arranged on the existing driving circuit, the voltage comparator can compare and output the detection signal containing the rising edge and the falling edge, so that the switching frequency is measured, the load judgment is realized, the device requirement is greatly reduced, and meanwhile, the detection accuracy is greatly improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit design, and particularly relates to a judgment circuit for output power of a flyback topology structure. BACKGROUND

[0002] The fast charging function can greatly improve the charging speed of various types of intelligent devices, so it is rapidly applied. Correspondingly, fast charging power supplies and fast charging chargers and other fast charging devices are also rapidly developed and iterated. For fast charging devices, in addition to the user's hope that the fast charging device can fast charge the intelligent device, the user also hopes that the size and weight of the fast charging device are smaller and smaller, and the user also hopes that the fast charging device can judge the no-load / load state by itself to adapt to the user's habit of plugging the fast charging device into the socket for a long time, so as to realize low power consumption in the no-load state and wake up to supply power in the load state.

[0003] However, most fast charging devices on the market need to at least perform current sampling and output voltage sampling to calculate the output power to determine the running state, which increases the hardware cost and makes it difficult to compress the size and weight of the device. In addition, the sampling resistor itself has a resistance deviation, and the output voltage and current will have ripples in actual use, which will adversely affect the sampling accuracy. SUMMARY

[0004] The embodiment discloses a judgment circuit for output power of a flyback topology structure, and specifically comprises:

[0005] The detection end is connected to the low end of the resistor R1 and the end of the synchronous rectification mos tube SR, a resistor R2 is connected in parallel between the detection end and the resistor R1, the synchronous rectification mos tube has a turns ratio of N1:N2, the input voltage is u0, and the output voltage is Vout;

[0006] The detection end comprises a diode clamping circuit composed of a diode D1 and a bias voltage source V B , and a low-connection current mirror composed of a triode Q1 and a triode Q2, the emitter of the triode Q2 is connected to a dynamic voltage Vcmp through a resistor R3;

[0007] The low-connection current mirror mirrors and transmits the detection current Idet output by the diode clamping circuit to the resistor R3;

[0008] The voltage comparator T1 compares the detection voltage Vcomp calculated based on the detection current Idet and the resistor R3 with a set voltage threshold Vset and outputs a detection signal;

[0009] The rising edge counter J1 measures the rising edge frequency of the detection signal and outputs a judgment result.

[0010] As an optional implementation, the detection power supply transmits a reference voltage Vdet to the anode of the diode D1 via the capacitor C1.

[0011] As an optional implementation, when the reference voltage Vdet<V D1 +V BIAS +Vgs, the diode D1 is reverse-cut off, the diode clamp circuit cuts off the current, and the reference voltage

[0012] Wherein, Vsr is the voltage value of the synchronous rectifier MOSFET SR terminal;

[0013] The dynamic voltage Vcmp=Idet*R3, the resistor R2 shunts the diode clamp circuit, and the current value of the resistor R2 is I R2 =Vdet / R2;

[0014] Furthermore, the detection voltage

[0015] As an optional implementation, when the reference voltage Vdet≥V D1 +V BIAS When +Vgs, the diode D1 is turned on;

[0016] Among them, V D1 is the conduction voltage drop of the diode D1, V BIAS The bias voltage source V B Vgs is the voltage value of the low-voltage current mirror;

[0017] The detection voltage

[0018] As an optional implementation, if the detection end is connected to the synchronous rectifier MOSFET SR via the high end of the resistor R1, the diode D2 and the bias power supply V B A diode clamp circuit is formed, transistor Q3 and transistor Q4 form a high-connection current mirror, and resistor R4 and capacitor C2 are connected in parallel with the diode clamp circuit and the high-connection current mirror;

[0019] The emitter of the transistor Q4 is connected to the dynamic voltage Vcmp via the resistor R5 , and the emitter of the transistor Q3 is connected to the external source voltage Vcc.

[0020] As an optional implementation, when the reference voltage Vdet≤V cc -Vgs-V BIAS When the reference voltage Vdet is clamped to V cc -Vgs-V D2 -VBIAS .

[0021] As an optional implementation, when the reference voltage Vdet>V cc -Vgs-V D2 -V BIAS When , the diode D2 is reverse-cut off, the diode clamping circuit cuts off the current, the resistor R4 shunts the current, or the resistor R4 discharges through the capacitor C2.

[0022] As an optional embodiment, when the diode D2 is in the clamping state, the reference voltage Vdet is fixed and the detection voltage

[0023] As an optional implementation, the protocol control unit is connected to the SR end of the synchronous rectifier MOSFET via the resistor R1.

[0024] As an optional implementation, the output end of the voltage comparator T1 is connected to the input end of the rising edge counter J1 via a Schmitt trigger S1.

[0025] Compared with the prior art, this embodiment has the following beneficial effects:

[0026] In this embodiment, only one resistor needs to be added to the existing driving circuit, and the voltage comparator can compare and output a detection signal containing rising and falling edges, thereby determining the switching frequency and realizing load judgment. The device requirements are greatly reduced, and the detection accuracy is greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solution in this embodiment, the following is a brief introduction to the drawings required for use in the embodiment. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1 This is a schematic diagram of the circuit principle of the detection end connected to the low end in the output power judgment circuit of a flyback topology structure disclosed in this embodiment;

[0029] Figure 2 This is a schematic diagram of the circuit principle of the low-end connection state of the detection end in the output power judgment circuit of the flyback topology structure disclosed in this embodiment;

[0030] Figure 3 This is a schematic diagram of the circuit principle of the output end of a flyback topology output power judgment circuit disclosed in this embodiment;

[0031] Figure 4This is a schematic diagram of the circuit principle of the detection end connected to the high end in the output power judgment circuit of a flyback topology structure disclosed in this embodiment;

[0032] Figure 5 This is a schematic diagram of the circuit principle of the high-end connection state of the detection end in the output power judgment circuit of the flyback topology structure disclosed in this embodiment. DETAILED DESCRIPTION

[0033] The following will clearly and completely describe the technical solutions in this embodiment with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0034] See also Figures 1 to 5 , this embodiment discloses a flyback topology output power determination circuit, comprising:

[0035] The detection end of the synchronous rectifier MOSFET SR is connected to the low end of the resistor R1, and the resistor R2 is connected in parallel between the detection end and the resistor R1. The double-end turns ratio of the synchronous rectifier MOSFET is N1:N2, the input voltage is u0, and the output voltage is Vout;

[0036] The detection terminal consists of a diode D1 and a bias voltage source V B A diode clamp circuit is formed by a transistor Q1 and a transistor Q2, and a low-connection current mirror is formed by the transistor Q1 and the transistor Q2. The emitter of the transistor Q2 is connected to the dynamic voltage Vcmp through the resistor R3;

[0037] The low-side current mirror transmits the detection current Idet output by the diode clamp circuit to the resistor R3;

[0038] The voltage comparator T1 calculates the detection voltage Vcomp based on the detection current Idet and the resistor R3, compares the detection voltage Vcomp with the set voltage threshold Vset, and outputs a detection signal;

[0039] The rising edge counter J1 measures the rising edge frequency of the detection signal and outputs the judgment result.

[0040] In this embodiment, the voltage comparator compares the detection voltage with the set voltage threshold and outputs a detection signal including a rising edge and a falling edge. If the detection voltage is higher than the set voltage threshold, it is determined to be a rising edge. If the detection voltage is not higher than the set voltage threshold, it is determined to be a falling edge.

[0041] The rising edge counter measures the rising edge frequency of the detection signal, that is, the number of rising edges per unit time.

[0042] Here, the rising edge frequency is used to determine whether the device is in a no-load state or a loaded state.

[0043] For example, based on the characteristic operating characteristics of the device, a no-load frequency threshold is set to represent the highest frequency value that the device can reach when in low-power standby or hibernation. Therefore, when the rising edge frequency is not greater than the no-load frequency threshold, it indicates that the device is in a no-load state; and when the rising edge frequency is greater than the no-load frequency threshold, it indicates that the device is in a loaded state.

[0044] Based on this, there is no need to set up special voltage / current sampling components. On the basis of the original circuit design, load detection can be easily realized and the operating status of the equipment can be judged, so that the volume and weight of the equipment can be effectively controlled.

[0045] In addition, since no sampling resistor is required, the detection accuracy is high and the output result is stable.

[0046] As an optional implementation, the detection power supply transmits a reference voltage Vdet to the anode of the diode D1 via the capacitor C1.

[0047] As an optional implementation, when the reference voltage Vdet<V D1 +V BIAS When +Vgs, diode D1 is reverse cutoff, the diode clamp circuit cuts off the current, and the reference voltage

[0048] Among them, Vsr is the voltage value of the synchronous rectifier MOSFET SR terminal;

[0049] Dynamic voltage Vcmp=Idet*R3, resistor R2 shunts the diode clamp circuit, so the current value of resistor R2 is I R2 =Vdet / R2;

[0050] Furthermore, the detection voltage

[0051] As an optional implementation, when the reference voltage Vdet≥V D1 +V BIAS When +Vgs, diode D1 is turned on;

[0052] Among them, V D1 is the forward voltage drop of diode D1, V BIAS is the bias voltage source V B The voltage value of Vgs is the conduction voltage drop of the low-side current mirror;

[0053] Detection voltage

[0054] Here, the detection end is connected to the low end of the synchronous rectifier MOSFET SR, the positive pulse voltage of Vsr is larger, and the negative pulse voltage is smaller.

[0055] The input voltage value of the flyback topology structure and the current value flowing through the detection terminal can be considered to be in direct proportion, that is, the higher the input voltage value of the flyback topology structure, the higher the current value flowing through the detection terminal.

[0056] By replacing the resistor R1 with a different resistance value, the ratio of the input voltage of the flyback topology structure to the current flowing through the detection terminal can be modified. Therefore, when the resistance value of the resistor R1 is determined, the ratio of the input voltage of the flyback topology structure to the current flowing through the detection terminal is also determined.

[0057] Assuming that the current value flowing through the detection terminal is A and the input voltage value of the flyback topology is B, when the input voltage value of the flyback topology is greater than B, the current value flowing through the detection terminal will also be greater than A. By setting the current threshold in the detection terminal, the actual input voltage value of the flyback topology can be obtained by monitoring the current value A.

[0058] In actual operation, the input voltage u0 fluctuates, and thus Vsr also fluctuates accordingly.

[0059] Here, by setting the voltage value corresponding to the current threshold to be less than the minimum value of the input voltage u0, full-range frequency monitoring can be achieved. When it is detected that the current exceeds the current threshold set at the detection end, it can be considered that the input voltage of the flyback topology structure is higher than the voltage value corresponding to this current threshold, which is a rising edge; otherwise, it is a falling edge.

[0060] Furthermore, by detecting the number of rising edges per unit time, that is, the rising edge frequency, the switching frequency of the switching device can be obtained.

[0061] It is understandable that when the output is unloaded, the switching frequency interval of the switching device is longer, and the energy output by the lower frequency can maintain low power consumption operation.

[0062] When the load is maintained, the switching device will maintain the output voltage through a higher switching frequency. Therefore, by monitoring the switching frequency, it is possible to accurately determine whether the current state is no-load or load.

[0063] As an optional implementation, if the detection end is connected to the synchronous rectifier MOSFET SR via the high end of the resistor R1, the diode D2 and the bias power supply V B A diode clamp circuit is formed, transistor Q3 and transistor Q4 form a high-connection current mirror, and resistor R4 and capacitor C2 are connected in parallel with the diode clamp circuit and the high-connection current mirror;

[0064] The emitter of the transistor Q4 is connected to the dynamic voltage Vcmp via the resistor R5 , and the emitter of the transistor Q3 is connected to the external source voltage Vcc.

[0065] As an optional implementation, when the reference voltage Vdet≤V cc -Vgs-V BIAS When the reference voltage Vdet is clamped to V cc -Vgs-V D2 -V BIAS .

[0066] As an optional implementation, when the reference voltage Vdet>V cc -Vgs-V D2 -V BIAS When , the diode D2 is reverse-cut off, the diode clamp circuit cuts off the current, the resistor R4 shunts the current, or R4 discharges through the capacitor C2.

[0067] As an optional embodiment, when the diode D2 is in the clamping state, the reference voltage Vdet is fixed and the detection voltage

[0068] Here, the detection end is connected to the high end of the synchronous rectifier MOSFET SR, the positive pulse voltage of Vsr is small, and the negative pulse voltage is large.

[0069] As an optional implementation, the protocol control unit is connected to the SR end of the synchronous rectifier MOSFET via the resistor R1.

[0070] Here, by configuring different protocol schemes for the protocol control unit, it is possible to detect the switching frequency of the switching device while maintaining a standby state in a no-load state while waking up the protocol control unit in a load state to perform corresponding electronic control operations, thereby broadening its application scenarios.

[0071] As an optional implementation, the output end of the voltage comparator T1 is connected to the input end of the rising edge counter J1 via a Schmitt trigger S1.

[0072] Specifically, the detection signal output by the voltage comparator is a low-voltage waveform. After being debounced and shaped by the Schmitt trigger, the low-voltage waveform forms a square wave signal with a regular pattern. The rising edge counter can accurately measure the switching frequency based on this.

[0073] Compared with the prior art, this embodiment has the following beneficial effects:

[0074] In this embodiment, only one resistor needs to be added to the existing driving circuit, and the voltage comparator can compare and output a detection signal containing rising and falling edges, thereby determining the switching frequency and realizing load judgment. The device requirements are greatly reduced, and the detection accuracy is greatly improved.

Claims

1. A circuit for determining the output power of a flyback topology structure, characterized in that: include: The detection end of the synchronous rectifier MOSFET SR is connected to the low end of the resistor R1, and a resistor R2 is connected in parallel between the detection end and the resistor R1. The double-end turns ratio of the synchronous rectifier MOSFET is N1:N2, the input voltage is u0, and the output voltage is Vout; The detection end includes a diode D1 and a bias voltage source V B A diode clamp circuit is formed, and a low-connection current mirror is formed by a transistor Q1 and a transistor Q2, wherein the emitter of the transistor Q2 is connected to a dynamic voltage Vcmp via a resistor R3; The low-connection current mirror transmits the detection current Idet output by the diode clamp circuit to the resistor R3; The voltage comparator T1 compares the detection voltage Vcomp obtained by calculating the detection current Idet and the resistor R3 with a set voltage threshold Vset and outputs a detection signal. The rising edge counter J1 measures the rising edge frequency of the detection signal and outputs a judgment result.

2. The flyback topology output power judgment circuit according to claim 1, characterized in that: include: The detection power supply transmits a reference voltage Vdet to the anode of the diode D1 via the capacitor C1 .

3. The flyback topology output power judgment circuit according to claim 2, characterized in that: include: When the reference voltage Vdet<V D1 +V BIAS +Vgs, the diode D1 is reverse-cut off, the diode clamp circuit cuts off the current, and the reference voltage Wherein, Vsr is the voltage value of the synchronous rectifier MOSFET SR terminal; The dynamic voltage Vcmp=Idet*R3, the resistor R2 shunts the diode clamp circuit, and the current value of the resistor R2 is I R2 =Vdet / R2; Furthermore, the detection voltage 4. The flyback topology output power judgment circuit according to claim 3, characterized in that: include: When the reference voltage Vdet ≥ V D1 +V BIAS When +Vgs, the diode D1 is turned on; Among them, V D1 is the conduction voltage drop of the diode D1, V BIAS The bias voltage source V B Vgs is the voltage value of the low-voltage current mirror; The detection voltage 5. The flyback topology output power judgment circuit according to claim 1, characterized in that: include: If the detection end is connected to the synchronous rectifier MOSFET SR through the high end of the resistor R1, the diode D2 and the bias power supply V B A diode clamp circuit is formed, transistor Q3 and transistor Q4 form a high-connection current mirror, and resistor R4 and capacitor C2 are connected in parallel with the diode clamp circuit and the high-connection current mirror; The emitter of the transistor Q4 is connected to the dynamic voltage Vcmp via the resistor R5 , and the emitter of the transistor Q3 is connected to the external source voltage Vcc.

6. The flyback topology output power judgment circuit according to claim 5, characterized in that: include: When the reference voltage Vdet≤V cc -Vgs-V BIAS When the reference voltage Vdet is clamped to V cc -Vgs-V D2 -V BIAS .

7. The flyback topology output power judgment circuit according to claim 6, characterized in that: include: When the reference voltage Vdet>V cc -Vgs-V D2 -V BIAS When , the diode D2 is reverse-cut off, the diode clamping circuit cuts off the current, the resistor R4 shunts the current, or the resistor R4 discharges through the capacitor C2.

8. The flyback topology output power judgment circuit according to claim 7, characterized in that: include: When the diode D2 is in the clamped state, the reference voltage Vdet is fixed and the detection voltage 9. The flyback topology output power judgment circuit according to claim 1, characterized in that: include: The protocol control unit is connected to the SR end of the synchronous rectifier MOSFET via the resistor R1.

10. The flyback topology output power judgment circuit according to claim 1, characterized in that: include: The output terminal of the voltage comparator T1 is connected to the input terminal of the rising edge counter J1 via a Schmitt trigger S1 .

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