Current source circuit, clock source circuit and clock source generating device

Abstract

The embodiment of the invention provides a current source circuit, a clock source circuit and a clock source generating device. The current source circuit comprises a bias current generating circuit and a temperature coefficient balancing circuit, the bias current generating circuit comprises a current adjusting module and an output module. The bias circuit is used for generating bias current with a corresponding positive temperature coefficient; the current adjusting module comprises a first triode and a second triode; the adjusting module is used for adjusting bias voltage applied to the first triode and the second triode according to the preset area ratio to obtain first current with a target current value; the output module is used for outputting bias current; and the temperature coefficient balancing circuit is used for generating a current with a negative temperature coefficient and adjusting the temperature coefficient of the bias current. The current source circuit provided by the invention can generate the bias current with the positive coefficient, adjusts the temperature coefficient of the bias current through the current with the negative temperature coefficient, and guarantees the stability of the output bias current.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of analog integrated circuit design, and in particular to a current source circuit, a clock source circuit and a clock source generation device. BACKGROUND

[0002] Clock source is a core element for providing accurate time reference and timing control, and its application range is extremely wide. Relaxation oscillator based on traditional resistor-capacitor (RC) circuit is widely used in clock design of microcontroller unit (MCU) and other circuits due to its characteristics. However, the devices in the clock source circuit have specific temperature coefficients, and within a certain temperature fluctuation range, the characteristic values of the devices will change. The heat generated during the operation of the clock source will also affect the devices in the circuit, thereby affecting the frequency of the clock signal, which is difficult to meet the higher precision clock demand. At present, the main solution to this problem is to collect the temperature of the main chip in the oscillator, and change the analog voltage of the variable capacitor according to the temperature, so as to change the capacitance value, thereby realizing the adjustment of the output clock frequency. However, this technology has the defect of complex circuit structure, and requires an additional temperature-voltage conversion control module to change the capacitance value, which increases the complexity and cost of circuit design, and also limits its application scenarios to some extent. In summary, there is an urgent need for a circuit that can adjust the temperature coefficient and ensure stable bias current output. SUMMARY

[0003] The present disclosure provides a current source circuit, a clock source circuit and a clock source generation device to adjust the temperature coefficient of the bias current and output stable bias current.

[0004] Based on the above problems, in a first aspect, the present disclosure provides a current source circuit, comprising: a bias current generation circuit and a temperature coefficient balancing circuit; The bias current generation circuit comprises a current adjusting module and an output module; the bias current generation circuit is configured to generate a bias current with a corresponding positive temperature coefficient; The current adjusting module comprises a first triode and a second triode; the first triode and the second triode are two symmetrical transistors with a preset area ratio; the current adjusting module is configured to adjust the bias voltage applied to the first triode and the second triode according to the preset area ratio, to obtain a first current with a target current value; The output module is configured to obtain the first current and output it as a bias current; The temperature coefficient balancing circuit comprises two resistors connected in parallel with the first transistor and the second transistor respectively; and the temperature coefficient balancing circuit is configured to generate a current with a negative temperature coefficient to adjust a temperature coefficient of the bias current generated by the bias current generation circuit.

[0005] With reference to the first aspect, in a possible implementation, the bias current generation circuit further comprises a bias voltage generation module. The bias voltage generation module is configured to convert a power supply voltage into two equal bias voltages and output the two equal bias voltages to the current adjustment module.

[0006] With reference to the first aspect, in a possible implementation, the bias voltage generation module comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first resistor, a second resistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. A source of the first PMOS transistor is connected to a power supply; a gate of the first PMOS transistor is connected to the output module, a gate of the second PMOS transistor, and a drain of the fourth PMOS transistor; and a drain of the first PMOS transistor is connected to a source of the third PMOS transistor. A source of the second PMOS transistor is connected to the power supply; and a drain of the second PMOS transistor is connected to a source of the fourth PMOS transistor. A gate of the third PMOS transistor is connected to the output module, a gate of the fourth PMOS transistor, and a drain of the second NMOS transistor; and a drain of the third PMOS transistor is connected to one end of the first resistor and a gate of the first NMOS transistor. A drain of the fourth PMOS transistor is connected to one end of the second resistor. A drain of the first NMOS transistor is connected to the other end of the first resistor and a gate of the third NMOS transistor; a gate of the first NMOS transistor is connected to a gate of the second NMOS transistor; a source of the first NMOS transistor is connected to a drain of the third NMOS transistor. A drain of the second NMOS transistor is connected to the other end of the second resistor; and a source of the second NMOS transistor is connected to a drain of the fourth NMOS transistor. A gate of the third NMOS transistor is connected to a gate of the fourth NMOS transistor; and a source of the third NMOS transistor is connected to the current adjustment module. A source of the fourth NMOS transistor is connected to the current adjustment module.

[0007] With reference to the first aspect, in a possible implementation, the current adjustment module further comprises a third resistor. The emitter of the first transistor is connected to the bias voltage generating module, and the base of the first transistor is connected to the collector of the first transistor and is grounded; One end of the third resistor is connected to the bias voltage generating module, and the other end of the third resistor is connected to the emitter of the second transistor; The base of the second transistor is connected to the collector of the second transistor and is grounded.

[0008] In combination with the first aspect, in a possible implementation manner, the output module includes: a fifth PMOS transistor and a sixth PMOS transistor; The source of the fifth PMOS transistor is connected to a power supply, the drain of the fifth PMOS transistor is connected to the sixth PMOS transistor, and the gate of the fifth PMOS transistor is connected to the bias voltage generating module; The gate of the sixth PMOS transistor is connected to the bias voltage generating module, and the drain of the sixth PMOS transistor serves as the output end of the current source circuit to output the bias current.

[0009] In combination with the first aspect, in a possible implementation manner, the temperature coefficient balancing circuit includes: a fourth resistor and a fifth resistor; One end of the fourth resistor is connected to the collector of the first transistor and is grounded, and the other end of the fourth resistor is connected to the emitter of the first transistor; One end of the fifth resistor is connected to one end of the third resistor, and the other end of the fifth resistor is connected to the collector of the second transistor and is grounded.

[0010] In combination with the first aspect, in a possible implementation manner, the device further includes: a starting circuit; The startup circuit is used to generate an initial excitation input to the bias current generating circuit when the current source circuit is powered on, so as to start the bias current generating circuit.

[0011] In combination with the first aspect, in a possible implementation manner, the startup circuit includes: a seventh PMOS transistor, an eighth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor; The source of the seventh PMOS transistor is connected to a power supply, the gate of the seventh PMOS transistor is connected to the bias current generating circuit, and the drain of the seventh PMOS transistor is connected to the drain of the fifth NMOS transistor and the gate of the eighth PMOS transistor respectively; The source of the eighth PMOS transistor is connected to a power supply, and the drain of the eighth PMOS transistor is connected to the bias current generating circuit; The gate of the fifth NMOS transistor, the gate of the sixth NMOS transistor, the gate of the seventh NMOS transistor, the gate of the eighth NMOS transistor and the gate of the ninth NMOS transistor are connected and grounded; The source of the fifth NMOS tube is connected to the drain of the sixth NMOS tube; the source of the sixth NMOS tube is connected to the drain of the seventh NMOS tube; the source of the seventh NMOS tube is connected to the drain of the eighth NMOS tube; the source of the eighth NMOS tube is connected to the drain of the ninth NMOS tube; and the source of the ninth NMOS tube is grounded.

[0012] A second aspect of the present disclosure further provides a clock source circuit, comprising: a current source module, a first comparator module, a second comparator module, and a logic control module; The current source module comprises the current source circuit according to any one of the first aspects, configured to output bias current to the first comparator module and the second comparator module respectively; The first comparator module includes: a first comparator, a first capacitor, and a first switch device; the first capacitor is used to charge according to the bias current; the first comparator is used to compare the voltage of the first capacitor with a reference voltage and output a first electrical signal according to the comparison result; the first switch device is used to control the charging and discharging state of the first capacitor according to the control signal output by the logic control module; The second comparator module includes: a second comparator, a second capacitor, and a second switch device; the second capacitor is used to charge according to the bias current; the second comparator is used to compare the voltage of the second capacitor with a reference voltage and output a second electrical signal according to the comparison result; the second switch device is used to control the charging and discharging state of the second capacitor according to the control signal output by the logic control module; The logic control module is used to shape the first electrical signal and the second electrical signal to obtain an oscillation waveform; and output a control signal according to a preset logic to control the first capacitor and the second capacitor to alternately charge and discharge.

[0013] A third aspect of the present disclosure further provides a clock source generating device, comprising the clock source circuit described in the second aspect.

[0014] The beneficial effects of the embodiments of the present disclosure include: The present disclosure provides a current source circuit, a clock source circuit, and a clock source generation device, including: a bias current generation circuit and a temperature coefficient balancing circuit; the bias current generation circuit includes: a current regulation module and an output module; for generating a bias current with a corresponding positive temperature coefficient; the current regulation module includes: a first transistor and a second transistor; the first transistor and the second transistor are two symmetrical transistors with a preset area ratio; the current regulation module is used to adjust the bias voltage applied to the first transistor and the second transistor according to the preset area ratio to obtain a first current with a target current value; the output module is used to obtain the first current and output it as a bias current; the temperature coefficient balancing circuit includes two resistors connected in parallel with the first transistor and the second transistor respectively; the temperature coefficient balancing circuit is used to generate a current with a negative temperature coefficient and adjust the temperature coefficient of the bias current in the bias current generation circuit. The current source circuit provided by the present disclosure can generate a bias current with a positive coefficient, adjust the temperature coefficient of the bias current through a current with a negative temperature coefficient, and ensure the stability of the output bias current. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic diagram of a current source circuit structure provided by an embodiment of the present disclosure; Figure 2 A schematic diagram of the structure of a current regulation module provided in an embodiment of the present disclosure; Figure 3 A schematic diagram of the bias voltage generation module structure provided in an embodiment of the present disclosure; Figure 4 A temperature coefficient comparison chart provided for an embodiment of the present disclosure; Figure 5 A schematic diagram of the clock source circuit structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] The present disclosure provides a current source circuit, a clock source circuit, and a clock source generation device. Preferred embodiments of the present disclosure are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are intended only to illustrate and explain the present disclosure and are not intended to limit the present disclosure. Furthermore, the embodiments and features within the embodiments of the present disclosure may be combined with one another unless there is a conflict.

[0017] The present disclosure provides a current source circuit, such as Figure 1 As shown, it includes: a bias current generating circuit 1 and a temperature coefficient balancing circuit 2; The bias current generating circuit 1 comprises: a current regulating module 12 and an output module 13; the bias current generating circuit 1 is used to generate a bias current with a corresponding positive temperature coefficient; like Figure 2 As shown, the current regulating module 12 includes: a first triode 121 and a second triode 122; the first triode 121 and the second triode 122 are two symmetrical transistors with a preset area ratio; the current regulating module 12 is used to adjust the bias voltage applied to the first triode 121 and the second triode 122 according to the preset area ratio to obtain a first current with a target current value; The output module 13 is used to obtain the first current and output it as a bias current; The temperature coefficient balancing circuit 2 includes two resistors connected in parallel with the first transistor 121 and the second transistor 122 respectively; the temperature coefficient balancing circuit 2 is used to generate a current with a negative temperature coefficient and adjust the temperature coefficient of the bias current in the bias current generating circuit 1.

[0018] In the disclosed embodiment, the current source circuit can provide a stable current for the clock source circuit, isolate the interference of noise in the power supply, and reduce the impact of power supply voltage fluctuations on the current.

[0019] The current source circuit may include a bias current generating circuit 1 and a temperature coefficient balancing circuit 2, wherein the bias current output by the bias current generating circuit 1 can be used as a reference current for the clock source circuit. By injecting this reference current, it is possible to ensure that the components in the clock source circuit operate in a preset operating state, thereby achieving a stable clock signal output.

[0020] Bias current output from bias current generating circuit 1 It can be a current with a positive temperature coefficient, that is, the current will increase as the temperature rises. Ideally, the devices in the clock source circuit also have a certain temperature coefficient. As the temperature changes, the changes in the temperature coefficients of different devices will offset each other, so that the final output clock signal remains stable. However, in actual applications, the positive temperature coefficient of the bias current may be too large, causing the clock source circuit to be overcompensated, so that the output clock signal will also change with temperature. In order to solve the above problem, the temperature coefficient balancing circuit 2 provided by the present disclosure can generate a negative temperature coefficient to adjust the temperature coefficient of the bias current, so that the temperature coefficient of the bias current matches the temperature coefficient of the clock source circuit, so that the output clock signal is not affected by temperature changes, thereby ensuring the stability of the output clock signal.

[0021] The current adjusting module 12 can include two transistors with a preset area ratio, which can be a first transistor 121 and a second transistor 122. Bias voltages are applied to the two transistors respectively, and a corresponding voltage difference can be generated according to the area ratio, so as to generate a first current with a corresponding current value in the bias current generating circuit 1.

[0022] The output module 13 can obtain the first current and output the first current as a bias current of a clock source circuit to the clock source circuit.

[0023] In yet another embodiment of the present disclosure, as shown in Figure 1 The bias current generating circuit 1 further includes a bias voltage generating module 11. The bias voltage generating module 11 is configured to convert a power supply voltage into two equal bias voltages and output the two equal bias voltages to the current adjusting module 12.

[0024] In the embodiment of the present disclosure, the bias current generating circuit 1 can be composed of the bias voltage generating module 11, the current adjusting module 12 and the output module 13.

[0025] The bias voltage generating module 11 can include a plurality of metal oxide semiconductor field effect transistors (MOS, Metal-Oxide-Semiconductor Field-Effect Transistor), specifically, a P-type channel metal oxide semiconductor field effect transistor (PMOS, P-channel Metal-Oxide-Semiconductor Field-Effect Transistor) and an N-type channel metal oxide semiconductor field effect transistor (NMOS, N-channel Metal-Oxide-Semiconductor Field-Effect Transistor). The power supply voltage can be converted into two equal bias voltages through a special connection relationship between the MOS tubes, and the two bias voltages are provided to the current adjusting module 12.

[0026] In yet another embodiment of the present disclosure, as shown in Figure 3 The bias voltage generating module 11 includes a first PMOS tube 1101, a second PMOS tube 1102, a third PMOS tube 1103, a fourth PMOS tube 1104, a first resistor 1105, a second resistor 1106, a first NMOS tube 1107, a second NMOS tube 1108, a third NMOS tube 1109 and a fourth NMOS tube 1110. The source of the first PMOS transistor 1101 is connected to a power supply, the gate of the first PMOS transistor 1101 is connected to the output module 13, the gate of the second PMOS transistor 1102 and the drain of the fourth PMOS transistor 1104 respectively, and the drain of the first PMOS transistor 1101 is connected to the source of the third PMOS transistor 1103; The source of the second PMOS transistor 1102 is connected to a power supply, and the drain of the second PMOS transistor 1102 is connected to the source of the fourth PMOS transistor 1104; The gate of the third PMOS transistor 1103 is connected to the output module 13, the gate of the fourth PMOS transistor 1104 and the drain of the second NMOS transistor 1108 respectively, the drain of the third PMOS transistor 1103 is connected to one end of the first resistor 1105 and the gate of the first NMOS transistor 1107 respectively; The drain of the fourth PMOS transistor 1104 is connected to one end of the second resistor 1106; The drain of the first NMOS transistor 1107 is connected to the other end of the first resistor 1105 and the gate of the third NMOS transistor 1109 respectively, the gate of the first NMOS transistor 1107 is connected to the gate of the second NMOS transistor 1108, the source of the first NMOS transistor 1107 is connected to the drain of the third NMOS transistor 1109; The drain of the second NMOS transistor 1108 is connected to the other end of the second resistor 1106, and the source of the second NMOS transistor 1108 is connected to the drain of the fourth NMOS transistor 1110; The gate of the third NMOS transistor 1109 is connected to the gate of the fourth NMOS transistor 1110, and the source of the third NMOS transistor 1109 is connected to the current adjusting module 12; The source of the fourth NMOS transistor 1110 is connected to the current adjusting module 12.

[0027] In the embodiments of the present disclosure, the first PMOS transistor 1101 and the second PMOS transistor 1102 constitute a current mirror structure, the gates of the first PMOS transistor 1101 and the second PMOS transistor 1102 are connected, the gate voltages of the two MOS transistors are the same, and the sources are connected to the power supply, so that if the sizes of the first PMOS transistor 1101 and the second PMOS transistor 1102 are the same and they work in the saturation region, the drain currents of the first PMOS transistor 1101 and the second PMOS transistor 1102 are the same. Similarly, the third PMOS transistor 1103 and the fourth PMOS transistor 1104 also constitute a corresponding current mirror structure.

[0028] And, the gate of the first PMOS transistor 1101 is connected with the gate of the second PMOS transistor 1102 and the drain of the fourth PMOS transistor 1104, forming a feedback structure. Assuming that the drain current of the fourth PMOS transistor 1104 becomes large, the drain voltage of the fourth PMOS transistor 1104 will decrease, thereby causing the absolute value of the gate voltage of the first PMOS transistor 1101 and the gate voltage of the second PMOS transistor 1102 to increase. The greater the absolute value of the gate voltage of the PMOS transistor, the greater the drain current, and the greater the current input to the source of the fourth PMOS transistor 1104, causing the drain voltage of the fourth PMOS transistor 1104 to rise, and the drain current to decrease. Similarly, when the drain current of the fourth PMOS transistor 1104 becomes small, the feedback structure can also prevent the drain current from decreasing. By feeding back the drain voltage of the fourth PMOS transistor 1104 to the gate of the first PMOS transistor 1101, a negative feedback loop is formed, which suppresses fluctuations in the circuit.

[0029] Further, the first NMOS transistor 1107 and the second NMOS transistor 1108, and the third NMOS transistor 1109 and the fourth NMOS transistor 1110 also form the same current mirror structure. Through the current mirror relationship, the source voltage of the third NMOS transistor 1109 and the source voltage of the fourth NMOS transistor 1110 can be clamped to the same value, which is output as a two-way bias voltage to the current regulation module 12.

[0030] In yet another embodiment of the present disclosure, as shown in Figure 2 The current regulation module 12 further comprises a third resistor 123; The collector of the first transistor 121 is connected with the bias voltage generation module 11, and the base of the first transistor 121 is connected with the emitter of the first transistor 121 and grounded. One end of the third resistor 123 is connected with the bias voltage generation module 11, and the other end of the third resistor 123 is connected with the collector of the second transistor 122. The base of the second transistor 122 is connected with the emitter of the second transistor 122 and grounded.

[0031] In the disclosed embodiment, both the first transistor 121 and the second transistor 122 may be PNP bipolar junction transistors (BJTs). They may be of the same type, but their emitter area ratios are set to a predetermined value. The first transistor 121 and the second transistor 122 each receive a bias voltage. Based on the emitter area ratio, a voltage difference is generated between the first transistor 121 and the second transistor 122. This voltage difference is solely dependent on temperature and the emitter area ratio, and further determines the current flowing through the third resistor 123. Since the forward voltage of a PNP triode junction transistor has a negative temperature coefficient, the voltage between the base and emitter of the first triode 121 and the second triode 122 also has a negative temperature coefficient. Basic deduction shows that the voltage difference between the first triode 121 and the second triode 122 has a positive temperature coefficient. Therefore, the voltage across the third resistor 123 has a positive temperature coefficient, and thus the current flowing through the third resistor 123 also has a positive temperature coefficient. The temperature coefficient can be determined by the area ratio of the emitters of the first triode 121 and the second triode 122.

[0032] According to the relationship between the base-emitter voltage and current of BJT, the base-emitter voltage of the transistor can be obtained. .in, is the thermovoltage, which is proportional to the absolute temperature; is the transistor collector current; is the reverse saturation current of the transistor. Then we can get the voltage difference between the base and emitter of the two transistors. .in, is the base-emitter voltage of the second transistor; is the base-emitter voltage of the second transistor; is the base-emitter voltage of the first transistor; is the emitter area ratio between the first transistor and the second transistor. The current of the third resistor (i.e., the first current) can be further obtained. ,in, According to the above formula, the magnitude of the first current is related to the resistance of the third resistor, temperature, and emitter area ratio. Therefore, when the resistor and transistor are fixed, the first current is proportional to the temperature and has a positive temperature coefficient.

[0033] In another embodiment provided by the present disclosure, Figure 1 As shown, the output module 13 includes: a fifth PMOS transistor 131 and a sixth PMOS transistor 132; The source of the fifth PMOS transistor 131 is connected to the power supply, the drain of the fifth PMOS transistor 131 is connected to the sixth PMOS transistor 132, and the gate of the fifth PMOS transistor 131 is connected to the bias voltage generating module 11; The gate of the sixth PMOS transistor 132 is connected to the bias voltage generating module 11 , and the drain of the sixth PMOS transistor 132 serves as the output end of the current source circuit to output the bias current.

[0034] In the embodiment of the present disclosure, the fifth PMOS transistor 131 can form a current mirror circuit with the second PMOS transistor 1102, and the sixth PMOS transistor 132 can form a current mirror circuit with the fourth PMOS transistor 1104 to mirror the first current to the output module 13 and output it as a bias current.

[0035] In another embodiment provided by the present disclosure, Figure 1 As shown, the temperature coefficient balancing circuit 2 includes: a fourth resistor 21 and a fifth resistor 22; One end of the fourth resistor 21 is connected to the collector of the first transistor 121 and is grounded, and the other end of the fourth resistor 21 is connected to the emitter of the first transistor 121; One end of the fifth resistor 22 is connected to one end of the third resistor 123 , and the other end of the fifth resistor 22 is connected to the collector of the second transistor 122 and is grounded.

[0036] In the embodiment of the present disclosure, the fourth resistor 21 is connected in parallel with the first transistor 121, and the fifth resistor 22 is connected in parallel with the branch formed by the third resistor 123 and the second transistor 122. Since the base-emitter voltage of the transistor has a negative temperature coefficient, the voltage across the fourth resistor 21 and the fifth resistor 22 also has a negative temperature coefficient. By adjusting the resistance values ​​of the fourth resistor 21 and the fifth resistor 22, two currents with negative temperature coefficients can be generated in the branch where the fifth resistor 22 is located, thereby reducing the positive temperature coefficient of the current of the third resistor 123, thereby achieving the purpose of adjusting the temperature coefficient. The current of the fifth resistor 22 ,in, is the resistance of the fifth resistor. It has negative temperature characteristics, so the current It also has negative temperature characteristics. By setting the resistance value of the fifth resistor, you can control The size of the first current is then adjusted to adjust the temperature coefficient of the first current.

[0037] In another embodiment provided by the present disclosure, Figure 1 As shown, the current source circuit further includes a starting circuit 3; The startup circuit 3 is used to generate an initial excitation input to the bias current generating circuit 1 when the current source circuit is powered on, so as to start the bias current generating circuit 1 .

[0038] In the embodiment of the present disclosure, the startup circuit 3 is used to provide an initial excitation signal to the bias current generating circuit 1, so as to break the zero current state in the bias current generating circuit 1, turn on the MOS tube in the bias current generating circuit 1, and establish the working current to enter a stable working state.

[0039] In another embodiment provided by the present disclosure, Figure 1 As shown, the startup circuit 3 includes: a seventh PMOS transistor 31, an eighth PMOS transistor 32, a fifth NMOS transistor 33, a sixth NMOS transistor 34, a seventh NMOS transistor 35, an eighth NMOS transistor 36 and a ninth NMOS transistor 37; The source of the seventh PMOS transistor 31 is connected to a power supply, the gate of the seventh PMOS transistor 31 is connected to the bias current generating circuit 1, and the drain of the seventh PMOS transistor 31 is connected to the drain of the fifth NMOS transistor 33 and the gate of the eighth PMOS transistor 32 respectively; The source of the eighth PMOS transistor 32 is connected to the power supply, and the drain of the eighth PMOS transistor 32 is connected to the bias current generating circuit 1; The gate of the fifth NMOS transistor 33, the gate of the sixth NMOS transistor 34, the gate of the seventh NMOS transistor 35, the gate of the eighth NMOS transistor 36 and the gate of the ninth NMOS transistor 37 are connected and grounded; The source of the fifth NMOS transistor 33 is connected to the drain of the sixth NMOS transistor 34; the source of the sixth NMOS transistor 34 is connected to the drain of the seventh NMOS transistor 35; the source of the seventh NMOS transistor 35 is connected to the drain of the eighth NMOS transistor 36; the source of the eighth NMOS transistor 36 is connected to the drain of the ninth NMOS transistor 37; and the source of the ninth NMOS transistor 37 is grounded.

[0040] In the disclosed embodiment, when the current source circuit is powered on, the seventh PMOS transistor 31 can form a current mirror structure with the first PMOS transistor 1101, the second PMOS transistor 1102, and the fifth PMOS transistor 131 to provide a startup circuit for each MOS transistor, breaking the zero-current state and enabling them to establish an initial current and enter normal operation. The eighth PMOS transistor 32 can provide a startup current at the drain of the third PMOS transistor 1103, establishing an initial current in the branch of the bias current generating circuit 1, further enabling the bias current generating circuit 1 to enter normal operation.

[0041] like Figure 4The following is a simulation comparison of the temperature coefficients of a conventional current source and the current source disclosed herein. The horizontal axis represents temperature in degrees Celsius (°C), while the vertical axis represents current in microamperes (μA). The upper curve shows the current versus temperature curve for the disclosed current source, while the lower curve shows the current versus temperature curve for the conventional current source. It can be seen that the slope of the current versus temperature curve for the disclosed current source is significantly lower than that for the conventional current source, indicating that the temperature coefficient of the disclosed current source is significantly lower than that of the conventional current source, demonstrating that the disclosed current source achieves its goal of regulating the temperature coefficient.

[0042] The present disclosure also provides a clock source circuit, such as Figure 5 As shown, it includes: a current source module 41, a first comparator module 42, a second comparator module 43 and a logic control module 44; The current source module 41 includes the current source circuit provided in any one of the above embodiments, and is configured to output bias current to the first comparator module 42 and the second comparator module 43 respectively; The first comparator module 42 includes: a first comparator 421, a first capacitor 422, and a first switch device 423; the first capacitor 422 is used to charge according to the bias current; the first comparator is used to compare the voltage of the first capacitor 422 with a reference voltage and output a first electrical signal according to the comparison result; the first switch device 423 is used to control the charging and discharging state of the first capacitor 422 according to the control signal output by the logic control module 44; The second comparator module 43 includes: a second comparator 431, a second capacitor 432, and a second switch device 433; the second capacitor 432 is used to charge according to the bias current; the second comparator is used to compare the voltage of the second capacitor 432 with a reference voltage and output a second electrical signal according to the comparison result; the second switch device 433 is used to control the charging and discharging state of the second capacitor 432 according to the control signal output by the logic control module 44; The logic control module 44 is used to shape the first electrical signal and the second electrical signal to obtain an oscillation waveform; and output a control signal according to a preset logic to control the first capacitor 422 and the second capacitor 432 to alternately charge and discharge.

[0043] In the embodiment of the present disclosure, Figure 5As shown, the logic control module 44 may include two NAND gates. The inputs of the first NAND gate 441 receive the output signal of the first comparator 421 and the output signal of the second NAND gate 442, respectively. The output of the first NAND gate 441 is connected to the first switch device 423. The inputs of the second NAND gate receive the output signal of the second comparator and the output signal of the first NAND gate 441, respectively. The output of the second NAND gate 442 is connected to the second switch device 433, forming a set-reset latch (SR latch) structure.

[0044] The bias current output by the current source circuit is input into the two comparator modules respectively. Assuming that in the initial state, the first capacitor 422 is charged and the second capacitor 432 is discharged, the first comparator outputs a high level and the second comparator outputs a low level. As the bias current charges the first capacitor 422, the voltage of the first capacitor 422 gradually rises. When the voltage of the first capacitor 422 rises to the reference voltage , the output level of the first comparator flips to a low level, and the output terminal of the first NAND gate 441 outputs a high level, turning on the first switch device 423 and discharging the first capacitor 422. At the same time, since the inputs of the second NAND gate 442 are both high, the second NAND gate 442 outputs a low level, turning off the second switch device 433, and the second capacitor 432 begins to charge. Until the voltage of the second capacitor 432 reaches the reference voltage, the output state of the second comparator flips, the second capacitor 432 begins to discharge, and the first capacitor 422 charges. By repeating the above process, a continuously oscillating signal can be output by the first NAND gate 441. Through the final buffer circuit in the logic control module 44, it can be output as a square wave to obtain a clock signal.

[0045] The final buffer circuit may include two stages of inverters and a high / low (H / L) output buffer 445. The first-stage inverter is implemented using a third NAND gate 443, one input of which receives a high level signal, and the other input is connected to the output of the first NAND gate 441, thereby inverting the signal output by the first NAND gate 441. The second-stage inverter is implemented using a NOT gate 444.

[0046] It should be noted that components such as capacitors in the clock source circuit also have temperature coefficients. By configuring the resistors and transistors in the current source, the temperature coefficients of the current source can be adjusted to match each other, thereby reducing the interference of temperature changes on the clock signal output by the clock source.

[0047] The present disclosure also provides a clock source generating device, comprising the clock source circuit in the above embodiment.

[0048] Through the above description of the embodiments, those skilled in the art will clearly understand that the embodiments of the present disclosure can be implemented through hardware or through software plus the necessary general-purpose hardware platform. Based on this understanding, the technical solutions of the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, or mobile hard drive) and includes a number of instructions for causing a computer device (such as a personal computer, server, or network device) to execute the methods described in the various embodiments of the present disclosure.

[0049] Those skilled in the art will understand that the accompanying drawings are merely schematic diagrams of a preferred embodiment, and the modules or processes in the accompanying drawings are not necessarily required for implementing the present disclosure.

[0050] Those skilled in the art will appreciate that the modules in the devices of the embodiments may be distributed in the devices of the embodiments as described in the embodiments, or may be located in one or more devices different from the embodiments with corresponding changes. The modules of the above embodiments may be combined into one module or further split into multiple submodules.

[0051] The serial numbers of the above-mentioned embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments.

[0052] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A current source circuit, characterized in that: include: Bias current generating circuit and temperature coefficient balancing circuit; The bias current generating circuit includes: a current regulating module and an output module; the bias current generating circuit is used to generate a bias current with a corresponding positive temperature coefficient; The current regulating module includes: a first transistor and a second transistor; the first transistor and the second transistor are two symmetrical transistors having a preset area ratio; the current regulating module is configured to adjust the bias voltage applied to the first transistor and the second transistor according to the preset area ratio to obtain a first current having a target current value; The output module is configured to obtain the first current and output it as a bias current; The temperature coefficient balancing circuit includes two resistors connected in parallel with the first transistor and the second transistor respectively; the temperature coefficient balancing circuit is used to generate a current with a negative temperature coefficient and adjust the temperature coefficient of the bias current in the bias current generating circuit.

2. The current source circuit according to claim 1, wherein: The bias current generating circuit further includes: a bias voltage generating module; The bias voltage generating module is used to convert the power supply voltage into two equal bias voltages and output them to the current regulating module.

3. The current source circuit according to claim 2, wherein: The bias voltage generating module includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first resistor, a second resistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor; The source of the first PMOS transistor is connected to a power supply, the gate of the first PMOS transistor is connected to the output module, the gate of the second PMOS transistor and the drain of the fourth PMOS transistor respectively, and the drain of the first PMOS transistor is connected to the source of the third PMOS transistor; The source of the second PMOS transistor is connected to a power supply, and the drain of the second PMOS transistor is connected to the source of the fourth PMOS transistor; The gate of the third PMOS transistor is respectively connected to the output module, the gate of the fourth PMOS transistor and the drain of the second NMOS transistor, and the drain of the third PMOS transistor is respectively connected to one end of the first resistor and the gate of the first NMOS transistor; The drain of the fourth PMOS tube is connected to one end of the second resistor; The drain of the first NMOS transistor is connected to the other end of the first resistor and the gate of the third NMOS transistor respectively, the drain and gate of the first NMOS transistor are connected to the gate of the second NMOS transistor, and the source of the first NMOS transistor is connected to the drain of the third NMOS transistor; The drain of the second NMOS transistor is connected to the other end of the second resistor, and the source of the second NMOS transistor is connected to the drain of the fourth NMOS transistor; The gate of the third NMOS tube is connected to the gate of the fourth NMOS tube, and the source of the third NMOS tube is connected to the current regulation module; The source of the fourth NMOS tube is connected to the current regulation module.

4. The current source circuit according to claim 2, wherein: The current regulating module further includes: a third resistor; The emitter of the first transistor is connected to the bias voltage generating module, and the base of the first transistor is connected to the collector of the first transistor and is grounded; One end of the third resistor is connected to the bias voltage generating module, and the other end of the third resistor is connected to the emitter of the second transistor; The base of the second transistor is connected to the collector of the second transistor and is grounded.

5. The current source circuit according to claim 2, wherein: The output module includes: a fifth PMOS tube and a sixth PMOS tube; The source of the fifth PMOS transistor is connected to a power supply, the drain of the fifth PMOS transistor is connected to the sixth PMOS transistor, and the gate of the fifth PMOS transistor is connected to the bias voltage generating module; The gate of the sixth PMOS transistor is connected to the bias voltage generating module, and the drain of the sixth PMOS transistor serves as the output end of the current source circuit to output the bias current.

6. The current source circuit according to claim 4, wherein: The temperature coefficient balancing circuit includes: a fourth resistor and a fifth resistor; One end of the fourth resistor is connected to the collector of the first transistor and is grounded, and the other end of the fourth resistor is connected to the emitter of the first transistor; One end of the fifth resistor is connected to one end of the third resistor, and the other end of the fifth resistor is connected to the collector of the second transistor and is grounded.

7. The current source circuit according to claim 1, wherein: Also included is a starting circuit; The startup circuit is used to generate an initial excitation input to the bias current generating circuit when the current source circuit is powered on, so as to start the bias current generating circuit.

8. The current source circuit according to claim 7, wherein: The startup circuit includes: a seventh PMOS transistor, an eighth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor and a ninth NMOS transistor; The source of the seventh PMOS transistor is connected to a power supply, the gate of the seventh PMOS transistor is connected to the bias current generating circuit, and the drain of the seventh PMOS transistor is connected to the drain of the fifth NMOS transistor and the gate of the eighth PMOS transistor respectively; The source of the eighth PMOS transistor is connected to a power supply, and the drain of the eighth PMOS transistor is connected to the bias current generating circuit; The gate of the fifth NMOS transistor, the gate of the sixth NMOS transistor, the gate of the seventh NMOS transistor, the gate of the eighth NMOS transistor and the gate of the ninth NMOS transistor are connected and grounded; The source of the fifth NMOS tube is connected to the drain of the sixth NMOS tube; the source of the sixth NMOS tube is connected to the drain of the seventh NMOS tube; the source of the seventh NMOS tube is connected to the drain of the eighth NMOS tube; the source of the eighth NMOS tube is connected to the drain of the ninth NMOS tube; and the source of the ninth NMOS tube is grounded.

9. A clock source circuit, characterized in that: include: A current source module, a first comparator module, a second comparator module and a logic control module; The current source module comprises the current source circuit according to any one of claims 1 to 8, and is configured to output bias current to the first comparator module and the second comparator module respectively; The first comparator module includes: a first comparator, a first capacitor, and a first switch device; the first capacitor is used to charge according to the bias current; the first comparator is used to compare the voltage of the first capacitor with a reference voltage and output a first electrical signal according to the comparison result; the first switch device is used to control the charging and discharging state of the first capacitor according to the control signal output by the logic control module; The second comparator module includes: a second comparator, a second capacitor, and a second switch device; the second capacitor is used to charge according to the bias current; the second comparator is used to compare the voltage of the second capacitor with a reference voltage and output a second electrical signal according to the comparison result; the second switch device is used to control the charging and discharging state of the second capacitor according to the control signal output by the logic control module; The logic control module is used to shape the first electrical signal and the second electrical signal to obtain an oscillation waveform; and output a control signal according to a preset logic to control the first capacitor and the second capacitor to alternately charge and discharge.

10. A clock source generating device, characterized in that: Includes the clock source circuit according to claim 9.

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