Fault simulation method and system of EtherCAT bus, storage medium and program product

Abstract

The invention provides an EtherCAT bus fault simulation method and system, a storage medium and a program product, and the method comprises the steps: receiving a fault injection request which comprises fault configuration information for fault simulation; wherein the fault configuration information is received through a preset fault configuration interface; and injecting a corresponding fault according to the fault configuration information contained in the received fault injection request so as to perform fault simulation. According to the scheme provided by the invention, various complex fault scenes can be flexibly simulated.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of control, and in particular to an EtherCAT bus fault simulation method, system, storage medium and program product. BACKGROUND

[0002] EtherCAT, as a high-speed real-time industrial Ethernet protocol, has been widely applied in the field of industrial automation. It is known for its high bandwidth, low latency and flexible topology structure, which can meet the needs of modern industrial control systems for efficient and reliable communication. EtherCAT protocol not only supports fast data transmission, but also enables synchronous operation between multiple devices, greatly improving production efficiency and system response speed.

[0003] However, although EtherCAT has many advantages, due to its complex network structure and high technical standards, EtherCAT networks are still prone to various faults during actual operation. These faults may be caused by a variety of factors, including physical layer cable damage, electrical interference, compatibility problems between devices, and software configuration errors. These faults not only may cause data transmission interruption, but also may affect the stability and safety of the entire system, and further cause production downtime and economic losses.

[0004] The fault detection and simulation methods in the related art can identify and locate some common faults to some extent, but when faced with complex and variable EtherCAT network environment, there are still many deficiencies. For example, the methods in the related art often rely on static fault models, which cannot comprehensively cover all possible fault scenarios; at the same time, many methods lack sufficient flexibility and accuracy in fault simulation, making it difficult to truly reproduce complex situations in the actual network. In addition, the fault detection means in the related art usually requires a long time and high cost, and in some cases may not be able to discover potential hidden dangers in time, resulting in the fault being discovered only after it occurs, increasing the difficulty and risk of system maintenance. SUMMARY

[0005] The main purpose of the present application is to overcome the defects of the above-mentioned related art, and to provide an EtherCAT bus fault simulation method, system, storage medium and program product, to solve the problem that the fault simulation method in the related art relies on static fault models and cannot comprehensively cover all possible fault scenarios.

[0006] The application provides a fault simulation method of an EtherCAT bus.

[0007] Optionally, the fault configuration information comprises: a target slave station of fault simulation, a fault type, and fault simulation configuration information; the fault type comprises at least one of a frame format or frame content error fault, a timeout fault, and a hardware fault.

[0008] Optionally, if the fault type is a frame format error or frame content error fault, the fault simulation configuration information comprises: error communication frame configuration information; injecting a corresponding fault according to the fault configuration information contained in the received fault injection request to perform fault simulation comprises: configuring a communication frame according to the error communication frame configuration information, and issuing the configured communication frame to a slave station control microprocessor to be sent through the EtherCAT bus.

[0009] Optionally, if the fault type is a timeout fault, the fault simulation configuration information comprises: a timeout time; injecting a corresponding fault according to the fault configuration information contained in the received fault injection request to perform fault simulation comprises: delaying a response according to the timeout time.

[0010] Optionally, if the fault type is a hardware fault, the fault simulation configuration information comprises: hardware error configuration information; the hardware error configuration information comprises: load resistance mismatch and / or open circuit; injecting a corresponding fault according to the fault configuration information contained in the received fault injection request to perform fault simulation comprises: if the hardware error configuration information is load resistance mismatch, performing fault simulation by controlling a hardware relay to disconnect and / or connect a different load resistance; and / or, if the hardware error configuration information is open circuit fault, performing fault simulation by controlling a hardware relay to disconnect and / or connect a physical bus.

[0011] Optionally, if the fault type is a protocol stack error fault, the fault simulation configuration information comprises: an error protocol rate; injecting a corresponding fault according to the fault configuration information contained in the received fault injection request to perform fault simulation comprises: switching to a protocol stack of a corresponding network protocol rate according to the error protocol rate to simulate a network protocol rate error.

[0012] Optionally, further comprising: receiving, by the user interface, an instruction to import a preset fault configuration and / or export a current fault configuration; importing the preset fault configuration from an external storage medium and / or exporting the current fault configuration to the external storage medium according to the instruction.

[0013] In another aspect, the application provides a fault simulation system of an EtherCAT bus, comprising: a logic control processor, a slave control microprocessor, an EtherCAT slave controller and a physical layer device; the logic control processor is configured to receive a fault injection request, wherein the fault injection request comprises fault configuration information for fault simulation; and inject corresponding faults according to the fault configuration information contained in the received fault injection request to perform fault simulation; and the slave control microprocessor, the EtherCAT slave controller and the physical layer device are configured to implement the functions of an EtherCAT slave station.

[0014] Optionally, the fault configuration information comprises: a target slave station for fault simulation, a fault type and fault simulation configuration information; and the fault type comprises at least one of a frame format or frame content error fault, a timeout fault and a hardware fault.

[0015] Optionally, if the fault type is a frame format error or frame content error fault, the fault simulation configuration information comprises error communication frame configuration information; and the logic control processor, according to the fault configuration information contained in the received fault injection request, injects corresponding faults to perform fault simulation, which comprises: configuring a communication frame according to the error communication frame configuration information, and issuing the configured communication frame to the slave control microprocessor to be sent through the EtherCAT bus.

[0016] Optionally, if the fault type is a timeout fault, the fault simulation configuration information comprises a timeout time; and the logic control processor, according to the fault configuration information contained in the received fault injection request, injects corresponding faults to perform fault simulation, which comprises: delaying the response according to the timeout time.

[0017] Optionally, if the fault type is a hardware fault, the fault simulation configuration information comprises hardware error configuration information; the hardware error configuration information comprises: a load resistance mismatch and / or a disconnection; and the logic control processor, according to the fault configuration information contained in the received fault injection request, injects corresponding faults to perform fault simulation, which comprises: if the hardware error configuration information is a load resistance mismatch, disconnecting and / or connecting different load resistances through a hardware relay to perform fault simulation; and / or, if the hardware error configuration information is a disconnection fault, disconnecting and / or connecting a physical bus through a hardware relay to perform fault simulation.

[0018] Optionally, if the fault type is a protocol stack error fault, the fault simulation configuration information includes an error protocol rate; and the logic control processor injects a corresponding fault according to the fault configuration information contained in the received fault injection request to perform fault simulation, including switching to a protocol stack of a corresponding network protocol rate according to the error protocol rate to simulate a network protocol rate error.

[0019] In yet another aspect, the present application provides a storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the preceding methods.

[0020] In yet another aspect, the present application provides a computer program product comprising a computer program, which, when executed by a processor, implements the steps of any of the preceding methods.

[0021] According to the technical solution of the present application, a dynamic fault simulation mechanism is adopted, which can flexibly simulate various complex fault scenarios. This dynamic simulation method can more realistically reflect the actual fault conditions in the EtherCAT network, improving the comprehensiveness and accuracy of fault detection.

[0022] According to the technical solution of the present application, through the precise fault injection mechanism, various fault phenomena can be realistically reproduced during simulation, not only improving the accuracy of simulation, but also allowing flexible adjustment of fault parameters according to different testing requirements, ensuring a high degree of credibility of the simulation results.

[0023] According to the technical solution of the present application, through the optimized algorithm and efficient hardware configuration, the time required for fault detection is greatly reduced, and the workload of manual troubleshooting is reduced. Not only does this reduce the maintenance cost of the system, but it also improves the efficiency of fault diagnosis.

[0024] The technical solution of the present application adopts modular design, making the system easy to integrate into existing EtherCAT networks, while also facilitating future functional expansion. This flexibility enables the system to adapt to industrial automation environments of different scales and complexities.

[0025] The fault detection methods in the related art usually require a long time and high cost. In some cases, it may be necessary to manually check each node and line one by one, resulting in a time-consuming and laborious fault diagnosis process, increasing the difficulty and risk of system maintenance.

[0026] The technical solution of the present application can improve the accuracy and efficiency of fault detection, reduce the maintenance cost of the system, and ensure the stable operation of industrial automation. BRIEF DESCRIPTION OF DRAWINGS

[0027] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

[0028] Figure 1 is a method schematic diagram of one embodiment of the fault simulation method of the EtherCAT bus provided by the application;

[0029] Figure 2 a system block diagram of the fault simulation system of the application is shown;

[0030] Figure 3 a structure and logic relationship block diagram of the hardware part of the fault simulation system of the application is shown;

[0031] Figure 4 the overall architecture of the system of the application is shown;

[0032] Figure 5 the EtherCAT frame format is shown;

[0033] Figure 6 one example of the fault configuration interface according to the application is shown;

[0034] Figure 7 is a method schematic diagram of one specific embodiment of the fault simulation method of the EtherCAT bus provided by the application. DETAILED DESCRIPTION

[0035] In order to make the objects, technical solutions and advantages of the application clearer, the technical solutions of the application will be described clearly and completely below in combination with specific embodiments of the application and corresponding drawings. Obviously, the described embodiments are only some of the embodiments of the application, but not all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the application.

[0036] It should be noted that the terms "first", "second" and the like in the specification and claims of the application and the above-described drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not necessarily have to include only those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to the process, method, product or device.

[0037] The EtherCAT bus fault detection and simulation methods in the related art have the following problems:

[0038] Limitations of static fault models: Most of the fault detection methods in the related art are based on static fault models, which cannot comprehensively cover all possible fault scenarios. These static models are difficult to adapt to the changing dynamic environment in the EtherCAT network, resulting in some potential faults that cannot be discovered in time.

[0039] Insufficient simulation accuracy: The fault simulation methods in the related art often lack sufficient accuracy and flexibility when simulating complex faults. This makes the real fault scenarios simulated in the laboratory environment differ greatly from the actual network, reducing the effectiveness of fault detection.

[0040] High cost and time consumption: The fault detection methods in the related art usually require a long time and high cost. In some cases, it may be necessary to manually check each node and line one by one, resulting in a time-consuming and laborious fault diagnosis process, increasing the difficulty and risk of system maintenance.

[0041] The present application provides a fault simulation method for an EtherCAT bus. The method of the present application can be implemented in any EtherCAT slave station. A logic control processor, specifically a logic control chip, is added to the EtherCAT slave station to control the EtherCAT slave station to execute the fault simulation method of the present application through the logic control chip.

[0042] Figure 1 is a method schematic diagram of an embodiment of the fault simulation method for an EtherCAT bus provided by the present application.

[0043] As shown in Figure 1 According to one embodiment of the present application, the fault simulation method includes at least steps S110 and S120.

[0044] Step S110, receiving a fault injection request.

[0045] Step S120, injecting a corresponding fault according to the fault configuration information contained in the received fault injection request to perform fault simulation.

[0046] The fault injection request contains fault configuration information for fault simulation. The fault configuration information can be received through a pre-set fault configuration interface.

[0047] The present application can include a software part and a hardware part, the software part including an upper computer (software) and a lower computer (software), and the hardware part including a logic control processor and an EtherCAT slave station, the EtherCAT slave station including a slave station control microprocessor, an EtherCAT slave station controller and a physical layer device.

[0048] The upper computer (software) is configured to receive the fault configuration information through a preset fault configuration interface, generate a fault injection request according to the received fault configuration information, and send the fault injection request to the lower computer (logic).

[0049] The lower computer (software) is configured to receive the fault injection request sent by the upper computer, and inject a corresponding fault according to the fault configuration information contained in the received fault injection request, so as to perform fault simulation.

[0050] The present application can be implemented as a fault simulation system or a fault simulator.

[0051] Figure 2 A system block diagram of the fault simulation system of the present application is shown. Figure 2 As shown, the hardware part implements both communication and control application functions, including a logic control processor, a slave station control microprocessor, an EtherCAT slave station controller and a physical layer device. Figure 3 A structure and logic relationship block diagram of the hardware part of the fault simulation system of the present application is shown. Figure 3 As shown, the EtherCAT slave station controller is responsible for processing data frames and data exchange; the slave station control microprocessor processes communication and control tasks; the physical layer device mainly includes a PHY chip and an isolation transformer, which ensures stable connection of the physical layer; and the logic control processor (logic control chip) performs fault simulation according to fault injection instructions, such as simulating a communication fault frame or other electrical faults.

[0052] The lower computer software runs on the logic control processor and is responsible for bottom layer control and data processing, mainly including fault injection, and can also include data acquisition and communication management. The upper computer software can run on a PC and provide a user interface as well as data analysis, real-time monitoring and fault simulation control. The upper computer (software) communicates with the lower computer (logic) through a TCP communication protocol, realizing centralized management and control of the entire system. When no fault is injected, the present system can be used as a slave station or a repeater.

[0053] Figure 4 A system overall architecture of the present application is shown. Figure 4As shown, the system can be divided into application layer, logic layer and physical layer. The application layer contains the host computer user control software for operating and monitoring the entire system. This is the user interface layer, which provides various control and management functions. Through the host computer software, fault configuration can be performed, for example, including frame format or frame content error simulation, timeout fault simulation, protocol content fault simulation and physical fault simulation. The application layer interacts with the logic layer through TCP network port communication.

[0054] The logic layer contains multiple sub-modules, including frame format error simulation, timeout fault simulation, protocol content fault simulation and physical fault simulation. These modules are used to simulate different types of faults to test the reliability of the system. The logic layer interacts with the monitoring module through TCP network port communication. The monitoring module is used to monitor all data on the EtherCAT bus and return to the logic layer in real time, which is returned to the application layer by the logic layer for user monitoring or processing.

[0055] The physical layer mainly involves EtherCAT slave controller, PHY chip and isolation transformer and other Ethernet physical layer devices. The EtherCAT bus is used to transmit data at the physical layer, ensuring high-speed and reliable data communication.

[0056] The hardware part of the fault simulation system of the present application includes:

[0057] EtherCAT slave controller: responsible for processing EtherCAT data frames, and using a dual-port memory area to realize data exchange between the EtherCAT master and the local application of the slave.

[0058] Slave control microprocessor: processes EtherCAT communication and completes control tasks. The microprocessor reads control data from the EtherCAT slave controller, implements device control functions, and samples feedback data from the device, which is written into the EtherCAT slave controller and read by the master.

[0059] Physical layer devices: including standard Ethernet physical layer devices, mainly including PHY chip and isolation transformer.

[0060] Logic control processor (logic control chip): cooperates with the slave control microprocessor, responsible for receiving host computer instructions, simulating communication fault frames or other electrical faults according to the instructions, and then injecting errors. The slave computer logic runs on the logic control chip (such as STM32, etc.), which is mainly responsible for the logic processing of the configured faults.

[0061] In one embodiment, the fault configuration information can specifically include: slave address to be simulated, fault type, and fault simulation configuration information; wherein the fault type can specifically include at least one of frame format or frame content error fault, timeout fault, and hardware fault.

[0062] Specifically, the corresponding fault is injected according to different fault types and fault simulation configuration information to perform fault simulation. The user can configure the fault through the fault configuration interface of the host computer. For example, Figure 6 An example of the fault configuration interface according to the present application is shown. As Figure 6 shown, the slave address to be simulated can be input in the fault configuration interface (the master station distinguishes different slave stations through different addresses, so each slave station on the bus has its own address), and the corresponding fault configuration is performed in the corresponding tab.

[0063] The fault simulation can include the following cases, for example:

[0064] (1) If the fault type is frame format or frame content error fault, the fault simulation configuration information includes: error communication frame configuration information. Correspondingly, the communication frame is configured according to the error communication frame configuration information, and the configured communication frame is sent to the slave station control microprocessor to be sent through the EtherCAT bus. The slave station control microprocessor sends the configured communication frame to the EtherCAT slave station controller to control the EtherCAT slave station controller to send the configured communication frame through the EtherCAT bus.

[0065] Figure 5 An EtherCAT frame format is shown. Figure 6 An example of the fault configuration interface is shown. The frame format error configuration is performed through the fault configuration interface of the PC (host computer software). Figure 5 The meanings of each field on the EtherCAT bus are shown. The specific error setting interface is as Figure 6As shown, users can freely modify the meaning of various fields on the EtherCAT bus to simulate different types of bus errors. For example, to modify the EtherCAT frame header, select the "EtherCAT Header" tab and select the fields to be modified (multiple selections are supported). Next, enter the desired fault value in the "Fault Value" column and enable the corresponding fields for fault injection. For example, to simulate an error in the address segment of a sub-message header, modify the row for the address segment in the tab list as follows: Enable: Yes; Inject Fault: Yes; then enter the desired fault value in the "Fault Value" column. For example, if the correct address value is "0x0123" and you want to send this data frame to the incorrect address "0xFFFF", enter "0xFFFF" in the "Fault Value" column. After completing the changes, click the "Send" button on the right, and the system will respond with the incorrect address.

[0066] (2) If the fault type is a timeout fault, the fault simulation configuration information includes: a timeout period; accordingly, a delayed response is performed according to the timeout period.

[0067] Specifically, according to the timeout period, the slave control microprocessor controls the EtherCAT slave controller to delay the response. For example, when a timeout fault needs to be simulated, Figure 6 Enter the timeout time (in microseconds) in the "Is it timed out (us)" column in the tab shown. When the host computer specifies that the fault type is a timeout fault, the timeout time passed in by the host computer controls the EtherCAT slave station to return a response frame after a delay of a period of time to determine the system's handling of the timeout error. The response frame refers to a reply to an instruction issued by the master station controller. The fault simulation system of the present invention is developed based on the EtherCAT bus and follows the master-slave communication mode of EtherCAT, that is, the master station controls the slave station action. The fault simulation system of the present invention is essentially a controllable simulation of the slave station, which injects various types of errors on the bus by simulating faults and detects the master station's handling of the errors.

[0068] Generating the corresponding response frame is one of the basic functions of an EtherCAT slave. The protocol implementation in an EtherCAT slave usually relies on an EtherCAT Slave Controller (ESC). The ESC is responsible for handling the specific details of the EtherCAT communication protocol, including receiving, parsing, processing, and sending data frames.

[0069] (3) If the fault type is a hardware fault, the fault simulation configuration information includes: hardware error configuration information; the hardware error configuration information includes: load resistance mismatch and / or open circuit; accordingly, if the hardware error configuration information is a load resistance mismatch, fault simulation is performed by controlling the hardware relay to disconnect and / or connect different load resistances; and / or, if the hardware error configuration information is an open circuit fault, fault simulation is performed by disconnecting and / or connecting a physical bus.

[0070] Specifically, the load resistance mismatch and / or open circuit can be configured in the hardware fault tab of the tabs shown. Figure 6 The hardware relay is controlled to disconnect, connect different load resistances, or disconnect, connect a physical bus by a button to achieve fault simulation of the hardware circuit.

[0071] (4) If the fault type is a protocol stack error fault, the fault simulation configuration information includes: an error protocol rate; accordingly, a protocol stack with a corresponding network protocol rate is switched according to the error protocol rate to simulate a network protocol rate error.

[0072] Specifically, the protocol stack of the network chip can be switched by a button to achieve switching between "100 Mbps", "Gigabit Ethernet", or "auto-negotiation rate" protocol stacks. If a slave station with a mismatched rate is connected to the bus, it may cause jitter or disconnection, so it is necessary to simulate a protocol stack error.

[0073] Optionally, the method further includes: receiving an instruction to import a preset fault configuration and / or export a current fault configuration through a user interface; importing the preset fault configuration from an external storage medium and / or exporting the current fault configuration to the external storage medium according to the instruction.

[0074] For example, as shown in Figure 4 The preset fault configuration can be imported and the current fault configuration can be exported through the "import preset" and "export configuration" functions on the host computer interface, so that the user can easily save and import the existing fault configuration, thereby facilitating repeated use and management.

[0075] When the application is implemented as a fault simulator or a fault simulation system, it can be connected to any position on the EtherCAT bus as a slave station. After starting all slave stations, the normal communication configuration is imported into the fault simulator, and then the master station is configured. At this time, the user interface can be configured according to the desired fault simulation. After the configuration is issued, it can be observed whether the feedback and processing mechanism of the entire system to the fault meet the expectations. In addition, it can also enter the monitoring interface to view the data on the EtherCAT bus and analyze the impact of the fault on the bus data.

[0076] To clearly illustrate the technical solution of the present invention, the execution flow of the fault simulation method for the EtherCAT bus provided by the present invention is described below with reference to a specific embodiment.

[0077] Figure 7 FIG. 1 is a schematic diagram of a method for simulating a fault of an EtherCAT bus according to a specific embodiment of the present invention. Figure 7 As shown, the user configures necessary EtherCAT slave information, such as PDOs (data frames that the slave must return according to the master's instructions when communicating with the master), and determines whether a fault injection is required. If not, the system operates according to the correct configuration. If a fault injection is required, the fault type is first determined. If it is a frame format or content fault, the system responds with a specified fault frame. If it is a delayed fault, the system responds with a delayed response frame. If it is a hardware fault, the system controls the hardware to simulate a hardware fault. The information is then sent to the slave control microprocessor, which determines whether the fault should be maintained. If not, the configured fault is cleared, and the process ends.

[0078] The present invention also provides a fault simulation system for an EtherCAT bus.

[0079] The fault simulation system may specifically include a logic control processor, a slave control microprocessor, an EtherCAT slave controller, and physical layer components. The logic control processor is configured to receive a fault injection request containing fault configuration information for performing fault simulation; and to inject a corresponding fault based on the fault configuration information contained in the received fault injection request to perform fault simulation. The slave control microprocessor, EtherCAT slave controller, and physical layer components are configured to implement the functionality of an EtherCAT slave.

[0080] Figure 3 The structure and logic relationship block diagram of the hardware part of the fault simulation system are shown in FIG. Figure 3 As shown in the figure, the EtherCAT slave controller is responsible for processing data frames and data exchange; the slave control microprocessor handles communication and control tasks; the physical layer devices include the PHY chip and isolation transformer to ensure stable connection of the physical layer; the logic control processor (logic control chip) performs fault simulation according to the fault injection instructions, such as simulating communication fault frames or other electrical faults.

[0081] The fault simulation system of the present invention comprises a software component and a hardware component. The software component comprises a host computer (software) and a slave computer (software). The hardware component comprises a logic control processor, a slave control microprocessor, an EtherCAT slave controller, and physical layer devices. The host computer (software) is configured to receive fault configuration information via a preset fault configuration interface, generate a fault injection request based on the received fault configuration information, and send the fault injection request to the slave computer (logic). The host computer software can be implemented on a computer device, such as a PC.

[0082] The lower computer (software) is used to receive the fault injection request sent by the upper computer and inject the corresponding fault according to the fault configuration information contained in the received fault injection request to perform fault simulation. The lower computer software can be implemented in a logic control processor.

[0083] More specifically, the present invention is implemented as a fault simulation system which may include a software part and a hardware part. Figure 2 FIG. 1 shows a system block diagram of the fault simulation system of the present invention. Figure 2 As shown, the hardware implements both communication and control application functions, including a logic control processor, a slave control microprocessor, an EtherCAT slave controller, and physical layer components. The slave software runs on the logic control processor and is responsible for low-level control and data processing, primarily including fault injection, but also data acquisition and communication management. The host software, which runs on a PC, provides a user interface, data analysis, real-time monitoring, and fault simulation control. The host (software) communicates with the slave (logic) via the TCP protocol, enabling centralized management and control of the entire system. When not injecting faults, this system can function as a general slave or repeater.

[0084] Figure 4 The overall system architecture of the present invention is shown. Figure 4 As shown, the system can be divided into application layer, logical layer and physical layer.

[0085] The application layer contains the host computer user control software, used to operate and monitor the entire system. This is the user interface layer, providing various control and management functions. This host computer software enables fault configuration, including simulation of at least one of frame format or content errors, timeout faults, protocol content faults, and physical faults. The application layer exchanges data with the logic layer via TCP network communication.

[0086] The logic layer includes a plurality of sub-modules, including frame format error simulation, timeout fault simulation, protocol content fault simulation, and physical fault simulation. These modules are used to simulate different types of faults to test the reliability of the system. The logic layer communicates with the monitoring module through the TCP network interface to exchange data. The monitoring module is used to monitor all data on the EtherCAT bus and return it to the logic layer in real time, which is returned to the application layer by the logic layer for user monitoring or processing.

[0087] The physical layer mainly involves EtherCAT slave controller, PHY chip, isolation transformer and other Ethernet physical layer devices. The EtherCAT bus is used to transmit data at the physical layer to ensure high-speed and reliable data communication.

[0088] The hardware part of the fault simulation system of the application includes:

[0089] EtherCAT slave controller: responsible for processing EtherCAT data frames, and using a dual-port memory area to realize data exchange of EtherCAT master and slave local applications.

[0090] Slave control microprocessor: processes EtherCAT communication and completes control tasks. The microprocessor reads control data from the EtherCAT slave controller, realizes device control functions, and samples the feedback data of the device, which is written into the EtherCAT slave controller and read by the master station.

[0091] Physical layer devices: including standard Ethernet physical layer devices, mainly including PHY chip and isolation transformer.

[0092] Logic control processor (logic control chip): cooperates with the slave control microprocessor, is responsible for receiving host computer instructions, simulating communication fault frames or other electrical faults according to the instructions, and then injecting errors. The lower computer logic runs on the logic control chip (such as STM32, etc.), which is mainly responsible for the logic processing of the configured faults.

[0093] In one specific embodiment, the fault configuration information can specifically include: the slave address to be simulated, the fault type, and the fault simulation configuration information; wherein the fault type can specifically include at least one of frame format or frame content error fault, timeout fault, and hardware fault.

[0094] The logic control processor injects corresponding faults according to different fault types and fault simulation information to perform fault simulation. The user can configure faults through the fault configuration interface of the host computer. For example, Figure 6 An example of a fault configuration interface according to the application is shown. As Figure 6As shown, the slave station address to be simulated can be input in the fault configuration interface (the master station distinguishes different slave stations by different addresses, so each slave station on the bus has its own address), and the corresponding fault configuration is performed in the corresponding tab.

[0095] The fault simulation may, for example, include the following cases:

[0096] (1) If the fault type is frame format or frame content error fault, the fault simulation configuration information includes error communication frame configuration information. Correspondingly, a communication frame is configured according to the error communication frame configuration information, and the configured communication frame is sent to the slave station control microprocessor for transmission through the EtherCAT bus. The slave station control microprocessor sends the configured communication frame to the EtherCAT slave station controller, and controls the EtherCAT slave station controller to transmit the configured communication frame through the EtherCAT bus.

[0097] Figure 5 An EtherCAT frame format is shown. Figure 6 An example of a fault configuration interface is shown. The frame format error configuration is performed through the fault configuration interface of the PC end (upper computer software).

[0098] Figure 5 The meanings of various fields on the EtherCAT bus are shown. A specific error setting interface is shown in Figure 6 As shown, the user can freely change the meanings of various fields on the EtherCAT bus to simulate different types of bus errors. For example, if the EtherCAT frame header needs to be changed, the “EtherCAT header” tab is selected, and the field to be modified (multiple selection is supported) is selected in the tab. Then, the fault value to be injected is input in the “fault value” column, and the corresponding field is enabled to inject the fault. For example, to simulate the value error of the address segment in the sub-message header, the line of the address segment in the tab list can be modified as follows: whether to enable: yes; whether to inject a fault: yes; then fill in the fault value to be simulated in the “fault value”, for example, the correct address value is “0x0123”, and the data frame is intended to be sent to the wrong address “0xFFFF”, so “0xFFFF” is filled in the “fault value”. After completing the modification, the right “send” button is clicked, and the system replies with the error address.

[0099] (2) If the fault type is a timeout fault, the fault simulation configuration information includes a timeout time; correspondingly, delayed response is performed according to the timeout time.

[0100] Specifically, according to the timeout time, the EtherCAT slave station controller is controlled by the slave station control microprocessor to perform delayed response. For example, when a timeout fault needs to be simulated, the “timeout time” can be input in the “fault configuration” interfaceFigure 6 The timeout time (in microseconds) is input in the "us" column of the tab shown. When the host computer specifies the fault type as a timeout fault, the timeout time transmitted by the host computer is used to control the EtherCAT slave station to return a response frame after a delay, so as to judge the system's handling of the timeout error. The response frame refers to a reply to the instruction issued by the master controller. The fault simulation system of the application is developed based on the EtherCAT bus and follows the master-slave communication mode of EtherCAT, that is, the master station controls the action of the slave station. The fault simulation system of the application is essentially a controllable simulation of the slave station, which injects various types of errors on the bus through simulation faults, and detects the handling of the master station to the errors.

[0101] Generating a corresponding response frame is one of the basic functions of the EtherCAT slave station. The protocol implementation in the EtherCAT slave station usually depends on the EtherCAT slave controller (ESC). The ESC is responsible for handling the specific details of the EtherCAT communication protocol, including the reception, parsing, processing, and sending of data frames.

[0102] (3) If the fault type is a hardware fault, the fault simulation configuration information includes: hardware error configuration information; the hardware error configuration information includes: load resistance mismatch and / or open circuit; accordingly, if the hardware error configuration information is load resistance mismatch, fault simulation is performed by controlling the hardware relay to disconnect and / or connect different load resistances; and / or, if the hardware error configuration information is open circuit fault, fault simulation is performed by disconnecting and / or connecting the physical bus.

[0103] Specifically, load resistance mismatch and / or open circuit can be realized by Figure 6 The configuration is performed in the hardware fault tab of the tab shown. The hardware relay is controlled to disconnect, connect different load resistances, or disconnect, connect the physical bus by buttons, to realize fault simulation of the hardware circuit.

[0104] (4) If the fault type is a protocol stack error fault, the fault simulation configuration information includes: error protocol rate; accordingly, according to the error protocol rate, the protocol stack of the corresponding network protocol rate is switched to simulate the network protocol rate error.

[0105] Specifically, the protocol stack of the network chip can be switched by buttons to realize switching between "100 Mbps", "Gigabit Ethernet", or "auto-negotiation rate" protocol stacks. If a slave station with a mismatched rate is connected to the bus, it may cause jitter or disconnection, so it is necessary to simulate the protocol stack error.

[0106] When the application is implemented as a fault simulator or a fault simulation system, it can be connected to any position on the EtherCAT bus as a slave station. After starting all slave stations, the normal communication configuration is imported into the fault simulator, and then the master station is configured. At this time, the configuration can be performed on the user interface according to the desired simulated fault. After the configuration is issued, it can be observed whether the feedback and processing mechanism of the entire system to the fault meet the expectations. In addition, the monitoring interface can be entered to view the data on the EtherCAT bus and analyze the influence of the fault on the bus data.

[0107] The application also provides a storage medium corresponding to the fault simulation method of the EtherCAT bus, which stores a computer program, and the program is executed by a processor to realize the steps of any of the preceding methods.

[0108] The application also provides a computer program product corresponding to the fault simulation method of the EtherCAT bus, which includes a computer program, and the computer program is executed by a processor to realize the steps of any of the preceding methods.

[0109] Accordingly, the scheme provided by the application adopts a dynamic fault simulation mechanism, which can flexibly simulate various complex fault scenarios. This dynamic simulation method can more realistically reflect the actual fault conditions in the EtherCAT network, improving the comprehensiveness and accuracy of fault detection.

[0110] The scheme provided by the application can reproduce various fault phenomena in the simulation process through an accurate fault injection mechanism, not only improving the simulation accuracy, but also flexibly adjusting the fault parameters according to different test requirements to ensure the high credibility of the simulation results.

[0111] The scheme provided by the application greatly shortens the time required for fault detection and reduces the workload of manual troubleshooting through an optimized algorithm and efficient hardware configuration. Not only does it reduce the maintenance cost of the system, but also improves the efficiency of fault diagnosis.

[0112] The scheme provided by the application adopts modular design, making the system easy to integrate into existing EtherCAT networks, and also facilitating future functional expansion. This flexibility enables the system to adapt to industrial automation environments of different scales and complexities.

[0113] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transferred over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope and spirit of the disclosure and appended claims. For example, due to the nature of software, functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations. Also, as used herein, including in the claims, "or" as used in a list of items prefaced by "comprising" to indicate a disjunctive list means each single item in the list has been recited before "or" one or more additional disjunctive items also have been recited. However, "or" in such a phrase does not mean that the list is inclusive of at least one of the items. Further, as used herein, "comprising" is to be interpreted as including the more restrictive terms "consisting of" and "consisting essentially of."

[0114] In several embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. Among them, the above-mentioned device embodiments are only schematic, for example, the division of the units can be a logical function division, and other division manners can be used in actual implementation, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed units can be indirect coupling or communication connection through some interfaces, units or modules, which can be electrical or other forms.

[0115] The units described as separate components can or can not be physically separated, and the components of the control device can or can not be physical units, i.e. can be located in one place or can be distributed on a plurality of units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0116] The integrated unit, if implemented in the form of a software function unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the part that contributes to the related art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, including a plurality of instructions to make a computer device (which can be a personal computer, a server or a network device, etc.) execute all or part of the steps of the method described in various embodiments of the present application. The aforementioned storage medium includes: a U disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store program codes.

[0117] The above merely illustrates the embodiments of the present application but should not be taken as limitations. Various changes and modifications can be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the scope of claims of the present application.

Claims

1. A fault simulation method for an EtherCAT bus, used for any EtherCAT slave station, characterized in that: include: Receive a fault injection request, wherein the fault injection request includes fault configuration information for performing fault simulation; wherein the fault configuration information is received through a preset fault configuration interface; A corresponding fault is injected according to the fault configuration information included in the received fault injection request to perform fault simulation.

2. The method according to claim 1, characterized in that The fault configuration information includes: a target slave station for fault simulation, a fault type, and fault simulation configuration information; The fault type includes at least one of a frame format or frame content error fault, a timeout fault, and a hardware fault.

3. The method according to claim 1, characterized in that If the fault type is a frame format error or a frame content error fault, the fault simulation configuration information includes: error communication frame configuration information; Injecting a corresponding fault according to the fault configuration information included in the received fault injection request to perform fault simulation includes: The communication frame is configured according to the erroneous communication frame configuration information, and the configured communication frame is sent to the slave station control microprocessor to be sent through the EtherCAT bus.

4. The method according to claim 1, wherein If the fault type is a timeout fault, the fault simulation configuration information includes: a timeout period; Injecting a corresponding fault according to the fault configuration information included in the received fault injection request to perform fault simulation includes: A delayed response is performed according to the timeout period.

5. The method according to claim 1, wherein If the fault type is a hardware fault, the fault simulation configuration information includes: hardware error configuration information; the hardware error configuration information includes: load resistance mismatch and / or open circuit; Injecting a corresponding fault according to the fault configuration information included in the received fault injection request to perform fault simulation includes: If the hardware error configuration information is load resistance mismatch, fault simulation is performed by controlling the hardware relay to disconnect and / or connect different load resistors; and / or, If the hardware error configuration information is a circuit breaker fault, the fault simulation is performed by controlling the hardware relay to disconnect and / or connect the physical bus.

6. The method according to claim 1, characterized in that If the fault type is a protocol stack error fault, the fault simulation configuration information includes: an error protocol rate; Injecting a corresponding fault according to the fault configuration information included in the received fault injection request to perform fault simulation includes: According to the error protocol rate, a protocol stack of a corresponding network protocol rate is switched to simulate a network protocol rate error.

7. The method according to claim 1, characterized in that Also includes: receiving, through the user interface, an instruction to import a preset fault configuration and / or export a current fault configuration; Import a preset fault configuration from an external storage medium and / or export a current fault configuration to an external storage medium according to the instructions.

8. A fault simulation system for an EtherCAT bus, characterized in that: include: Logic control processor, slave control microprocessor, EtherCAT slave controller and physical layer devices; The logic control processor is configured to receive a fault injection request, wherein the fault injection request includes fault configuration information for performing fault simulation; Injecting a corresponding fault according to the fault configuration information included in the received fault injection request to perform fault simulation; The slave station control microprocessor, EtherCAT slave station controller and physical layer device are used to realize the function of the EtherCAT slave station.

9. The fault simulation system according to claim 8, characterized in that: The fault configuration information includes: a target slave station for fault simulation, a fault type, and fault simulation configuration information; The fault type includes at least one of a frame format or frame content error fault, a timeout fault, and a hardware fault.

10. The fault simulation system according to claim 8, characterized in that: If the fault type is a frame format error or a frame content error fault, the fault simulation configuration information includes: error communication frame configuration information; The logic control processor injects a corresponding fault according to the fault configuration information included in the received fault injection request to perform fault simulation, including: The communication frame is configured according to the erroneous communication frame configuration information, and the configured communication frame is sent to the slave station control microprocessor to be sent through the EtherCAT bus.

11. The fault simulation system according to claim 8, characterized in that: If the fault type is a timeout fault, the fault simulation configuration information includes: a timeout period; The logic control processor injects a corresponding fault according to the fault configuration information included in the received fault injection request to perform fault simulation, including: A delayed response is performed according to the timeout period.

12. The fault simulation system according to claim 8, characterized in that: If the fault type is a hardware fault, the fault simulation configuration information includes: hardware error configuration information; the hardware error configuration information includes: load resistance mismatch and / or open circuit; The logic control processor injects a corresponding fault according to the fault configuration information included in the received fault injection request to perform fault simulation, including: If the hardware error configuration information is load resistance mismatch, fault simulation is performed by controlling the hardware relay to disconnect and / or connect different load resistors; and / or, If the hardware error configuration information is a circuit breaker fault, the fault simulation is performed by controlling the hardware relay to disconnect and / or connect the physical bus.

13. The fault simulation system according to claim 8, characterized in that: If the fault type is a protocol stack error fault, the fault simulation configuration information includes: an error protocol rate; The logic control processor injects a corresponding fault according to the fault configuration information included in the received fault injection request to perform fault simulation, including: According to the error protocol rate, a protocol stack of a corresponding network protocol rate is switched to simulate a network protocol rate error.

14. A storage medium, characterized in that A computer program is stored thereon, and when the program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

15. A computer program product, characterized in that The invention comprises a computer program, which implements the steps of the method according to any one of claims 1 to 7 when the computer program is executed by a processor.

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