Cache of artificial intelligence chip and operation method thereof

Abstract

The invention provides a cache of an artificial intelligence chip and an operation method of the cache so as to efficiently execute a management operation command for the cache. The cache includes a command table and a hit-miss check unit. The hit-miss check unit is coupled to the command table. In response to one of the plurality of computing cores transmitting the management operation command to the cache, the hit-miss checking unit registers the management operation command in the command table in place of execution of the management operation command. In response to one of the plurality of computing cores transmitting the access request to the cache, the hit-miss check unit also executes the management operation command registered in the command table during execution of the access request.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of Artificial Intelligence (AI) chip, and in particular, to a cache of an AI chip and an operation method thereof. BACKGROUND

[0002] By sending a management operation command to the cache, an operation device such as an AI chip, a Graphics Processing Unit (GPU), and a General-Purpose GPU (GPGPU) can implement a management operation on the cache, such as an invalidate operation or some operation of modifying a priority. These management operations are operations on the entire cache, and in a multi-kernel parallel system, a management operation command issued by a certain kernel affects cache lines being used by other kernels. In addition, when executing a management operation command for the entire cache, if the command information is actually written to a Tag RAM, it is necessary to update each set once. If the number of sets is large, the latency of the management operation command will be large. How to implement the cache is one of many technical issues in the field. SUMMARY

[0003] The present disclosure provides a cache of an AI chip and an operation method thereof to efficiently execute a management operation command on the cache.

[0004] In an embodiment according to the present disclosure, the cache includes a command table and a hit-miss check unit. The hit-miss check unit is coupled to the command table. In response to one of the plurality of compute cores sending a management operation command to the cache, the hit-miss check unit registers the management operation command in the command table without executing the management operation command temporarily. In response to one of the plurality of compute cores sending an access request to the cache, the hit-miss check unit executes the management operation command registered in the command table in the process of executing the access request.

[0005] In an embodiment according to the present disclosure, the operation method includes: in response to one of the plurality of compute cores sending a management operation command to the cache, registering, by a hit-miss check unit of the cache, the management operation command in a command table of the cache without executing the management operation command temporarily; and in response to one of the plurality of compute cores sending an access request to the cache, executing, by the hit-miss check unit, the management operation command registered in the command table in the process of executing the access request.

[0006] Based on the above, in some embodiments, the cache is configured with a command table. A certain computing core sends a management operation command to the cache, and the cache registers the management operation command in the command table without executing the management operation command temporarily. Thus, the management operation command is executed efficiently for the command sending computing core. In response to a certain computing core sending an access request to the cache, the cache executes the access request and also executes the management operation command registered in the command table in the process of executing the access request. For the cache, the execution of the access request and the execution of the management operation command registered in the command table can be performed simultaneously. Thus, the execution of the management operation command does not affect the efficiency of the cache in executing the access request. In this way, the cache can efficiently execute the management operation command for the cache.

[0007] In embodiments according to the present disclosure, the cache includes a tag array and a hit-miss checking unit. The tag array includes a plurality of tag sets. Each of the plurality of tag sets includes a plurality of tags. Each of the plurality of tags is used to store corresponding cache line information. Each of the plurality of tags further includes a kernel identifier field. The kernel identifier field is used to distinguish which computing core is using the current cache line (i.e., the kernel identifier field is used to distinguish the computing core using the current cache line). The hit-miss checking unit is coupled to the tag array. In response to a command sending computing core of the plurality of computing cores sending a management operation command to the cache, the hit-miss checking unit iteratively operates on each of the plurality of tag sets to execute the management operation command. The iterative operation includes: the hit-miss checking unit reading a current tag set of the plurality of tag sets from the tag array; the hit-miss checking unit checking the kernel identifier field of each of the plurality of tags of the current tag set to select a target tag corresponding to the command sending computing core from the plurality of tags of the current tag set; in response to the current tag set having the target tag corresponding to the command sending computing core, the hit-miss checking unit executing the management operation command on the target tag corresponding to the command sending computing core, and the hit-miss checking unit not executing the management operation command on the remaining tags of the current tag set; in response to the current tag set not having the target tag corresponding to the command sending computing core, the hit-miss checking unit not executing the management operation command on the current tag set; and the hit-miss checking unit writing the current tag set back to the tag array.

[0008] In an embodiment according to the present disclosure, the operation method comprises: in response to a command sending computing core sending a management operation command to the cache, a hit-miss checking unit of the cache iteratively operates each of a plurality of tag groups of a tag array of the cache to execute the management operation command. Each of the plurality of tag groups comprises a plurality of tags. Each of the plurality of tags is used to store corresponding cache line information. Each of the plurality of tags further comprises a core identifier field. The core identifier field is used to distinguish which computing core is currently using the cache line. The iterative operation comprises: reading a current tag group from the plurality of tag groups from the tag array; checking the core identifier field of each of the plurality of tags of the current tag group to select a target tag corresponding to the command sending computing core from the plurality of tags of the current tag group; in response to the current tag group having the target tag corresponding to the command sending computing core, executing the management operation command on the target tag corresponding to the command sending computing core and not executing the management operation command on the remaining tags in the current tag group; in response to the current tag group not having the target tag corresponding to the command sending computing core, not executing the management operation command on the current tag group; and writing the current tag group back to the tag array.

[0009] Based on the above, in another embodiment, each tag of the tag array of the cache is configured with a core identifier field to refine the granularity of the management operation. When the computing core sends a management operation command to the cache, the cache only executes the management operation command on the target tag corresponding to the command sending computing core in the tag array and does not execute the management operation command on the remaining tags in the tag array. Accordingly, in a multi-core parallel system, the management operation command issued by a certain computing core does not affect the cache lines being used by other computing cores, and the cache can efficiently execute the management operation command on the cache. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a circuit block schematic diagram of an artificial intelligence chip according to an embodiment of the present disclosure; Figure 2 is a schematic diagram of a tag array according to an embodiment; Figure 3 is a schematic diagram of a tag array according to an embodiment of the present disclosure; Figure 4 is a flowchart schematic diagram of an operation method of a cache according to an embodiment of the present disclosure; Figure 5 is a circuit block schematic diagram of an artificial intelligence chip according to another embodiment of the present disclosure; Figure 6 is a flowchart schematic diagram of an operation method of a cache according to another embodiment of the present disclosure; Figure 7is a schematic diagram of a command table illustrated in accordance with an embodiment of the present disclosure; Figure 8 is a schematic diagram of a command table illustrated in accordance with another embodiment of the present disclosure.

[0011] BRIEF DESCRIPTION OF THE DRAWINGS

[0012] 100, a first artificial intelligence chip, 500, a second artificial intelligence chip, 110, a first compute core, 510, a second compute core, 120, a first cache, 520, a second cache, 121, a first hit-miss check unit, 521, a second hit-miss check unit, 122, a first tag array, 200, a second tag array, 300, a third tag array, 522, a fourth tag array, 123, a first operation engine, 523, a second operation engine, 124, a first cache line array, 524, a second cache line array, 130, a first main memory, 530, a second main memory, 210_1, a first_1 tag group, 210_2, a first_2 tag group, 210_c, a first_c tag group, 310_1, a second_1 tag group, 310_2, a second_2 tag group, 310_c, a second_c tag group, 525, a first command table, 700, a second command table, 800, a third command table, 710_1, a first_1 group command graph, 710_2, a first_2 group command graph, 710_c, a first_c group command graph, 810_1, a second_1 group command graph, 810_2, a second_2 group command graph, 810_c, a second_c group command graph, 811_1, a first core command graph, 811_2, 2nd core command map, 811_n, n* core command map, cmd_1, 1st command enable bit, cmd_2, 2nd command enable bit, cmd_m, m* command enable bit, tag2_1, 1st_1 tag, tag2_2, 1st_2 tag, tag2_d, 1st_d tag, tag3_1, 2nd_1 tag, tag3_2, 2nd_2 tag, tag3_d, 2nd_d tag. DETAILED DESCRIPTION

[0013] Reference will now be made in detail to the exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the various drawing figures and the same or similar reference numbers will be used for similar or like parts.

[0014] The term "coupled (or connected) to" used in the detailed description of the present disclosure, both in the claims and / or in the accompanying drawings, can refer to either a direct connection, or an indirect connection via another device or means. For example, if a first device is coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or that the first device can be indirectly connected to the second device via other devices or means. The terms "first", "second", and the like used in the detailed description of the present disclosure, both in the claims and / or in the accompanying drawings, are used to name components (elements) or to distinguish different embodiments or ranges, and are not intended to limit the upper or lower limit of the number of components, nor the order of the components. In addition, wherever possible, the same reference numbers are used for the same components, members, steps in the drawings and embodiments. Components, members, steps using the same reference numbers or using the same terms in different embodiments can be referred to each other in the relevant description. It should be understood that the features of each of the following embodiments can be combined with each other. For example, the features of the second embodiment can be combined with the features of the first embodiment. Those skilled in the art can select the appropriate combination of features according to the actual design needs.

[0015] An operation device such as an artificial intelligence chip can provide tremendous computing power. The tremendous computing power of an artificial intelligence chip is derived from a large number of hardware cores inside. An artificial intelligence chip usually contains a plurality of programmable processors, for example, a stream processor cluster (SPC). Each programmable processor usually contains a plurality of compute units (CUs, or computing units), and each compute unit usually contains a plurality of execution units (EUs, or execution cores). The execution cores include at least one of a tensor core (Tcore), an integer (INT) core, a floating point (FP) core, and a vector core (Vcore), for example. By programming the organization of each compute unit, an artificial intelligence chip can support general-purpose computing, scientific computing, and neural network computing. The compute units of an artificial intelligence chip usually access data in the main memory through a cache, such as a last level cache (LLC). The following embodiments will illustrate various implementation examples of the cache.

[0016] Figure 1 Figure 1 is a circuit block diagram of an artificial intelligence chip according to an embodiment of the present disclosure. Figure 1 The first artificial intelligence chip 100 shown includes a plurality of first compute units 110, a first cache 120, and a first main memory 130. The number of first compute units 110 can be determined according to actual design and application. The first compute units 110 are also referred to as first computing units. Although not shown in the figure, each first compute unit 110 usually includes a plurality of execution units and a shared memory. Different execution units in the same compute unit can exchange data with each other through the shared memory. Figure 1 The first cache 120 is coupled between the first compute units 110 and the first main memory 130. The first cache 120 can be a last level cache or other cache of the first artificial intelligence chip 100. The first compute units 110 access data in the first main memory 130 through the first cache 120.

[0017] In the following embodiments, the first artificial intelligence chip 100 is taken as an example to illustrate the implementation examples of the cache. Figure 1In the illustrated embodiment, the first cache 120 includes a first hit-miss check unit 121, a first tag array 122, a first operation engine 123, and a first cache line array 124. Depending on different designs, in some embodiments, the implementation of at least one of the first hit-miss check unit 121 and the first operation engine 123 can be in the form of hardware circuit. In other embodiments, the implementation of at least one of the first hit-miss check unit 121 and the first operation engine 123 can be in the form of a combination of more than one of hardware, firmware, and software (i.e., program).

[0018] In terms of hardware, at least one of the first hit-miss check unit 121 and the first operation engine 123 can be implemented in the form of logic circuit on an integrated circuit. For example, the functions of at least one of the first hit-miss check unit 121 and the first operation engine 123 can be implemented in various logic blocks, modules, and circuits in one or more hardware controllers, microcontrollers, hardware processors, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), central processing units (CPUs), or other processing units. The functions of at least one of the first hit-miss check unit 121 and the first operation engine 123 can be implemented in hardware circuit, such as various logic blocks, modules, and circuits in an integrated circuit, using hardware description languages (e.g., Verilog HDL or VHDL) or other suitable programming languages.

[0019] In software or firmware form, the functions of at least one of the first hit-miss check unit 121 and the first operation engine 123 can be implemented as programming codes. For example, at least one of the first hit-miss check unit 121 and the first operation engine 123 can be implemented by using general programming languages (e.g., C, C++, or assembly language) or other suitable programming languages. The programming codes can be recorded or stored in a "non-transitory machine-readable storage medium". In some embodiments, the non-transitory machine-readable storage medium includes, for example, semiconductor memories and / or storage devices. An electronic device (e.g., a CPU, a hardware controller, a microcontroller, a hardware processor, or a microprocessor) can read and execute the programming codes from the non-transitory machine-readable storage medium, thereby implementing the functions of at least one of the first hit-miss check unit 121 and the first operation engine 123.

[0020] The first hit-miss check unit 121 is coupled to the first tag array 122 and the first compute core 110. The first tag array 122 includes a plurality of tag groups, and each tag group includes a plurality of tags. The first operation engine 123 is coupled to the first hit-miss check unit 121, the first cache line array 124, and the first main memory 130. The first cache line array 124 includes a plurality of cache lines. The plurality of cache lines of the first cache line array 124 one-to-one correspond to the plurality of tags of the first tag array 122. Each tag is used to store corresponding cache line information.

[0021] For example, Figure 2 is a schematic diagram of a tag array according to an embodiment. Figure 2 The illustrated second tag array 200 can be used as Figure 1 one of the implementation examples of the illustrated first tag array 122. In Figure 2In the illustrated embodiment, the second tag array 200 includes a plurality of tag sets (a first_1 tag set 210_1, a first_2 tag set 210_2,..., a first_c tag set 210_c). The number c of the first_1 tag set 210_1 to the first_c tag set 210_c can be determined according to actual design and application. Each of the first_1 tag set 210_1 to the first_c tag set 210_c includes a plurality of tags. For example, the first_1 tag set 210_1 includes a plurality of tags (a first_1 tag tag2_1, a first_2 tag tag2_2,..., a first_d tag tag2_d). The number d of the first_1 tag tag2_1 to the first_d tag tag2_d can be determined according to actual design and application. The other tag sets (the first_2 tag set 210_2 to the first_c tag set 210_c) other than the first_1 tag set 210_1 can refer to the related description of the first_1 tag set 210_1 and be analogized, and thus will not be described herein.

[0022] In Figure 2 In the illustrated embodiment, each of the first_1 tag tag2_1 to the first_d tag tag2_d includes a tag address field, a valid bit field, and a dirty bit field. Generally, the access request sent by the computing core carries a set address and a tag address. Please refer to Figure 1 With Figure 2 The first hit-miss check unit 121 takes out the corresponding tag set from the first tag array 122 (e.g., the second tag array 200) based on the set address, and then compares the tag address field of each tag in the corresponding tag set with the tag address carried in the access request. If the tag address field content of a certain tag matches the tag address carried in the access request, the first hit-miss check unit 121 determines that it is a "hit". In response to the first hit-miss check unit 121 determining that the access request of the first computing core 110 is a hit, the first operation engine 123 accesses the target cache line corresponding to the access request in the plurality of cache lines of the first cache line array 124. If the tag address field content of each tag does not match the tag address carried in the access request, the first hit-miss check unit 121 determines that it is a "miss". In response to the first hit-miss check unit 121 determining that the access request of the first computing core 110 is a miss, the first operation engine 123 accesses the first main memory 130.

[0023] The first artificial intelligence chip 100 can implement management operations, such as a clear operation or some priority modification operation, on the first cache 120 by sending a management operation command to the first cache 120. In response to a certain first computing core 110 sending a management operation command to the first cache 120, the first hit-miss check unit 121 iterates each of the plurality of tag groups of the first tag array 122 (for example, each of the first_1 tag group 210_1 to the first_c tag group 210_c of the second tag array 200) to execute the management operation command. The iteration operation includes: reading a certain tag group in the plurality of tag groups from the first tag array 122 as a current tag group; executing the management operation command (for example, a clear command) on each tag of the target tag group; and writing the current tag group back to the first tag array 122. Generally, the first tag array 122 is stored in a random access memory (RAM) of the first cache 120, and the random access memory is coupled to the first hit-miss check unit 121. When executing the management operation command for the entire first cache 120, if the command information is actually written to the tag memory, it needs to be updated once for each tag group. If the number of groups is large, the delay of the management operation command will be large. Furthermore, these management operations are operations on the entire first cache 120, and in a multi-core parallel system, the management operation command issued by a certain first computing core 110 will affect the cache lines being used by other cores.

[0024] Figure 3 is a schematic diagram of a tag array according to an embodiment of the present disclosure. Figure 3 The third tag array 300 shown can be used as Figure 1 one of the many embodiments of the first tag array 122. In Figure 3 In the embodiment shown, the third tag array 300 includes a plurality of tag groups (the second_1 tag group 310_1, the second_2 tag group 310_2, …, the second_c tag group 310_c). The number c of the second_1 tag group 310_1 to the second_c tag group 310_c can be determined according to actual design and application. Each of the second_1 tag group 310_1 to the second_c tag group 310_c includes a plurality of tags. For example, the second_1 tag group 310_1 includes a plurality of tags (the second_1 tag tag3_1, the second_2 tag tag3_2, …, the second_d tag tag3_d). The number d of the second_1 tag tag3_1 to the second_d tag tag3_d can be determined according to actual design and application. The other tag groups (the second_2 tag group 310_2 to the second_c tag group 310_c) other than the second_1 tag tag3_1 can refer to the related description of the second_1 tag tag3_1 and be analogized, and therefore will not be described again.Figure 3 The 3rd tag array 300, the 2nd_1 tag group 310_1 to the 2nd_c tag group 310_c, and the 2nd_1 tag tag3_1 to the 2nd_d tag tag3_d shown in FIG. 3 can refer to the related descriptions of the 1st tag array 122, the 1st_1 tag group 122_1 to the 1st_c tag group 122_c, and the 1st_1 tag tag1_1 to the 1st_d tag tag1_d shown in FIG. 2 and be analogized, and thus are not described herein again. Figure 2 The 2nd tag array 200, the 1st_1 tag group 210_1 to the 1st_c tag group 210_c, and the 1st_1 tag tag2_1 to the 1st_d tag tag2_d shown in FIG. 2 can refer to the related descriptions of the 1st tag array 122, the 1st_1 tag group 122_1 to the 1st_c tag group 122_c, and the 1st_1 tag tag1_1 to the 1st_d tag tag1_d shown in FIG. 1 and be analogized, and thus are not described herein again.

[0025] Unlike the embodiment shown in FIG. 1, Figure 2 the embodiment shown in FIG. 2, Figure 3 Each tag shown in FIG. 3 further includes a kernel identifier field. In response to a request sent by one of the plurality of 1st computing cores 110 using a corresponding cache line of the 1st cache line array 124 of the 1st cache 120, the 1st hit-miss check unit 121 places a kernel ID carried by the request into the kernel identifier field of a target tag of the plurality of tags of the 1st tag array 122 corresponding to the corresponding cache line. Thus, the kernel identifier field can be used to distinguish which computing core is using the current cache line.

[0026] Figure 4 FIG. 4 is a flowchart of an operation method of a cache according to an embodiment of the present disclosure. Please refer to Figure 1 , Figure 3 and Figure 4 In step S410, one of the plurality of 1st computing cores 110 sends a management operation command to the 1st cache 120. In response to the command sending computing core of the plurality of 1st computing cores 110 sending the management operation command to the 1st cache 120, the 1st hit-miss check unit 121 iterates each of the plurality of tag groups (e.g., each of the 2nd_1 tag group 310_1 to the 2nd_c tag group 310_c) to execute the management operation command (step S420). In Figure 4 In the embodiment shown in FIG. 4, the iteration operation includes steps S421 to S429.

[0027] In step S421, the 1st hit-miss check unit 121 reads one of the plurality of tag groups from the 1st tag array 122 as a current tag group (e.g., reads one of the 2nd_1 tag group 310_1 to the 2nd_c tag group 310_c from the 3rd tag array 300). In step S422, the 1st hit-miss check unit 121 checks the kernel identifier field of each of the plurality of tags of the current tag group to select a target tag from the plurality of tags of the current tag group corresponding to the command sending computing core.

[0028] In step S423, it is determined whether the current tag set has a target tag corresponding to the command sending computing core. In response to the current tag set having a target tag corresponding to the command sending computing core (the determination result of step S423 is "Yes"), the first hit-miss check unit 121 executes the management operation command on the target tag corresponding to the command sending computing core, and the first hit-miss check unit 121 does not execute the management operation command on the remaining tags in the current tag set (step S424). In response to the current tag set not having a target tag corresponding to the command sending computing core (the determination result of step S423 is "No"), the first hit-miss check unit 121 does not execute the management operation command on all tags in the current tag set (step S425).

[0029] After completing step S424 or step S425, in step S426, the first hit-miss check unit 121 writes the current tag set back to the first tag array 122 (for example, the third tag array 300). The first hit-miss check unit 121 determines whether the first tag array 122 has a next tag set that has not been processed. In step S427, it is determined whether the first tag array 122 has a next tag set that has not been processed. In response to the first tag array 122 having a next tag set that has not been processed (the determination result of step S427 is "Yes"), the first hit-miss check unit 121 selects the next tag set as the current tag set (step S428), and then returns to step S421. In response to the first tag array 122 not having a next tag set that has not been processed (the determination result of step S427 is "No"), the first hit-miss check unit 121 ends the iteration operation of the management operation command (step S429).

[0030] In summary, each tag of the first tag array 122 (for example, the third tag array 300) of the first cache 120 is configured with a core identifier field to refine the granularity of the management operation. When a management operation command is sent to the first cache 120 by a certain first computing core 110, the first cache 120 only executes the management operation command on the target tag corresponding to the command sending computing core, and does not execute the management operation command on the remaining tags in the first tag array 122. Accordingly, in a multi-computing core parallel system, the management operation command issued by a certain computing core does not affect the cache line being used by other computing cores, and the first cache 120 can efficiently execute the management operation command on the first cache 120.

[0031] Figure 5 is a circuit block schematic diagram of an artificial intelligence chip according to another embodiment of the present disclosure. Figure 5 The second artificial intelligence chip 500 shown includes a plurality of second computing cores 510, a second cache 520, and a second main memory 530.Figure 5 The second cache 520 shown includes a second hit-miss check unit 521 , a fourth tag array 522 , a second operation engine 523 , and a second cache line array 524 . Figure 5 The second artificial intelligence chip 500, the second computing core 510, the second cache 520, the second hit-miss check unit 521, the fourth tag array 522, the second operation engine 523, the second cache line array 524 and the second main memory 530 can be referred to. Figure 1 The related descriptions of the first artificial intelligence chip 100, the first computing core 110, the first cache 120, the first hit-miss check unit 121, the first tag array 122, the first operation engine 123, the first cache line array 124 and the first main memory 130 are shown and can be deduced by analogy, so they are not repeated here.

[0032] Different from Figure 1 The embodiment shown, Figure 5 The second artificial intelligence chip 500 further includes a first command table 525. A second hit-miss check unit 521 is coupled to the first command table 525. Generally speaking, the fourth tag array 522 is stored in a random access memory (RAM) of the second cache 520, and the RAM is coupled to the second hit-miss check unit 521. Figure 5 In the illustrated embodiment, the first command table 525 may be stored in a flip-flop (FF) array or other storage element array, and the flip-flop array (or other storage element array) is coupled to the second hit-miss check unit 521 .

[0033] Figure 6 This is a flow chart of a cache operation method according to another embodiment of the present disclosure. Figure 5 and Figure 6 In step S610, one of the plurality of second computing cores 510 sends a management operation command to the second cache 520. In response to the command-sending computing core among the plurality of second computing cores 510 sending the management operation command to the second cache 520, the second hit-miss check unit 521 registers the management operation command in the first command table 525 and temporarily does not execute the management operation command (step S620).

[0034] Figure 7 FIG. 2 is a schematic diagram of a command table according to an embodiment of the present disclosure. Figure 7 The second command table 700 shown can be used as Figure 5 One of many implementation examples of the first command table 525 is shown. Figure 7In the illustrated embodiment, the second command table 700 includes a plurality of set command maps, such as a first_1 set command map 710_1, a first_2 set command map 710_2,..., and a first_c set command map 710_c. The first_1 set command map 710_1 to the first_c set command map 710_c of the second command table 700 correspond one-to-one to the plurality of tag sets of the fourth tag array 522. Based on actual design and application, in some embodiments, Figure 2 The illustrated second tag array 200 can serve as one of the many embodiments of the fourth tag array 522. In other embodiments, Figure 5 The illustrated third tag array 300 can serve as one of the many embodiments of the fourth tag array 522. Figure 3 The illustrated fourth tag array 522 can serve as one of the many embodiments of the fourth tag array 522. Figure 5 The illustrated fourth tag array 522 can serve as one of the many embodiments of the fourth tag array 522.

[0035] Please refer to Figure 5 and Figure 7 Each of the first_1 set command map 710_1 to the first_c set command map 710_c includes a plurality of command enable bits (a first command enable bit cmd_1, a second command enable bit cmd_2,..., and an mth command enable bit cmd_m) for representing different management commands. For example (but not limited to), the first command enable bit cmd_1 can correspond to a clear operation command, and the other command enable bits (the second command enable bit cmd_2 to the mth command enable bit cmd_m) other than the first command enable bit cmd_1 can correspond to other different operation commands. The number m of the first command enable bit cmd_1 to the mth command enable bit cmd_m can be determined based on the number of types of management commands in an actual application scenario.

[0036] Suppose that the management operation command sent by the second computing core 510 to the second cache 520 is a clear operation command. The effect of this clear operation command includes that the second hit-miss check unit 521 will reset the valid bit field of all tags of the second tag array 200 to a logic "false", such as a logic value "0". Figure 2 The illustrated second tag array 200 can serve as one of the many embodiments of the fourth tag array 522. In other embodiments,

[0037] In detail, "the 2nd hit-miss check unit 521 registers the clear operation command in the 1st command table 525" means that the 1st command enable bit cmd_1 of each of the 1st_1 group command graph 710_1 to the 1st_c group command graph 710_c is set to logic "true", e.g. logic value "1". The 1st command enable bit cmd_1 of a certain group command graph is set to logic "true" indicates that the valid bit clear operation for a corresponding tag group in the 4th tag array 522 has not been performed. In response to the 2nd computing core 510 sending a management operation command to the 2nd cache 520, the 2nd hit-miss check unit 521 sets the target command enable bit corresponding to the management operation command in the 1st command enable bit cmd_1 to the mth command enable bit cmd_m of each of the 1st_1 group command graph 710_1 to the 1st_c group command graph 710_c. Assuming that the management operation command sent by the 2nd computing core 510 to the 2nd cache 520 is a clear operation command, and assuming that the 1st command enable bit cmd_1 of each of the 1st_1 group command graph 710_1 to the 1st_c group command graph 710_c corresponds to the clear operation command. In response to the 2nd computing core 510 sending the clear operation command to the 2nd cache 520, the 2nd hit-miss check unit 521 sets the target command enable bit (the 1st command enable bit cmd_1) of each of the 1st_1 group command graph 710_1 to the 1st_c group command graph 710_c to logic "true".

[0038] Please refer to Figure 5 、 Figure 6 and Figure 7 In step S630, one of the plurality of 2nd computing cores 510 sends an access request to the 2nd cache 520. In response to any one of the 2nd computing cores 510 sending an access request to the 2nd cache 520, the 2nd hit-miss check unit 521 performs a management operation command registered in the 1st command table 525 in the process of performing the access request (step S640). When the 2nd hit-miss check unit 521 receives an access request sent by any one of the 2nd computing cores 510, the 2nd hit-miss check unit 521 queries the target group command graph corresponding to the target tag group in the 1st_1 group command graph 710_1 to the 1st_c group command graph 710_c of the 1st command table 525 based on the target tag group of the access request.

[0039] Further, the 2nd hit-miss check unit 521 reads, from the 4th tag array 522, a target tag group among the plurality of tag groups (1st_1 tag group 210_1 to 1st_c tag group 210_c) in the 2nd calculation core 510 based on the access request. The 2nd hit-miss check unit 521 executes, on the target tag group, the management operation command registered in the 1st command table 525. The 2nd hit-miss check unit 521 executes the access request. After the execution of the access request by the 2nd hit-miss check unit 521 is completed, the 2nd hit-miss check unit 521 writes back the target tag group to the 4th tag array 522.

[0040] For example, assume that the 1st command enable bit cmd_1 of each of the 1st group command map 710_1 to the 1st c group command map 710_c corresponds to a clear operation command, and assume that the 1st command enable bit cmd_1 of each of the 1st group command map 710_1 to the 1st c group command map 710_c has been set to logic "true", and assume that the target tag group of the access request (the 1st 1 tag group 210_1) corresponds to the target group command map of the 1st 1 group command map 710_1. When the 2nd hit-miss check unit 521 receives an access request issued by any one of the 2nd computing cores 510, the 2nd hit-miss check unit 521 queries the target group command map (the 1st 1 group command map 710_1) based on the target tag group of the access request (the 1st 1 tag group 210_1). Because the target command enable bit (the 1st command enable bit cmd_1) of the target group command map (the 1st 1 group command map 710_1) is logic "true", the 2nd hit-miss check unit 521 can know that the valid bit field of the target tag group (the 1st 1 tag group 210_1) should be logic "false" (although the valid bit field of the 1st 1 tag group 210_1 is actually logic "true" at this time). At this time, the 2nd hit-miss check unit 521 performs the access request with the condition that "the valid bit field of the target tag group (the 1st 1 tag group 210_1) should be logic "false", and the 2nd hit-miss check unit 521 also performs the clear operation command registered in the 1st command table 525 on the target tag group (the 1st 1 tag group 210_1) in the process of performing the access request. That is, the 2nd hit-miss check unit 521 resets the valid bit field of all tags of the target tag group (the 1st 1 tag group 210_1) to logic "false". After the 2nd hit-miss check unit 521 completes the execution of the access request, the 2nd hit-miss check unit 521 writes the target tag group (the 1st 1 tag group 210_1) back to the 4th tag array 522. In response to the 2nd hit-miss check unit 521 performing the clear operation command registered in the 1st command table 525 on the target tag group (the 1st 1 tag group 210_1) in the 4th tag array 522, the 2nd hit-miss check unit 521 resets the target command enable bit (the 1st command enable bit cmd_1) corresponding to the clear operation command in the target group command map (the 1st 1 group command map 710_1) to logic "false".

[0041] In summary, the second cache 520 is configured with the first command table 525. When a second computing core 510 sends a management operation command to the second cache 520, the second cache 520 registers the management operation command in the first command table 525 but temporarily refrains from executing the management operation command. Therefore, for the command-sending computing core (the second computing core 510), the management operation command is efficiently executed. In response to an access request sent by a second computing core 510 to the second cache 520, the second cache 520 also executes the management operation command registered in the first command table 525 while executing the access request. For the second cache 520, the execution of the access request and the execution of the management operation command registered in the first command table 525 can occur simultaneously. Therefore, the execution of the management operation command does not affect the efficiency of the second cache 520 in executing the access request. Consequently, the second cache 520 can efficiently execute the cache management operation command.

[0042] Figure 8 is a schematic diagram of a command table according to another embodiment of the present disclosure. Figure 8 The third command table 800 shown can be used as Figure 5 One of many implementation examples of the first command table 525 is shown. Figure 7 In the illustrated embodiment, the third command table 800 includes a plurality of group command graphs, such as the 2_1st group command graph 810_1, the 2_2nd group command graph 810_2, ..., the 2_cth group command graph 810_c. The 2_1st group command graph 810_1 to the 2_cth group command graph 810_c of the third command table 800 correspond one-to-one to the plurality of tag groups of the fourth tag array 522. Based on actual design and application, in some embodiments, Figure 3 The third tag array 300 shown can be used as Figure 5 This is one of many exemplary implementations of the fourth tag array 522. In response to a request sent by one of the plurality of second computing cores 510 to use a corresponding cache line in the second cache 520, the second hit-miss check unit 521 places the core identifier (ID) included in the request into the core identifier field of the target tag corresponding to the corresponding cache line in one of the plurality of tag groups (e.g., tag groups 2_1 through 2_c, 310_c) in the fourth tag array 522. The core identifier field can be used to distinguish which computing core is currently using the cache line.

[0043] Please refer to Figure 3 、 Figure 5 and Figure 8Each of the 2_1st group of command figures 810_1 to the 2_cth group of command figures 810_c includes a plurality of core command figures. Take the 2_1st group of command figures 810_1 as an example, the rest of the group of command figures (the 2_2nd group of command figures 810_2 to the 2_cth group of command figures 810_c) can refer to the relevant description of the 2_1st group of command figures 810_1 and be analogized, and thus will not be described again. The 2_1st group of command figures 810_1 includes a plurality of core command figures (a 1st core command figure 811_1, a 2nd core command figure 811_2, …, an n-th core command figure 811_n). The core command figures (such as the 1st core command figure 811_1 to the n-th core command figure 811_n) in the same group of command figures (such as the 2_1st group of command figures 810_1) correspond to the plurality of 2nd computing cores 510 (it is assumed that the number of the 2nd computing cores 510 is n) in one-to-one. Each of the 1st core command figure 811_1 to the n-th core command figure 811_n includes a plurality of command enable bits (a 1st command enable bit cmd_1, a 2nd command enable bit cmd_2, …, an m-th command enable bit cmd_m) for representing different management commands. For example (but not limited to), the 1st command enable bit cmd_1 can correspond to a clear operation command, and the other command enable bits (the 2nd command enable bit cmd_2 to the m-th command enable bit cmd_m) other than the 1st command enable bit cmd_1 can correspond to other different operation commands. The number m of the 1st command enable bit cmd_1 to the m-th command enable bit cmd_m can be determined based on the number of the types of the management commands in the actual application scenario.

[0044] In response to a certain one of the second computing cores 510 sending a management operation command to the second cache 520, the second hit-miss check unit 521 selects a target core command graph corresponding to the command sending computing core (the second computing core 510) from the core command graphs (e.g., the first core command graph 811_1 to the n-th core command graph 811_n) of each of the second_1 group of command graphs 810_1 to the second_c group of command graphs 810_c, and the second hit-miss check unit 521 sets a target command enable bit corresponding to the management operation command to a logic "true" (e.g., a logic value of "1") in the target core command graph of each of the second_1 group of command graphs 810_1 to the second_c group of command graphs 810_c. For example, assume that the management operation command sent by a certain one of the second computing cores 510 to the second cache 520 is a clear operation command, that the target core command graph corresponding to the command sending computing core (the second computing core 510) is the first core command graph 811_1 in each of the second_1 group of command graphs 810_1 to the second_c group of command graphs 810_c, and that the command enable bit corresponding to the clear operation command is the first command enable bit cmd_1. In response to a certain one of the second computing cores 510 sending a clear operation command to the second cache 520, the second hit-miss check unit 521 selects the first core command graph 811_1 of each of the second_1 group of command graphs 810_1 to the second_c group of command graphs 810_c as the target core command graph corresponding to the command sending computing core (the second computing core 510), and the second hit-miss check unit 521 sets the target command enable bit (the first command enable bit cmd_1) in the target core command graph (the first core command graph 811_1) of each of the second_1 group of command graphs 810_1 to the second_c group of command graphs 810_c to a logic "true" (e.g., a logic value of "1"). The first command enable bit cmd_1 of a certain one of the core command graphs of a certain one of the group of command graphs being set to a logic "true" indicates that a valid bit clear operation for a tag corresponding to a computing core in a certain one of the corresponding tag groups of the fourth tag array 522 has not been performed.

[0045] Based on the group address carried by the access request of the certain second computing core 510, the second hit-miss check unit 521 reads the target tag group (e.g., the second_1 tag group 310_1) corresponding to the access request from the plurality of tag groups (the second_1 tag group 310_1 to the second_c tag group 310_c) of the third tag array 300. In addition, the second hit-miss check unit 521 obtains the plurality of command enable bits (the first command enable bit cmd_1 to the mth command enable bit cmd_m) of each target core command graph (e.g., the first core command graph 811_1 to the nth core command graph 811_n) in the group command graph (e.g., the second_1 group command graph 810_1) corresponding to the target tag group from the third command table 800. The second hit-miss check unit 521 determines which command sending computing core sends the management operation command based on the first command enable bit cmd_1 to the mth command enable bit cmd_m of different core command graphs in the first core command graph 811_1 to the nth core command graph 811_n (i.e., the management operation command registered in the third command table 800) from the plurality of second computing cores 510.

[0046] The second hit-miss check unit 521 checks the core identifier field of each tag of the target tag group to select the target tag corresponding to the command sending computing core from the plurality of tags of the target tag group. In response to the target tag group having the target tag corresponding to the command sending computing core, the second hit-miss check unit 521 executes the management operation command registered in the third command table 800 on the target tag corresponding to the command sending computing core, and the second hit-miss check unit 521 does not execute the management operation command registered in the third command table 800 on the remaining tags of the target tag group other than the target tag. In response to the target tag group not having the target tag corresponding to the command sending computing core, the second hit-miss check unit 521 does not execute the management operation command registered in the third command table 800 on the target tag group.

[0047] For example, assume that the target tag group (the 2_1 tag group 310_1) corresponds to the 2_1 group command map 810_1 in the 3rd command table 800, only the 1st command enable bit cmd_1 of the 1st core command map 811_1 in the target group command map (the 2_1 group command map 810_1) is logic "true", and other command enable bits in the target group command map (the 2_1 group command map 810_1) are all logic "false". The 2nd hit-miss check unit 521 can learn from the target group command map (the 2_1 group command map 810_1) that the clear operation command previously sent by the computing core corresponding to the 1st core command map 811_1 has not been executed for the target tag group (the 2_1 tag group 310_1). The 2nd hit-miss check unit 521 checks the core identifier field of each of the 2_1 tag tag3_1 to the 2_d tag tag3_d of the target tag group (the 2_1 tag group 310_1) to select the target tag corresponding to the command sending computing core from the plurality of tags (the 2_1 tag tag3_1 to the 2_d tag tag3_d) of the target tag group (the 2_1 tag group 310_1). Assume that the 2_1 tag tag3_1 is the target tag corresponding to the command sending computing core, the 2nd hit-miss check unit 521 executes the clear operation command (reset the valid bit field of the 2_1 tag tag3_1 to logic "false") for the target tag (the 2_1 tag tag3_1), and the 2nd hit-miss check unit 521 does not execute the clear operation command for the remaining tags (the 2_2 tag tag3_2 to the 2_d tag tag3_d) other than the target tag (the 2_1 tag tag3_1) in the target tag group (the 2_1 tag group 310_1). Assume that the core identifier field of all tags (the 2_1 tag tag3_1 to the 2_d tag tag3_d) of the target tag group (the 2_1 tag group 310_1) does not match the command sending computing core (i.e. in response to the target tag group (the 2_1 tag group 310_1) not having the target tag corresponding to the command sending computing core), the 2nd hit-miss check unit 521 does not execute the clear operation command for the target tag group (the 2_1 tag group 310_1).

[0048] While performing the operation of the preceding paragraph on the target tag group (the 2_1 tag group 310_1), the 2 hit-miss check unit 521 can also perform an access request. After the 2 hit-miss check unit 521 completes the execution of the access request, the 2 hit-miss check unit 521 writes the target tag group (the 2_1 tag group 310_1) back to the 3 tag array 300. In response to the 2 hit-miss check unit 521 executing a management operation command (e.g., a clear operation command) registered in the 3 command table 800 on the target tag group (the 2_1 tag group 310_1), the 2 hit-miss check unit 521 selects a target core command graph (e.g., the 1st core command graph 811_1) corresponding to the command sending computing core from the plurality of core command graphs (the 1st core command graph 811_1 to the nth core command graph 811_n) of the target group command graph (the 2_1 group command graph 810_1), and the 2 hit-miss check unit 521 resets a target command enable bit (e.g., the 1st command enable bit cmd_1) corresponding to the management operation command in the target core command graph (e.g., the 1st core command graph 811_1) of the target group command graph (the 2_1 group command graph 810_1).

[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than limit them; although the present disclosure has been described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A cache for an artificial intelligence chip, characterized in that: The cache includes: command table; and A hit-miss check unit is coupled to the command table, wherein In response to one of the plurality of computing cores sending a management operation command to the cache, the hit-miss check unit registers the management operation command in the command table and temporarily does not execute the management operation command; and In response to one of the plurality of computing cores sending an access request to the cache, the hit-miss check unit further executes the management operation command registered in the command table during execution of the access request.

2. The cache according to claim 1, wherein: The cache also includes: a tag array coupled to the hit-miss check unit, wherein the tag array includes a plurality of tag groups, each of the plurality of tag groups includes a plurality of tags, and each of the plurality of tags is used to store corresponding cache line information; The hit-miss check unit reads a target tag group corresponding to the access request from the tag array based on the access request; The hit-miss check unit executes the management operation command registered in the command table on the target tag group; The hit-miss check unit executes the access request; and After the hit-miss check unit completes executing the access request, the hit-miss check unit writes the target tag group back to the tag array.

3. The cache according to claim 2, wherein: The cache also includes: a flip-flop array coupled to the hit-miss check unit, wherein the command table is stored in the flip-flop array; and A random access memory is coupled to the hit-miss check unit, wherein the tag array is stored in the random access memory.

4. The cache according to claim 2, wherein: The command table includes a plurality of group command maps, the plurality of group command maps of the command table corresponding one-to-one to the plurality of tag groups of the tag array, each of the plurality of group command maps including a plurality of command enable bits for representing different management commands, and In response to one of the plurality of computing cores sending the management operation command to the cache, the hit-miss check unit sets a target command enable bit corresponding to the management operation command among the plurality of command enable bits in each of the plurality of group command maps.

5. The cache according to claim 4, wherein: The target tag group corresponds to a target group command graph among the plurality of group command graphs, and In response to the hit-miss check unit executing the management operation command registered in the command table on the target tag group, the hit-miss check unit resets the target command enable bit corresponding to the management operation command in the target group command map.

6. The cache according to claim 2, wherein: The cache also includes: a cache line array comprising a plurality of cache lines, wherein the plurality of cache lines of the cache line array correspond one-to-one to the plurality of tags of the tag array; and An operation engine is coupled to the hit-miss check unit and the cache line array, wherein: In response to the hit-miss check unit determining that the access request is a hit, the operation engine accesses a target cache line corresponding to the access request among the plurality of cache lines in the cache line array; and In response to the hit-miss check unit determining that the access request is a miss, the operation engine accesses the main memory.

7. The cache according to claim 1, wherein: The cache also includes: a tag array coupled to the hit-miss check unit, wherein the tag array includes a plurality of tag groups, each of the plurality of tag groups includes a plurality of tags, each of the plurality of tags is used to store corresponding cache line information, and each of the plurality of tags further includes a core identifier field, the core identifier field is used to distinguish which computing core is currently using the cache line; The hit-miss check unit reads a target tag group corresponding to the access request from the tag array based on the access request; The hit-miss check unit identifies a command-sending computing core that sends the management operation command from among the plurality of computing cores based on the management operation command registered in the command table; The hit-miss check unit checks the core identifier field of each of the plurality of tags of the target tag group to select a target tag corresponding to the command-issuing computing core from the plurality of tags of the target tag group; In response to the target tag corresponding to the command-issuing computing core existing in the target tag group, the hit-miss checking unit executes the management operation command registered in the command table on the target tag corresponding to the command-issuing computing core, and the hit-miss checking unit does not execute the management operation command registered in the command table on the remaining tags in the target tag group; In response to the target tag group not having the target tag corresponding to the command-issuing computing core, the hit-miss checking unit does not execute the management operation command registered in the command table on the target tag group; The hit-miss check unit executes the access request; and After the hit-miss check unit completes executing the access request, the hit-miss check unit writes the target tag group back to the tag array.

8. The cache according to claim 7, wherein: In response to a request sent by one of the multiple computing cores to use the corresponding cache line of the cache, the hit-miss check unit places the core identifier of the request in the core identifier field of the target tag corresponding to the corresponding cache line among the multiple tags.

9. The cache according to claim 7, wherein: The command table includes a plurality of group command maps, the plurality of group command maps of the command table correspond one-to-one to the plurality of tag groups of the tag array, each of the plurality of group command maps includes a plurality of core command maps, the plurality of core command maps in the same group command map correspond one-to-one to the plurality of computing cores, and each of the plurality of core command maps includes a plurality of command enable bits for representing different management commands; and In response to the command sending computing core sending the management operation command to the cache, the hit-miss check unit selects a target core command graph corresponding to the command sending computing core from the multiple core command graphs of each of the multiple group command graphs, and the hit-miss check unit sets the target command enable bit corresponding to the management operation command among the multiple command enable bits of the target core command graph of each of the multiple group command graphs.

10. The cache according to claim 9, wherein: The target tag group corresponds to a target group command graph among the plurality of group command graphs, and In response to the hit-miss check unit executing the management operation command registered in the command table on the target tag group, the hit-miss check unit selects the target core command graph corresponding to the command sending computing core from the multiple core command graphs of the target group command graph, and the hit-miss check unit resets the target command enable bit corresponding to the management operation command in the target core command graph of the target group command graph.

11. A method for operating a cache of an artificial intelligence chip, characterized in that: The operation method includes: In response to one of the plurality of computing cores sending a management operation command to the cache, a hit-miss check unit of the cache registers the management operation command in a command table of the cache and temporarily does not execute the management operation command, wherein the hit-miss check unit is coupled to the command table; and In response to one of the plurality of computing cores sending an access request to the cache, the hit-miss check unit executes the management operation command registered in the command table while executing the access request.

12. The operating method according to claim 11, characterized in that: The operation method further includes: The hit-miss check unit reads, based on the access request, a target tag group corresponding to the access request from a tag array of the cache memory among a plurality of tag groups in the tag array, wherein the tag array is coupled to the hit-miss check unit, each of the plurality of tag groups includes a plurality of tags, and each of the plurality of tags is used to store corresponding cache line information; executing, by the hit-miss check unit, the management operation command registered in the command table on the target tag group; executing the access request by the hit-miss checking unit; and After the hit-miss check unit completes executing the access request, the hit-miss check unit writes the target tag group back to the tag array.

13. The operating method according to claim 12, characterized in that: The operation method further includes: storing the command table in a flip-flop array of the cache, wherein the flip-flop array is coupled to the hit-miss check unit; and The tag array is stored in a random access memory of the cache, wherein the random access memory is coupled to the hit-miss check unit.

14. The operating method according to claim 12, characterized in that: The command table includes a plurality of group command maps, the plurality of group command maps of the command table corresponding one-to-one to the plurality of tag groups of the tag array, each of the plurality of group command maps including a plurality of command enable bits for representing different management commands, and the operating method further comprising: In response to one of the plurality of computing cores sending the management operation command to the cache, the hit-miss check unit sets a target command enable bit corresponding to the management operation command in the plurality of command enable bits of each of the plurality of group command maps.

15. The operating method according to claim 14, characterized in that: The target tag group corresponds to a target group command graph among the plurality of group command graphs, and the operation method further includes: In response to the hit-miss check unit executing the management operation command registered in the command table on the target tag group, the hit-miss check unit resets the target command enable bit corresponding to the management operation command in the target group command map.

16. The operating method according to claim 12, characterized in that: The operation method further includes: In response to the hit-miss check unit determining that the access request is a hit, an operation engine of the cache accesses a target cache line corresponding to the access request among a plurality of cache lines in a cache line array of the cache, wherein the plurality of cache lines in the cache line array correspond one-to-one to the plurality of tags in the tag array, and the operation engine is coupled to the hit-miss check unit and the cache line array; and In response to the hit-miss check unit determining that the access request is a miss, the operation engine accesses the main memory.

17. The operating method according to claim 11, characterized in that: The operation method further includes: The hit-miss check unit reads a target tag group corresponding to the access request from a tag array of the cache based on the access request, wherein the tag array is coupled to the hit-miss check unit, each of the plurality of tag groups includes a plurality of tags, each of the plurality of tags is used to store corresponding cache line information, and each of the plurality of tags further includes a core identifier field, wherein the core identifier field is used to distinguish which computing core is currently using the cache line; The hit-miss check unit identifies a command-sending computing core that sends the management operation command from the plurality of computing cores based on the management operation command registered in the command table; The hit-miss check unit checks the core identifier field of each of the plurality of tags in the target tag group to select a target tag corresponding to the command-issuing computing core from the plurality of tags in the target tag group; In response to the target tag corresponding to the command-issuing computing core existing in the target tag group, the hit-miss check unit executes the management operation command registered in the command table on the target tag corresponding to the command-issuing computing core, and the hit-miss check unit does not execute the management operation command registered in the command table on the remaining tags in the target tag group; In response to the target tag group not having the target tag corresponding to the command-issuing computing core, the hit-miss checking unit does not execute the management operation command registered in the command table on the target tag group; executing the access request by the hit-miss checking unit; and After the hit-miss check unit completes executing the access request, the hit-miss check unit writes the target tag group back to the tag array.

18. The operating method according to claim 17, characterized in that: The operation method further includes: In response to a request sent by one of the multiple computing cores to use the corresponding cache line of the cache, the hit-miss check unit places the core identifier of the request in the core identifier field of the target tag corresponding to the corresponding cache line among the multiple tags.

19. The operating method according to claim 17, characterized in that: The command table includes a plurality of group command maps, the plurality of group command maps of the command table correspond one-to-one to the plurality of tag groups of the tag array, each of the plurality of group command maps includes a plurality of core command maps, the plurality of core command maps in the same group command map correspond one-to-one to the plurality of computing cores, each of the plurality of core command maps includes a plurality of command enable bits for representing different management commands, and the operating method further includes: In response to the command sending computing core sending the management operation command to the cache, the hit-miss check unit selects a target core command graph corresponding to the command sending computing core from the multiple core command graphs of each of the multiple group command graphs, and the hit-miss check unit sets the target command enable bit corresponding to the management operation command among the multiple command enable bits of the target core command graph of each of the multiple group command graphs.

20. The operating method according to claim 19, characterized in that: The target tag group corresponds to a target group command graph among the plurality of group command graphs, and the operation method further includes: In response to the hit-miss check unit executing the management operation command registered in the command table on the target tag group, the hit-miss check unit selects the target core command graph corresponding to the command sending computing core from the multiple core command graphs of the target group command graph, and the hit-miss check unit resets the target command enable bit corresponding to the management operation command in the target core command graph of the target group command graph.

21. A cache of an artificial intelligence chip, characterized in that: The cache includes: A tag array, wherein the tag array includes a plurality of tag groups, each of the plurality of tag groups includes a plurality of tags, each of the plurality of tags is used to store corresponding cache line information, each of the plurality of tags further includes a core identifier field, and the core identifier field is used to distinguish which computing core is using the current cache line; and A hit-miss check unit is coupled to the tag array, wherein In response to a command sending computing core among the plurality of computing cores sending a management operation command to the cache, the hit-miss checking unit performs an iterative operation on each of the plurality of tag groups to execute the management operation command, and the iterative operation includes: The hit-miss check unit reads a current tag group among the plurality of tag groups from the tag array; The hit-miss check unit checks the core identifier field of each of the plurality of tags in the current tag group to select a target tag corresponding to the command-issuing computing core from the plurality of tags in the current tag group; In response to the target tag corresponding to the command-issuing computing core existing in the current tag group, the hit-miss check unit executes the management operation command on the target tag corresponding to the command-issuing computing core, and the hit-miss check unit does not execute the management operation command on the remaining tags in the current tag group; In response to the current tag group not having the target tag corresponding to the command-issuing computing core, the hit-miss checking unit does not execute the management operation command on the current tag group; and The hit-miss check unit writes the current tag set back to the tag array.

22. The cache according to claim 21, wherein: In response to a request sent by one of the multiple computing cores to use the corresponding cache line of the cache, the hit-miss check unit places the core identifier of the request in the core identifier field of the target tag corresponding to the corresponding cache line among the multiple tags.

23. A method for operating a cache of an artificial intelligence chip, characterized in that: The operation method includes: In response to a command sending computing core in the plurality of computing cores sending a management operation command to the cache, a hit-miss checking unit of the cache performs an iterative operation on each of a plurality of tag groups in a tag array of the cache to execute the management operation command, wherein each of the plurality of tag groups includes a plurality of tags, each of the plurality of tags is used to store corresponding cache line information, each of the plurality of tags also includes a core identifier field, the core identifier field is used to distinguish which computing core is currently using the cache line, and the iterative operation includes: reading a current tag group from the tag array; checking the core identifier field of each of the plurality of tags in the current tag group to select a target tag corresponding to the command-issuing computing core from the plurality of tags in the current tag group; In response to the presence of the target tag corresponding to the command-sending computing core in the current tag group, executing the management operation command on the target tag corresponding to the command-sending computing core, and not executing the management operation command on the remaining tags in the current tag group; In response to the current tag group not having the target tag corresponding to the command-sending computing core, not executing the management operation command on the current tag group; and Write the current tag set back to the tag array.

24. The operating method according to claim 23, characterized in that: The operation method further includes: In response to a request sent by one of the multiple computing cores to use the corresponding cache line of the cache, the core identifier of the request is placed in the core identifier field of the target tag corresponding to the corresponding cache line in the multiple tags.

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