Line parameter determination method and device in power supply scheme, equipment and storage medium

Abstract

The invention discloses a line parameter determination method and device in a power supply scheme, equipment and a storage medium. The method comprises the steps that module parameters of a target chip module are acquired; determining the incidence relation between the line spacing parameter and the line width parameter of the ground wire or the power line and the line voltage drop and the routing track utilization rate under the constraint of the module parameters; carrying out machine learning on the line voltage drop and the wiring track utilization rate along with changes of the line spacing parameter and the line width parameter to obtain a change rule model; and performing optimization iterative operation on the line spacing parameter and the line width parameter according to the change rule model to obtain an optimal line spacing parameter and an optimal line width of which the corresponding line voltage drop is smaller than a voltage drop threshold value and the line track utilization rate is smaller than a utilization rate threshold value, and taking the optimal line spacing parameter and the optimal line width as the line parameter of the power supply scheme of the target chip module. According to the invention, the time length and manpower consumed by the design of the power supply scheme are reduced to a great extent, and the design cost of the power supply scheme is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of chip circuit design, and in particular to a method, device, equipment and computer-readable storage medium for determining circuit parameters in a power supply solution. Background Art

[0002] In the field of semiconductor manufacturing technology, the power plan design of chip modules is crucial. The trade-off between the resources occupied by power lines, ground lines, and signal lines will directly affect the working performance of the chip modules.

[0003] Currently, the design of power supply solutions for chip modules typically involves referring to reference power supply solutions for corresponding process nodes provided by process manufacturers, relying on their own experience to determine various circuit parameters, and then using PI (Power Integrity) simulation tools to verify whether the power supply solution under these circuit parameters meets requirements in terms of voltage drop, electromigration, and other aspects. As long as the requirements are met, the power supply solution is considered complete. This power supply solution design approach is highly dependent on the designer's experience, and there may be significant differences between different designers. Power supply design is also a complex process involving a large number of parameters and design rules. Manually adjusting circuit parameters and design rules is very difficult and prone to omissions and errors. Therefore, conventional power supply solution design methods are often unable to complete the design efficiently and accurately when faced with large-scale and complex chip designs. PI simulation cycles are also long. If the PI simulation tool is required to verify different power supply solutions for the same chip module multiple times, the power supply solution design cycle will undoubtedly be extended and require more manpower investment. Summary of the Invention

[0004] The purpose of the present invention is to provide a method, device, equipment and computer-readable storage medium for determining line parameters in a power supply solution, which can simplify the design difficulty of the power supply solution in the chip module to a certain extent and reduce the design cycle and manpower investment of the power supply solution.

[0005] To solve the above technical problems, the present invention provides a method for determining line parameters in a power supply solution, comprising:

[0006] Get the module parameters of the target chip module;

[0007] Determine the correlation between the line spacing parameter and line width parameter of the ground line or power line and the line voltage drop and the utilization rate of the routing track under the constraints of the module parameters;

[0008] Based on the correlation, machine learning is performed on the variation patterns of the line voltage drop and the routing track utilization rate as the line spacing parameter and the line width parameter vary, to obtain a variation pattern model;

[0009] The line spacing parameters and the line width parameters are optimized iteratively according to the change law model to obtain the optimal line spacing parameters and optimal line width corresponding to the line voltage drop being less than the voltage drop threshold and the routing track utilization being less than the utilization threshold, and the optimal line spacing parameters and the optimal line width are used as the line parameters of the power supply solution of the target chip module.

[0010] In an optional embodiment of the present application, determining the correlation between the line spacing parameter and the line width parameter and the line voltage drop and the routing track utilization under the constraints of the module parameters includes:

[0011] Constructing an initial power supply network and a current density of the target chip module according to the module parameters;

[0012] Normalizing the current value from the k-1th layer circuit to the standard device in the target chip module according to the current density to obtain an average current value at the power supply connection point between the k-1th layer circuit and the kth layer circuit in the initial power supply network after the normalization process; wherein k is 2 or 3;

[0013] According to the average current value, determine the voltage drop formula of the shortest current path from the outermost line to the inner line in the initial power supply network ;in, is the voltage drop; is the average current value; is the block electrical value parameter; For the Line width parameters of layer lines; is the number of layers of the outermost circuit; when hour, According to the Layer to The line spacing parameters of the layer circuit are determined by the Layer 1 line Layer lines are respectively Layer lines and Line length parameters of the two nearest power supply connection points between layer lines; is a positive integer greater than k-1; when hour, For the Layer 1 line Layer lines and Line length parameters between the nearest power supply connection point and the power terminal between layer lines;

[0014] According to the number of routing tracks on each layer and the spacing between routing tracks on each layer in the initial power supply network, the utilization correlation relationship between routing track utilization and line spacing parameters is determined;

[0015] use the voltage drop formula and the utilization correlation as the correlation.

[0016] In an alternative embodiment of the present application, according to the module parameters, an initial power supply network is constructed and the current density of the initial power supply network is determined, comprising:

[0017] According to the module parameters, the module operating frequency, the number of standard devices, the proportion of registers and logic devices, the average flip rate of all standard devices, the module static power consumption coefficient, the module dynamic power consumption coefficient, the module area, the module operating voltage, the number of routing tracks on each layer, the spacing of routing tracks on each layer, and the sheet resistance parameters are determined;

[0018] According to the number of standard devices, the number of routing tracks, and the spacing of routing tracks, an initial power supply network is constructed;

[0019] According to the current density formula , the current density of the target chip module is determined; wherein, is the current density, F is the module operating frequency, T is the average flip rate, V is the module operating voltage, and C is the proportion, is the module dynamic power consumption coefficient, is the module static power consumption coefficient, and A is the module area.

[0020] In an alternative embodiment of the present application, according to the current density, the current value from the k-1 layer circuit to the standard device in the target chip module is normalized to obtain the average current value of the power supply connection point between the k-1 layer circuit and the k layer circuit in the initial power supply network after normalization, comprising:

[0021] A rectangular normalization window is drawn in the initial power supply network; wherein the rectangular normalization window encloses at least a set number of standard devices, and a set number of lines in the 0th layer to the k-1 layer circuit are enclosed respectively;

[0022] According to the product of the current density and the window area of the rectangular normalization window, the total current value of the rectangular normalization window is determined;

[0023] The ratio of the total current value to the number of lines in the k-1 layer circuit contained in the rectangular normalization window is taken as the average current value.

[0024] In an alternative embodiment of the present application, further comprising:

[0025] According to the big data statistical principle, the corresponding relationship between the pin density of the standard device and the interface density of the chip module and the utilization threshold is determined in advance;

[0026] After the module parameters of the target chip module are acquired, further comprising:

[0027] According to the number of pins and the number of interfaces of the standard device in the module parameters, a current pin density and a current interface density are determined;

[0028] According to the current pin density and the current interface density and the corresponding relationship, the utilization threshold is determined.

[0029] In an optional embodiment of the present application, according to the correlation relationship, machine learning is performed on the change rule of the line voltage drop and the track utilization rate with the line spacing parameter and the line width parameter, and the change rule model is obtained, comprising:

[0030] According to the correlation relationship, a plurality of line spacing samples and line width samples are determined, and line voltage drop samples and track utilization rate samples corresponding to the line spacing samples and the line width samples are determined;

[0031] Neural network learning is performed on each group of the line spacing samples, the line width samples, the line voltage drop samples and the track utilization rate samples, a neural network model representing the change rule is obtained, and the neural network model is taken as the change rule model;

[0032] Accordingly, according to the change rule, iterative operation is performed on the line spacing parameter and the line width parameter, comprising:

[0033] According to the change rule model and the correlation relationship, the line spacing parameter and the line width parameter are iteratively operated by using a greedy algorithm, and the optimal line spacing parameter and the optimal line width are obtained.

[0034] A line parameter determination device in a power supply scheme, comprising:

[0035] A parameter acquisition module is configured to acquire module parameters of a target chip module;

[0036] A data relationship module is configured to determine a correlation relationship between a line spacing parameter and a line width parameter of a ground wire or a power supply wire and a line voltage drop and a track utilization rate under the constraint of the module parameters;

[0037] A model training module is configured to, according to the correlation relationship, perform machine learning on a change rule of the line voltage drop and the track utilization rate with the line spacing parameter and the line width parameter, and obtain a change rule model;

[0038] An optimization operation module is used to perform iterative optimization operation on the line spacing parameters and the line width parameters according to the change law model, obtain the corresponding optimal line spacing parameters and optimal line width in which the line voltage drop is less than the voltage drop threshold and the routing track utilization is less than the utilization threshold, and use the optimal line spacing parameters and the optimal line width as the line parameters of the power supply solution of the target chip module.

[0039] In an optional embodiment of the present application, the data relationship module specifically includes:

[0040] A first computing unit, configured to construct an initial power supply network and a current density of the target chip module according to the module parameters;

[0041] a second computing unit, configured to normalize the current value from the k-1th layer circuit to the standard device in the target chip module according to the current density, and obtain an average current value of the power supply connection point between the k-1th layer circuit and the kth layer circuit in the initial power supply network after the normalization; wherein k is 2 or 3;

[0042] The third operation unit is used to determine the voltage drop formula of the shortest current path from the outermost line to the inner line in the initial power supply network according to the average current value. ;in, is the voltage drop; is the average current value; is the block electrical value parameter; For the Line width parameters of layer lines; is the number of layers of the outermost circuit; when hour, According to the Layer to The line spacing parameters of the layer circuit are determined by the Layer 1 line Layer lines are respectively Layer lines and Line length parameters of the two nearest power supply connection points between layer lines; is a positive integer greater than k-1; when hour, For the Layer 1 line Layer lines and Line length parameters between the nearest power supply connection point and the power terminal between layer lines;

[0043] a fourth computing unit, configured to determine a correlation between a utilization rate of the routing tracks and a line spacing parameter according to the number of routing tracks in each layer and the spacing between the routing tracks in each layer in the initial power supply network;

[0044] a fifth operation unit configured to use the voltage drop formula and the utilization correlation as the correlation.

[0045] A line parameter determination device in a power supply scheme, comprising:

[0046] a memory configured to store a computer program;

[0047] a processor configured to execute the computer program to implement the steps of the line parameter determination method in a power supply scheme according to any one of the above.

[0048] A computer readable storage medium, the computer readable storage medium storing a computer program, the computer program being executed to implement the steps of the line parameter determination method in a power supply scheme according to any one of the above.

[0049] The line parameter determination method, device, design and computer readable storage medium of the power supply scheme provided by the application, the method can include obtaining the module parameters of the target chip module; determining the correlation between the line spacing parameters and the line width parameters of the ground wire or the power supply wire and the line voltage drop and the track utilization rate under the constraint of the module parameters; according to the correlation, machine learning is performed on the change rule of the line voltage drop and the track utilization rate with the change of the line spacing parameters and the line width parameters, and a change rule model is obtained; according to the change rule model, the line spacing parameters and the line width parameters are optimized and iterated, and the optimal line spacing parameters and the optimal line width corresponding to the line voltage drop less than the voltage drop threshold and the track utilization rate less than the utilization rate threshold are obtained, and the optimal line spacing parameters and the optimal line width are taken as the line parameters of the power supply scheme of the target chip module.

[0050] In the application, based on the heat module parameters of the target chip module, the correlation between the line spacing parameters and the line width parameters of any one of the ground wire or the power supply wire in the power supply scheme and the voltage drop and the track utilization rate is determined, and machine learning is performed based on the correlation, a change rule model of the line voltage drop and the track utilization rate with the change of the line spacing parameters and the line width parameters is determined, and the line spacing parameters and the line width parameters are optimized and iterated according to the change rule model, and finally the optimal line spacing parameters and the optimal line width parameters that can meet the voltage drop threshold and the utilization rate threshold requirements at the same time are determined; compared with the power supply scheme design method of manually debugging a large number of line parameters, the line parameters of the ground wire or the power supply wire in the power supply scheme can be determined by the iterative operation of the computer, which greatly reduces the time and manpower consumed by the power supply scheme design, and reduces the cost of the power supply scheme design. BRIEF DESCRIPTION OF DRAWINGS

[0051] In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0052] Figure 1 A schematic diagram of the structure of a portion of the power supply network in the chip module provided in an embodiment of the present application;

[0053] Figure 2 A flow chart of a method for determining line parameters in a power supply solution provided in an embodiment of the present application;

[0054] Figure 3 A schematic diagram of the structure of another part of the power supply network in the chip module provided in an embodiment of the present application;

[0055] Figure 4 This is a structural block diagram of a circuit parameter determination device in a power supply solution provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0056] The core of the present invention is to provide a method for determining circuit parameters in a power supply solution, which can greatly shorten the power supply solution design cycle and reduce human resource investment.

[0057] In order to enable those skilled in the art to better understand the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0058] like Figure 1 As shown, Figure 1 This is a schematic diagram of the structure of part of the power supply network in the chip module provided in an embodiment of the present application.

[0059] It should be noted that in the power supply scheme of the chip module, the circuits that need to be laid out and designed mainly include power lines, ground lines and signal lines. In addition to the above-mentioned circuits, the chip module also includes standard devices connected to each circuit, such as registers and logic gates. Among them, the standard devices are arranged at the bottom layer of the chip module, and multiple layers of circuits are laid out layer by layer from the standard devices upwards. Each layer of circuits includes power lines, ground lines and signal lines. Figure 1In the four-layer circuit shown from M0 to M3, the power lines and the ground lines in each layer are evenly arranged with equal spacing, and the routing directions of the two adjacent layers of circuits are perpendicular to each other, and the same types of circuits in the two adjacent layers are electrically connected by through-holes at the intersection.

[0060] On this basis, this application mainly involves how to determine the line parameters of the power lines and ground lines in the power supply scheme, and the line parameters mainly involve the line spacing parameters and line width parameters of the power lines in each layer of lines, or the line spacing parameters and line width parameters of the ground lines in each layer of lines. In practical applications, the method for determining the line parameters in the power supply scheme in this application can determine the line parameters of the ground line or the line parameters of the power line. In short, after determining a set of optimal line parameters, the power lines and ground lines can be laid out according to the same line parameters.

[0061] like Figure 2 As shown, Figure 2 A flow chart of a method for determining line parameters in a power supply solution provided in an embodiment of the present application.

[0062] S1: Get the module parameters of the target chip module.

[0063] The target chip module in this embodiment may be a CPU chip module, or any other chip module that requires a power supply solution design, which is not specifically limited in this embodiment.

[0064] After selecting the target chip module, the back-end input components of the target chip module can be determined, such as: netlist, timing constraints (sdc), work scenario requirements (spec), etc.; the module parameters can be further extracted from the netlist, timing constraints and work scenario requirements; for example, the standard devices contained in the target chip module and the number of various standard devices, the number of pins of the standard devices, the number of interfaces of the target chip module, etc. can be obtained from the netlist; the frequency parameters of the target chip module can be extracted from the timing constraints, and the work scenario requirements can be used to extract the work scenario of the module, the shape and size information of the module, etc.

[0065] S2: Determine the correlation between the line spacing parameters and line width parameters of the ground line or power line and the line voltage drop and the routing track utilization under the constraints of the module parameters.

[0066] As described above, multiple layers of circuits are arranged sequentially from bottom to top in the target chip module. The line spacing parameter in this embodiment refers to the spacing between the same type of circuits in each layer, and the line width parameter refers to the line width of each type of circuit in each layer.

[0067] On this basis, the target chip module is provided with a plurality of layers of wiring tracks, that is, tracks accommodating the power lines, ground lines and information lines. The wiring tracks of each layer are uniformly arranged; after the target chip module is selected, the number of wiring tracks corresponding to each layer of lines and the spacing between the wiring tracks can be known. Thus, when the line spacing parameter is actually set, the line spacing of each layer of lines should be an integer multiple of the spacing between adjacent wiring tracks in the line layer.

[0068] It can be understood that the line voltage drop in the embodiment refers to the voltage drop value of the supply voltage of the current from the outermost layer of lines of the target chip module to the standard device of the innermost layer of the target chip module in the power supply process of the target chip module, which is obviously related to the line circuit formed by the arrangement of each layer of lines based on the line spacing parameter, and the resistance value of each layer of lines; and the resistance value of each layer of lines is determined by the line width parameter and the line spacing parameter. Based on this relationship principle, it is obvious that the correlation between the line spacing parameter and the line width parameter and the line voltage drop can be deduced.

[0069] The wiring track utilization rate is the utilization rate of the wiring tracks that need to be occupied according to the arrangement of the line spacing parameter in each wiring track, which is obviously directly determined by the line spacing parameter and the number of each layer of wiring tracks. Of course, the line width parameter of each layer of lines will also affect the wiring track utilization rate to some extent, for example, for each line, there is a minimum line width limit, when the line width of a line in a wiring track is too large, the line width of the line in the adjacent two wiring tracks cannot be arranged, which means that one line occupies the layout space of three wiring tracks, which also affects the utilization rate of the wiring tracks.

[0070] Based on this, the correlation between the line spacing parameter and the line width parameter and the line voltage drop and the wiring track utilization rate can be determined.

[0071] As described above, the line parameters determined in the present application can be line parameters of power lines or line parameters of ground lines; in the present embodiment and each subsequent embodiment, each layer of lines can be regarded as all power line lines or all ground line lines, and does not include the case that part of the layer lines are power line lines and the other part of the lines are ground line lines, or the case that some of the lines in the same layer are power lines and some are ground lines, which will not be repeated hereinafter.

[0072] S3: According to the correlation, machine learning is performed on the change rule of the line voltage drop and the wiring track utilization rate with the change of the line spacing parameter and the line width parameter, to obtain a change rule model.

[0073] It can be understood that the above association relationship and change rule model in the embodiment essentially represent the correlation between the line spacing parameter and the line width parameter and the line voltage drop and the track utilization rate.

[0074] In addition, the reason why the machine learning training is further needed to determine the change rule model on the basis of the known association relationship is that the number of lines to be set in the single-layer line of the target chip module is hundreds or thousands, and the total number of lines to be set in the multi-layer line is huge. In such a complex line layout, each adjustment of the line spacing parameter and the line width parameter needs a large amount of data operation process to determine the corresponding line voltage drop and track utilization rate. Therefore, the embodiment further obtains a model that can quickly and accurately predict the corresponding line voltage drop and track utilization rate under the determination of the line spacing parameter and the line width parameter through machine learning.

[0075] Optionally, the learning and creating process of the change rule model in the embodiment can include:

[0076] determining the line voltage drop sample and the track utilization rate sample corresponding to each group of line spacing sample and line width sample according to the association relationship;

[0077] performing neural network learning on each group of line spacing sample, line width sample, line voltage drop sample and track utilization rate sample to obtain a neural network model representing the change rule, and taking the neural network model as the change rule model.

[0078] The embodiment determines a plurality of groups of line spacing sample, line width sample, and corresponding line voltage drop sample and track utilization rate sample by using the above association relationship. Therefore, the neural network model training can be performed based on the above sample data, and the specific training process is similar to the conventional neural network model training process, which will not be limited and described herein.

[0079] S4: performing optimization iteration operation on the line spacing parameter and the line width parameter according to the change rule model to obtain optimal line spacing parameter and optimal line width corresponding to the line voltage drop less than the voltage drop threshold and the track utilization rate less than the utilization rate threshold, and taking the optimal line spacing parameter and the optimal line width as the power scheme parameter of the target chip module.

[0080] The line spacing parameter and the line width parameter can be repeatedly adjusted and optimized in the embodiment, and the line voltage drop and the track utilization corresponding to the updated line spacing parameter and line width parameter are predicted by combining the updated neural network model, and it is judged whether the updated line spacing parameter and line width parameter meet the requirements, until the line voltage drop corresponding to the finally determined line spacing parameter and line width parameter is less than the voltage drop threshold and the track utilization is less than the utilization threshold, and the line spacing parameter and line width parameter at this time are the optimal line spacing parameter and the optimal line width.

[0081] Further optionally, the process of optimizing and iterating the line spacing parameter and the line width parameter can include:

[0082] According to the change rule model and the association relationship, the line spacing parameter and the line width parameter are iteratively calculated by using a greedy algorithm to obtain the optimal line spacing parameter and the optimal line width.

[0083] It should be noted that in the process of optimizing and iterating the line spacing parameter and the line width parameter, there can be multiple groups of line spacing parameters and line width parameters corresponding to the line voltage drop less than the voltage drop threshold and the track utilization less than the utilization threshold; in actual application, the group of line spacing parameter and line width parameter corresponding to the minimum track utilization on the basis of the line voltage drop less than the voltage drop threshold should be selected as the optimal line spacing parameter and the optimal line width.

[0084] As described above, the line in the present application mainly refers to the line parameters of ground wire and power line, and signal line also needs to be laid out in the power scheme; in order to ensure the balance between the track resources occupied by the power line, the ground wire and the signal line, it is necessary to limit the track utilization corresponding to the power line and the ground wire, therefore, the utilization threshold in the embodiment is the maximum utilization of the track occupied by the power line and the ground wire.

[0085] In an optional embodiment of the present application, the process of determining the utilization threshold can include:

[0086] The corresponding relationship between the pin density of the standard device and the interface density of the chip module and the utilization threshold is determined in advance according to the big data statistical principle;

[0087] After obtaining the module parameters of the target chip module, it further includes:

[0088] According to the pin number and the interface number of the standard device in the module parameters, the current pin density and the current interface density are determined;

[0089] According to the current pin density and the current interface density and the corresponding relationship, the utilization threshold is determined.

[0090] The embodiment is based on big data statistical principle, and combines the pin density of various standard devices in different chip modules, the interface density of the chip modules, and the utilization rate of the ground wire or power wire to the track, to fit and determine the corresponding relationship between the pin density of the standard device, the interface density of the chip module, and the utilization rate threshold, so that the reasonable utilization rate threshold can be determined based on the corresponding relationship and the current pin density and interface density in the target chip module.

[0091] It can be understood that the pin density in the embodiment is calculated by the ratio between the number of pins arranged on the standard device and the length of the circumference on which the pins can be arranged on the standard device, and the interface density is calculated by the ratio between the number of interfaces in the target chip module and the length of the axis on which the interfaces can be arranged on the target chip module.

[0092] In summary, in the present application, based on the module parameters of the target chip module, the correlation between the line spacing parameter and the line width parameter of the ground wire or the power wire in the power supply scheme and the voltage drop and the track utilization rate is determined based on the module parameters; and based on this, learning is performed to determine the change rule of the line voltage drop and the track utilization rate with the change of the line spacing parameter and the line width parameter, and the line spacing parameter and the line width parameter are optimized and iterated to finally determine the optimal line spacing parameter and the optimal line width parameter that can meet the voltage drop threshold and the utilization rate threshold requirement; compared with the manual debugging of a large number of line parameters, the determination of the line parameters of the ground wire or the power wire in the power supply scheme in the present application can be automatically completed by computer operation, which greatly reduces the time and manpower consumed in the power supply scheme design and reduces the power supply scheme design cost.

[0093] Based on the above embodiment, in an optional embodiment of the present application, the process of determining the correlation between the line spacing parameter and the line width parameter and the line voltage drop and the track utilization rate based on the module parameters can specifically include:

[0094] S21: constructing an initial power supply network and a current density of the target chip module according to the module parameters.

[0095] According to the module parameter density, at least the module working frequency, the number of standard devices, the proportion of registers and logic devices, the average flip rate of all standard devices, the module static power consumption coefficient, the module dynamic power consumption coefficient, the module area, the module working voltage, the number of track layers, the track spacing between layers, and the square resistance parameter can be determined.

[0096] It can be understood that after obtaining the module parameters of the target chip module, the basic framework of the power supply network of the target chip module can be determined, that is, similar to the power supply network structure shown in Figure 1 .

[0097] On this basis, the initial line spacing and initial line width of each layer of lines in the power supply network can be set first, and the initial power supply network of the target chip module can be constructed based on the basic framework of the power supply network structure and the initial line spacing and initial line width.

[0098] In addition, the target chip module in the embodiment refers to the current surface density of the entire target chip module.

[0099] On this basis, the current density of the target chip module can be determined based on the current density formula , wherein is the current density, F is the module working frequency, T is the average flip rate, V is the module working voltage, C is the proportion, is the module dynamic power consumption coefficient, is the module static power consumption coefficient, and A is the module area.

[0100] S22: According to the current density, the current value from the k-1 layer line to the standard device in the target chip module is normalized to obtain the average current value of the power supply connection point between the k-1 layer line and the k layer line in the power supply network after normalization; wherein k is 2 or 3.

[0101] As mentioned above, the current density in the embodiment is the current density of the entire surface of the target chip module. The reason why the current density of the entire target chip module is determined in the embodiment is to determine the voltage drop of the power supply from the outermost layer line to the innermost layer line through the initial power supply network to the standard device.

[0102] It can be understood that the power supply voltages of different standard devices in the target chip module are not the same, and therefore the voltage drops between the outermost layer line and the voltage input ends of different standard devices are also not the same, and therefore the voltage drop between the voltage input end of any standard device and the outermost layer line cannot accurately represent the voltage drop between each layer of lines of the entire target chip module.

[0103] Based on this, the current of the circuit below the k-1 layer is normalized in the embodiment, that is, the average current of each power supply connection point (that is, the position point of the two layer lines crossing each other is electrically connected through the via hole) between the k-1 layer line and the k layer line is used to represent the current from the standard device to the k-1 layer line; therefore, based on this average current value, the voltage drop from the k-1 layer line to the outermost layer line is further determined, which is equivalent to representing the voltage drop of each layer of lines of the target chip module with the average voltage drop between the outermost layer line and the standard device.

[0104] Further optionally, referenceFigure 1 The process of normalizing the current value from the k-1 layer lines to the standard devices in the target chip module to obtain the average current value can include:

[0105] defining a rectangular normalization window in the initial power network; wherein the rectangular normalization window encloses at least a set number of standard devices, and a set number of lines in the 0th layer to the k-1 layer lines respectively;

[0106] determining the total current value of the rectangular normalization window according to the product of the current density and the window area of the rectangular normalization window;

[0107] taking the ratio of the total current value and the number of lines in the k-1 layer lines enclosed in the rectangular normalization window as the average current value.

[0108] As shown in the embodiment of Figure 1 , taking k=3 as an example to define the rectangular normalization window, M0, M1, M2, M3 represent the 0th layer lines to the 3rd layer lines respectively. It should be noted that when the embodiment is to determine the line spacing parameter and the line width parameter of the ground wire, the three layers of lines M1 to M3 are all ground wires; while the lines in the M0 layer should contain both power lines and ground wires. When the embodiment is to determine the line spacing parameter and the line width parameter of the power line, the three layers of lines M1 to M3 are all power lines; while the lines in the M0 layer should also contain both power lines and ground wires.

[0109] It should be noted that the long side and the short side of the rectangular normalization window are respectively parallel to the two different direction axis tracks of the target chip module. A set number of standard devices are enclosed in the normalization window, and in general, at least three different types of standard devices are enclosed in the rectangular normalization window; in addition, the number of lines in the 0th layer lines (i.e. the lines in the M0 layer) enclosed in the rectangular normalization window is not less than 3. In Figure 1 the embodiment shown in the figure, the number of lines in the 0th layer lines enclosed in the rectangular normalization window is 5, the number of lines in the 1st layer lines enclosed is 3, and the number of lines in the 2nd and 3rd layer lines enclosed is 1.

[0110] On this basis, the standard devices, the 0th layer lines, the 1st layer lines and the 2nd layer lines enclosed in the rectangular normalization window are regarded as an integral module, that is, the current in the standard devices, the 0th layer to the 2nd layer lines is normalized, and the product of the area of the rectangular normalization window and the current density of the target chip module is taken as the average value of the current flowing into and out of the rectangular normalization window.

[0111] As shown in Figure 1 , in order to simplify the operation process, in Figure 1In the illustrated embodiment, one line of each of the k-1th layer line and the kth layer line should be located on the center line of the rectangular normalized window. That is, the rectangular normalized window in this embodiment is a window centered on a power supply connection point between the k-1th layer line and the kth layer line.

[0112] Therefore, the average value of the current flowing from the third-layer circuit to the second-layer circuit is equal to the product of the area of ​​the rectangular normalization window and the current density. It can be understood that if there are two second-layer circuits enclosed in the rectangular normalization window, the average value of the current flowing from the third-layer circuit to the second-layer circuit should be equal to half the product of the area of ​​the rectangular normalization window and the current density. If there are three second-layer circuits enclosed in the rectangular normalization window, the average value of the current flowing from the third-layer circuit to the second-layer circuit should be equal to one-third the product of the area of ​​the rectangular normalization window and the current density.

[0113] The above description uses k=3 as an example. In practical applications, the current from the M1 layer circuit to the standard device can also be normalized, that is, k=2. In this case, the rectangular normalization window can be smaller than the rectangular normalization window when k=3, as long as at least one circuit in the M1 layer is divided and passes through the rectangular normalization window. The calculation method of the average current value and voltage drop when k=2 is exactly the same as when k=3, and is not fully elaborated here.

[0114] S23: Based on the average current value, determine the voltage drop formula for the shortest current path from the outermost line to the inner line in the initial power network. ;in, is the voltage drop; is the average current value; is the block electrical value parameter; For the Line width parameters of layer lines; is the number of layers of the outermost circuit; when hour, According to the Layer to The line spacing parameters of the layer circuit are determined by the Layer 1 line Layer lines are respectively Layer lines and Line length parameters of the two nearest power supply connection points between layer lines; is a positive integer greater than k-1; when hour, For the Layer 1 line Layer lines and The line length parameter between the nearest power supply connection point and the power terminal between layer lines.

[0115] As described above, after the standard devices and the lines from layer 0 to layer 2 enclosed in the above-mentioned rectangular normalized window are regarded as an integral module, based on the principle that the current path in the circuit should be the path with the least resistance, the shortest current path from the outermost line to the innermost line is determined; this shortest current path is also the shortest current path from the outermost line to the rectangular normalized window, specifically, the shortest current path from the outermost line to the power supply connection point between the second layer line and the third layer line in the rectangular normalized window is determined.

[0116] Reference Figure 3 , Figure 3 The shortest circuit path from the M7 layer line to the rectangular normalized window is shown in Figure 3 The current path indicated by the arrows in the figure. In the actual process of determining the shortest current path, the power supply connection point between a line in the second layer and a line in the third layer divided into the rectangular normalized window can be used as the first node of the starting node, and the shortest current path is determined along the reverse direction of the current, that is, the power supply connection point between the second layer and the third layer in the rectangular normalized window is used as the first node, and the power supply connection point closest to the first node among the power supply connection points of the third layer and the fourth layer of the initial power network determined based on the initial line spacing is used as the second node. The first node and the second node are respectively the power supply connection points between the third layer and the second layer and the fourth layer. In the same way, the power supply connection point closest to the second node among the power supply connection points between the 4th layer line and the 5th layer line can be determined as the third node. The second node and the third node are also the two nearest power supply connection points between the 4th layer line and the 3rd layer line and the 5th layer line respectively. Similarly, a power supply connection point between the outermost layer line and the outermost layer line can be determined as the Nth node. The shortest current path is from the Nth node as the current starting point through the N-1th node to the 1st node. The voltage drop between the Nth node and the 1st node is the voltage drop in the target chip module.

[0117] Based on the above shortest current path, as well as the initial line spacing parameters and initial line width in each layer of the line, the current magnitude and voltage drop between two adjacent nodes under the set initial line spacing parameters and initial line width conditions can be determined. The cumulative value of the voltage drop between each two adjacent nodes is the voltage drop between the Nth node and the first node, which can also be used as the voltage drop in the target chip module. Based on this, the voltage drop formula can be determined as follows: Although the voltage drop formula does not involve the line spacing parameter, Yes On the layer line, Layer lines and Between the layers, and Layer lines and The line length parameter between the two nearest power supply connection points between the layer lines; obviously, this line length parameter is determined by the Layer line to the The line spacing parameters of the layer are determined; and when hour, For the Layer 1 line Layer lines and The line length parameter between the nearest power supply connection point between the layer lines (that is, the Nth node determined when determining the shortest current path) and the power terminal (if the line is a power line, it is the power supply terminal; if the line is a ground line, it is the power ground terminal); obviously, it also changes with the kth layer line to the nth layer line. The voltage drop formula is determined by the line spacing parameters of the layer circuit; therefore, the voltage drop formula is also a formula that characterizes the correlation between the line spacing parameters and line width parameters and the line voltage drop.

[0118] S24: Determine a utilization correlation relationship between a routing track utilization rate and a line spacing parameter based on the number of routing tracks on each layer and the routing track spacing on each layer in the initial power supply network.

[0119] As mentioned above, the line spacing parameters of each layer of lines are integer multiples of the track spacing of the layer on which they are located. Based on this principle, the utilization correlation relationship between the track utilization and the line spacing parameters can be determined.

[0120] S25: The voltage drop formula and the utilization rate correlation are used as the correlation relationship.

[0121] The following introduces a device for determining line parameters in a power supply solution provided by an embodiment of the present invention. The device for determining line parameters in a power supply solution described below and the method for determining line parameters in a power supply solution described above can refer to each other.

[0122] Figure 4 The structural block diagram of the circuit parameter determination device in the power supply scheme provided by the embodiment of the present invention, refer to Figure 4 The circuit parameter determination device in the power supply scheme may include:

[0123] The parameter acquisition module 100 is used to obtain the module parameters of the target chip module;

[0124] A data relationship module 200 is used to determine the correlation between the line spacing parameter and line width parameter of the ground line or power line and the line voltage drop and the utilization rate of the routing track under the constraints of the module parameters;

[0125] The model training module 300 is configured to perform machine learning on the change rule of the line voltage drop and the track utilization rate with the line spacing parameter and the line width parameter according to the correlation, and obtain the change rule model.

[0126] The optimization operation module 400 is configured to perform optimization iterative operation on the line spacing parameter and the line width parameter according to the change rule model, and obtain the optimal line spacing parameter and the optimal line width corresponding to the line voltage drop less than the voltage drop threshold and the track utilization rate less than the utilization rate threshold, and take the optimal line spacing parameter and the optimal line width as the line parameters of the power supply scheme of the target chip module.

[0127] In an optional embodiment of the present application, the data relationship module specifically includes:

[0128] The first operation unit is configured to construct an initial power supply network and a current density of the target chip module according to the module parameters.

[0129] The second operation unit is configured to perform normalization processing on the current value from the k-1 layer line to the standard device in the target chip module according to the current density, and obtain the average current value of the power supply connection point between the k-1 layer line and the k layer line in the initial power supply network after the normalization processing; wherein k is 2 or 3.

[0130] The third operation unit is configured to determine the voltage drop formula of the shortest current path from the outermost layer line to the inner layer line in the initial power supply network according to the average current value ; wherein, is the voltage drop; is the average current value; is the square resistance parameter; is the line width parameter of the k-1 layer line; is the number of layers of the outermost layer line; when is greater than k-1, the voltage drop formula of the shortest current path from the outermost layer line to the inner layer line in the initial power supply network is determined according to the line spacing parameter of the k-1 layer line to the k layer line. is the line length parameter of the two nearest power supply connection points between the k-1 layer line and the k layer line and the k-1 layer line on the k-1 layer line, respectively. is greater than k-1, the voltage drop formula of the shortest current path from the outermost layer line to the inner layer line in the initial power supply network is determined according to the line spacing parameter of the k-1 layer line to the k layer line. is greater than k-1, the voltage drop formula of the shortest current path from the outermost layer line to the inner layer line in the initial power supply network is determined according to the line spacing parameter of the k-1 layer line to the k layer line. ​​​​​​​​​​a line length parameter between a nearest power supply connection point of a layer line and a power supply terminal;

[0131] a fourth operation unit configured to determine a utilization correlation between a track utilization and a track spacing parameter according to a number of tracks of each layer and a spacing between tracks in an initial power supply network;

[0132] a fifth operation unit configured to use the voltage drop formula and the utilization correlation as the correlation.

[0133] In an optional embodiment of the present application, the first operation unit is specifically configured to determine a module operating frequency, a number of standard devices, a proportion of registers and logic devices, an average flip rate of all standard devices, a module static power consumption coefficient, a module dynamic power consumption coefficient, a module area, a module operating voltage, a number of tracks of each layer, a spacing between tracks of each layer, and a sheet resistance parameter according to the module parameters; to construct an initial power supply network according to the number of standard devices, the number of tracks of each layer, and the spacing between tracks of each layer; and to determine a current density of the target chip module according to a current density formula , wherein is the current density, F is the module operating frequency, T is the average flip rate, V is the module operating voltage, and C is the proportion. is the module dynamic power consumption coefficient. is the module dynamic power consumption coefficient, and A is the module area.

[0134] In an optional embodiment of the present application, the second operation unit is specifically configured to demarcate a rectangular normalized window in the initial power supply network; wherein at least a set number of standard devices are contained in the rectangular normalized window, and a set number of lines in each of the 0th layer to the k-1th layer are contained in the rectangular normalized window; to determine a total current value of the rectangular normalized window according to a product of the current density and a window area of the rectangular normalized window; and to use a ratio of the total current value to a number of lines in the k-1th layer contained in the rectangular normalized window as the average current value.

[0135] In an optional embodiment of the present application, a data statistics module is further included and configured to determine a corresponding relationship between a pin density of a standard device and an interface density of a chip module and a utilization threshold value according to a big data statistics principle in advance;

[0136] A utilization module is further included and specifically configured to determine a current pin density and a current interface density according to a number of pins and a number of interfaces of the standard device in the module parameters; and to determine the utilization threshold value according to the current pin density, the current interface density, and the corresponding relationship.

[0137] In an optional embodiment of the present application, the model training module 300 is specifically configured to determine line voltage drop samples and track utilization samples corresponding to each group of line spacing samples and line width samples according to the correlation; perform neural network learning on each group of the line spacing samples, the line width samples, the line voltage drop samples and the track utilization samples, obtain a neural network model representing the change rule, and use the neural network model as the change rule model.

[0138] Correspondingly, the optimization operation module 400 is specifically configured to perform iterative operation on the line spacing parameter and the line width parameter according to the neural network model and the correlation by using a greedy algorithm, and obtain the optimal line spacing and the optimal line width.

[0139] The power scheme line parameter determination device of the present embodiment is used to implement the power scheme line parameter determination method described above, and thus the specific embodiments of the power scheme line parameter determination device can be seen from the foregoing embodiment part of the power scheme line parameter determination method. The specific embodiments can be referred to the description of the corresponding embodiment part, and will not be described herein again.

[0140] The present application also provides an embodiment of a power scheme line parameter determination device, which can include:

[0141] a memory for storing a computer program;

[0142] a processor for executing the computer program to implement the steps of the power scheme line parameter determination method according to any one of the foregoing embodiments.

[0143] The present application also provides an embodiment of a computer readable storage medium, which stores a computer program, and the computer program is executed to implement the steps of the power scheme line parameter determination method according to any one of the foregoing embodiments.

[0144] The computer readable storage medium can be a random access memory (RAM), a memory, a read only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the technical field.

[0145] It is to be noted that, in the present text, relational terms such as first and second and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without limitation, an element preceded by "comprises... a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the recited element. Also, the above-described technical solutions provided by the embodiments of the present application have not been described in detail in the present text, in order not to make the present text too long, in the case where the implementation principles of the corresponding technical solutions in the prior art are consistent.

[0146] The principles and implementation manners of the present application are described herein by using specific examples, and the above description of the embodiments is only for helping to understand the method of the present application and its core idea. It should be noted that, for those skilled in the art, without departing from the principles of the present application, some improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the present application.

Claims

1. A method for determining line parameters in a power supply solution, characterized in that: include: Get the module parameters of the target chip module; Determine the correlation between the line spacing parameter and line width parameter of the ground line or power line and the line voltage drop and the utilization rate of the routing track under the constraints of the module parameters; Based on the correlation, machine learning is performed on the variation patterns of the line voltage drop and the routing track utilization rate as the line spacing parameter and the line width parameter vary, to obtain a variation pattern model; The line spacing parameters and the line width parameters are optimized iteratively according to the change law model to obtain the optimal line spacing parameters and optimal line width corresponding to the line voltage drop being less than the voltage drop threshold and the routing track utilization being less than the utilization threshold, and the optimal line spacing parameters and the optimal line width are used as the line parameters of the power supply solution of the target chip module.

2. The method for determining line parameters in a power supply solution according to claim 1, wherein: Determine the correlation between the line spacing parameter and the line width parameter and the line voltage drop and the utilization rate of the routing track under the constraints of the module parameters, including: Constructing an initial power supply network and a current density of the target chip module according to the module parameters; Normalizing the current value from the k-1th layer circuit to the standard device in the target chip module according to the current density to obtain an average current value at the power supply connection point between the k-1th layer circuit and the kth layer circuit in the initial power supply network after the normalization process; wherein k is 2 or 3; According to the average current value, determine the voltage drop formula of the shortest current path from the outermost line to the inner line in the initial power supply network ;in, is the voltage drop; is the average current value; is the block electrical value parameter; For the Line width parameters of layer lines; is the number of layers of the outermost circuit; when hour, According to the Layer to The line spacing parameters of the layer circuit are determined by the Layer 1 line Layer lines are respectively Layer lines and Line length parameters of the two nearest power supply connection points between layer lines; is a positive integer greater than k-1; when hour, For the Layer 1 line Layer lines and Line length parameters between the nearest power supply connection point and the power terminal between layer lines; Determining a correlation between a utilization rate of the routing tracks and a line spacing parameter based on the number of routing tracks on each layer and the spacing between the routing tracks on each layer in the initial power supply network; The voltage drop formula and the utilization rate correlation relationship are used as the correlation relationship.

3. The method for determining line parameters in a power supply solution according to claim 2, wherein: Constructing an initial power supply network according to the module parameters and determining a current density of the initial power supply network includes: According to the module parameters, determine the module operating frequency, the number of standard devices, the ratio of registers to logic devices, the average flip rate of all standard devices, the module static power consumption coefficient, the module dynamic power consumption coefficient, the module area, the module operating voltage, the number of routing tracks on each layer, the spacing between routing tracks on each layer, and the square resistance parameters; constructing the initial power supply network according to the number of standard components, the number of routing tracks, and the spacing between routing tracks; According to the current density formula , determine the current density of the target chip module; wherein, is the current density, F is the module operating frequency, T is the average flip rate, V is the module operating voltage, C is the ratio, is the module dynamic power consumption coefficient, is the static power consumption coefficient of the module, and A is the area of ​​the module.

4. The method for determining line parameters in a power supply solution according to claim 2, wherein: Normalizing the current value from the k-1th layer circuit to the standard device in the target chip module according to the current density to obtain an average current value at a power supply connection point between the k-1th layer circuit and the kth layer circuit in the initial power supply network after the normalization, including: A rectangular normalized window is defined in the initial power supply network; wherein the rectangular normalized window includes at least a set number of standard components and a set number of circuits in each of the 0th to k-1th layers; Determining a total current value of the rectangular normalized window according to a product of the current density and the window area of ​​the rectangular normalized window; The average current value is determined by taking a ratio of the total current value to the number of lines in the k-1th layer of lines contained in the rectangular normalization window.

5. The method for determining line parameters in a power supply solution according to claim 1, wherein: Also includes: Determine in advance the corresponding relationship between the pin density of standard devices and the interface density of chip modules and the utilization threshold based on big data statistical principles; After obtaining the module parameters of the target chip module, the method further includes: Determining a current pin density and a current interface density according to the number of pins and the number of interfaces of the standard device in the module parameters; The utilization threshold is determined according to the current pin density, the current interface density, and the corresponding relationship.

6. The method for determining line parameters in a power supply solution according to any one of claims 1 to 5, wherein: According to the association, machine learning is performed on the variation pattern of the line voltage drop and the routing track utilization rate as the line spacing parameter and the line width parameter change to obtain the variation pattern model, including: Determine line voltage drop samples and routing track utilization rate samples corresponding to multiple groups of line spacing samples and line width samples according to the association relationship; Performing neural network learning on each group of the line spacing samples, the line width samples, the line voltage drop samples, and the routing track utilization rate samples to obtain a neural network model that characterizes the change law, and using the neural network model as the change law model; Accordingly, performing an iterative optimization operation on the line spacing parameter and the line width parameter according to the variation rule includes: According to the variation law model and the association relationship, a greedy algorithm is used to iteratively calculate the line spacing parameter and the line width parameter to obtain the optimal line spacing parameter and the optimal line width.

7. A device for determining line parameters in a power supply scheme, characterized in that: include: A parameter acquisition module is used to obtain module parameters of the target chip module; A data relationship module, used to determine the correlation between the line spacing parameter and line width parameter of the ground line or power line and the line voltage drop and the utilization rate of the routing track under the constraints of the module parameters; A model training module is used to perform machine learning on the variation patterns of the line voltage drop and the routing track utilization rate as the line spacing parameter and the line width parameter change based on the association relationship, so as to obtain a variation pattern model; An optimization operation module is used to perform iterative optimization operation on the line spacing parameters and the line width parameters according to the change law model, obtain the corresponding optimal line spacing parameters and optimal line width in which the line voltage drop is less than the voltage drop threshold and the routing track utilization is less than the utilization threshold, and use the optimal line spacing parameters and the optimal line width as the line parameters of the power supply solution of the target chip module.

8. The circuit parameter determination device in the power supply scheme according to claim 7, characterized in that: The data relationship module specifically includes: A first computing unit, configured to construct an initial power supply network and a current density of the target chip module according to the module parameters; a second computing unit, configured to normalize the current value from the k-1th layer circuit to the standard device in the target chip module according to the current density, and obtain an average current value of the power supply connection point between the k-1th layer circuit and the kth layer circuit in the initial power supply network after the normalization; wherein k is 2 or 3; The third operation unit is used to determine the voltage drop formula of the shortest current path from the outermost line to the inner line in the initial power supply network according to the average current value. ;in, is the voltage drop; is the average current value; is the block electrical value parameter; For the Line width parameters of layer lines; is the number of layers of the outermost circuit; when hour, According to the Layer to The line spacing parameters of the layer circuit are determined by the Layer 1 line Layer lines are respectively Line length parameters of the two nearest power supply connection points between the first layer line and the second layer line; is a positive integer greater than k-1; when hour, For the Layer 1 line Layer lines and Line length parameters between the nearest power supply connection point and the power terminal between layer lines; a fourth computing unit, configured to determine a correlation relationship between a utilization rate of the routing tracks and a line spacing parameter according to the number of routing tracks in each layer and the spacing between the routing tracks in each layer in the initial power supply network; A fifth operation unit is configured to use the voltage drop formula and the utilization rate correlation relationship as the correlation relationship.

9. A device for determining line parameters in a power supply solution, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the steps of the method for determining line parameters in a power supply solution according to any one of claims 1 to 6.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and the computer program is executed to implement the steps of the method for determining line parameters in a power supply solution according to any one of claims 1 to 6.

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