Circuit board test point determination method and electronic device

Abstract

The application provides a circuit board test point determination method and electronic equipment, which can be applied to the technical field of circuit boards. The circuit board test point determination method comprises: a test point determination program acquires design data for a target circuit board, wherein the design data comprises physical information of at least one wiring network; for any wiring network, in the case that the name of any wiring network fails to match a first naming rule in a first naming rule library, attribute information of any wiring network is matched with an attribute rule to obtain an attribute matching result; according to the attribute matching result, the network type of any wiring network is determined, wherein the network type is one of a first type network and a second type network, and in response to the network type of any wiring network being the first type network, a test point position for any wiring network is determined according to a test point layout rule and the position of any wiring network relative to the target circuit board.

Description

Technical Field

[0001] This application relates to the field of circuit board technology, and more specifically to a method for determining test points on a circuit board and an electronic device. Background Technology

[0002] Printed circuit boards (PCBs) are the carriers for the electrical connections of electronic components. They are important electronic components that support electronic components and provide circuit connections for them in electronic devices.

[0003] After the PCB design is completed, test points need to be added to the PCB to check the electrical properties of the components and the soldering. However, the methods for adding test points in related examples are generally manual, which is prone to omissions and is inefficient. Summary of the Invention

[0004] In view of the above problems, this application provides a method for determining test points on a circuit board and an electronic device.

[0005] According to a first aspect of this application, a method for determining test points on a circuit board is provided. The method includes: a test point determination procedure acquiring design data for a target circuit board, wherein the design data includes physical information of at least one routing network, the physical information including at least one of the following: name and attribute information; for any routing network, if the name of the routing network fails to match a first naming rule in a first naming rule library, matching the attribute information of the routing network with attribute rules to obtain an attribute matching result; determining the network type of the routing network based on the attribute matching result, wherein the network type is one of a first type network and a second type network; and in response to the network type of the routing network being a second type network, determining the test point position for the routing network based on test point layout rules and the position of the routing network relative to the target circuit board.

[0006] A second aspect of this application provides a circuit board test point determination apparatus, the apparatus comprising: an acquisition module for acquiring design data for a target circuit board, wherein the design data includes physical information of at least one routing network, the physical information including at least one of the following: name and attribute information; a matching module for matching attribute information of any routing network with attribute rules to obtain an attribute matching result if the name of any routing network fails to match a first naming rule in a first naming rule library; a first determination module for determining the network type of any routing network based on the attribute matching result, wherein the network type is one of a first type network and a second type network; and a second determination module for determining the test point position for any routing network based on a test point layout rule and the position of any routing network relative to the target circuit board in response to the network type of any routing network being a second type network.

[0007] A third aspect of this application provides an electronic device comprising: one or more processors; and a memory for storing one or more computer programs, wherein the one or more processors execute the one or more computer programs to implement the steps of the method described above.

[0008] A fourth aspect of this application also provides a computer-readable storage medium having a computer program or instructions stored thereon, which, when executed by a processor, implement the steps of the above-described method.

[0009] The fifth aspect of this application also provides a computer program product, including a computer program or instructions that, when executed by a processor, implement the steps of the above-described method.

[0010] This application employs a technical solution that acquires name and attribute information from circuit board design data, matches the name and attribute information sequentially, automatically identifies the network type of the routing network based on the matching results, and then intelligently determines the test point location for routing networks belonging to the second type of network by combining test point layout rules and the location of the routing network. This solution can automatically exclude first type of networks, such as prohibited layout networks, and accurately place test points on second type of networks, such as allowed layout networks, thereby achieving automated test point placement and helping to improve the efficiency and accuracy of circuit board testing. Attached Figure Description

[0011] The above-mentioned contents, other objects, features and advantages of this application will become clearer from the following description of embodiments of this application with reference to the accompanying drawings.

[0012] Figure 1 A schematic diagram showing the addition of test points on a circuit board is shown.

[0013] Figure 2 The diagram illustrates application scenarios of the circuit board test point determination method, apparatus, electronic device, storage medium, and program product according to embodiments of this application.

[0014] Figure 3 A flowchart of a method for determining circuit board test points according to an embodiment of this application is shown.

[0015] Figure 4 A flowchart illustrating the determination of network type according to an embodiment of this application is shown.

[0016] Figure 5 A schematic diagram illustrating the determination of test point locations according to an embodiment of this application is shown.

[0017] Figure 6 A schematic diagram of adding test points according to an embodiment of this application is shown.

[0018] Figure 7 A flowchart of a method for determining circuit board test points according to another embodiment of this application is shown.

[0019] Figure 8 A structural block diagram of a circuit board test point determination device according to an embodiment of this application is shown.

[0020] Figure 9 A block diagram of an electronic device suitable for implementing a circuit board test point determination method according to an embodiment of this application is shown. Detailed Implementation

[0021] The embodiments of this application will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of this application. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of this application for ease of explanation. However, it will be apparent that one or more embodiments may be implemented without these specific details. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0023] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0024] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0025] Terminology Explanation:

[0026] A stub or stray wire refers to a section of unintended branch or mismatched end in the signal transmission path. In other words, it is a path or wire end that the signal is not intended to pass through. These wire ends may cause signal integrity problems, such as signal reflection or impedance discontinuity, thereby affecting the performance of the circuit.

[0027] In-Circuit Test (ICT) is a testing method used to inspect the quality of circuit board assembly. It mainly uses a bed of nails to connect test points on the circuit board to detect the electrical properties of components and whether there are open circuits, short circuits, or other problems in the soldering.

[0028] Prohibited Layout Area: To prevent test points from being too close to the device and thus undetectable, a prohibited layout area is added to the device when creating the device package to avoid this situation, ensuring that test points cannot be added below or at close range to the device.

[0029] Circuit network: refers to the collection of all conductive elements in a circuit board that have electrical connections, including wires, pads, vias, copper foil, etc. These elements are physically connected to form an electrical whole to jointly complete specific signal transmission or power supply functions.

[0030] In cloud computing applications, servers serve as the core carrier, undertaking core tasks such as data storage, computational processing, and service response. Whether it's everyday social communication, online entertainment, and transactions, or big data analysis and artificial intelligence training, all rely on the efficient operation of servers.

[0031] With the continuous growth of data volume, higher demands are placed on the computing power, storage efficiency, and signal transmission rate of servers. For example, the signal transmission rate of PCBs in servers has increased from 1Gbps to 32Gbps, such as PCIe 5.0 (Peripheral Component Interconnect Express 5.0) signals. High-speed signals significantly increase the sensitivity to circuit integrity; even a 0.5mm stub can cause signal reflectivity to exceed -10dB, leading to test misjudgments or system crashes. As the interface for ICT testing, the reasonable layout of test points directly affects the feasibility of production testing and the integrity of system signals.

[0032] In one relevant example, the layout of test points relies on manual addition. Before adding them, test point addition criteria (such as test point size) are set, and then they are manually added one by one to network signals outside the prohibited layout area.

[0033] Figure 1 A schematic diagram showing the addition of test points on a circuit board is shown.

[0034] like Figure 1 As shown, the circuit board 100 includes routing networks and prohibited layout regions. The routing networks include, for example, a first routing network 111, a second routing network 112, etc., and the prohibited layout regions include, for example, regions 121, 122, and 123. When adding test points, test points are added at the routing paths or vias outside the prohibited layout regions. For example, test point a is added on the routing path of the first routing network 111, and test point b is added on the routing path of the second routing network 112.

[0035] However, this method relies on manual labeling, which is prone to omissions. In addition, manually added test points are scattered and prone to errors (such as inappropriate test point positions, difficulty in detection, and omissions) and low efficiency.

[0036] In another related example, test point layout can also be added programmatically. First, networks that should not be tested are manually marked in advance, such as all high-speed signal networks within the PCB, so that test points are not added to these networks during program execution. Then, the criteria for adding test points (e.g., test point dimensions) and execution mode (e.g., adding to trace paths or vias) are manually set in advance. During program execution, test points are added based on the manually marked networks and prohibited layout areas. However, this method still has the following problems: it cannot guarantee that all trace networks will have test points added; for complex boards, there are often hundreds of trace networks without test points, requiring manual addition later. Furthermore, after generating test points, manual adjustments are often needed, such as manually adding missing test points, deleting or adjusting improperly positioned test points, etc., which is cumbersome and inefficient. In addition, this method requires manually marking trace networks that should not have test points added before the program can run, making it difficult to intelligently optimize according to different design requirements and scenarios, and difficult to adapt to complex PCB layouts and routing situations. This method is also difficult to meet the requirements for high test point coverage.

[0037] In view of the above-mentioned technical problems, embodiments of this application provide a method for determining test points on a circuit board, comprising: acquiring design data for a target circuit board, wherein the design data includes physical information of at least one routing network, the physical information including at least one of the following: name and attribute information; for any routing network, if the name of the routing network fails to match a first naming rule in a first naming rule library, matching the attribute information of the routing network with attribute rules to obtain an attribute matching result; determining the network type of the routing network based on the attribute matching result, wherein the network type is one of a first type network and a second type network; and in response to the network type of the routing network being a second type network, determining the test point position for the routing network based on test point layout rules and the position of the routing network relative to the target circuit board. By adopting a technical solution that automatically identifies network types based on the physical information of the trace network, and then intelligently determines the test point positions for the trace network of the second type of network by combining the test point layout rules and the position of the trace network, this method can automatically exclude prohibited layout networks without manual marking, and can accurately place test points on allowed layout networks, realizing the automated placement of test points and helping to improve the efficiency and accuracy of circuit board testing.

[0038] Figure 2 The diagram illustrates application scenarios of the circuit board test point determination method, apparatus, electronic device, storage medium, and program product according to embodiments of this application.

[0039] like Figure 2As shown, application scenario 200 according to this embodiment may include a first terminal device 201, a second terminal device 202, a third terminal device 203, a network 204, and a server 205. The network 204 serves as a medium for providing a communication link between the first terminal device 201, the second terminal device 202, the third terminal device 203, and the server 205. The network 204 may include various connection types, such as wired or wireless communication links, or fiber optic cables, etc.

[0040] Users can use the first terminal device 201, the second terminal device 202, and the third terminal device 203 to interact with the server 205 through the network 204 to receive or send messages, etc.

[0041] The first terminal device 201, the second terminal device 202, and the third terminal device 203 can be various electronic devices with displays and web browsing capabilities, including but not limited to smartphones, tablets, laptops, and desktop computers. Applications for circuit board design can be installed on the first terminal device 201, the second terminal device 202, and the third terminal device 203. After the user completes the circuit board design using the application on the first terminal device 201, the second terminal device 202, and the third terminal device 203, design data for the circuit board will be generated. This design data may include electrical connections and physical information, physical layout data, etc.

[0042] Server 205 can be a server that provides various services, can analyze and process the received circuit board design data, and feed back the processing results (such as test point location information) to the terminal device.

[0043] It should be noted that the circuit board test point determination method provided in this application embodiment can generally be executed by server 205. Correspondingly, the circuit board test point determination device provided in this application embodiment can generally be located in server 205. The circuit board test point determination method provided in this application embodiment can also be executed by a server or server cluster that is different from server 205 and capable of communicating with the first terminal device 201, the second terminal device 202, the third terminal device 203, and / or server 205. Correspondingly, the circuit board test point determination device provided in this application embodiment can also be located in a server or server cluster that is different from server 205 and capable of communicating with the first terminal device 201, the second terminal device 202, the third terminal device 203, and / or server 205. Alternatively, the circuit board test point determination method provided in this application embodiment can also be executed by the first terminal device 201, the second terminal device 202, or the third terminal device 203, or it can be executed by other terminal devices different from the first terminal device 201, the second terminal device 202, or the third terminal device 203. Accordingly, the circuit board test point determination device provided in the embodiments of this application may also be set in the first terminal device 201, the second terminal device 202 or the third terminal device 203, or in other terminal devices different from the first terminal device 201, the second terminal device 202 or the third terminal device 203.

[0044] For example, the circuit board design data may originally be stored in any one of the first terminal device 201, the second terminal device 202, or the third terminal device 203 (e.g., the first terminal device 201, but not limited thereto), or it may be stored on an external storage device and imported into the first terminal device 201. Then, the first terminal device 201 may locally execute the circuit board test point determination method provided in the embodiments of this application, or send the circuit board design data to other terminal devices, servers, or server clusters, and have the other terminal devices, servers, or server clusters that receive the circuit board design data execute the circuit board test point determination method provided in the embodiments of this application.

[0045] It should be understood that Figure 2 The number of first terminal devices, second terminal devices, third terminal devices, networks, and servers shown in the diagram is merely illustrative. Depending on implementation needs, any number of terminal devices, networks, and servers can be included.

[0046] The following will be based on Figure 2 The described scene, through Figures 3-7 The method for determining circuit board test points according to embodiments of this application will be described in detail.

[0047] Figure 3A flowchart of a method for determining circuit board test points according to an embodiment of this application is shown.

[0048] like Figure 3 As shown, the circuit board test point determination method of this embodiment includes operations S310 to S340.

[0049] In operation S310, the test point determination program acquires design data for the target circuit board, wherein the design data includes physical information of at least one routing network.

[0050] Design data can include complete design files for the PCB that needs to be analyzed or tested. For example, design data can include PCB schematics, PCB layout and routing files (such as traces, vias, layer stack-up structures, etc.), netlists (such as electrical connection definitions for trace networks), and design constraints (such as high-speed signal length matching, impedance requirements, etc.).

[0051] A trace network can be an electrical path on a PCB that connects multiple component pins. For example, if an output pin of one component is connected to an input pin of another component, this entire path is a trace network.

[0052] Physical information may include at least one of the following: name, attribute information. Attribute information may include at least one of the following: routing information, signal transmission rate, etc. Routing information may include routing width, routing parallelism, routing length difference, impedance value, etc.

[0053] In operation S320, for any routing network, if the name of any routing network fails to match the first naming rule in the first naming rule library, the attribute information of any routing network is matched with the attribute rule to obtain the attribute matching result.

[0054] In operation S330, based on the above attribute matching results, the network type of any of the above routing networks is determined, wherein the network type is one of the first type network and the second type network.

[0055] A name is a unique identifier for a routing network, usually a text string, assigned by the designer when drawing circuit diagrams or defining system architecture. The name generally reflects information such as the network's function and attributes.

[0056] The first naming rule library can be a predefined naming rule library for high-speed signal networks, used to determine prohibited layout networks. The first naming rule can be a naming rule specific to high-speed signal networks. The first naming rule can be a protocol identifier (such as PCIe, DDR) or a function description (such as TX) in the name, used to match a class of names. For example, the first naming rule could be "PCIe" to match all high-speed signal networks containing "PCIe". The first naming rule could also be "DDR" to match all high-speed signal networks containing "DDR". The first naming rule could also be "TX" to match all high-speed signal networks containing "TX".

[0057] For example, networks with names including PCIe, DDR, and TX are high-speed signal networks; networks with names including VCC and GND are power networks. PCIe is an abbreviation for Peripheral Component Interconnect Express, a high-speed serial point-to-point differential signal interface used to connect high-performance peripherals. DDR is an abbreviation for Double Data Rate. TX is an abbreviation for Transmit, referring to the signal at the data transmitting end; in high-speed serial protocols, TX is typically a differential pair. VCC is the circuit's supply voltage. GND is an abbreviation for Grounded, the common reference point of the circuit, serving as the reference for all voltages.

[0058] Matching the name of any trace network against the first naming rule in the first naming rule library can be achieved quickly using regular expressions. In PCB design, trace networks can be classified into different types based on their electrical characteristics and functions. Common network types include: high-speed signal networks, power networks, and ordinary low-speed signal networks. High-speed signal networks are characterized by high frequency (e.g., >100MHz), strict impedance control (e.g., differential 100Ω), and timing sensitivity. Power networks are characterized by carrying large currents, requiring low noise, and having multiple nodes. Ordinary low-speed signal networks are characterized by low frequency (e.g., <10MHz) and no strict impedance requirements.

[0059] Matching the attribute information of any routing network with attribute rules to obtain attribute matching results, and determining the network type of any routing network based on the attribute matching results may include: extracting the attribute information of the routing network, matching at least one of the attribute information, such as routing information and signal transmission rate, with the corresponding attribute rules, and classifying the routing network based on the matching results.

[0060] Attribute rules can include routing rules and rate rules. If the physical information includes routing information, the routing information is matched with the routing rules to obtain the routing matching result, which includes the routing matching result.

[0061] For example, routing information can be extracted from the routing network, and the routing network can be classified according to the routing information. For example, a high-speed signal network can be defined as a network where the parallelism of two traces is greater than or equal to 95%; a high-speed signal network can be defined as a network where the difference in trace length is less than or equal to 50 mil; and a high-speed signal network can be defined as a network with an impedance value of 85Ω±10% or 100Ω±10%.

[0062] If the physical information includes the signal transmission rate, then the signal transmission rate is matched with the rate rules to obtain the rate matching result. In this case, the matching result includes the rate matching result. For example, the signal transmission rate of a cabling network can be extracted, and the cabling network can be classified according to the signal transmission rate. For instance, a signal transmission rate greater than or equal to 10Gbps is classified as a high-speed signal network; a signal transmission rate less than 10Gbps is classified as a normal low-speed signal network.

[0063] In operation S340, in response to any trace network being a second type of network, the test point location for any trace network is determined according to the test point layout rules and the position of any trace network relative to the target board.

[0064] The second type of network can be a pre-defined network type that allows for the placement of test points. For example, the second type of network can include power networks and ordinary low-speed signal networks.

[0065] Test point layout rules can include priority layout locations, such as prioritizing layout on the surface trace path, and adding in the via area when the surface trace path cannot be added (e.g., the surface trace path is located in a prohibited layout area) or there is insufficient space to add.

[0066] Test point layout rules can also include layout rules for power networks, such as test points on the power network being evenly distributed on the power copper foil or trace paths at the power input and output ends.

[0067] The position of any trace network relative to the target circuit board can be determined by the physical distribution and path of the trace network's traces on the PCB. Only by knowing the specific location of the trace network can available spaces be found on or near it to add test points.

[0068] In response to any trace network being a second type of network, the test point layout rules and the position of any trace network relative to the target circuit board may include: when the trace network is a normal low-speed signal network, it indicates that test points are allowed to be laid out on the trace network. In this case, the test point position can be determined according to the test point layout rules and the position of the trace network relative to the target circuit board.

[0069] According to an embodiment of this application, the above method further includes: if the name of any routing network successfully matches a first naming rule in a first naming rule library, determining that any routing network is a first type network, marking the any routing network as a prohibited layout network, and not laying test points on the routing network.

[0070] This application employs a technical solution that acquires name and attribute information from circuit board design data, matches the name and attribute information sequentially, automatically identifies the network type of the routing network based on the matching results, and then intelligently determines the test point location for routing networks belonging to the second type by combining test point layout rules and the location of the routing network. This solution can automatically exclude first-type networks, such as prohibited layout networks, and accurately place test points on second-type networks, such as permitted layout networks, thereby achieving automated test point placement and helping to improve the efficiency and accuracy of circuit board testing.

[0071] According to embodiments of this application, the attribute information includes at least one of the following: routing information, signal transmission rate; the attribute rules include at least one of the following: routing rules, rate rules; and the attribute matching results include at least one of the following: routing matching results, rate matching results.

[0072] According to embodiments of this application, if the first naming rules in the first naming rule library are not maintained in a timely manner, some first-type networks may not be filtered out. In this case, attribute information can be used for re-matching. Specifically, this may include: matching routing information with routing rules to obtain routing matching results; and / or matching signal transmission rates with rate rules to obtain rate matching results.

[0073] The routing rules include at least one of the following: the parallelism of the routing is greater than or equal to a first threshold, the routing length is less than or equal to a second threshold, and the impedance value meets a preset impedance threshold; the rate rules include the signal transmission rate being greater than or equal to a preset rate threshold.

[0074] For example, routing rules include parallelism of two traces ≥95%, no obvious intersections or branches, and a trace length difference ≤50mil; impedance values ​​are 85Ω±10% and 100Ω±10%. For example, rate rules can include rate thresholds, such as a rate threshold ≥10Gbps.

[0075] According to an embodiment of this application, when the attribute matching result only includes the routing matching result, determining the network type of any routing network based on the attribute matching result may include: when the routing matching result indicates that the routing information and routing rules are successfully matched, determining the network type as a first type network.

[0076] If the routing matching result indicates that the routing information and routing rules fail to match, the network type is determined based on the rate matching result obtained by matching the signal transmission rate with the rate rules.

[0077] Determining the network type based on the rate matching result obtained by matching the signal transmission rate with the rate rule can include: if the rate matching result indicates that the signal transmission rate and the rate rule have failed to match, the network type is determined to be a first type network; if the rate matching result indicates that the signal transmission rate and the rate rule have failed to match, the network type is determined to be a second type network.

[0078] According to an embodiment of this application, when the attribute matching result only includes the rate matching result, determining the network type of any routing network based on the attribute matching result may include: if the rate matching result indicates that the signal transmission rate and the rate rule are successfully matched, determining the network type as a first type network.

[0079] If the rate matching result indicates that the signal transmission rate fails to match the rate rule, the network type is determined based on the routing matching result obtained by matching the routing information with the routing rule.

[0080] Based on the routing matching result obtained by matching routing information with routing rules, the network type can be determined as follows: if the routing matching result indicates that the routing information and routing rules are successfully matched, the network type is determined to be a first type network; if the routing matching result indicates that the routing information and routing rules are not matched, the network type is determined to be a second type network.

[0081] According to embodiments of this application, when the attribute matching result includes routing matching result and rate matching result, determining the network type of any routing network based on the attribute matching result may include: if either the routing matching result or the rate matching result is a successful match, then the routing network is determined to be a first type network. If both the routing matching result and the rate matching result are unsuccessful matches, then the routing network is determined to be a second type network.

[0082] For example, the attribute matching result includes name matching sub-result and routing matching sub-result. If the name matching sub-result indicates that the name matching failed, and the routing matching sub-result indicates that the routing matching succeeded, then it can be determined as a prohibited layout network.

[0083] For example, the matching results include name matching sub-results, routing matching sub-results, and rate matching sub-results. If the name matching sub-result indicates name matching failure, the routing matching sub-result indicates routing matching failure, and the rate matching sub-result indicates rate matching failure, then it can be determined as a permitted layout network. If the name matching sub-result indicates name matching failure, the routing matching sub-result indicates routing matching failure, but the rate matching sub-result indicates rate matching success, then it can be determined as a prohibited layout network.

[0084] According to an embodiment of this application, the running program traverses all trace networks within the PCB and performs a three-level matching of name, trace information, and signal transmission rate for each trace network. If any level of matching is successful, the network is marked as a prohibited layout network, and no test points are generated for the vias and traces associated with it; networks that fail to match are determined to be allowed layout networks.

[0085] This application achieves more accurate high-speed signal network identification by combining routing information and signal transmission rate for supplementary matching after name matching fails, and performing secondary matching through physical characteristics and electrical parameters, thus avoiding misjudgment caused by non-standard naming. In addition, based on the rapid name matching screening, supplementary matching is only performed on routing networks where name matching fails, balancing processing speed and completeness.

[0086] According to an embodiment of this application, after the running program traverses all trace networks within the PCB, the above method further includes: generating network type analysis results, which include trace network name matching results, trace information matching results, and signal transmission rate matching results; determining trace networks that meet preset conditions based on the name matching results, trace information matching results, and signal transmission rate matching results, and marking them for manual verification.

[0087] The preset condition can be a routing network where the matching conclusions of the name matching result, routing information matching result, and signal transmission rate matching result are inconsistent. For example, for the first routing network, its name matching result indicates that the name does not match, but the routing information matching result indicates that the routing information matches, and the signal transmission rate result indicates that the signal transmission rate matches. In this case, the characterization of the first routing network needs to be focused on.

[0088] By analyzing the network type results and marking the routing networks that meet the preset conditions, we can capture design anomalies in the design data (such as mistakenly naming a high-speed signal network as a regular signal network), insufficient rule base (for new network types, the naming rule base does not cover its naming pattern), and abnormal attribute definitions (such as incorrect definition of the signal transmission rate of the routing network). This helps prevent potential problems caused by incomplete rules or human negligence from flowing into the next stage.

[0089] Furthermore, by analyzing these flagged "abnormal" networks, loopholes in the rule base can be continuously discovered and patched, making the automated system increasingly intelligent and reliable.

[0090] Power signals are the energy source for all active devices on a PCB, such as the CPU and memory. Their stability directly determines whether the system can function properly. Compared to ordinary low-speed signals, power signals carry a larger current, are more sensitive to noise, and have a wider coverage area, requiring more test points to comprehensively monitor the global status of power signals. Therefore, it is necessary to further distinguish between power networks and non-power networks within the permissible layout network. Non-power networks are the routing networks other than power networks within the permissible layout network, and can be the ordinary low-speed signal networks mentioned above.

[0091] According to an embodiment of this application, the second type of network includes a power network and a non-power network; the method further includes: matching the name of any routing network with a second naming rule in a second naming rule library; in response to a successful match between the name of any routing network and the second naming rule, determining that the network type of any routing network is a power network; in response to a failure to match between the name of any routing network and the second naming rule, determining that the network type of any routing network is a non-power network.

[0092] The second naming rule library can be a naming rule library used to identify power networks. The second naming rule can be a naming rule specifically for power networks. The second naming rule can be a wildcard or a regular expression used to match the naming conventions of power networks. For example: VDD (internal operating voltage of the chip), VSS (reference ground of the chip), VCC, GND, 3V3 (3.3 volt power network), 5V (5 volt power network), etc.

[0093] It should be noted that the second naming rule library can be customized to add naming rules according to actual needs.

[0094] This application allows for further differentiation of network layout into power networks and non-power networks by matching a second naming rule library. This enables differentiated test point strategies based on network type; for example, power networks can have multiple test points evenly distributed, while non-power networks can have only one test point. Furthermore, this further differentiation allows for precise resource allocation, preventing the misuse of ordinary signal test points for power networks and reducing over-design of ordinary networks, thus achieving refined control over test point generation.

[0095] According to an embodiment of this application, when the network type of any trace network is a power network, determining the test point location for any trace network based on the test point layout rules and the position of any trace network relative to the target circuit board includes: determining the target power type in the preset power types based on the voltage information of any trace network; and determining a preset number of test point locations for any trace network based on the test point layout rules, the position of any trace network relative to the target circuit board, and a preset number for the target power type.

[0096] The preset power supply type can be a different type of power network predefined based on voltage. For example, the preset power supply type can include a high-voltage type and a low-voltage type. The high-voltage type can be a power network with a voltage greater than or equal to a preset voltage threshold; the low-voltage type can be a power network with a voltage less than a preset voltage threshold. The preset voltage threshold can be determined according to actual needs; for example, the preset voltage threshold can be 6V, 8V, 10V, etc.

[0097] Different types of power networks require different numbers of test points, and preset numbers can be configured for different power types. For example, a larger number of test points, such as 15, can be configured for high-voltage power networks, while a smaller number of test points, such as 5, can be configured for low-voltage power networks.

[0098] The system automatically matches the preset power supply type based on the voltage level and dynamically generates the corresponding number of test point layout positions, which not only meets the multi-point detection requirements of high current networks (such as reducing contact resistance) but also avoids space waste caused by excessive testing.

[0099] Figure 4 A flowchart illustrating the determination of network type according to an embodiment of this application is shown.

[0100] like Figure 4 As shown, the determination of network type in this embodiment includes operations S410 to S490.

[0101] The S410 is used to obtain the physical information of the routing network. This physical information includes the name, routing information, and signal transmission rate.

[0102] In operation S420, it is determined whether the name matches the first naming rule. If they do not match, operation S430 is executed; if they match, operation S490 is executed.

[0103] In operation S430, it is determined whether the routing information matches the routing rules. If they do not match, operation S440 is executed; if they match, operation S490 is executed.

[0104] In operation S440, it is determined whether the signal transmission rate is greater than or equal to the rate threshold. If it is less than the threshold, operations S450 to S480 are executed; if it is greater than or equal to the threshold, operation S490 is executed.

[0105] In operation S450, determine the network type of any routing network as a second type network.

[0106] In operation S460, it is determined whether the name matches the second naming rule. If they do not match, operation S470 is executed; if they match, operation S480 is executed.

[0107] In operation S470, determine that the network type of any routing network is a non-power network.

[0108] In operation S480, determine the network type of any routing network as a power network.

[0109] In operation S490, the network type of any routing network is determined to be a first type network.

[0110] The program runs through all trace networks within the PCB, and after classifying them by type, it proceeds to the next stage: determining the test point locations.

[0111] The following is combined Figure 5 The process of determining the location of the test points is explained in detail.

[0112] According to embodiments of this application, the design data includes prohibited layout areas.

[0113] Figure 5 A schematic diagram illustrating the determination of test point locations according to an embodiment of this application is shown.

[0114] like Figure 5 As shown, this embodiment illustrates a schematic diagram of determining test point locations for any routing network 510. Specifically, it includes: determining a permissible layout area 550 for any routing network 510 based on the relative position 520 of any routing network 510 relative to the target circuit board and the prohibited layout area 530 in the design data; and then determining the test point location 560 for any routing network 510 within the permissible layout area 550 according to the test point layout rule 540.

[0115] A prohibited layout region is a predefined area on a PCB design containing prohibited layout test points, for example... Figure 1 The regions shown are 121, 122, and 123.

[0116] Prohibited layout areas generally include:

[0117] Component physical area: especially the area beneath tall components, which is inaccessible to test probes.

[0118] Mounting hole / mechanical fastener area: No electronic objects should be placed around screw holes, brackets, etc.

[0119] Board edges and cutout areas: Test points cannot be reliably placed too close to the board edges or internal cutout areas.

[0120] By combining the actual routing locations and prohibited layout areas of the routing network, all unusable spaces are first intelligently eliminated, and the allowed layout area corresponding to the routing network is accurately calculated. Then, within this safe area, the optimal test point location is automatically determined according to the test point layout rules. This method effectively ensures the physical manufacturability and accessibility of the test points, as well as minimal impact on the integrity of the original circuit signals, achieving automated and precise test point layout.

[0121] According to embodiments of this application, the permitted layout area may include at least one of the following: a trace path area, a via area.

[0122] Determining the test point location within the allowed layout area, based on the test point layout rules and the position of any trace network relative to the target circuit board, may further include: determining the test point location in the trace path area if the allowed layout area includes the trace path area; and determining the test point location in the via area if the allowed layout area does not include the trace path area, or if the trace path area does not meet the test point layout conditions.

[0123] The cabling path area refers to the physical area occupied by the conductors (such as copper wires) of the cabling network itself and the available safe space in its vicinity. That is, the wire itself and the area around it.

[0124] A via is a vertical channel connecting different PCB layers. The via area refers to the physical area occupied by the pads of the vias used in the routing network and the available safety space nearby.

[0125] Test point layout conditions can include whether there is enough space, such as whether the trace itself is wide enough, or whether there is enough space next to it to place a test pad without violating the spacing rules.

[0126] By prioritizing the addition of test points in the routing path area of ​​the trace network, superior electrical performance and simplicity can be ensured. When the routing path area does not exist or cannot meet the layout conditions such as space and spacing, the via area of ​​the trace network is automatically selected to add test points. This ensures automated layout of test points and intelligently selects the best or feasible location with the least impact on the original design within a limited space, effectively balancing testability, signal integrity and manufacturing feasibility.

[0127] According to embodiments of this application, the via region includes at least one via; determining the test point location in the via region may include achieving a tangential layout between the test point and the via through dynamic geometric calculation. Specifically, this may include: determining test point routing information based on the via size information of the target via and the test point size information in at least one via; and determining the test point location based on the test point routing information.

[0128] The target via can be a specific via selected from the via region, serving as the object to be connected to by the test point. It can be any via within the region.

[0129] Via size information may include the diameter of the via pad. Test point size information may include the diameter of the test point pad.

[0130] The test point routing information includes the test point routing length and the test point routing angle. The test point routing angle is the angle between the signal routing connected to the target via and the test point routing.

[0131] A test point trace is a branch path that extends from the trace network to connect test points.

[0132] The test point trace length is the physical length of the test point trace.

[0133] The following is combined Figure 6 Further discussion is needed regarding the length and angle of the test point traces in the United States.

[0134] Figure 6 A schematic diagram of adding test points according to an embodiment of this application is shown.

[0135] like Figure 6 As shown, in this embodiment, a test point 630 is added near the via 620 of the trace network 610 to which the test point is to be added. The line connecting the center of the test point 630 and the center of the via 620 is the test point trace 640, and the angle α between the trace network 610 to which the test point is to be added and the test point trace 640 is the test point trace angle.

[0136] According to an embodiment of this application, determining the test point routing information based on the via size information and test point size information of the target via in at least one via includes: determining the distance between the center of the target via and the center of the test point when the target via is connected to the test point, and determining the distance as the test point routing length; determining the test point routing angle based on the test point routing length and a preset included angle condition.

[0137] When determining that the target via is connected to the test point, the distance between the center of the target via and the center of the test point can be the distance between the centers of the circles when the target via and the test point are tangent.

[0138] For example, the target via diameter is D, the test point diameter is d, and the test point trace length is (D / 2) + (d / 2), where d can be configured according to the actual situation.

[0139] In some embodiments, the preset angle condition includes an angle greater than or equal to 90° between the signal trace and the test point trace of the target via. During PCB manufacturing etching, residual chemicals can easily remain at the angle, leading to short circuits or signal integrity issues. Therefore, the preset angle condition can be greater than or equal to 90°, preferably 90°.

[0140] In other embodiments, the preset included angle condition may also be: Figure 6 The included angle shown satisfy ≥0;

[0141] in, Indicates the direction in which the network signal is connected to the target via. Indicates the direction of the line connecting the target via and the test point. for and The included angle, This means that the angle between the test point trace and the network signal trace is not acute.

[0142] Determining the test point routing angle based on the test point routing length and preset angle conditions can include: prioritizing adding a test point at a position where the test point routing angle is 90°. If there is a conflict at this position, the test point routing length can be kept unchanged, the test point routing angle can be adjusted, and the test point position can be redefined. This process can be repeated until the conflict is eliminated.

[0143] A conflict could be caused by another component's pad, another trace, a via, or a violation of minimum spacing rules.

[0144] Adjusting the test point routing angle can include increasing the test point routing angle, for example, increasing the test point routing angle by ≤5°.

[0145] By calculating the required center-to-center distance when the target via diameter and the test point diameter are tangentially connected, this geometric distance is directly determined as the test point trace length. Then, a 90° perpendicular routing scheme is initially prioritized to ensure signal integrity and process compliance. When this location conflicts with other components, traces, or vias due to insufficient spacing, a small-step, incremental strategy is used to fine-tune the routing angle and recalculate the position, while maintaining the test point trace length. This process is iterated until a conflict-free feasible location is found. This method automatically generates a tangential layout scheme that ensures the shortest electrical connection, minimal impact on signal integrity, and meets manufacturing process requirements, achieving dual optimization of test point layout in terms of both space and electrical performance.

[0146] According to embodiments of this application, the above method may further include: after the test points are determined, outputting a PCB test point coverage report, wherein the test point coverage report may include test point configuration parameters (such as test point size information), an overall overview of test point addition such as the total number of networks covered by high-speed network signals, power signals, and ordinary low-speed signal networks, and the number of test points successfully added; it may also include the test point coverage rate on surface traces, the via tangent test point coverage rate; and it may also include details of trace networks without added test points, providing a basis for subsequent optimization.

[0147] This application's embodiment achieves closed-loop quality management and data-driven optimization of the design process by automatically generating a PCB test point coverage report after test point placement. This report not only records test point configuration parameters and adds an overall overview, but also deeply evaluates the effectiveness and manufacturability of the placement strategy through quality indicators such as surface test point coverage and via tangency coverage, and accurately exposes a detailed list of uncovered nets. This function transforms automated placement results into quantifiable insights, directly providing a basis for decision-making regarding design rule iteration, priority adjustment, and targeted manual intervention, significantly improving the testability design level and continuous optimization efficiency of PCBs.

[0148] Figure 7 A flowchart of a method for determining circuit board test points according to another embodiment of this application is shown.

[0149] like Figure 7 As shown, the method for determining the test points on the circuit board in this embodiment includes operations S710 to S760.

[0150] When operating the S710, the program is loaded and run in the command window to obtain the physical information of the wiring network.

[0151] In operation S720, the network type is determined based on the physical information. When the network type is a prohibited layout network, operation S731 is executed; when the network type is a power network, operations S741 to S743 are executed; when the network type is a non-power network, operations S751 to S755 are executed.

[0152] When operating S731, mark the routing network as a prohibited layout network.

[0153] When operating the S741, mark the routing network as the power network.

[0154] When operating the S742, determine the number of test points corresponding to the power network.

[0155] When operating the S743, add test points evenly on the power network according to the number of test points.

[0156] When operating the S751, mark the routing network as a non-power network.

[0157] In operation S752, determine whether there is a trace area in the non-power network. If it exists, proceed to operation S753; otherwise, proceed to operation S755.

[0158] In operation S753, determine if the routing area meets the test point layout conditions. If it does, proceed to operation S754; otherwise, proceed to operation S755.

[0159] When operating the S754, add test points in the trace area.

[0160] When operating the S755, add a test point in the via area and make the test point tangent to the via.

[0161] In operation S760, based on the execution results of operations S731, S743, S754, and S755, a test point coverage report is generated and output.

[0162] The method for automatically generating test points tangent to vias in this application can accurately exclude high-speed signal networks, avoid signal reflection and impedance discontinuity caused by adding test points, and solve the problem of high omission rate of manual marking in related technologies. In addition, the tangent layout of vias and test points in the space-constrained PCB minimizes stubs and improves signal stability. At the same time, the tangent layout allows test points and vias to share the surrounding space, maximizing the utilization of space within the PCB. Furthermore, after the entire process of adding test points is automated, a test point coverage report is output, which improves design efficiency, saves manpower, and avoids omissions and misjudgments.

[0163] Based on the above-described method for determining circuit board test points, this application also provides a device for determining circuit board test points. The following will be combined with... Figure 8 The device is described in detail.

[0164] Figure 8 A structural block diagram of a circuit board test point determination device according to an embodiment of this application is shown.

[0165] like Figure 8 As shown, the circuit board test point determination device 800 of this embodiment includes an acquisition module 810, a matching module 820, a first determination module 830, and a second determination module 840.

[0166] The acquisition module 810 is used to acquire design data for the target circuit board, wherein the design data includes physical information of at least one routing network, and the physical information includes at least one of the following: name and attribute information. In one embodiment, the acquisition module 810 can be used to perform the operation S310 described above, which will not be repeated here.

[0167] The matching module 820 is used to match the attribute information of any routing network with attribute rules if the name of any routing network fails to match the first naming rule in the first naming rule library, thereby obtaining an attribute matching result. In one embodiment, the matching module 820 can be used to perform the operation S320 described above, which will not be repeated here.

[0168] The first determining module 830 is used to determine the network type of any of the above-mentioned routing networks based on the attribute matching results, wherein the network type is one of a first type network and a second type network. In one embodiment, the first determining module 830 can be used to perform the operation S330 described above, which will not be repeated here.

[0169] The second determining module 840 is configured to, in response to the fact that any of the aforementioned trace networks is a second type of network, determine the test point positions for any of the aforementioned trace networks based on the test point layout rules and the position of any of the aforementioned trace networks relative to the aforementioned target circuit board. In one embodiment, the second determining module 840 may be used to perform the operation S340 described above, which will not be repeated here.

[0170] According to embodiments of this application, the attribute information includes at least one of the following: routing information, signal transmission rate; the attribute rules include at least one of the following: routing rules, rate rules; and the attribute matching results include at least one of the following: routing matching results, rate matching results.

[0171] According to an embodiment of this application, the matching module 820 includes: a first matching submodule and a second matching submodule.

[0172] The first matching submodule is used to match routing information with routing rules to obtain routing matching results.

[0173] The second matching submodule is used to match the signal transmission rate with the rate rule to obtain the rate matching result.

[0174] According to an embodiment of this application, the first determining module 830 includes: a first determining submodule and a second determining submodule.

[0175] The first determination submodule is used to determine the network type based on the rate matching result obtained by matching the signal transmission rate with the rate rule when the attribute matching result includes the routing matching result and the routing matching result indicates that the routing information and routing rules have failed to match.

[0176] The second determination submodule is used to determine the network type based on the routing matching result obtained by matching routing information with routing rules when the attribute matching result includes the rate matching result and the rate matching result represents the signal transmission rate and the rate rule fails to match.

[0177] According to embodiments of this application, the second type of network includes a power network and a non-power network.

[0178] According to an embodiment of this application, the circuit board test point determination device further includes: a third matching submodule, a third determination submodule, and a fourth determination submodule.

[0179] The third matching submodule is used to match the name of any routing network with the second naming rule in the second naming rule library.

[0180] The third determination submodule is used to determine the network type of any trace network as a power network in response to a successful match between the name of any trace network and the second naming rule.

[0181] The fourth determination submodule is used to determine that the network type of any trace network is a non-power network in response to the failure of any trace network name to match the second naming rule.

[0182] According to an embodiment of this application, the second determining module 840 includes a fifth determining submodule and a sixth determining submodule.

[0183] The fifth determination submodule is used to determine the target power type from the preset power types based on the voltage information of any trace network when the network type of any trace network is a power network.

[0184] The sixth determination submodule is used to determine the preset number of test point positions for any trace network based on the test point layout rules, the position of any trace network relative to the target circuit board, and the preset number for the target power type.

[0185] According to embodiments of this application, the design data includes prohibited layout areas.

[0186] According to an embodiment of this application, the second determining module 840 includes a seventh determining submodule and an eighth determining submodule.

[0187] The seventh determination submodule is used to determine the allowed layout area for any routing network based on the prohibited layout area.

[0188] The eighth determination submodule is used to determine the test point location within the allowed layout area based on the test point layout rules and the position of any trace network relative to the target circuit board.

[0189] According to embodiments of this application, the permitted layout area may include at least one of the following: a trace path area, a via area.

[0190] According to an embodiment of this application, the tenth determining submodule includes: a first determining component and a second determining component.

[0191] The first component unit is used to determine the location of test points in the wiring path area, provided that the layout area is allowed to include the wiring path area.

[0192] The second component unit is used to determine the test point location in the via area when the allowed layout area does not include the routing path area, or the routing path area does not meet the test point layout conditions.

[0193] According to an embodiment of this application, the via region includes at least one via.

[0194] According to an embodiment of this application, the second determining component includes: a first determining unit and a second determining unit.

[0195] The first determining unit is used to determine the test point routing information based on the via size information of the target via and the test point size information of at least one via.

[0196] The second determining unit is used to determine the location of the test point based on the test point routing information.

[0197] According to an embodiment of this application, the test point routing information includes the test point routing length and the test point routing angle, wherein the test point routing angle is the angle between the signal routing connecting the target via and the test point routing.

[0198] According to an embodiment of this application, the first determining unit includes: a first determining subunit and a second determining subunit.

[0199] The first determining subunit is used to determine the distance between the center of the target via and the center of the test point when the target via is connected to the test point, based on the via size information and the test point size information, and to determine the distance as the test point trace length.

[0200] The second determining subunit is used to determine the test point routing angle based on the test point routing length and preset angle conditions, wherein the preset angle conditions include an angle between the signal routing of the target via and the test point routing greater than or equal to 90°.

[0201] According to embodiments of this application, any multiple modules among the acquisition module 810, matching module 820, first determination module 830, and second determination module 840 can be combined into one module, or any one of these modules can be split into multiple modules. Alternatively, at least some of the functions of one or more of these modules can be combined with at least some of the functions of other modules and implemented in one module. According to embodiments of this application, at least one of the acquisition module 810, matching module 820, first determination module 830, and second determination module 840 can be at least partially implemented as hardware circuitry, such as a field-programmable gate array (FPGA), a programmable logic array (PLA), a system-on-a-chip, a system-on-a-substrate, a system-on-package, an application-specific integrated circuit (ASIC), or implemented in hardware or firmware by any other reasonable means of integrating or packaging the circuitry, or implemented in any one of the three implementation methods of software, hardware, and firmware, or in a suitable combination of any of these. Alternatively, at least one of the acquisition module 810, matching module 820, first determination module 830 and second determination module 840 may be implemented at least partially as a computer program module, which can perform corresponding functions when the computer program module is run.

[0202] Figure 9 A block diagram of an electronic device suitable for implementing a circuit board test point determination method according to an embodiment of this application is shown.

[0203] like Figure 9 As shown, an electronic device 900 according to an embodiment of this application includes a processor 901, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 902 or a program loaded from a storage portion 908 into a random access memory (RAM) 903. The processor 901 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 901 may also include onboard memory for caching purposes. The processor 901 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of this application.

[0204] RAM 903 stores various programs and data required for the operation of electronic device 900. Processor 901, ROM 902, and RAM 903 are interconnected via bus 904. Processor 901 executes various operations of the method flow according to embodiments of this application by executing programs in ROM 902 and / or RAM 903. It should be noted that the programs may also be stored in one or more memories other than ROM 902 and RAM 903. Processor 901 may also execute various operations of the method flow according to embodiments of this application by executing programs stored in said one or more memories.

[0205] According to embodiments of this application, the electronic device 900 may further include an input / output (I / O) interface 905, which is also connected to a bus 904. The electronic device 900 may also include one or more of the following components connected to the input / output (I / O) interface 905: an input section 906 including a keyboard, mouse, etc.; an output section 907 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 908 including a hard disk, etc.; and a communication section 909 including a network interface card such as a LAN card, modem, etc. The communication section 909 performs communication processing via a network such as the Internet. A drive 910 is also connected to the input / output (I / O) interface 905 as needed. A removable medium 911, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 910 as needed so that computer programs read from it can be installed into the storage section 908 as needed.

[0206] This application also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into the device / apparatus / system. The computer-readable storage medium carries one or more programs, which, when executed, implement the method according to the embodiments of this application.

[0207] According to embodiments of this application, the computer-readable storage medium can be a non-volatile computer-readable storage medium, such as including but not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this application, the computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to embodiments of this application, the computer-readable storage medium may include ROM 902 and / or RAM 903 and / or one or more memories other than ROM 902 and RAM 903 described above.

[0208] Embodiments of this application also include a computer program product comprising a computer program containing program code for performing the methods shown in the flowchart. When the computer program product is run on a computer system, the program code is used to cause the computer system to implement the methods provided in the embodiments of this application.

[0209] When the computer program is executed by the processor 901, it performs the functions defined in the system / apparatus of this application embodiment. According to the embodiments of this application, the systems, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0210] In one embodiment, the computer program may rely on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may also be transmitted and distributed in the form of signals over a network medium, and downloaded and installed via the communication section 909, and / or installed from a removable medium 911. The program code contained in the computer program can be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination thereof.

[0211] In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 909, and / or installed from the removable medium 911. When the computer program is executed by the processor 901, it performs the functions defined in the system of this application embodiment. According to the embodiments of this application, the systems, devices, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0212] According to embodiments of this application, program code for executing the computer programs provided in the embodiments of this application can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C", or similar programming languages. The program code can be executed entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0213] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0214] Those skilled in the art will understand that the features described in the various embodiments of this application can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this application. In particular, the features described in the various embodiments of this application can be combined and / or combined in various ways without departing from the spirit and teachings of this application. All such combinations and / or combinations fall within the scope of this application.

[0215] The embodiments of this application have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of this application. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Without departing from the scope of this application, those skilled in the art can make various substitutions and modifications, all of which should fall within the scope of this application.

Claims

1. A method for determining test points on a circuit board, characterized in that, The method includes: The test point determination program acquires design data for the target circuit board, wherein the design data includes physical information of at least one routing network, and the physical information includes at least one of the following: name and attribute information; For any routing network, if the name of any routing network fails to match the first naming rule in the first naming rule library, the attribute information of any routing network is matched with the attribute rule to obtain the attribute matching result. Based on the attribute matching results, the network type of any routing network is determined, wherein the network type is one of a first type network and a second type network; and In response to the fact that the network type of any of the trace networks is a second type network, the test point positions for any of the trace networks are determined according to the test point layout rules and the position of any of the trace networks relative to the target circuit board.

2. The method according to claim 1, characterized in that, The attribute information includes at least one of the following: routing information, signal transmission rate; the attribute rules include at least one of the following: routing rules, rate rules; and the attribute matching results include at least one of the following: routing matching results, rate matching results. The step of matching the attribute information of any routing network with attribute rules to obtain the attribute matching result includes: Match the routing information with the routing rules to obtain the routing matching result; and / or The signal transmission rate is matched with the rate rule to obtain the rate matching result.

3. The method according to claim 2, characterized in that, Determining the network type of any routing network based on the attribute matching result includes: If the attribute matching result includes the routing matching result, and the routing matching result indicates that the routing information fails to match the routing rule, the network type is determined based on the rate matching result obtained by matching the signal transmission rate with the rate rule. If the attribute matching result includes the rate matching result, and the rate matching result indicates that the signal transmission rate fails to match the rate rule, the network type is determined based on the routing matching result obtained by matching the routing information with the routing rule.

4. The method according to any one of claims 1 to 3, characterized in that, The second type of network includes power networks and non-power networks; The method further includes: Match the name of any of the routing networks with the second naming rule in the second naming rule library; In response to the successful match between the name of any of the routing networks and the second naming rule, the network type of any of the routing networks is determined to be a power network; In response to the failure of any routing network name to match the second naming rule, the network type of any routing network is determined to be a non-power network.

5. The method according to claim 4, characterized in that, When the network type of any of the trace networks is a power network, determining the test point locations for any trace network based on the test point layout rules and the position of any trace network relative to the target circuit board includes: Based on the voltage information of any of the routing networks, determine the target power type among the preset power types; Based on the test point layout rules, the position of any trace network relative to the target circuit board, and the preset number for the target power type, a preset number of test point positions are determined for any trace network.

6. The method according to claim 1, characterized in that, The design data includes prohibited layout areas; Determining the test point location for any trace network based on the test point layout rules and the position of any trace network relative to the target circuit board includes: Based on the prohibited layout area, determine the permitted layout area for any of the routing networks; The test point location is determined in the allowed layout area based on the test point layout rules and the position of any trace network relative to the target circuit board.

7. The method according to claim 6, characterized in that, The permitted layout area includes at least one of the following: a trace path area, a via area; Determining the test point location within the allowed layout area based on the test point layout rules and the position of any trace network relative to the target circuit board includes: If the permitted layout area includes the wiring path area, the test point location is determined in the wiring path area. If the allowed layout area does not include the trace path area, or if the trace path area does not meet the test point layout conditions, the test point location is determined in the via area.

8. The method according to claim 7, characterized in that, The via region includes at least one via; Determining the test point location in the via region includes: Based on the via size information of the target via and the test point size information of the at least one via, the test point routing information is determined; The location of the test point is determined based on the wiring information of the test point.

9. The method according to claim 8, characterized in that, The test point routing information includes the test point routing length and the test point routing angle, wherein the test point routing angle is the angle between the signal routing connecting the target via and the test point routing. Based on the via size information of the target via and the test point size information in the at least one via, the test point routing information is determined as follows: Based on the via size information and the test point size information, determine the distance between the center of the target via and the center of the test point when the target via is connected to the test point, and determine the distance as the trace length of the test point; The test point routing angle is determined based on the test point routing length and a preset angle condition, wherein the preset angle condition includes an angle between the signal routing of the target via and the test point routing greater than or equal to 90°.

10. An electronic device, comprising: One or more processors; Memory, used to store one or more computer programs. The characteristic feature is that the one or more processors execute the one or more computer programs to implement the steps of the method according to any one of claims 1 to 9.

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