Solder offset reduction for integrated circuit package

Abstract

The invention discloses solder offset reduction for integrated circuit packages. In some embodiments, a packaged integrated circuit includes a bottom pad, a main semiconductor die having a bottom side attached to the bottom pad and a top side including stress sensitive circuitry fabricated thereon, and a stress relief die attached to the top side of the main semiconductor die. The stress relief die is used to provide stress relief that places the stress sensitive circuit at or near a stress neutral region of a package that is affected by deformation caused by a solder process.

Description

TECHNICAL FIELD

[0001] The field generally relates to electronics, and more specifically to packaging integrated circuits. BACKGROUND

[0002] Integrated circuits are typically packaged to couple to larger electronic systems by attaching an integrated circuit die to a package substrate and encapsulating the integrated circuit die with a molding material. Some of the electronic circuits in the integrated circuit die can be sensitive to stress, temperature, humidity, and / or other factors that can negatively impact the performance of the electronic circuits. Packages have been developed to protect the integrated circuit die and facilitate connection to the larger system. However, in some cases, the package can negatively impact the performance of the sensitive electronic circuitry. SUMMARY

[0003] Aspects of the present disclosure relate to eliminating package stresses caused by a soldering process of a packaged integrated circuit. In certain embodiments, a packaged integrated circuit includes a bottom pad, a main semiconductor die having a bottom side attached to the bottom pad and a top side including a stress-sensitive circuit fabricated thereon, and a stress-elimination die attached to the top side of the main semiconductor die. The stress-elimination die is used to provide stress elimination that places the stress-sensitive circuit at or near a stress-neutral region of the package that is affected by deformation caused by the soldering process. Such solder stress-elimination techniques provide an economically effective way to reduce and / or eliminate performance degradation of the packaged integrated circuit due to the soldering process.

[0004] In one aspect, an integrated circuit package includes a bottom pad, a main semiconductor die having a first side attached to the bottom pad and a second side including a stress-sensitive circuit, and a stress-elimination die attached to the second side of the main semiconductor die. The stress-elimination die is used to provide stress elimination resulting from soldering the integrated circuit package to a circuit board.

[0005] In another aspect, an electronic system includes a circuit board and an integrated circuit package soldered to the circuit board. The integrated circuit package includes a bottom pad, a main semiconductor die having a first side attached to the bottom pad and a second side including a stress-sensitive circuit, and a stress-elimination die attached to the second side of the main semiconductor die. The stress-elimination die is used to provide stress elimination resulting from soldering the integrated circuit package to the circuit board.

[0006] In another aspect, a method of packaging an integrated circuit includes attaching a bottom side of a main semiconductor die to a bottom pad, attaching a stress-elimination die to a top side of the main semiconductor die, the top side including a stress-sensitive circuit, and providing stress elimination resulting from soldering the bottom pad to a circuit board using the stress-elimination die. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1A is a schematic cross-sectional view of one example of a packaged integrated circuit.

[0008] Figure 1B is a schematic cross-sectional view of one example of a packaged integrated circuit. Figure 1A

[0009] Figure 2A is a schematic cross-sectional view of a packaged integrated circuit according to one embodiment.

[0010] Figure 2B is a schematic cross-sectional view of one example of a packaged integrated circuit. Figure 2A

[0011] Figure 3 is a schematic plan view of a packaged integrated circuit according to one embodiment.

[0012] Figure 4 is a schematic circuit diagram of a stress sensitive circuit according to one embodiment.

[0013] Figure 5 is a graph of one example of measured solder shift versus simulated solder stress.

[0014] Figure 6A is a schematic cross-sectional view of an electronic system according to one embodiment.

[0015] Figure 6B is a graph of one example of reference voltage shift versus circuit board strain or bending.

[0016] Figure 7 is a schematic cross-sectional view of a packaged integrated circuit according to another embodiment. DETAILED DESCRIPTION

[0017] The following detailed description of embodiments presents various descriptions of specific embodiments of the present application. However, the present application can be embodied in many different forms. In this description, reference is made to the drawings, where like numbers can indicate like or similar elements throughout the several figures. It will be understood that the figures are not necessarily drawn to scale. Additionally, it should be understood that certain embodiments can include more elements and / or subsystems than graphically represented in a figure. Furthermore, some embodiments can incorporate elements from two or more figures in any suitable combination.

[0018] Mechanical stresses of soldering a packaged integrated circuit (also referred to herein as a package) to a circuit board can cause package stress, resulting in distortion.

[0019] ​​For example, a packaged integrated circuit can include a semiconductor die and various packaging structures, each of which has different rates of thermal expansion and contraction. Moreover, after such a package undergoes extreme soldering high temperatures (e.g., a lead-free infrared reflow profile with a peak temperature of 260 °C or higher), the package can deform. Inexpensive packages, such as quad flat no-lead (QFN) packages, exhibit particularly large package warpage due to mechanical deformation after the soldering process.

[0020] Package deformation can degrade the performance of a packaged integrated circuit that includes stress-sensitive circuitry, such as a voltage reference. For example, warpage in a packaged integrated circuit that includes a voltage reference (e.g., a bandgap reference circuit) can cause the post-soldering output reference voltage to shift.

[0021] Various embodiments disclosed herein relate to eliminating package stress caused by a soldering process of a packaged integrated circuit. In certain embodiments, a packaged integrated circuit includes a bottom pad, a main semiconductor die having a bottom side attached to the bottom pad and a top side that includes stress-sensitive circuitry fabricated thereon, and a stress-elimination die attached to the top side of the main semiconductor die. The stress-elimination die is used to provide stress elimination that places the stress-sensitive circuitry at or near a stress-neutral region of the package that is affected by deformation caused by the soldering process.

[0022] In certain implementations, the stress-elimination die is implemented as a thick dummy die that is much thicker than a thin main die that includes the stress-sensitive circuitry system. The stack of the bottom pad, the thin main die, and the thick dummy die can cause the stress-sensitive circuitry to be located closer to the stress-neutral region.

[0023] For example, the stress-neutral region can correspond to one or more points and / or axes in the deformation beam where tensile stress and compressive stress cancel each other out. Moreover, the dummy die and the main die can form a composite that approximates the single-beam property. When the dummy die and the main die are formed of the same material (e.g., a semiconductor, such as silicon), both have the same coefficient of thermal expansion (CTE). Moreover, the dummy die protects the main die from bulk and local molding compound stress, while the local stress is mainly due to particles (e.g., silica particles) in the molding compound.

[0024] The soldering stress-elimination techniques herein provide an economically effective way to reduce and / or eliminate performance degradation of a packaged integrated circuit due to a soldering process.

[0025] Figure 1A is a schematic cross-sectional view of an example of a packaged integrated circuit 20. The packaged integrated circuit 20 includes a bottom pad 1, a semiconductor die 5, a molding material or encapsulation 7, a bottom pad soldering region 8, a bond wire 9, a die attach 11, a die pad 16, a package lead 17, and a package lead soldering region 18.

[0026] like Figure 1A As shown, semiconductor die 5 includes stress-sensitive circuit 15 fabricated thereon.

[0027] Figure 1B yes Figure 1A FIG. 1 is a schematic cross-sectional view of an example of a packaged integrated circuit 20 after soldering.

[0028] like Figure 1B As shown, the extremely high temperatures of the soldering process cause the packaged integrated circuit 20 to deform or warp.

[0029] Deformation of the packaged integrated circuit 20 may be caused by the semiconductor die 5 and the various packaging structures (eg, the foot pad 1 and / or the molding material 7 ), each of which has different rates of thermal expansion and contraction.

[0030] The different rates of thermal expansion and contraction result in compressive forces 21 near the top of semiconductor die 5 and tensile forces 22 near the bottom of semiconductor die 5 .

[0031] like Figure 1B As shown, the stress-neutral region 23 is away from the stress-sensitive circuit 15. In one example, the stress-sensitive circuit 15 is a bandgap reference circuit that outputs an absolute voltage. Deformation applied to such a bandgap reference circuit can cause unacceptable shifts in the output voltage, thereby degrading the overall performance of the packaged integrated circuit 20.

[0032] Figure 2A FIG1 is a schematic cross-sectional view of a packaged integrated circuit 50 according to one embodiment. The packaged integrated circuit 50 includes a bottom pad 31, a main semiconductor die 35, a stress relief die 36, a molding material 37, a bottom pad bonding area 38, bond wires 39, a first die attach 41, a second die attach 42, a die pad 46, package leads 47, and a package lead bonding area 48.

[0033] like Figure 2A As shown, the main semiconductor die 35 includes stress-sensitive circuitry 45 fabricated on the top, or active, side of the die 35. Furthermore, the bottom, or inactive, side of the main semiconductor die 35 is attached to the bottom pad 31 via a first die attach 41, which may be, for example, a conductive or non-conductive epoxy. The bottom pad 31, for example, an exposed copper bottom pad, helps provide heat dissipation during operation.

[0034] Continue to refer Figure 2A , stress relief die 36 is attached to the top side of main semiconductor die 35 by second die attach 42. Second die attach 42 can be any suitable material for providing die attach and can be the same or different material than first die attach 41.

[0035] As shown in Figure 2A , molding material 37 is formed over the stack of bottom pad 31, main semiconductor die 35, and stress relief die 36. Molding material 37 helps protect the semiconductor dies during use. In certain embodiments, molding material 37 can comprise a plastic material including an epoxy resin molding compound such as FR-4.

[0036] In Figure 2A embodiments, die pads 46 of main semiconductor die 35 are electrically coupled to package leads 47 by bond wires 39. Bond wires 39 can be made of any suitable electrically conductive material such as gold or copper. While only one attachment between main semiconductor die 35 and the lead frame of the package is shown, typically many bond wires are used to attach multiple die pads to the leads of the lead frame.

[0037] Although in Figure 2A the main semiconductor die 35 is wire bonded to the package leads of the lead frame, it should be understood that the main semiconductor die 35 can be electrically connected in other ways. For example, in some embodiments such as those that utilize a printed circuit board as the package substrate, the main semiconductor die 35 can be attached (e.g., soldered) to the package substrate, and internal traces within the package substrate can provide electrical communication between the main semiconductor die 35 and an external circuit board. In some embodiments, the main semiconductor die 35 can also be flip-chip mounted and coupled to the package substrate. In further arrangements, the main semiconductor die 35 can be electrically coupled to the package substrate using non-conductive paste (NCP) or anisotropic conductive film (ACF) technology.

[0038] Accordingly, the teachings herein are applicable to various types of packages. Thus, the teachings herein are applicable not only to QFN packages, but also to other types of packages such as low profile quad flat package (LQFP) packages, ball grid array (BGA) packages, and other types of packages including those that use flip-chip technology.

[0039] Further, other configurations of the stack are possible. In one embodiment, bottom pad 31 is positioned above main semiconductor die 35, and main semiconductor die 35 is positioned above stress relief die 36.

[0040] In Figure 2A, stress-sensitive circuitry 45 is schematically depicted. However, those skilled in the art will appreciate that stress-sensitive circuitry 45 can be fabricated from layers of the main semiconductor die 35. In contrast to circuits that output or measure relative voltages and are insensitive to stress, stress-sensitive circuitry 45 can be precision components whose performance degrades due to stress. Examples of stress-sensitive circuitry 45 include, but are not limited to, reference circuits (current references or voltage references, such as bandgap reference circuits), oscillators, sensors, data converters (e.g., digital-to-analog converters or analog-to-digital converters), and / or amplifiers. Such stress-sensitive circuitry can include one or more stress-sensitive components, such as stress-sensitive transistors, resistors, capacitors, and / or matching structures.

[0041] In some embodiments, main semiconductor die 35 is a battery management system (BMS) integrated circuit (IC) that includes battery management circuitry that operates using stress-sensitive circuit 45. For example, stress-sensitive circuit 45 may include a bandgap reference circuit that provides a bandgap reference voltage to the battery management circuitry of the BMS IC.

[0042] like Figure 2A As shown, solder is placed along the bottom side of the packaged integrated circuit 50 for connection to the circuit board ( Figure 2A The packaged integrated circuit 50 can be attached to the circuit board for operation in a larger electronic system by making electrical connections thereto (not shown). For example, a bottom pad soldering area 38 is provided for the bottom pad 31, and a package lead soldering area 48 is provided for the package lead 47 and other leads of the lead frame.

[0043] The mechanical stress of soldering the packaged integrated circuit 50 to a circuit board (eg, a printed circuit board or PCB) may cause packaging stress, which may result in deformation of the packaged integrated circuit 50 .

[0044] like Figure 2A As shown, stress relief die 36 is placed over the top side of main semiconductor die 35. The stacking of bottom pad 31, main semiconductor die 35, and stress relief die 36 may result in the location of stress-sensitive circuit 45 being closer to the stress-neutral region after soldering. In some embodiments, stress relief die 36 is selected to have the same material (e.g., semiconductor, such as silicon) as main semiconductor die 35 so that the two dies have the same CTE.

[0045] Although stress relief die 36 may be a semiconductor die, the teachings herein also apply to embodiments where stress relief die 36 is not a semiconductor.

[0046] In the illustrated embodiment, the stress relief die 36 also completely covers the stress-sensitive circuitry 45, which prevents the molding material 37 from contacting the upper surface of the main semiconductor die 35 near where the stress-sensitive circuitry 45 is manufactured. Since particles in the molding material 37 (e.g., silicon dioxide particles) can cause localized stresses, completely covering the stress-sensitive circuitry 45 with the stress relief die 36 can reduce the impact of localized stresses on the performance of the stress-sensitive circuitry 45 to improve performance.

[0047] Figure 2A Various thickness dimensions of the components of the packaged integrated circuit 50 are labeled schematically. For example, the bottom pad 31 has a thickness dl, the main semiconductor die 35 has a thickness d2, the stress relief die 36 has a thickness d3, the first die attach 41 has a thickness d4, the second die attach 42 has a thickness d5, the solder has a thickness d6, and the molding material 37 has a thickness d7.

[0048] The thicknesses can be any suitable values. In certain embodiments, the thickness dl is selected to be in a range of 100 pm to 400 pm (or more specifically, in a range of 160 pm to 240 pm), such as 200 pm. In some embodiments, the thickness d2 is selected to be in a range of 80 pm to 120 pm, such as 100 pm. In various embodiments, the thickness d3 is selected to be in a range of 80 pm to 700 pm (or more specifically, in a range of 200 pm to 300 pm), such as 250 pm. In certain embodiments, the thicknesses d4 and d5 are selected to be less than 50 pm, such as 20 pm. In some embodiments, the thickness d6 is selected to be in a range of 50 pm to 75 pm, such as 63 pm. In various embodiments, the thickness d7 is selected to be in a range of 600 pm to 900 pm, such as 750 pm.

[0049] While example thickness ranges have been provided, other thickness values can also be used.

[0050] In certain embodiments, the stress relief die 36 is implemented as a thick dummy die, and the main semiconductor die 35 is implemented as a thin main die that includes the stress-sensitive circuitry 45. For example, in some embodiments, the thickness of the stress relief die 36 is between 0.5 and 10 times (or more specifically, between 1.5 and 5 times) the thickness of the main semiconductor die 35.

[0051] In embodiments where the stress relief die 36 is a dummy die, the stress relief die 36 does not include any operational circuitry. In other embodiments, the stress relief die 36 includes circuitry that operates in conjunction with the circuitry of the main semiconductor die 35 (including the stress-sensitive circuitry 45) to implement the desired overall functionality of the packaged integrated circuit 50.

[0052] In some embodiments, the thickness of stress relief die 36 is selected to be approximately the same as the thickness of foot pad 31. For example, in certain implementations, the thickness of stress relief die 36 is in the range of approximately 50% to 150% of the thickness of foot pad 31.

[0053] Despite Figure 2A One main semiconductor die 35 is attached to the bottom pad 31, but in other embodiments, one or more additional main semiconductor dies may also be attached to the bottom pad 31. Such additional main semiconductor dies may be implemented with or without a stress relief die for stress relief.

[0054] Figure 2B yes Figure 2A FIG. 5 is a schematic cross-sectional view of an example of a packaged integrated circuit 50 after soldering.

[0055] like Figure 2B As shown, the extreme high temperatures of the soldering process cause deformation or warping of packaged integrated circuit 50. For example, varying rates of thermal expansion and contraction can create compressive forces 51 near the top of stress relief die 36 and tensile forces 52 near the bottom of main semiconductor die 35.

[0056] However, in contrast to the case where the stress-neutral region 23 is far from the stress-sensitive circuit 15, Figure 1B The warpage of the packaged integrated circuit 20 is compared to Figure 2B The warped packaged integrated circuit 50 includes a stress-neutral region 53 located at or near the stress-sensitive circuit 45 .

[0057] In certain embodiments, the stress relief die 36 provides stress relief, which results in the stress-neutral region 23 not being completely located at the location of the stress-sensitive circuit 45 and only reducing the stress level at the stress-sensitive circuit 45 .

[0058] In some embodiments, stress differences caused by the soldering process are substantially minimized by moving the stress-neutral point closer to the sensitive circuitry. Additionally or alternatively, in some embodiments, the stress relief die positions the stress-neutral region within 100 μm of the stress-sensitive circuitry after soldering.

[0059] Thus, stress relief die 36 and main semiconductor die 35 can form a composite body that approximates the characteristics of a single beam. Furthermore, in embodiments where stress relief die 36 and main semiconductor die 35 are formed from the same material (e.g., a semiconductor such as silicon), both have the same CTE. Furthermore, stress relief die 36 protects main semiconductor die 35 from both global and local stresses in molding material 37, with local stresses primarily resulting from particles (e.g., silicon dioxide particles) in molding material 37.

[0060] Figure 3 is a schematic plan view of a packaged integrated circuit 80 according to one embodiment. The packaged integrated circuit 80 is implemented as a QFN package that includes a leadframe that includes leads 47. In addition, a main semiconductor die 31 is attached to a bottom pad 31 (e.g., a bare copper bottom pad), while a stress relief die 36 is attached to the main semiconductor die 31. The main semiconductor die 31 includes pads 46 that are attached to the leads 47 of the leadframe by bond wires 39. The main semiconductor die 31 includes stress sensitive circuitry, such as a bandgap reference voltage.

[0061] As shown in Figure 3 , the leads 47 can surround and be electrically isolated from (or, in another implementation, fused to) the bottom pad 31. The pads 46 can be formed around the perimeter of the main semiconductor die 35, and the stress relief die 36 can leave the pads 46 bare to enable wire bonding of the bond wires 39 to the leads 47. In some implementations, the stress relief die 36 covers about 50% to about 90% of the top surface of the main semiconductor die 35. In certain implementations, the stress relief die 36 completely covers the stress sensitive circuitry of the main semiconductor die 35 to protect the stress sensitive circuitry from the bulk and local stresses of the molding material (not shown in Figure 3 for clarity).

[0062] Figure 4 is a schematic circuit diagram of a stress sensitive circuit 110 according to one embodiment. In this embodiment, the stress sensitive circuit 110 corresponds to a bandgap reference circuit.

[0063] While the stress sensitive circuit 110 depicts one example of a stress sensitive circuit that can be included in a packaged integrated circuit, the packaged integrated circuits herein can include other types of stress sensitive circuits. For example, examples of stress sensitive circuits include, but are not limited to, reference circuits (current or voltage references, such as bandgap reference circuits), oscillators, sensors, data converters (e.g., digital to analog or analog to digital converters), and / or amplifiers.

[0064] In the illustrated embodiment, the stress sensitive circuit 110 includes a pair of proportional bipolar transistors 100, a first resistor 101, a second resistor 102, a third resistor 103, a fourth resistor 104, and an amplifier 105. The stress sensitive circuit 110 receives a first voltage V+ and a second voltage V- that, in some implementations, correspond to a supply voltage and a ground voltage, respectively. The stress sensitive circuit 110 also outputs a bandgap voltage V BGAP that is expected to be substantially constant even in the presence of package warpage due to soldering.

[0065] With continued reference to Figure 4 , the pair of proportioned bipolar transistors 100 includes a first NPN bipolar transistor A and a second NPN bipolar transistor B that are electrically coupled to the inverting input and the non-inverting input of the amplifier 105, respectively. For example, the first NPN bipolar transistor A includes a collector that is connected to the inverting input of the amplifier 105, while the second NPN bipolar transistor B includes a collector that is connected to the non-inverting input of the amplifier 105.

[0066] As shown in Figure 4 , the output of the amplifier 105 provides a bandgap voltage V BGAP and is connected to the base of the first NPN bipolar transistor A and the base of the second NPN bipolar transistor B. The inverting input of the amplifier 105 is also connected to the first voltage V+ through a third resistor 103, while the non-inverting input of the amplifier 105 is also connected to the first voltage V+ through a fourth resistor 104. The emitter of the first NPN bipolar transistor A is connected to the second voltage V- through a series combination of a first resistor 101 and a second resistor 102, while the emitter of the second NPN bipolar transistor B is connected to the second voltage V- through the second resistor 102.

[0067] With continued reference to Figure 4 , the first NPN bipolar transistor A has an area that is greater than the area of the second NPN bipolar transistor B. For example, as shown, the ratio of the emitter areas of the first NPN bipolar transistor A to the second NPN bipolar transistor B can be N: 1, where N can be, for example, at least 2.

[0068] The stability of the bandgap voltage V BGAP may depend on electrical characteristics related to the precise ratio of the emitter area of the first NPN bipolar transistor A to the emitter area of the second NPN bipolar transistor B. However, the electrical characteristics of the first NPN bipolar transistor A and the second NPN bipolar transistor B can be affected by mechanical stress caused by package deformation.

[0069] Accordingly, stress applied to the stress-sensitive circuit 110 can cause unacceptable voltage shifts in the bandgap voltage V BGAP , thereby degrading the performance of an electronic system that operates based on the bandgap voltage V BGAP .

[0070] Figure 5 is a graph of one example of measured soldering shifts versus simulated soldering stress. The graph compares a 9x9 mm QFN package of one embodiment of the package integrated circuit 20 according to Figure 1A to a 9x9 mm QFN package of the package integrated circuit 20 according to Figure 2AFIG. 5 shows a soldering-induced bandgap voltage shift change of a 9×9 mm QFN package of an implementation of a packaged integrated circuit 50 after soldering.

[0071] like Figure 5 As shown, using a thick dummy die to provide stress relief can significantly reduce the soldering shift of the bandgap voltage.

[0072] Figure 6A 1 is a schematic cross-sectional view of an electronic system 140 according to one embodiment. The electronic system 140 includes a circuit board 141 and a packaged integrated circuit 50 attached to the circuit board 141.

[0073] Figure 6A The electronic system 150 depicts Figure 2A FIG4 is an example of a packaged integrated circuit 50 after being soldered to a circuit board 141. Due to the inclusion of the stress relief die 36, the packaged integrated circuit 50 exhibits better fiducial stability when the circuit board 141 is flexed. For example, flexing the circuit board 141 can cause the packaged integrated circuit 50 to deform, but the deformation has less of an effect when the fiducial is in a stress-neutral position.

[0074] Figure 6B is a graph of an example of reference voltage offset versus board strain or bending. Figure 6B Figure 2 compares the reference voltage excursion of a packaged integrated circuit with a stress relief die and a packaged integrated circuit without a stress relief die. The packaged integrated circuit with the stress relief die exhibits better reference stability when the circuit board is flexed.

[0075] Figure 7 is a schematic cross-sectional view of a packaged integrated circuit 150 according to another embodiment. Figure 7 The packaged integrated circuit 150 is Figure 2A 1 is similar to the packaged integrated circuit 50, except that in this example, the packaged integrated circuit 150 also includes a third die attach 43 and an additional main semiconductor die 49 that does not include a stress relief semiconductor die. However, in another embodiment, a stress relief die is also included above the additional main semiconductor die 49.

[0076] Any number of semiconductor dies may be included in the packaged integrated circuits disclosed herein.

[0077] in conclusion

[0078] The above description can refer to elements or features as being “connected” or “coupled” together. As used herein, unless expressly stated to the contrary, “connected” means that one element / feature is directly or indirectly connected to another element or feature, and not necessarily mechanically. Likewise, unless expressly stated to the contrary, “coupled” means that one element / feature is directly or indirectly connected to another element or feature, and not necessarily mechanically. As a result, although various illustrative diagrams can depict example arrangements of elements and components, additional intermediate elements, devices, features, or components (e.g., as examples of the depicted circuitry’s functionality) can be present in an actual implementation so long as the desired functionality remains intact.

[0079] While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel devices, methods and systems described herein can be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein can be made without departing from the spirit of the disclosure. For example, while the disclosed embodiments are presented in a given arrangement, alternative embodiments can perform similar functionality using different components and / or circuit topologies, and some elements can be deleted, moved, added, subdivided, combined, and / or modified. Each of these elements can be implemented in a variety of different ways. Any suitable combination of the elements and acts of the various embodiments described above can be combined to provide further embodiments. Thus, the scope of the application is to be determined solely by the appended claims.

[0080] While the claims presented herein are submitted to the United States Patent and Trademark Office in a single dependency format, it is understood that any claim can depend on any previous claim of the same type unless it is technically infeasible to do so.

Claims

1. An integrated circuit package, comprising: bottom pad; a main semiconductor die having a first side attached to the foot pad and a second side including stress-sensitive circuitry; and A stress relief die is attached to the second side of the main semiconductor die, wherein the stress relief die is used to provide stress relief resulting from soldering the integrated circuit package to a circuit board. 2 . The integrated circuit package of claim 1 , wherein the stress relief die positions a stress-neutral region within 100 μm of the stress-sensitive circuit after soldering.

3. The integrated circuit package of claim 1, wherein stress differences due to a soldering process are substantially minimized by moving a stress-neutral point closer to the stress-sensitive circuit. 4 . The integrated circuit package of claim 1 , further comprising a molding material over the stress relief die, the main semiconductor die, and the foot pad.

5. The integrated circuit package of claim 1, wherein the stress relief die completely covers the portion of the main semiconductor die including the stress-sensitive circuitry.

6. The integrated circuit package of claim 1, wherein the stress relief die leaves a plurality of pads of the main semiconductor die exposed for wire bonding. 7 . The integrated circuit package of claim 6 , further comprising a lead frame comprising a plurality of leads and a plurality of bond wires electrically coupling the plurality of leads to the plurality of pads of the main semiconductor die.

8. The integrated circuit package of claim 1, wherein the stress-sensitive circuit comprises a bandgap reference circuit.

9. The integrated circuit package of claim 1, wherein the stress relief die has a thickness that is 0.5 to 10 times greater than a thickness of the main semiconductor die.

10. The integrated circuit package of claim 1, wherein the stress relief die has a thickness in a range of 80 μm to 700 μm, and the main semiconductor die has a thickness in a range of 80 μm to 120 μm. The integrated circuit package of claim 10 , wherein the foot pad has a thickness in a range of 100 μm to 400 μm.

12. The integrated circuit package of claim 1, wherein the stress relief die is a dummy die or includes operating circuitry.

13. The integrated circuit package of claim 1, wherein the main semiconductor die and the stress relief die are formed of the same material to provide the same coefficient of thermal expansion (CTE). The integrated circuit package of claim 13 , wherein the same material is silicon.

15. The integrated circuit package of claim 1, implemented in a quad flat no-lead (QFN) package.

16. The integrated circuit package of claim 1, further comprising at least one additional main semiconductor die located on the foot pad.

17. The integrated circuit package of claim 16, wherein the at least one additional main semiconductor die is not stacked with any stress relief die.

18. An electronic system comprising: circuit boards; and an integrated circuit package soldered to the circuit board, the integrated circuit package comprising: bottom pad; a main semiconductor die having a first side attached to the foot pad and a second side including stress-sensitive circuitry; and A stress relief die is attached to the second side of the main semiconductor die, wherein the stress relief die is used to provide stress relief resulting from soldering the integrated circuit package to the circuit board.

19. The electronic system of claim 18, wherein the stress relief provided by the stress relief die counteracts stress effects due to flexure of the circuit board.

20. A method of packaging an integrated circuit, the method comprising: attaching a bottom side of the main semiconductor die to the bottom pad; attaching a stress relief die to a top side of the main semiconductor die, the top side including stress sensitive circuitry; and Stress relief is provided by soldering the bottom pad to a circuit board using the stress relief die.

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