Three-dimensional memory

Abstract

The invention provides a three-dimensional memory and a preparation method thereof. The preparation method comprises the following steps: sequentially forming a sacrificial layer and a laminated structure on a substrate; the channel structure and the gate gap structure penetrate through the laminated structure and extend to the sacrificial layer, the dummy channel structure penetrates through the laminated structure and extends to the substrate, and the channel structure comprises a channel layer and a functional layer; removing the substrate and a portion of the dummy channel structure extending into the substrate; removing the part, corresponding to the channel structure, of the sacrificial layer and the part, extending into the sacrificial layer, of the functional layer so as to expose the channel layer; and forming a semiconductor layer to cover the channel structure, a portion of the sacrificial layer corresponding to the dummy channel structure, and a portion of the sacrificial layer corresponding to the gate gap structure. According to the three-dimensional memory and the preparation method thereof provided by the invention, short-circuit electric leakage between the gate layer (word line) and the semiconductor layer can be avoided, so that the reliability of the prepared three-dimensional memory is improved.

Description

[0001] This application is a divisional application of the Chinese Invention Patent Application with the application date of September 22, 2021, the application number of 202111118001.2, and the application title of “Three-dimensional Memory and Manufacturing Method Thereof”. TECHNICAL FIELD

[0002] The present application relates to the technical field of semiconductor technology, and more particularly, to a three-dimensional memory and a manufacturing method thereof. BACKGROUND

[0003] To improve the storage capacity per unit area, three-dimensional (3D) NAND memory developing in the vertical direction emerges as the times require to solve the problem of increasing the storage capacity per unit area. However, with the increase of the number of stacked layers, the manufacturing processes such as the step structure, the channel hole etching, and the gate slit etching in the three-dimensional memory will bring corresponding challenges, especially in the process of realizing the circuit loop formed by the channel layer in the channel hole and the substrate.

[0004] In some prior art, for the process method of removing the ONOPO layer at the bottom of the channel hole by using the deep hole etching process, due to the shift of the overlay window of the channel hole of the upper and lower two stacked structures, the sidewall of the functional (ONO) layer at the junction of the upper and lower stacked structures will be damaged or the ONOPO layer at the bottom of the channel hole will be etched insufficiently, thereby causing the short circuit leakage of the storage unit formed in the channel hole.

[0005] In another prior art, for the process method of removing the functional layer on the sidewall of the channel hole by using the gate slit (GLS), it is necessary to deposit the protective layer in the gate slit multiple times and cooperate with the etching process, so as to remove the pre-formed polysilicon sacrificial layer and the functional layer corresponding to the polysilicon sacrificial layer on the sidewall of the channel hole.

[0006] In the above process method, with the increase of the number of stacked layers, great challenges are brought to the etching process. In order to ensure sufficient etching precision, the manufacturing cost will inevitably be increased. In addition, the above process method cannot meet the manufacturing requirements of the increasing number of stacked layers in the three-dimensional memory.

[0007] In some practical applications, to solve the above technical problems, a part of the function in the channel structure can be removed from the back side of the substrate after the channel structure is formed on the substrate, and a semiconductor layer similar in function to the substrate is reformed. However, due to the formation of structures such as dummy channel structures or gate slit structures on / in the substrate, the process of removing the substrate may cause damage to these structures, thereby causing the semiconductor layer formed subsequently to have a short circuit leakage with the above structures or other structures indirectly connected with the above structures, thereby affecting the reliability of the electrical connection of the three-dimensional memory.

[0008] Therefore, how to solve the above technical problems existing in the preparation process of the three-dimensional memory is one of the technical problems to be solved by the person skilled in the art at present. SUMMARY

[0009] The present application provides a preparation method of a three-dimensional memory, comprising: sequentially forming a sacrificial layer and a stack structure on a substrate; forming a channel structure and a gate slit structure extending to the sacrificial layer and a dummy channel structure extending to the substrate through the stack structure, wherein the channel structure comprises a channel layer and a functional layer; removing the substrate and the part of the dummy channel structure extending into the substrate; removing the part of the sacrificial layer corresponding to the channel structure and the part of the functional layer extending into the sacrificial layer to expose the channel layer; and forming a semiconductor layer to cover the channel structure, the part of the sacrificial layer corresponding to the dummy channel structure, and the part of the sacrificial layer corresponding to the gate slit structure.

[0010] In some embodiments, before the step of sequentially forming the sacrificial layer and the stack structure on the substrate, the method can further comprise: forming a stop layer on the substrate.

[0011] In some embodiments, before the step of removing the part of the sacrificial layer corresponding to the channel structure and the part of the functional layer extending into the sacrificial layer, the method can comprise: removing the part of the stop layer corresponding to the channel structure.

[0012] In some embodiments, while removing the part of the functional layer extending into the sacrificial layer, the part of the stop layer corresponding to the dummy channel structure and the part of the stop layer corresponding to the gate slit structure can be removed to expose the dummy channel structure.

[0013] In some embodiments, after removing the part of the functional layer extending into the sacrificial layer, the method can comprise: removing the part of the stop layer corresponding to the dummy channel structure and the part of the stop layer corresponding to the gate slit structure to expose the dummy channel structure.

[0014] In some embodiments, while removing the part of the stop layer corresponding to the dummy channel structure, a part of the dummy channel structure close to the sacrificial layer can be removed so that the dummy channel structure forms a groove with the sacrificial layer.

[0015] In some embodiments, the semiconductor layer can extend into the groove.

[0016] In some embodiments, the three-dimensional memory comprises a through-contact structure extending to the sacrificial layer, and the step of removing the part of the stop layer corresponding to the channel structure can comprise: removing the part of the stop layer corresponding to the through-contact structure.

[0017] In some embodiments, the portion of the sacrificial layer corresponding to the through via contact structure can be removed at the same time as the portion of the functional layer extending into the sacrificial layer is removed.

[0018] In some embodiments, the material of the sacrificial layer can include polysilicon.

[0019] In some embodiments, the material of the stop layer can include silicon oxide.

[0020] The present application also provides a three-dimensional memory, comprising: a semiconductor layer; a sacrificial layer located in the semiconductor layer, comprising a first sacrificial layer portion and a second sacrificial layer portion separated from each other; a stack structure located on the sacrificial layer; a channel structure penetrating through the stack structure and extending into the semiconductor layer, comprising a channel layer and a functional layer, the channel layer extending into the semiconductor layer and being in contact with the semiconductor layer; a dummy channel structure at least partially penetrating through the stack structure and extending into the first sacrificial layer portion; and a gate slit structure penetrating through the stack structure and extending into the second sacrificial layer portion.

[0021] In some embodiments, the semiconductor layer can be in contact with the dummy channel structure extending into the first sacrificial layer portion.

[0022] In some embodiments, the three-dimensional memory can further comprise: a through via contact structure at least partially located on the semiconductor layer and extending in a direction towards the semiconductor layer.

[0023] In some embodiments, the three-dimensional memory further comprises: a polysilicon layer located between the stack structure and the semiconductor layer; and an oxide layer located between the polysilicon layer and the first sacrificial layer portion and between the polysilicon layer and the second sacrificial layer portion; wherein the channel structure passes through the polysilicon layer, and the dummy channel structure and the gate slit structure pass through the polysilicon layer and the oxide layer.

[0024] In some embodiments, the material of the sacrificial layer can include polysilicon.

[0025] According to the three-dimensional memory and the preparation method thereof provided by some embodiments of the present application, by retaining the sacrificial layer in the portion corresponding to the dummy channel structure and the portion corresponding to the gate slit, short circuit leakage between the gate layer (word line) and the semiconductor layer can be avoided. In addition, short circuit leakage between the gate layer of the bottom select transistor and the semiconductor layer can also be avoided, thereby improving the reliability of the three-dimensional memory after the preparation is completed. BRIEF DESCRIPTION OF DRAWINGS

[0026] Other features, objects, and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments thereof, read in conjunction with the accompanying drawings: FIG. 1 is a flowchart of a preparation method of a three-dimensional memory according to an embodiment of the present application; FIG. 2A to FIG. 2N is a process cross-sectional view schematic of a method of fabricating a three-dimensional memory according to embodiments of the present application.

[0027] FIG. 3 is a top view schematic of a method of fabricating a three-dimensional memory according to embodiments of the present application. DETAILED DESCRIPTION

[0028] For a better understanding of the present application, various aspects of the present application will be described in greater detail below with reference to the accompanying drawings. It is to be understood that the detailed description is merely descriptive of exemplary embodiments of the present application and is not intended to limit the scope of the present application in any way.

[0029] The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used in this specification, the terms “comprises,” “comprising,” “includes,” and / or “including” mean the presence of stated features, integers, elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, elements, components, and / or combinations thereof.

[0030] The example embodiments disclosed herein are described with reference to the accompanying drawings, which are used to better understand the example embodiments. The example embodiments disclosed herein should not be construed as being limited to the specific shapes and dimensions shown, but include various equivalent structures that can achieve the same functions, as well as shape and dimensional deviations that occur, for example, during manufacturing. The positions shown in the drawings are schematic in nature and are not intended to limit the positions of the components.

[0031] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0032] As used in this article, the term "layer" refers to a material portion including an area with a thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far away from the substrate. A layer can extend over the entire underlying structure or superstructure, or can have a range smaller than the underlying structure or superstructure. In addition, a layer can be an area of ​​a uniform or uneven continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer can be located at the top and bottom surfaces of a continuous structure or between any set of horizontal planes therebetween. A layer can extend horizontally, vertically and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, above and / or below. A layer can contain multiple layers.

[0033] The present application provides a method 1000 for preparing a three-dimensional memory. FIG. 1 FIG. 1 is a flow chart of a method 1000 for manufacturing a three-dimensional memory according to an embodiment of the present application. FIG. 1 As shown, the method 1000 for manufacturing a three-dimensional memory includes steps S110 to S150.

[0034] In some embodiments, a method for preparing a three-dimensional memory can be used to prepare a three-dimensional memory based on an Xtacking architecture. The three-dimensional memory based on the Xtacking architecture may include a first semiconductor structure for forming a memory cell array and a second semiconductor structure for forming a peripheral circuit. After the first semiconductor structure and the second semiconductor structure are prepared separately, the first semiconductor structure and the second semiconductor structure are bonded together, and a back-end-of-the-line (BOL) structure is formed on the back side of the first semiconductor structure or the second semiconductor structure (i.e., the side where the memory cell array or peripheral circuit is not formed). Steps S110 and S120 of the method 1000 for preparing a three-dimensional memory provided in accordance with an embodiment of the present application may be a preparation process for forming the first semiconductor structure, and steps S130 to S150 may be a preparation process for forming the BOL structure.

[0035] FIG. 2A to FIG. 2N 1 is a schematic cross-sectional view of a method 1000 for manufacturing a three-dimensional memory according to an embodiment of the present application. FIG. 3 1 is a top view schematic diagram of the portion corresponding to the channel structure and the sacrificial layer removed in the method for preparing a three-dimensional memory according to an embodiment of the present application. FIG. 2A to FIG. 2N is based on FIG. 3 Schematic cross-section of the semiconductor structure along the section line CC' is shown. It should be understood that the steps shown in method 1000 are not exclusive, and other steps may be performed before, after, or between any of the steps shown. In addition, some of the steps may be performed simultaneously or in different steps. FIG. 1 The following is combined with the order shown.FIG. 2A to FIG. 2N The above steps S110 to S150 are further described.

[0036] S110, sequentially forming a sacrificial layer and a stack structure on a substrate.

[0037] In step S110, FIG. 2A As shown, the substrate 111 may include silicon (e.g., single crystal silicon, polycrystalline silicon), silicon germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), glass, III-V compound semiconductors, and any other suitable material. During the process of forming the first semiconductor structure, the substrate 111 may serve as a support structure for channels, dummy channel structures, and gate gap structures formed thereon, and is removed after the first semiconductor structure 100 and the second semiconductor structure 200 are bonded together.

[0038] A stop layer 112 and a sacrificial layer 113 may be sequentially formed on the substrate 111. Methods for forming the stop layer 112 and the sacrificial layer 113 may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, thermal oxidation, or any combination thereof. For example, the material of the stop layer 112 may include silicon oxide, and the material of the sacrificial layer 113 may include polysilicon. At least a portion of the sacrificial layer 113 may be removed during subsequent processing. The stop layer 112 allows the substrate 111 to stop at this layer during the removal process. It should be understood that the stop layer 112 and the step of forming the stop layer 112 may be omitted.

[0039] In this step, if FIG. 2B As shown, the stacked structure 120 may be formed on the sacrificial layer 113. In some embodiments, the stacked structure 120 may include a plurality of dielectric layers 121 and a plurality of gate sacrificial layers 122 alternately stacked in a direction perpendicular to the substrate 111. The method for forming the stacked structure 120 may include a thin film deposition process such as CVD, PVD, ALD or any combination thereof. The number of stacked layers of the dielectric layer 121 and the gate sacrificial layer 122 in the stacked structure 120 may be 8 layers, 32 layers, 64 layers, 128 layers, etc. The more stacked layers the stacked structure 120 has, the higher the integration level and the greater the number of memory cells formed thereby. The number of stacked layers and the stacking height of the stacked structure 120 may be designed according to actual storage requirements, and this application does not specifically limit this.

[0040] In some embodiments, the dielectric layer 121 and the gate sacrificial layer 122 can have different etching selectivity, and the gate sacrificial layer 122 can be removed in a subsequent process to form a sacrificial gap, and the sacrificial gap, i.e., the space of the gate sacrificial layer 122, can be filled with a conductive material to form a gate layer, i.e., a word line. Optionally, the material of the dielectric layer 121 can include silicon oxide, and the material of the gate sacrificial layer 122 can include silicon nitride.

[0041] It should be understood that although the present application adopts the embodiment in which the gate sacrificial layer 122 is subsequently replaced by a conductive material to form a gate layer, the implementation of the gate layer in the present application is not limited thereto, and can also be implemented in a manner such as directly alternatingly stacking a dielectric layer and a gate layer.

[0042] In some embodiments, before forming the stack structure 120, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to sequentially form the oxide layer 114 and the polysilicon layer 115 on the sacrificial layer 113, so that the oxide layer 114 and the polysilicon layer 115 are formed between the sacrificial layer 113 and the stack structure 120. The material of the oxide layer 114 can be selected to be the same material as the stop layer 112, for example, silicon oxide.

[0043] S120, forming a channel structure and a gate slit structure extending through the stack structure and the sacrificial layer, and a dummy channel structure extending through at least part of the stack structure and the substrate, wherein the channel structure comprises a channel layer and a functional layer. FIG. 2C

[0044] In step S120, as shown in FIG. 3 , the channel structure 130 penetrates the stack structure 120 of the alternatingly stacked dielectric layer 121 and gate sacrificial layer 122, and extends into the sacrificial layer 113 in a direction perpendicular to the substrate 111. The channel structure 130 can have a general outline shape of a cylinder, a circular truncated cone, or a prism, and can include an outer wall structure of the functional layer 131 and the channel layer 132 sequentially arranged from outside to inside. Optionally, the functional layer 131 can be a composite layer structure of a blocking layer, a charge trapping layer, and a tunneling layer sequentially arranged from outside to inside. The materials of the blocking layer, the charge trapping layer, and the tunneling layer can be silicon oxide, silicon nitride, and silicon oxide, respectively, thereby forming a functional layer 131 with an ONO structure. The material of the channel layer 132 can include a semiconductor material such as amorphous silicon, polysilicon, monocrystalline silicon, etc. It can be understood that a plurality of channel structures 130 can be arranged in a two-dimensional array in a plane parallel to the substrate 111, and the area for forming the plurality of channel structures 130 can be referred to as a core region A (refer to FIG. 1B). FIG. 2D .

[0045] In some embodiments, the channel structure 130 can be formed by photolithography and etching processes and thin film deposition processes. Illustratively, a channel hole can be first formed through the stack structure 120 and extending into the sacrificial layer 113 using, for example, photolithography and etching processes (dry or wet etching processes). Further, thin film deposition processes such as CVD, PVD, ALD or any combination thereof can be used to form the functional layers 131 including the blocking layer, the charge trapping layer and the tunneling layer, and the channel layer 132 in sequence on the inner walls of the channel hole. Optionally, a dielectric material such as silicon oxide can be filled in the channel hole with the functional layers 131 and the channel layer 132 formed therein using thin film deposition processes such as CVD, PVD, ALD or any combination thereof. Optionally, one or more air gaps can be formed during the filling process to relieve structural stress by controlling the channel filling process.

[0046] In some embodiments, the channel structure 130 can further include a channel plug 133 at the end thereof distal to the substrate 111. The channel plug 133 can be made of the same semiconductor material as the channel layer 132 and in contact with the channel layer 132. The channel plug 133 can function as the drain of the channel structure 130.

[0047] It can be appreciated that the functional layers 131 and the channel layer 132 in the channel structure 130, together with the portion of each gate sacrificial layer 122 (i.e. the subsequently formed gate layer 123) in the stack structure 120 and the gate sacrificial layer 122, form a memory cell. The gate layer can correspond to the control terminal of the memory cell. The plurality of memory cells in the channel structure 130 are arranged in series in the direction perpendicular to the substrate 111 and share the channel layer 132. The memory cells in the channel structure 130 are controlled by the voltage of the gate layer to cause a large number of carriers in the channel layer 132 to enter the charge trapping layer in the functional layers 131 or to cause a large number of carriers in the charge trapping layer of the functional layers 131 to return to the channel layer 132, so as to cause the memory cells to be in a programmed state or an erased state (unprogrammed state). In addition, the memory cells at both ends of the plurality of memory cells arranged in series in the direction perpendicular to the substrate 111 can function as selection transistors for controlling the turn-on or turn-off of the plurality of memory cells arranged in series. Illustratively, the selection transistors can be referred to as top selection transistors or bottom selection transistors according to their positions. Optionally, the top selection transistors can be close to the channel plug 133.

[0048] In some embodiments, as FIG. 3As shown, the step structure can be formed at the edge of the stack structure 120, and can be formed by performing multiple "trim-etch" cycle processes on the alternately stacked plurality of dielectric layers 121 and plurality of gate sacrificial layers 122. In which, in the direction parallel to the substrate 111, a pair of dielectric layers 121 and gate sacrificial layers 122 away from the substrate 111 covers a pair of dielectric layers 121 and sacrificial layers 132 adjacent and close to the substrate 111, so that the gate sacrificial layer 122 in the pair of dielectric layers 121 and gate sacrificial layers 122 close to the substrate 111 has an area exposed to the pair of dielectric layers 121 and gate sacrificial layers 122 adjacent and away from the substrate 111. The exposed area of the gate sacrificial layer 122 can serve as an electrical connection area of the conductive channel formed in the vertical direction in the subsequent process. Optionally, the top side of the step structure can be filled with at least one insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride, etc. It can be understood that the area for forming the step structure can be referred to as the step region B (refer to FIG. 2E ).

[0049] In this step, as shown in FIG. 2F , the dummy channel structure 134 penetrates at least part of the stack structure 120 and extends into the substrate 111 in the direction perpendicular to the substrate 111. The dummy channel structure 134 can have a similar profile shape as the channel structure 130. Exemplarily, the process method for forming the dummy channel structure 134 is also similar to the process method for forming the channel structure 130, and it is worth noting that in some embodiments, after forming the dummy channel hole, at least one insulating material such as silicon oxide can be directly filled in the dummy channel hole by using a thin film deposition process such as CVD, PVD, ALD or any combination thereof, so that the dummy channel structure 134 does not have a functional layer and a channel layer. At this time, the dummy channel structure 134 can be used to provide mechanical support. Optionally, by controlling the channel filling process, one or more air gaps can be formed during the filling process to alleviate structural stress.

[0050] In this step, as shown in FIG. 3 , the gate slit structure 141 penetrates the stack structure 120 and extends into the sacrificial layer 113 in the direction perpendicular to the substrate 111, and the gate slit structure 141 can extend in the direction parallel to the substrate 111 to divide the plurality of channel structures 130 into memory blocks. Specifically, as shown in FIG. 2FAs shown, the plurality of channel structures 130 are staggered in rows, and the gate slit structures 140 extend in a direction parallel to the rows of channel structures, and the plurality of rows of channel structures partitioned by adjacent gate slit structures 140 can form a channel structure array (also referred to as a memory cell array), and this portion of the channel structure array can be referred to as a memory block. Optionally, a plurality of (e.g., five) sub-gate slit structures 141 can be included between adjacent gate slit structures 140 and extend parallel thereto, and the sub-gate slit structures 141 further divide the plurality of rows of channel structures into sub-memory blocks. Note that the sub-gate slit structures 141 and the gate slit structures 140 have similar structures, and in this disclosure, the sub-gate slit structures 141 and the gate slit structures 140 are collectively referred to as gate slit structures. Optionally, the gate slit structures 141 can include a common source portion 141-1 and a support portion 141-2.

[0051] The method of forming the support portion 141-2 of the gate slit structure 141 is described in detail below. In some embodiments, referring back to FIG. 2G , a gate slit extending through the stack structure 120 and into the sacrificial layer 113 can be formed first using, for example, photolithography and etching processes (dry or wet etching processes). Further, in the case where the sacrificial layer 113 is made of a polysilicon material, a portion of the sacrificial layer 113 and the polysilicon layer 115 exposed by the gate slit can be converted into silicon oxide using, for example, a thermal oxidation process, so that the end of the gate slit extending out of the stack structure 120 is surrounded by silicon oxide. Further, the gate slit can be used to replace the gate sacrificial layer 122 in the stack structure 120 with a gate layer 123, where the gate layer 123 can be a composite layer structure, and specifically, the gate layer 123 can include a conductive core and an adhesion layer and a high-k layer sequentially at least partially surrounding the conductive core. The material of the conductive core can include a conductive material such as tungsten, cobalt, copper, aluminum, or any combination thereof. The material of the adhesion layer can include a material such as titanium, titanium nitride, tantalum, tantalum nitride, or any combination thereof, for adhering the conductive core to the high-k layer and effectively preventing the conductive material of the conductive core from diffusing. The material of the high-k layer can include a material such as aluminum oxide, hafnium oxide, or any combination thereof. Optionally, the high-k layer can cover the inner wall of the gate slit. Further, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to sequentially form an isolation layer 143 and a conductive layer 144 inside the gate slit to form the gate slit structure 141. The material of the isolation layer 143 can be selected from, for example, silicon oxide, silicon nitride, or silicon oxynitride. The material of the conductive layer 144 can be selected from, for example, tungsten, cobalt, copper, aluminum, or a doped semiconductor material.

[0052] It is understood that since this application uses the support portion 141-2 in the gate slot structure as an example for description, the conductive layer in the gate slot structure does not contact the sacrificial layer 113. However, in the common source portion of the gate slot structure, the conductive layer in the gate slot structure should contact the sacrificial layer 113 to allow the conductive layer to contact the semiconductor layer during subsequent processing, thereby serving as an electrical connection structure for the common source when the semiconductor layer serves as the common source electrical coupling region. Therefore, for the support portion in the gate slot structure, at least one insulating material can also be directly filled into the corresponding gate slot.

[0053] In some embodiments, as FIG. 2H As shown, the top side of the substrate 111 and the stop layer 112, sacrificial layer 113, oxide layer 114 and polysilicon layer 115 located thereon may be filled with insulating material, and this portion may be referred to as a peripheral region. The through-contact structure 151 may penetrate the insulating material corresponding to the peripheral region and extend into the sacrificial layer 113. The through-contact structure 151 may be used to transmit electrical signals between the two semiconductors after the first semiconductor structure 100 and the second semiconductor structure 200 are bonded together, and to enable interaction between the electrical signals of the two semiconductor structures and external control signals. Therefore, the material of the through-silicon contact structure 151 may be a conductive material such as tungsten, cobalt, copper, aluminum or a doped semiconductor material.

[0054] In some embodiments, the plurality of conductive vias 152 may extend perpendicular to the substrate 111 to the electrical connection regions of the plurality of gate layers 123, such that one end of the conductive via 152 contacts the gate layer 123. The conductive vias 152 may be formed through photolithography and etching processes, as well as thin film deposition processes, and the material of the conductive vias 152 may include a conductive material such as tungsten, cobalt, copper, aluminum, or any combination thereof. Optionally, the through-contact structures 151 and the conductive vias 152 may have an outer wall structure formed of an adhesion layer (or metal barrier layer).

[0055] In some embodiments, a first interconnect layer 160 is formed on the top side of the stack structure 120 for transferring electrical signals to and from the second semiconductor structure 200. The first interconnect layer 160 can include a plurality of interconnect lines (not shown) extending laterally in a direction parallel to the substrate 111 and a plurality of interconnect vias 161 extending in a direction perpendicular to the substrate 111. The first interconnect layer 160 can further include a plurality of interlayer dielectric (ILD) layers in which the interconnect lines and the interconnect vias 161 can be formed. In other words, the first interconnect layer 160 can include the interconnect lines and the interconnect vias 161 in a plurality of interlayer dielectric layers. The material of the interconnect lines and the interconnect vias 161 can include a conductive material such as tungsten, cobalt, copper, aluminum, or any combination thereof. The material of the interlayer dielectric layers can include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, low-k material, or any combination thereof. It is noted that the interconnect lines and / or the interconnect vias 161 in the first interconnect layer 160 can be in contact with the other end of the conductive vias 152 and the other end of the through-contact structures 151, such that the first interconnect layer 160 is electrically connected to the gate layer 123 through the conductive vias 152 and to the second semiconductor structure 200 through the through-contact structures 151.

[0056] In some embodiments, as shown in FIG. 2, the first semiconductor structure 100 and the second semiconductor structure 200 can be connected by, for example, bonding after the first semiconductor structure 100 is processed as described above. S130, removing part of the substrate and the dummy channel structure extending into the substrate. The second semiconductor structure 200 can include a plurality of peripheral devices formed therein. The peripheral devices can include any suitable semiconductor devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), diodes, resistors, inductors, and capacitors. The plurality of peripheral devices can form digital, analog, and / or mixed-signal circuit modules that support the plurality of channel structures 130 to perform various functions. For example, the circuit modules can include page buffers, address decoders, and sense amplifiers.

[0057] In some embodiments, the second semiconductor structure 200 can include a second interconnect layer for transferring electrical signals to and from the first semiconductor structure 100. The second interconnect layer can have a similar structure and formation method as the first interconnect layer, which will not be described herein.

[0058] For example, when the first semiconductor structure 100 and the second semiconductor structure 200 are connected by bonding, the first semiconductor structure 100 may have a first bonding surface 101 that is remote from the substrate 111. The interconnect lines and / or interconnect channels 162 in the first interconnect layer 160 may be exposed at the first bonding surface 101 and may serve as first bonding contacts of the first semiconductor structure 100. Similarly, the second semiconductor structure 200 may have a second bonding surface 201. The interconnect lines and / or interconnect channels in the second interconnect layer may be exposed at the second bonding surface 201 and may serve as second bonding contacts of the second semiconductor structure 200. Furthermore, the first semiconductor structure 100 may be positioned on the second semiconductor structure 200 by aligning the first bonding contacts with the second bonding contacts, thereby electrically connecting the first and second bonding contacts at the aligned positions. This in turn electrically couples structures such as the channel structure 130 and the through-contact structure 151 in the first semiconductor structure 100 with peripheral devices in the second semiconductor structure 200.

[0059] FIG. 2I

[0060] In step S130, the substrate 111 and the portion of the dummy channel structure 134 extending into the substrate 111 may be removed from the back side of the substrate 111 (the side where the channel structure 130 is not formed) by, for example, a photolithography and etching process (dry or wet etching process) or a mechanical chemical polishing (CMP) process.

[0061] In some embodiments, as FIG. 2J As shown, when the first semiconductor structure 100 includes a stop layer 112 made of silicon oxide and the substrate 111 is made of silicon material, the process of removing the substrate 111 can be stopped at the stop layer 112 and the stop layer 112 is exposed, which is conducive to controlling the uniformity of the process of removing the substrate 111. S140, removing part of the sacrificial layer corresponding to the channel structure and part of the functional layer extending into the sacrificial layer, to expose the channel layer. As shown, the portion of the stop layer 112 corresponding to the channel structure 130 and the portion corresponding to the through-contact structure 151 can be removed using, for example, a photolithography and etching process (dry or wet etching process), thereby exposing the portion of the sacrificial layer 113 corresponding to the channel structure 130. After the above-described processing, the stop layer 112 may include two separate portions 112-1 and 112-2. Specifically, one portion 112-1 of the stop layer may correspond to the dummy channel structure 134, and the other portion 112-2 of the stop layer may correspond to the gate slit structure 141. By removing a portion of the stop layer 112, the sacrificial layer 113 corresponding to the dummy channel structure 134 and the gate slit structure 141 can be effectively protected during the subsequent process of removing the sacrificial layer 113.

[0062] It should be understood that when the first semiconductor structure 100 does not include the stop layer 112 , the substrate 111 can be removed to expose the sacrificial layer 113 , for example, by controlling process parameters such as etching time or etching rate.

[0063] FIG. 2K FIG. 2L

[0064] In step S140, first, a portion of the sacrificial layer 113 corresponding to the channel structure 130 may be removed from the back side of the sacrificial layer 113 using, for example, a photolithography and etching process (dry or wet etching process) to expose a portion of the channel structure 130 extending into the sacrificial layer 113. In some embodiments, as FIG. 3 As shown, in the case where the first semiconductor structure 100 includes a stop layer 112 and the sacrificial layer 113 is made of polysilicon, during the process of removing the portion of the sacrificial layer 113 corresponding to the channel structure 130, the two portions (112-1 and 112-2) of the stop layer 112 retained after the above-mentioned process can stop the process of removing the polysilicon sacrificial layer 113 at the two portions of the stop layer 112, thereby effectively protecting the sacrificial layer 113 below the stop layer 112 and corresponding to the dummy channel structure 134 and the gate gap structure 141.

[0065] In this step, the portion of the functional layer 131 extending into the sacrificial layer 113 may be removed by, for example, photolithography and etching processes (dry or wet etching processes) to expose the channel layer 132 of the channel structure 130 extending into the sacrificial layer 113 .

[0066] In some embodiments, as S150, forming a semiconductor layer to cover the channel structure, part of the sacrificial layer corresponding to the dummy channel structure, and part of the sacrificial layer corresponding to the gate slit structure. As shown, when the first semiconductor structure 100 includes a stop layer 112 and an oxide layer 114, and both are made of the materials described above, since the functional layer 131 can be a composite layer structure made of silicon oxide-silicon nitride-silicon oxide materials, during the process of sequentially removing the silicon oxide-silicon nitride-silicon oxide material layers, the portion 112-1 of the stop layer 112 corresponding to the dummy channel structure 134 and the portion 112-2 of the stop layer 112 corresponding to the gate gap structure 141 can be removed by the same etching process. Furthermore, since the dummy channel structure 134 is provided through the sacrificial layer 113, the end surface of the dummy channel structure 134 can be exposed after the stop layer 112 is removed. Optionally, the silicon oxide-silicon nitride-silicon oxide material layers can be removed in sequence through multiple etching processes, and then the portion 112-1 of the stop layer 112 corresponding to the dummy channel structure 134 and the portion 112-2 of the stop layer 112 corresponding to the gate gap structure 141 can be removed. This application does not make specific restrictions on this.

[0067] Optionally, in the process of removing the portion 112-1 of the stop layer 112 corresponding to the dummy channel structure 134, a portion of the dummy channel structure 134 close to the sacrificial layer 113 can be further removed, so that the dummy channel structure 134 forms a trench with the sacrificial layer 113-1.

[0068] It should be understood that the oxide layer 114 can be removed in this step. After the above process, the sacrificial layer 113 between the adjacent gate slit structures 140 / 141 in the core region A is removed (see FIG. 2M ), and the remaining portion of the sacrificial layer 113 can be retained. Specifically, the retained sacrificial layer 113 can include a first sacrificial layer portion 113-1 corresponding to the dummy channel structure 134 and a second sacrificial layer portion 113-2 corresponding to the gate slit structure 140 / 141, and the first and second sacrificial layer portions 113-1 and 113-2 can serve as a protective layer to avoid short-circuiting and leakage between the gate layer (word line) and the subsequently formed semiconductor layer. In the case where the gate layer close to the sacrificial layer 113 serves as the gate layer of the bottom select transistor, using the preparation method of retaining at least part of the sacrificial layer 113 as described above can further avoid short-circuiting and leakage between the gate layer of the bottom select transistor and the subsequently formed semiconductor layer, thereby improving the electrical connection reliability of the three-dimensional memory after preparation.

[0069] In some embodiments, the sacrificial layer 113, the oxide layer 114, and the polysilicon layer 115 corresponding to the through-contact structure 151 can be removed from the back side of the sacrificial layer 113 using, for example, photolithography and etching processes (dry or wet etching processes), so that the insulating material surrounds the through-contact structure 151 in the subsequent process, thereby electrically isolating the plurality of through-contact structures 151 from each other.

[0070] FIG. 2N ​

[0071] In step S150, as shown in ​ , a semiconductor layer 170 can be formed on the back side of the sacrificial layer 113 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, so that the semiconductor layer 170 covers and surrounds the channel structure 130, covers the surface of the first sacrificial layer portion 113-1 corresponding to the dummy channel structure 134, and covers the surface of the second sacrificial layer portion 113-2 corresponding to the gate slit structure 141. Optionally, the surface of the deposited semiconductor layer 170 can be planarized using, for example, a CMP process.

[0072] It should be understood that the semiconductor layer 170 forms a circuit loop by contacting and electrically connecting the channel layer 132 . Furthermore, the semiconductor layer 170 can serve as a common source electrical coupling region for multiple channel structures 130 .

[0073] In some embodiments, a doped region may be formed in a portion of the channel layer 132 adjacent to the semiconductor layer 170 using, for example, an ion implantation process and a laser annealing process. The height of the doped region in a direction perpendicular to the semiconductor layer 170 may be greater than the height of the at least one gate layer 123. The doped region of the channel layer 132 and the corresponding functional layer 131 may be used to form a bottom selection transistor, and the bottom selection transistor may have different threshold voltage values ​​by adjusting the doping concentration of the doped region.

[0074] In some embodiments, during the process of forming the semiconductor layer 170, the semiconductor layer 170 can cover and surround the through-contact structure 151, and the portion of the semiconductor layer 170 corresponding to the through-contact structure 151 can be removed in a subsequent process and filled with an insulating material.

[0075] In some embodiments, as ​ As shown, after the above-mentioned processing, the method may further include the following steps. Specifically, the portion of the semiconductor layer 170 corresponding to the through-contact structure 151 formed in step S150 may be removed using, for example, photolithography and etching processes. Furthermore, the space formed by removing the portion of the semiconductor layer 170 corresponding to the through-contact structure 151 may be filled with an insulating material using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The insulating material may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or other suitable low-k dielectric constant materials. Furthermore, a first contact 182 in contact with the through-contact structure 151 and a second contact 183 in contact with the semiconductor layer 170 may be formed using, for example, photolithography and etching processes and a thin film deposition process. The first contact 182 and the second contact 183 may serve as electrical connection structures between the through-contact structure 151 and the semiconductor layer 170, respectively. The material of the first contact 182 and the second contact 183 may include a conductive material such as tungsten, cobalt, copper, aluminum, or a combination thereof.

[0076] The application also provides a three-dimensional memory. The three-dimensional memory comprises: a semiconductor layer; a sacrificial layer located in the semiconductor layer, comprising a first sacrificial layer part and a second sacrificial layer part separated from each other; a stack structure located on the sacrificial layer; a channel structure penetrating through the stack structure and extending into the semiconductor layer, comprising a channel layer and a functional layer, the channel layer extending into the semiconductor layer and being in contact with the semiconductor layer; a dummy channel structure at least partially penetrating through the stack structure and extending into the first sacrificial layer part; and a gate slit structure penetrating through the stack structure and extending into the second sacrificial layer part.

[0077] Since the contents and structures involved in the preparation method 1000 described above can be completely or partially applicable to the three-dimensional memory device described herein, the contents related or similar thereto will not be repeated.

[0078] According to the three-dimensional memory and the preparation method thereof provided by the embodiments of the application, by retaining the sacrificial layer in the part corresponding to the dummy channel structure and the part corresponding to the gate slit, the short circuit leakage between the gate layer (word line) and the semiconductor layer can be avoided. In particular, the short circuit leakage between the gate layer of the bottom select transistor and the semiconductor layer can be avoided, thereby improving the reliability of the three-dimensional memory after the preparation is completed.

[0079] The above description is merely preferred embodiments of the application and a description of the principles of the technology used. Those skilled in the art should understand that the scope of the application involved in the application is not limited to the technical solutions formed by the specific combinations of the technical features described above, and should also cover other technical solutions formed by any combinations of the above technical features or equivalent features without departing from the inventive concept. For example, the technical solutions formed by replacing the above features with the technical features disclosed in the application (but not limited to) having similar functions.

Claims

1. A three-dimensional memory, characterized in that: include: A stacked structure comprising a plurality of dielectric layers and gate layers overlapped along a first direction; a first polysilicon layer, an oxide layer, and a second polysilicon layer stacked along the first direction, wherein the oxide layer is located between the first polysilicon layer and the second polysilicon layer, and the first polysilicon layer is located between the stacked structure and the oxide layer; a dummy channel structure, penetrating the stacked structure, the first polysilicon layer, and the oxide layer along the first direction and extending into the second polysilicon layer; and A gate gap structure penetrates the stacked structure, the first polysilicon layer and the oxide layer along the first direction and extends into the second polysilicon layer.

2. The three-dimensional memory according to claim 1, wherein: The oxide layer includes a first portion and a second portion that are spaced apart from each other. The dummy channel structure passes through the first portion, and the gate gap structure passes through the second portion.

3. The three-dimensional memory according to claim 2, wherein: The three-dimensional memory further includes: a channel structure, penetrating the stacked structure along the first direction and comprising a channel layer extending along the first direction; The semiconductor layer is located on one side of the stacked structure along the first direction and contacts the channel layer.

4. The three-dimensional memory according to claim 3, wherein: The semiconductor layer is included between the first portion and the second portion.

5. The three-dimensional memory according to claim 3, wherein: The three-dimensional memory further includes: a through contact structure extending along the first direction and insulated from the semiconductor layer; and The first contact contacts the through-contact structure.

6. The three-dimensional memory according to claim 5, characterized in that The three-dimensional memory further includes: The peripheral circuit is located on a side of the stacked structure relatively far away from the semiconductor layer along the first direction.

7. The three-dimensional memory according to claim 6, wherein: The three-dimensional memory further includes: The first interconnection layer is located between the stacked structure and the peripheral circuit and includes an interconnection channel; wherein, One end of the through contact structure arranged along the first direction contacts the first contact, and the other end contacts the interconnection channel.

8. The three-dimensional memory according to claim 3, wherein: The three-dimensional memory further includes: The second contact contacts the semiconductor layer and is located at a side of the semiconductor layer relatively far away from the stacked structure along the first direction.

9. The three-dimensional memory according to claim 3, wherein: The channel structure further includes a functional layer, wherein the functional layer is located between the channel layer and the stacked structure, and one end of the channel layer disposed along the first direction contacts the semiconductor layer.

10. The three-dimensional memory according to claim 2, wherein: The three-dimensional memory further includes a step area and a core area, wherein: The step region includes the dummy channel structure, the core region includes a channel structure, the channel structure penetrates the stacked structure along the first direction and includes a channel layer extending along the first direction; and The first portion is located in the step area, and the second portion is located in the core area.

11. The three-dimensional memory according to claim 10, wherein: The step area further includes a step structure and a protective layer and a filling layer covering the step structure, wherein the protective layer is located between the step structure and the filling layer; The three-dimensional memory further includes a conductive channel, which sequentially penetrates the filling layer, the protection layer, and the corresponding dielectric layer along the first direction and contacts the corresponding gate layer.

12. The three-dimensional memory according to claim 1, wherein: The gate gap structure includes an isolation layer, which penetrates the stacked structure along the first direction and includes a plurality of protrusions arranged along the first direction, and one of the protrusions contacts one of the gate layers.

13. The three-dimensional memory according to claim 12, wherein: The gate gap structure further includes a conductive layer, and the isolation layer is located between the conductive layer and the stacked structure.

14. A three-dimensional memory, characterized in that: include: semiconductor layer; a stacked structure comprising a plurality of dielectric layers and gate layers overlappingly arranged along a first direction and located on a first side of the semiconductor layer; a channel structure, penetrating the stacked structure and extending into the semiconductor layer, comprising a channel layer and a functional layer, wherein the channel layer is in contact with the semiconductor layer; a first polysilicon layer, an oxide layer, and a second polysilicon layer stacked along the first direction, wherein the oxide layer is located between the first polysilicon layer and the second polysilicon layer, and the first polysilicon layer is located between the stacked structure and the oxide layer; a dummy channel structure, penetrating the stacked structure, the first polysilicon layer, and the oxide layer along the first direction and extending into the second polysilicon layer; and a gate gap structure, penetrating the stacked structure and extending into the semiconductor layer and comprising an isolation layer; The isolation layer penetrates the stacked structure along the first direction and includes a plurality of protrusions arranged along the first direction, and one of the protrusions contacts one of the gate layers.

15. The three-dimensional memory according to claim 14, wherein: The gate gap structure further includes a conductive layer, and the isolation layer is located between the conductive layer and the stacked structure.

16. The three-dimensional memory according to claim 15, wherein: The conductive layer includes a semiconductor material.

17. The three-dimensional memory according to claim 15, wherein: The conductive layer includes metal tungsten.

18. The three-dimensional memory according to claim 15, wherein: The gate layer includes a conductive core, and an adhesion layer and a high dielectric constant layer sequentially at least partially surrounding the conductive core.

19. The three-dimensional memory according to claim 18, wherein: The conductive core includes metallic tungsten, the adhesion layer includes at least one of Ti or TiN, and the high dielectric constant layer includes aluminum oxide.

20. The three-dimensional memory according to claim 14, wherein: The three-dimensional memory further includes: The peripheral circuit is located on a side of the stacked structure relatively far away from the semiconductor layer along the first direction.

21. The three-dimensional memory according to claim 14, further comprising: a penetrating contact structure extending along the first direction and insulated from the semiconductor layer; as well as The first contact contacts the through-contact structure.

22. The three-dimensional memory according to claim 21, further comprising: The peripheral circuit is located on a side of the stacked structure relatively far away from the semiconductor layer along the first direction; wherein, The through-contact structure is electrically connected to the peripheral circuit.

23. The three-dimensional memory according to claim 14, further comprising: The second contact is located on a second side of the semiconductor layer and contacts the semiconductor layer. The first side and the second side are arranged opposite to each other in the first direction.

24. The three-dimensional memory according to claim 14, further comprising: Step structure; a protective layer and a filling layer covering the step structure, wherein the protective layer is located between the step structure and the filling layer; as well as A conductive channel, wherein the conductive channel sequentially penetrates the filling layer, the protection layer and the corresponding dielectric layer along the first direction and contacts the corresponding gate layer.

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