Multi-current-path bidirectional SCR device for ESD protection

Abstract

The invention provides a multi-current-path bidirectional SCR device for ESD protection. The multi-current-path bidirectional SCR device comprises a P-type substrate, an N-type epitaxial layer, a first P-type buried layer, an N-type buried layer, a second P-type buried layer, a first P-type well region, an N-type well region, a second P-type well region, an anode P + region, an anode N + region, a floating N + region, a cathode N + region and a cathode P + region. On the basis of the structure of a traditional bidirectional SCR device for ESD protection, a buried layer structure is introduced, a current path in the device is divided into a well region current path and a buried layer current path, heat distribution in the device is optimized, the heat distribution of the device is more uniform, the failure current of the device is improved on the basis that the area of the device is not increased, and the reliability of the device is improved. The performance of the device in unit area is increased, and the anti-surge capability of the device is enhanced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, and particularly relates to a multi-current-path bidirectional SCR device for ESD protection. BACKGROUND

[0002] ESD, electrostatic discharge, is an ancient natural phenomenon. ESD exists in every corner of people's daily life. However, such a common electrical phenomenon is a fatal threat to precision integrated circuits. Electrical surges / transient voltages refer to random and high voltages or large currents that suddenly appear in a circuit, which are characterized by short occurrence time and very large transient energy. Electrical surges have strong destructive power on electronic components and integrated circuits. Light ones may induce the misoperation of logic circuits, and heavy ones may cause secondary breakdown of transistors, latch-up effect of CMOS devices (Complementary Metal Oxide Semiconductor) and other serious thermal effects to make the devices or integrated circuits fail. Electrical surges usually have two random sources. The first one is the instability of the power grid, such as sudden switching on / off, sudden start of capacitive or inductive load, hot plug of related equipment, unstable operation of related power supply, etc. The second one is external sudden interference, such as lightning, electrostatic discharge, etc.

[0003] With the improvement of integrated circuit manufacturing process, the minimum line width has been reduced to the sub-micron or even nanometer level. While bringing about the improvement of chip performance, the ESD resistance of the integrated circuit is also greatly reduced, and thus the electrostatic damage is more serious. Most of the ESDs can cause non-fatal damage to the integrated circuit, thereby reducing the service life and reliability of the integrated circuit, and further causing the degradation of system function, which greatly hinders the realization of large-scale and high-reliability integration. SUMMARY

[0004] In order to realize an ESD protection device with excellent heat dissipation and electrical surge resistance, the embodiment of the present application provides a multi-current-path bidirectional SCR device for ESD protection, which optimizes the heat distribution inside the device and enhances the electrical surge resistance of the device. To achieve the above technical purpose, the technical scheme adopted by the embodiment of the present application is as follows: The embodiment of the present application provides a multi-current-path bidirectional SCR device for ESD protection, which comprises: a P-type substrate, an N-type epitaxial layer, a first P-type buried layer, an N-type buried layer, a second P-type buried layer, a first P-type well region, an N-type well region, a second P-type well region, an anode P+ region, an anode N+ region, a floating N+ region, a cathode N+ region and a cathode P+ region. The anode P+ region and the anode N+ region are located inside the first P-type well region, the upper edge of which is tangent to the upper edge of the first P-type well region, and the lower edge of which is higher than the lower edge of the first P-type well region; the anode P+ region is located left to the anode N+ region, and the right edge of the anode P+ region is tangent to the left edge of the anode N+ region, both of which are located on the same horizontal line as the lower edge of the floating N+ region; the left edge of the anode P+ region is spaced apart from the left edge of the first P-type well region; the right edge of the anode N+ region is spaced apart from the left edge of the floating N+ region; The floating N+ region is located inside the N-type well region, the upper edge of which is tangent to the upper edge of the N-type well region, and the lower edge of which is higher than the lower edge of the N-type well region; the left edge of the floating N+ region is spaced apart from the right edge of the anode N+ region, and the right edge of the floating N+ region is spaced apart from the left edge of the cathode N+ region; The cathode N+ region and the cathode P+ region are located inside the second P-type well region, the upper edge of which is tangent to the upper edge of the second P-type well region, and the lower edge of which is higher than the lower edge of the second P-type well region; the cathode N+ region is located left to the cathode P+ region, and the right edge of the cathode N+ region is tangent to the left edge of the cathode P+ region, both of which are located on the same horizontal line as the lower edge of the floating N+ region; the right edge of the cathode P+ region is spaced apart from the right edge of the second P-type well region; the left edge of the cathode N+ region is spaced apart from the right edge of the floating N+ region; The first P-type well region and the N-type well region and the second P-type well region are all located inside the N-type epitaxial layer; the left edge of the first P-type well region is tangent to the left edge of the N-type epitaxial layer, the right edge of which is tangent to the left edges of the floating N+ region and the N-type well region, and the lower edge of which is tangent to the upper edge of the first P-type buried layer; the left edge of the N-type well region is tangent to the right edge of the first P-type well region, the lower edge of which is tangent to the upper edge of the N-type buried layer, and the right edge of which is tangent to the left edge of the second P-type well region; the left edge of the second P-type well region is tangent to the right edges of the floating N+ region and the N-type well region, and the right edge of which is tangent to the right edge of the N-type epitaxial layer, and the lower edge of which is tangent to the upper edge of the second P-type buried layer; The first P-type buried layer and the N-type buried layer and the second P-type buried layer are all located inside the N-type epitaxial layer, and the lower edges of the three are located on the same horizontal line and are higher than the lower edge of the N-type epitaxial layer; the left edge of the first P-type buried layer is tangent to the left edge of the N-type epitaxial layer, the upper edge of which is tangent to the lower edge of the first P-type well region, and the right edge of which is tangent to the left edge of the N-type buried layer; the upper edge of the N-type buried layer is tangent to the lower edge of the N-type well region; the left edge of the second P-type buried layer is tangent to the right edge of the N-type buried layer, the upper edge of which is tangent to the lower edge of the second P-type well region, and the right edge of which is tangent to the right edge of the N-type epitaxial layer; The lower edge of the N-type epitaxial layer is tangent to the upper edge of the P-type substrate, and the lower edge of the N-type epitaxial layer is higher than the lower edge of the P-type substrate.

[0005] Further, the reverse breakdown voltage of the PN junction formed by the floating N+ region and the second P-type well region is less than the reverse breakdown voltage of the PN junction formed by the N-type buried layer and the second P-type buried layer.

[0006] Further, the reverse breakdown voltage of the PN junction formed by the floating N+ region and the second P-type well region is V B1 , the reverse breakdown voltage of the PN junction formed by the N-type buried layer and the second P-type buried layer is V B2 ; V B2 / V B1 =n (n>1), the relationship between the reduced concentration N0 of the PN junction formed by the floating N+ region and the second P-type well region and V B2 , V B1 is shown in formula (1): (1).

[0007] Further, the range of n is 1.1

[0008] Further, the ratio of the donor impurity concentration N nB of the N-type buried layer and the acceptor impurity concentration N pB of the second P-type buried layer is shown in formula (2): (2) Wherein, N0 is the reduced concentration of the PN junction formed by the floating N+ region and the second P-type well region.

[0009] The technical scheme provided by the embodiment of the application has the beneficial effects that: on the basis of the structure of the traditional bidirectional SCR device for ESD protection, the buried layer structure is introduced, the internal current path of the device is divided into the well region current path and the buried layer current path, the heat distribution in the device is optimized, the heat distribution of the device is more uniform, the failure current of the device is improved without increasing the area of the device, the performance of the device per unit area is increased, and the anti-electric surge capability of the device is enhanced. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 It is a structure schematic diagram of the traditional bidirectional SCR device for ESD protection.

[0011] Figure 2 It is a structure schematic diagram of the multi-current-path bidirectional SCR device for ESD protection in the embodiment of the application.

[0012] Figure 3 It is a new current path schematic diagram of the multi-current-path bidirectional SCR device for ESD protection in the embodiment of the application.

[0013] Figure 4 It is an I-V characteristic curve schematic diagram of the traditional bidirectional SCR device for ESD protection.

[0014] Figure 5An I-V characteristic curve diagram of the multi-current path bidirectional SCR device for ESD protection in the embodiment of the present application. DETAILED DESCRIPTION

[0015] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0016] In the description of the embodiments of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", "third" are only for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0017] In the description of the embodiments of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood in a broad sense, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication between two elements, it can be wireless connection, or it can be wired connection. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0018] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0019] The conventional bidirectional SCR device for ESD protection, as shown in Figure 1 includes a P-type substrate 001, an N-type epitaxial layer 100, a first P-type well region 301, an N-type well region 302, a second P-type well region 303, an anode P+ region 401, an anode N+ region 402, a floating N+ region 403, a cathode N+ region 404, and a cathode P+ region 405. The multi-current path bidirectional SCR device for ESD protection (hereinafter referred to as bidirectional SCR device) provided in the embodiment of the present application, compared with the conventional bidirectional SCR device, increases the buried layer structure, i.e. the first P-type buried layer 201, the N-type buried layer 202, and the second P-type buried layer 203; as shown in Figure 2 The multi-current path bidirectional SCR device for ESD protection provided in the embodiment of the present application comprises: P-type substrate 001, N-type epitaxial layer 100, first P-type buried layer 201, N-type buried layer 202, second P-type buried layer 203, first P-type well region 301, N-type well region 302, second P-type well region 303, anode P+ region 401, anode N+ region 402, floating N+ region 403, cathode N+ region 404, cathode P+ region 405; The anode P+ region 401 and the anode N+ region 402 are located inside the first P-type well region 301, the upper edge of which is tangent to the upper edge of the first P-type well region 301, and the lower edge of which is higher than the lower edge of the first P-type well region 301; the anode P+ region 401 is located on the left side of the anode N+ region 402, and the right edge of which is tangent to the left edge of the anode N+ region 402, both of which are located on the same horizontal line as the lower edge of the floating N+ region 403; the left edge of the anode P+ region 401 is spaced apart from the left edge of the first P-type well region 301; the right edge of the anode N+ region 402 is spaced apart from the left edge of the floating N+ region 403; The floating N+ region 403 is inside the N-type well region 302, the upper edge of which is tangent to the upper edge of the N-type well region 302, and the lower edge of which is higher than the lower edge of the N-type well region 302; the left edge of the floating N+ region 403 is a certain distance from the right edge of the anode N+ region 402, and the right edge of the floating N+ region 403 is a certain distance from the left edge of the cathode N+ region 404; The cathode N+ region 404 and the cathode P+ region 405 are located inside the second P-type well region 303, the upper edge of which is tangent to the upper edge of the second P-type well region 303, and the lower edge of which is higher than the lower edge of the second P-type well region 303; the cathode N+ region 404 is located on the left side of the cathode P+ region 405, and the right edge of which is tangent to the left edge of the cathode P+ region 405, both of which are located on the same horizontal line as the lower edge of the floating N+ region 403; the right edge of the cathode P+ region 405 is spaced apart from the right edge of the second P-type well region 303; the left edge of the cathode N+ region 404 is spaced apart from the right edge of the floating N+ region 403; The first P-type well region 301 and the N-type well region 302 and the second P-type well region 303 are all located inside the N-type epitaxial layer 100; the left edge of the first P-type well region 301 is tangent to the left edge of the N-type epitaxial layer 100, the right edge of which is tangent to the left edges of the floating N+ region 403 and the N-type well region 302, and the lower edge of which is tangent to the upper edge of the first P-type buried layer 201; the left edge of the N-type well region 302 is tangent to the right edge of the first P-type well region 301, the lower edge of which is tangent to the upper edge of the N-type buried layer 202, and the right edge of which is tangent to the left edge of the second P-type well region 303; the left edge of the second P-type well region 303 is tangent to the right edges of the floating N+ region 403 and the N-type well region 302, the right edge of which is tangent to the right edge of the N-type epitaxial layer 100, and the lower edge of which is tangent to the upper edge of the second P-type buried layer 203; The first P-type buried layer 201, the N-type buried layer 202, and the second P-type buried layer 203 are all located inside the N-type epitaxial layer 100, and their lower edges are located on the same horizontal line and are higher than the lower edge of the N-type epitaxial layer 100. The left edge of the first P-type buried layer 201 is tangent to the left edge of the N-type epitaxial layer 100, its upper edge is tangent to the lower edge of the first P-type well region 301, and its right edge is tangent to the left edge of the N-type buried layer 202. The upper edge of the N-type buried layer 202 is tangent to the lower edge of the N-type well region 302. The left edge of the second P-type buried layer 203 is tangent to the right edge of the N-type buried layer 202, its upper edge is tangent to the lower edge of the second P-type well region 303, and its right edge is tangent to the right edge of the N-type epitaxial layer 100. The lower edge of the N-type epitaxial layer 100 is tangent to the upper edge of the P-type substrate 001 , and the lower edge thereof is higher than the lower edge of the P-type substrate 001 .

[0020] Based on the structure of a traditional bidirectional SCR device for ESD protection, this application introduces a buried layer structure, divides the internal current path of the device into a well region current path and a buried layer current path, optimizes the heat distribution inside the device, makes the heat distribution of the device more uniform, increases the failure current of the device without increasing the device area, increases the performance of the device per unit area, and enhances the device's ability to withstand electrical surges.

[0021] like Figure 3 As shown, when the ESD voltage comes, if the voltage is small, the PN junction formed by the floating N+ region 403 and the second P-type well region 303 is reversely broken down, and the current starts from the anode P+ region 401, flows through the first P-type well region 301, the N-type well region 302, the floating N+ region 403, the second P-type well region 303 in sequence, and finally discharges through the cathode P+ region 405. At this time, the current is small; As holes accumulate in the second P-type well region 303, the PN junction formed by the second P-type well region 303 and the cathode N+ region 404 conducts forward, and the current increases further. At this point, the first trigger voltage of the device is reached, forming a current path when the traditional bidirectional SCR device is turned on: the current starts from the anode P+ region 401, flows through the first P-type well region 301, the N-type well region 302, the second P-type well region 303, and finally discharges through the cathode N+ region 404. The above two paragraphs describe the well current path; the internal current path of the traditional bidirectional SCR device is only the well current path; like Figure 3As shown by the middle dotted line a, when the voltage increases further, the PN junction formed by the N-type buried layer 202 and the second P-type buried layer 203 in the buried layer structure reversely breaks down. At this time, a new non-conducting SCR structure is formed under the well region. The new current path is: the current starts from the anode P+ region 401, flows through the first P-type well region 301, the first P-type buried layer 201, the N-type buried layer 202, the second P-type buried layer 203, the second P-type well region 303, and finally discharges through the cathode P+ region 405; like Figure 3 As shown by the middle dotted line b, when the voltage increases further, as holes accumulate in the second P-type well region 303, the PN junction formed in the vertical direction between the second P-type well region 303 and the cathode N+ region 404 is turned on, and the current further increases. At this time, the second trigger voltage of the device is reached. At this time, a new conductive SCR structure is formed below the well region. The new current path is: the current starts from the anode P+ region 401, flows through the first P-type well region 301, the first P-type buried layer 201, the N-type buried layer 202, the second P-type buried layer 203, the second P-type well region 303, and finally discharges through the cathode N+ region 404; The above two paragraphs describe the buried layer current path added in this application; the IV characteristic curve of the traditional bidirectional SCR device is as follows Figure 4 As shown, the IV characteristic curve of the bidirectional SCR device proposed in this application is as follows Figure 5 As shown, it can be seen that the present application divides the internal current path of the device into a well region current path and a buried layer current path. The new current path enables the device to have an additional snapback (quick recovery) when the current is high. The reverse breakdown voltage of the PN junction formed by the floating N+ region 403 and the second P-type well region 303 is slightly lower than the reverse breakdown voltage of the PN junction formed by the N-type buried layer 202 and the second P-type buried layer 203; thereby, the well region current path is generated before the buried layer current path. The buried layer current path is a supplement to the well region current path, which makes the area of ​​the current path larger, optimizes the heat distribution inside the device, makes the heat distribution inside the device more uniform, and enhances the device's ability to resist electrical surges.

[0022] The reverse breakdown voltage of the PN junction formed by the floating N+ region 403 and the second P-type well region 303 is V B1 The reverse breakdown voltage of the PN junction formed by the N-type buried layer 202 and the second P-type buried layer 203 is V B2 ; V B2 / V B1 =n (n>1), then the reduced concentration N0 of the PN junction formed by the floating N+ region 403 and the second P-type well region 303 is related to V B2 、V B1 The relationship is shown in formula (1): (1) For example, the reverse breakdown voltage V B1 of the PN junction formed by the floating N+ region 403 and the second P-type well region 303 is about 7.5V, and the reverse breakdown voltage V B2 of the PN junction formed by the N-type buried layer 202 and the second P-type buried layer 203 is about 9V. B1 V 17 , then the reduced concentration N0 of the PN junction formed by the floating N+ region 403 and the second P-type well region 303 is 1.3x10 -3 cm nB -2, for example, 1.2, 1.4, 1.6, 1.8, etc. Further, the present application also proposes a proportional relationship between the donor impurity concentration N pB of the N-type buried layer 202 and the acceptor impurity concentration N nB of the second P-type buried layer 203, as shown in formula (2): (2) Wherein, N0 is the reduced concentration of the PN junction formed by the floating N+ region 403 and the second P-type well region 303; this proportional relationship is not a simple application of the traditional empirical formula, but a structural parameter specially designed by the present application to ensure the stable operation of the ESD protection device; by accurately setting the doping concentration proportional relationship of the PN junction formed between the N-type buried layer 202 and the second P-type buried layer 203, i.e. the proportional relationship between the donor impurity concentration N nB of the N-type buried layer 202 and the acceptor impurity concentration N pB of the second P-type buried layer 203, the controllability of the reverse breakdown voltage, the conduction characteristic and the triggering behavior is realized.

[0023] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present application and not to limit it. Although the present application has been described in detail with reference to the embodiments, it should be understood by those skilled in the art that the technical solutions of the present application can be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present application, and they should be covered in the scope of the claims of the present application.

Claims

1. A multi-current path bidirectional SCR device for ESD protection, characterized in that: include: P-type substrate (001), N-type epitaxial layer (100), first P-type buried layer (201), N-type buried layer (202), second P-type buried layer (203), first P-type well region (301), N-type well region (302), second P-type well region (303), anode P+ region (401), anode N+ region (402), floating N+ region (403), cathode N+ region (404), cathode P+ region (405); The anode P+ region (401) and the anode N+ region (402) are located inside the first P-type well region (301), and their upper edges are tangent to the upper edge of the first P-type well region (301), and their lower edges are higher than the lower edge of the first P-type well region (301); the anode P+ region (401) is located on the left side of the anode N+ region (402), and its right edge is tangent to the left edge of the anode N+ region (402), and both are located on the same horizontal line as the lower edge of the floating N+ region (403); the left edge of the anode P+ region (401) is spaced a certain distance from the left edge of the first P-type well region (301); the right edge of the anode N+ region (402) is spaced a certain distance from the left edge of the floating N+ region (403); The floating N+ region (403) is inside the N-type well region (302), and its upper edge is tangent to the upper edge of the N-type well region (302), and its lower edge is higher than the lower edge of the N-type well region (302); the left edge of the floating N+ region (403) is a certain distance away from the right edge of the anode N+ region (402), and the right edge of the floating N+ region (403) is a certain distance away from the left edge of the cathode N+ region (404); The cathode N+ region (404) and the cathode P+ region (405) are located inside the second P-type well region (303), with their upper edges being tangent to the upper edge of the second P-type well region (303), and their lower edges being higher than the lower edge of the second P-type well region (303); the cathode N+ region (404) is located on the left side of the cathode P+ region (405), and its right edge is tangent to the left edge of the cathode P+ region (405), and both are located on the same horizontal line as the lower edge of the floating N+ region (403); the right edge of the cathode P+ region (405) is spaced a certain distance from the right edge of the second P-type well region (303); and the left edge of the cathode N+ region (404) is spaced a certain distance from the right edge of the floating N+ region (403); The first P-type well region (301), the N-type well region (302) and the second P-type well region (303) are all located inside the N-type epitaxial layer (100); the left edge of the first P-type well region (301) is tangent to the left edge of the N-type epitaxial layer (100), the right edge thereof is tangent to the floating N+ region (403) and the left edge of the N-type well region (302), and the lower edge thereof is tangent to the upper edge of the first P-type buried layer (201); the left edge of the N-type well region (302) is tangent to the left edge of the N-type epitaxial layer (100); The upper edge of the second P-type well region (303) is tangent to the right edge of the first P-type well region (301), the lower edge is tangent to the upper edge of the N-type buried layer (202), and the right edge is tangent to the left edge of the second P-type well region (303); the left edge of the second P-type well region (303) is tangent to the floating N+ region (403) and the right edge of the N-type well region (302), the right edge is tangent to the right edge of the N-type epitaxial layer (100), and the lower edge is tangent to the upper edge of the second P-type buried layer (203); The first P-type buried layer (201), the N-type buried layer (202), and the second P-type buried layer (203) are all located inside the N-type epitaxial layer (100), and the lower edges of the three are located on the same horizontal line and are higher than the lower edge of the N-type epitaxial layer (100); the left edge of the first P-type buried layer (201) is tangent to the left edge of the N-type epitaxial layer (100), the upper edge thereof is tangent to the lower edge of the first P-type well region (301), and the right edge thereof is tangent to the left edge of the N-type buried layer (202); the upper edge of the N-type buried layer (202) is tangent to the lower edge of the N-type well region (302); the left edge of the second P-type buried layer (203) is tangent to the right edge of the N-type buried layer (202), the upper edge thereof is tangent to the lower edge of the second P-type well region (303), and the right edge thereof is tangent to the right edge of the N-type epitaxial layer (100); The lower edge of the N-type epitaxial layer (100) is tangent to the upper edge of the P-type substrate (001), and the lower edge of the N-type epitaxial layer (100) is higher than the lower edge of the P-type substrate (001).

2. The multi-current path bidirectional SCR device for ESD protection according to claim 1, characterized in that: The reverse breakdown voltage of the PN junction formed by the floating N+ region (403) and the second P-type well region (303) is lower than the reverse breakdown voltage of the PN junction formed by the N-type buried layer (202) and the second P-type buried layer (203).

3. The multi-current path bidirectional SCR device for ESD protection according to claim 2, wherein: The reverse breakdown voltage of the PN junction formed by the floating N+ region (403) and the second P-type well region (303) is V B1 , the reverse breakdown voltage of the PN junction formed by the N-type buried layer (202) and the second P-type buried layer (203) is V B2 ; V B2 / V B1 =n (n>1), then the reduced concentration N0 of the PN junction formed by the floating N+ region (403) and the second P-type well region (303) is related to V B2 、V B1 The relationship is shown in formula (1): (1)。 4. The multi-current path bidirectional SCR device for ESD protection according to claim 2, wherein: The range of n is 1.1<n<2.

5. The multi-current path bidirectional SCR device for ESD protection according to claim 2, wherein: Donor impurity concentration N of the N-type buried layer (202) nB and the second P-type buried layer (203) has an acceptor impurity concentration N pB The proportional relationship is shown in formula (2): (2) Wherein, N0 is the reduced concentration of the PN junction formed by the floating N+ region (403) and the second P-type well region (303).

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