LDMOS device with stepped LTO and manufacturing method thereof

Abstract

The invention discloses an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device with a stepped LTO (Low Temperature Oxide) and a manufacturing method thereof. The stepped field plate structure is added on the basis of an original LDMOS device structure, and compared with the original LDMOS device structure, under the same drift region doping concentration, the drift region of the stepped field plate LDMOS structure can be better depleted, so that equipotential lines are arranged more widely and uniformly, the breakdown voltage of the device is remarkably improved, the on-resistance is maintained, and the performance of the device is improved. And the overall performance of the device is improved. On the basis of an original LDMOS device structure, the stepped field plate structure can be achieved only by adding two etching steps, better device performance is obtained while the process complexity of the LDMOS device is not remarkably increased, and mass production and application of the structure are facilitated.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor integrated circuits, and particularly relates to an LDMOS device with stepped LTO and a manufacturing method thereof. BACKGROUND

[0002] Power integrated circuits and power devices play a vital role in people's life and the development of science and technology. Lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS) is an important part of power devices and also a core device of BCD technology. Due to its excellent characteristics of high withstand voltage and low on-resistance, LDMOS is widely used in advanced fields such as communication, battery and aerospace. The research on LDMOS devices constantly promotes the development of integrated circuit technology and the improvement of chip performance.

[0003] A conventional N-type LDMOS device is shown in FIG. 1, wherein 100 is a P-type silicon substrate. 101 is an N-type drift region above the silicon substrate, which is the main part of the LDMOS device. The introduction of the drift region significantly improves the breakdown voltage of the device. 102 is a P-well. 103a and 103b are N-type heavily doped regions, which are used to significantly reduce the contact resistance of the device. 104 is a P-type heavily doped region. 103a and 101 together form the drain region of the device, and 104, 103b and 102 form the source region of the device. 107 is the side wall of the device, 106 is the polysilicon gate, and 105 is the gate dielectric layer. Figure 1 For LDMOS devices, the main performance indicators are breakdown voltage BV and on-resistance. It is desired to have a large breakdown voltage and a small on-resistance at the same time. However, the two performance indicators of LDMOS devices are mutually restrictive, and it is impossible to improve the breakdown voltage while reducing the on-resistance. For example, to improve the breakdown voltage, methods such as reducing the doping concentration of the drift region and extending the length of the drift region can be used, but these methods will significantly increase the on-resistance of the device, which may not meet the expected performance requirements of the device. Therefore, for the design of LDMOS devices, the breakdown voltage of the device is first made to meet the requirements, and then various process methods are used to make the on-resistance of the device as small as possible. The final performance of the device is measured by calculating the figure of merit (FOM), where FOM = BV 2 / R ON，SP .

[0004]

[0005] ​In the prior art, in order to improve the breakdown voltage of the LDMOS device, the most common method is to reduce the doping concentration of the drift region. Although reducing the doping concentration of the drift region can significantly improve the breakdown voltage of the device, it will also cause the on-resistance of the device to increase significantly. High doping concentration of the drift region can significantly reduce the on-resistance of the device, but it will also cause the breakdown voltage of the device to decrease significantly, which is caused by the fact that the drift region cannot be completely depleted. In order to overcome such shortcomings, the field plate (FP) technology is introduced in the conventional LDMOS device.

[0006] The N-type LDMOS device structure with a field plate is shown in FIG. 1. Figure 2 In which 200 is a P-type silicon substrate, 201 and 203a constitute the drain region of the device, 203b, 204 and 202 constitute the source region of the device, 206 and 205 together constitute the field plate and gate oxide layer of the device, 207 is the side wall of the device, and 208 is the polysilicon gate. Since the device introduces a field plate, the field plate expands the electric field distribution, making the electric field distribution on the surface of the LDMOS device more uniform, reducing the concentration of the electric field, making the electric field distribution more uniform, and greatly improving the breakdown voltage of the device. At the same time, due to the uniform electric field distribution, the current path can be more uniform, thereby improving the on-resistance. In addition, the field plate can also reduce the formation of local hot spots, reduce the temperature rise of the device during operation, and improve the reliability.

[0007] However, the existing field plate technology has very limited performance improvement for the device, and its ability to expand the depletion region is insufficient. In the case of high doping concentration of the drift region, the drift region of the LDMOS device cannot be completely depleted, thereby causing the electric field to be concentrated, limiting the improvement of the breakdown voltage of the device. Lower doping concentration of the drift region can better deplete and thereby improve the breakdown voltage of the device, but it will greatly sacrifice the on-resistance of the device. From the perspective of improving the performance of the device, its role is very limited. And from the design point of view, the ordinary field plate design is relatively fixed and cannot be flexibly adjusted according to the requirements of the device. The introduction of the field plate requires additional processes such as light exposure, etching, and deposition, which increases the cost and has limited performance improvement, and the cost performance is relatively low. SUMMARY

[0008] The present application provides a LDMOS device with stepped LTO and a manufacturing method thereof.

[0009] A LDMOS device with stepped LTO, comprising:

[0010] A P-type silicon substrate;

[0011] An N-type drift region located above the P-type silicon substrate;

[0012] A drain region composed of the N-type drift region and an N-type heavily doped region;

[0013] a source region, which is composed of a P-type heavily doped region, an N-type heavily doped region and a P-well;

[0014] a polysilicon gate;

[0015] a gate dielectric layer, which is located below the polysilicon gate;

[0016] a stepped field plate, which, together with the gate dielectric layer, forms a stepped field plate structure, and the stepped field plate can more finely adjust the surface electric field of the device, so that the drift region is better depleted, thereby improving the breakdown voltage of the device and maintaining the on-resistance;

[0017] a side wall, which is located on both sides of the polysilicon gate, and is used to provide side wall protection and insulation performance.

[0018] a manufacturing method of the above device, comprising the following steps:

[0019] providing a P-type silicon substrate;

[0020] forming an N-type drift region above the P-type silicon substrate;

[0021] forming a drain region, which is composed of the N-type drift region and an N-type heavily doped region;

[0022] forming a source region, which is composed of a P-type heavily doped region, an N-type heavily doped region and a P-well;

[0023] forming a polysilicon gate and a gate dielectric layer;

[0024] forming a side wall on both sides of the polysilicon gate, and the material of the side wall is silicon nitride, and the thickness is 50-200 nanometers, which is used to provide side wall protection and insulation performance;

[0025] forming a stepped field plate through an etching step, and the stepped field plate, together with the gate dielectric layer, forms a stepped field plate structure, which can more finely adjust the surface electric field of the device, so that the drift region is better depleted, thereby improving the breakdown voltage of the device and maintaining the on-resistance.

[0026] Advantages of the present application:

[0027] The present application adds a stepped field plate structure on the basis of the original LDMOS device structure, and compared with the original LDMOS device structure, under the same drift region doping concentration, the drift region of the stepped field plate LDMOS structure can be better depleted, so that the arrangement of equipotential lines is more wide and uniform, the breakdown voltage of the device is significantly improved, and the on-resistance is maintained, so that the overall performance of the device is improved.

[0028] The application only needs to increase two etching steps to realize the stepped field plate structure on the basis of the original LDMOS device structure, and better device performance is obtained without significantly increasing the process complexity of the LDMOS device, which is conducive to the mass production and use of the structure. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 An N-type LDMOS device structure in the prior art is shown in the figure;

[0030] Figure 2 An N-type LDMOS device structure with a field plate and a variable-doping drift region in the prior art is shown in the figure;

[0031] Figure 3 An N-type LDMOS device structure with a stepped field plate according to the application is shown in the figure;

[0032] Figure 4 An N-type stepped field plate LDMOS device according to the application in an open condition is shown in the figure;

[0033] Figure 5 Simulation results of the depletion regions of two LDMOS devices are shown in the figure;

[0034] Figure 6 Simulation results of the equipotential line distribution of two LDMOS devices are shown in the figure;

[0035] Figure 7 A manufacturing flowchart of the stepped field plate part of the LDMOS device with a stepped field plate structure is shown in the figure. DETAILED DESCRIPTION

[0036] The application will be further described below in combination with the drawings and embodiments.

[0037] The LDMOS device structure with a stepped field plate provided by the application is shown in the figure Figure 3 , and the most critical part is 306, which is a stepped field plate. The remaining parts are the same as those of a common LDMOS device structure. 300 is a silicon substrate, 301 and 303a constitute the drain region of the device, 302, 304, and 303b constitute the source region of the device, 305 and 306 jointly constitute the stepped field plate and the gate oxide, 307 is a side wall, and 308 is a polysilicon gate.

[0038] Further, the stepped field plate includes two steps with different heights, and the height difference of each step is 100-500 nanometers, so as to finely adjust the electric field distribution.

[0039] Further, the doping concentration of the N-type drift region is 8.0×10 16 -3.0×10 17 cm -3, to keep a low on-resistance while improving the breakdown voltage.

[0040] Further, the sidewall is made of silicon nitride with a thickness of 120 nm to provide better sidewall protection and insulation performance.

[0041] The LDMOS device with the asymmetric trench structure has the same working principle as a common LDMOS device. When corresponding voltages are applied to the three terminals (gate, drain and source) of the device, the P-type region below the gate will undergo inversion to form a conductive channel, and electrons will flow from the source to the drain. Since the current direction is opposite to the electron flow direction, the current flows from the drain to the source, as shown in FIG. 1. Figure 4 Since the current flows through the drift region, the drift region has a voltage dividing effect, which can greatly improve the breakdown voltage of the LDMOS device.

[0042] Due to the presence of the stepped field plate, the drift region of the LDMOS with the stepped field plate can be better depleted than the common LDMOS with a field plate. Figure 5 As shown in FIG. 2, the white solid line in the figure is the depletion region boundary, and the drift region has the same 1.75 x 10 17 cm -3 The drift region of the LDMOS device with the stepped field plate has a larger depletion region under the same 1.75 x 10

[0043] The distribution of the equipotential lines of the device is shown in FIG. 3, and the black solid line in the figure is the equipotential line. Figure 6 As can be seen from the figure, the equipotential line distribution of the LDMOS device with the stepped field plate is more uniform.

[0044] For the stepped field plate LDMOS device, the application also provides a manufacturing scheme based on the manufacturing process of a common LDMOS device, which only needs to add a few simple additional process steps to realize, which is convenient for production and manufacturing, and also reduces the cost of manufacturing the device.

[0045] Figure 7 The key process manufacturing steps of the stepped field plate LDMOS are shown in FIG. 4, and the other process flows are the same as those of the common LDMOS device. Figure 7As shown, on the basis of the original LDMOS field plate process, the stepped field plate structure can be realized by repeated etching, wherein the etching gas used in the etching step is a mixed gas of chlorine and nitrogen trifluoride, and the etching temperature is 20-25 degrees Celsius, so as to ensure the accuracy and uniformity of etching. After forming the stepped field plate, a step of oxidizing the surface of the stepped field plate is further included to enhance its insulation performance and stability. The step of forming the side wall includes: depositing a silicon nitride film; and forming a side wall structure by a plasma etching process, and the thickness of the side wall is 120 nanometers. Compared with the original process, only two masks are needed to realize the structure, which does not greatly increase the complexity of the process, while the overall performance of the LDMOS device is greatly improved.

[0046] In summary, by introducing the stepped field plate technology into the ordinary field plate technology, the surface electric field of the device is more finely adjusted, more flexibility is provided for the structure design of the field plate LDMOS device to adapt to different application scenarios, and the expansion of the depletion region is improved based on the original field plate structure LDMOS device, the breakdown voltage of the device is further improved, the on-resistance of the device is reduced, the performance of the LDMOS device is obviously improved, and higher device breakdown voltage is obtained under the same device parameters.

[0047] In addition, compared with the original ordinary field plate LDMOS, the device performance is better without additional excessive process steps, the performance-price ratio of the LDMOS device process manufacturing is improved, new ideas are provided for the structure design of other LDMOS devices, the application of the LDMOS device in the field of high frequency and high power is strengthened, and the research and development of the performance improvement of the LDMOS device are promoted.

[0048] The above is the preferred embodiment of the present application, and it should be pointed out that for ordinary skilled persons in the technical field, a number of improvements and refinements can be made without departing from the principles of the present application, and these improvements and refinements are also considered to be within the protection scope of the present application.

Claims

1. An LDMOS device with stepped LTO, characterized in that: include: P-type silicon substrate (300); An N-type drift region (301) located above the P-type silicon substrate; A drain region, consisting of the N-type drift region (301) and an N-type heavily doped region (303a); A source region, consisting of a P-type heavily doped region (304), an N-type heavily doped region (303b) and a P-well (302); polysilicon gate (308); A gate dielectric layer (305) is located below the polysilicon gate (308); A stepped field plate (306) and the gate dielectric layer (305) together form a stepped field plate structure, wherein the stepped field plate can more finely adjust the surface electric field of the device, thereby better depleting the drift region, thereby increasing the breakdown voltage of the device and maintaining the on-resistance; The sidewalls (307) are located on both sides of the polysilicon gate (308) and are used to provide sidewall protection and insulation performance.

2. The LDMOS device with stepped LTO according to claim 1, wherein: The stepped field plate (306) comprises a plurality of steps of different heights, and the height difference of each step is 10-40 nanometers, so as to achieve fine adjustment of the electric field distribution.

3. The LDMOS device with stepped LTO according to claim 1, wherein: The doping concentration of the N-type drift region (301) is 8×10 16 -3×10 17 cm -3 , in order to increase the breakdown voltage while maintaining a low on-resistance.

4. The LDMOS device with stepped LTO according to claim 2, wherein: The number of steps of the stepped field plate (306) is 2-5, so as to optimize the electric field distribution and performance of the device.

5. The LDMOS device with stepped LTO according to any one of claims 1 to 4, characterized in that: The material of the sidewall (307) is silicon nitride with a thickness of 120 nanometers to provide better sidewall protection and insulation performance.

6. A method for manufacturing an LDMOS device with a stepped LTO, characterized in that: The following steps are involved: Providing a P-type silicon substrate (300); forming an N-type drift region (301) above the P-type silicon substrate; forming a drain region, wherein the drain region is composed of the N-type drift region (301) and the N-type heavily doped region (303a); forming a source region, wherein the source region is composed of a P-type heavily doped region (304), an N-type heavily doped region (303b) and a P well (302); forming a polysilicon gate (308) and a gate dielectric layer (305); forming sidewalls (307) on both sides of the polysilicon gate (308), wherein the sidewalls are made of silicon nitride and have a thickness of 120 nanometers, and are used to provide sidewall protection and insulation performance; A stepped field plate (306) is formed by etching, and the stepped field plate and the gate dielectric layer (305) together constitute a stepped field plate structure, which can more finely adjust the surface electric field of the device, so that the drift region is better depleted, thereby increasing the breakdown voltage of the device and maintaining the on-resistance.

7. The method for manufacturing an LDMOS device with a stepped LTO according to claim 6, wherein: The etching gas used in the etching step is a mixed gas of chlorine and nitrogen trifluoride, and the etching temperature is 30-50 degrees Celsius to ensure the accuracy and uniformity of the etching.

8. The method for manufacturing an LDMOS device with a stepped LTO according to claim 6, wherein: After forming the stepped field plate (306), the method further includes a step of oxidizing the surface of the stepped field plate to enhance its insulation performance and stability.

9. The method for manufacturing an LDMOS device with a stepped LTO according to claim 6, wherein: The steps of forming the sidewall (307) include: Deposition of silicon nitride thin films; The sidewall structure is formed by a plasma etching process, and the thickness of the sidewall is 120 nanometers.

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