A method and apparatus for verifying signal isolation values ​​based on signal reset operation

Abstract

This invention belongs to the field of low-power design and discloses a method and apparatus for verifying signal isolation values ​​based on signal reset operation. The method includes: acquiring design specification data and power management description files of the circuit under test; generating a verification platform in a simulation environment and identifying multiple signals under test; applying control signals to the circuit under test through the verification platform to make the circuit under test enter an isolated state, and acquiring first signal isolation values ​​corresponding to the multiple signals under test before the circuit under test is powered on; acquiring second signal isolation values ​​corresponding to the multiple signals under test after the circuit under test is powered on and the reset operation is effective; comparing whether the expected signal isolation value, the first signal isolation value and the second signal isolation value corresponding to each of the multiple signals under test are consistent; and generating a signal isolation value verification result for each signal under test based on the comparison results, ensuring that the effectiveness of the ISO mechanism can be detected early in the circuit design process.

Description

Technical Field

[0001] This invention belongs to the field of low-power design technology, and specifically relates to a method and apparatus for verifying signal isolation values ​​based on signal reset operation. Background Technology

[0002] In VLSI design, ISO (isolation) is a key technology for achieving multi-voltage domain power management. Specifically, in low-power mode, certain circuit modules are isolated by cutting off power or setting specific signal states.

[0003] In existing technologies, the correctness of ISO values ​​is typically verified through comprehensive simulation testing after the circuit design is completed. This method of checking ISO accuracy has technical problems of high time and high modification costs. Specifically, it requires significant resources to be invested in testing late in the design process, extending the overall development cycle and resulting in high time costs. Furthermore, if ISO-related issues are discovered later, large-scale modifications to the circuit design are necessary, increasing development costs and reducing verification efficiency. Summary of the Invention

[0004] The purpose of this invention is to use a reset signal as a trigger point to automatically acquire and compare the ISO value of the signal, ensuring that the effectiveness of the ISO mechanism can be detected early in the circuit design process.

[0005] In a first aspect, embodiments of the present invention provide a method for verifying signal isolation values ​​based on a signal reset operation, the method comprising:

[0006] Obtain the design specification data and power management description file of the circuit under test. The design specification data includes the expected signal isolation values ​​corresponding to multiple test signals in the circuit under test.

[0007] Based on the power management description file, a verification platform is generated in the simulation environment, and multiple signals to be tested are identified;

[0008] The verification platform applies control signals to the circuit under test to make the circuit under test enter an isolated state, and collects the first signal isolation values ​​corresponding to the multiple test signals before the circuit under test is powered on.

[0009] After the circuit under test is powered on and stabilized and the reset operation takes effect, the second signal isolation values ​​corresponding to the multiple test signals are collected respectively.

[0010] Compare whether the expected signal isolation value, the first signal isolation value, and the second signal isolation value corresponding to each of the plurality of test signals are consistent;

[0011] Based on the comparison results, a verification result of the signal isolation value for each of the signals to be tested is generated.

[0012] Optionally, the step of generating a signal isolation value verification result for each of the signals under test based on the comparison results includes:

[0013] For each of the plurality of test signals, if the comparison result shows that the expected signal isolation value, the first signal isolation value, and the second signal isolation value corresponding to the test signal are consistent, it is determined that the signal isolation value of the test signal has passed the verification, and a verification result is generated.

[0014] If the comparison results show that the expected signal isolation value, the first signal isolation value, and the second signal isolation value corresponding to the signal under test are inconsistent, query the preset exemption list;

[0015] If the signal to be tested is in the exemption list, the signal isolation value verification of the signal to be tested is deemed successful.

[0016] If the signal to be tested is not in the exemption list, an error report is generated.

[0017] Optionally, the exemption list includes at least one of the following:

[0018] Signal markers that do not require signal isolation checks;

[0019] Rules that allow abnormal signal isolation values ​​under specific operating modes, wherein the specific operating modes include at least one of the following modes: test mode, debug mode, low power mode, and security mode.

[0020] Optionally, the error report includes identification information for locating the position of the signal under test in the design code;

[0021] The method further includes: automatically generating suggested modification schemes for the design code based on the error report.

[0022] Optionally, after automatically generating suggested modifications to the design code based on the error report, the method further includes:

[0023] Obtain the design code modified based on the modification suggestion scheme. For the target test signal that fails the verification, apply a control signal to the circuit under test through the verification platform to make it enter the isolation state, and collect the first signal isolation value corresponding to the target test signal before the circuit under test is powered on.

[0024] After the circuit under test is powered on and the reset operation takes effect, the second signal isolation value corresponding to the target test signal is collected;

[0025] Compare whether the expected signal isolation value, the first signal isolation value, and the second signal isolation value corresponding to the target signal to be tested are consistent;

[0026] If they match, the signal isolation value of the target signal to be tested has been verified as passed.

[0027] If there is a discrepancy, check the default exemption list;

[0028] If the target signal to be tested is in the exemption list, the signal isolation value verification of the target signal to be tested is deemed successful.

[0029] If the target test signal is not in the exemption list, an error report is generated again. Based on the regenerated error report, a modification suggestion scheme for the design code is automatically generated. The modified design code based on the regenerated modification suggestion scheme is obtained, and the process returns to the steps of applying a control signal to the circuit under test through the verification platform to put it into an isolated state and collecting the first signal isolation value corresponding to the target test signal before the circuit under test is powered on, until the signal isolation value of the target test signal is verified.

[0030] Optionally, based on the power management description file, a verification platform is generated in a simulation environment, including:

[0031] In the simulation environment, based on the power management description file, the first component, the second component, and the third component of the verification platform are automatically generated;

[0032] The first component is used to apply an isolation enable signal and a reset signal to the circuit under test;

[0033] The second component is used to acquire the first signal isolation value corresponding to each test signal of the circuit under test under the control of the isolation enable signal, and the second signal isolation value corresponding to each test signal of the circuit under test under the control of the reset signal.

[0034] The third component is used to compare whether the expected signal isolation value, the first signal isolation value, and the second signal isolation value corresponding to each signal to be tested are consistent.

[0035] Secondly, embodiments of the present invention provide a signal isolation value verification device based on a signal reset operation, the device comprising:

[0036] The file acquisition module is used to acquire the design specification data and power management description file of the circuit under test. The design specification data includes the expected signal isolation values ​​corresponding to multiple test signals in the circuit under test.

[0037] The verification platform generation module is used to generate a verification platform in a simulation environment based on the power management description file and identify multiple signals to be tested.

[0038] The first signal isolation value acquisition module is used to apply a control signal to the circuit under test through the verification platform to make the circuit under test enter the isolation state, and to acquire the first signal isolation values ​​corresponding to the multiple test signals before the circuit under test is powered on.

[0039] The second signal isolation value acquisition module is used to acquire the second signal isolation values ​​corresponding to the plurality of test signals respectively after the circuit under test is powered on and the reset operation takes effect.

[0040] The signal isolation value comparison module is used to compare whether the expected signal isolation value, the first signal isolation value and the second signal isolation value corresponding to each of the plurality of signals to be tested are consistent.

[0041] The verification result generation module is used to generate a signal isolation value verification result for each of the signals to be tested based on the comparison results.

[0042] Thirdly, embodiments of the present invention provide an electronic device, including:

[0043] At least one processor;

[0044] Memory for storing the at least one processor-executable instruction;

[0045] The at least one processor is configured to execute the instructions to implement the method described in the first aspect.

[0046] Fourthly, embodiments of the present invention provide a computer-readable storage medium that, when instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to perform the method described in the first aspect.

[0047] Fifthly, embodiments of the present invention provide a computer program product, including a computer program that, when executed by a processor, implements the method described in the first aspect.

[0048] The technical solution provided by this invention involves acquiring design specification data and a power management description file for the circuit under test (TBT), wherein the design specification data includes expected signal isolation values ​​corresponding to multiple test signals in the TBT; based on the power management description file, a verification platform is generated in a simulation environment, and multiple test signals are identified; through the verification platform, control signals are applied to the TBT to induce it into an isolated state, and first signal isolation values ​​corresponding to multiple test signals are acquired before the TBT is powered on; after the TBT is powered on and stabilized and the reset operation takes effect, second signal isolation values ​​corresponding to multiple test signals are acquired; the expected signal isolation value, first signal isolation value, and second signal isolation value corresponding to each test signal are compared to see if they are consistent; based on the comparison results, a signal isolation value verification result for each test signal is generated.

[0049] As can be seen, this invention utilizes a reset signal as a trigger point to automatically acquire and compare the ISO values ​​of signals, ensuring that the effectiveness of the ISO mechanism can be detected early in the circuit design process. It completely solves the problems of delayed, inefficient, costly, and high-risk signal isolation verification in traditional circuit design processes. It transforms ISO verification from a passive, late-stage detection activity into a proactive, end-to-end preventative safeguard, significantly improving the first-time success rate of circuit design and having significant value in ensuring the smooth mass production of complex, low-power chips. Attached Figure Description

[0050] Figure 1 A flowchart of a signal isolation value verification method based on signal reset operation provided in an embodiment of the present invention;

[0051] Figure 2 for Figure 1 A flowchart of a specific implementation of S160 in China;

[0052] Figure 3 A flowchart illustrating the overall technical solution provided in the embodiments of the present invention;

[0053] Figure 4 This is a schematic diagram of a signal isolation value verification device based on signal reset operation provided in an embodiment of the present invention;

[0054] Figure 5 This is a schematic diagram of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0055] The present invention will be described in detail below through embodiments.

[0056] In VLSI design, ISO (isolation) is a key technology for achieving multi-voltage domain power management. Specifically, in low-power mode, certain circuit modules are isolated by cutting off power or setting specific signal states.

[0057] In existing technologies, the correctness of ISO values ​​is typically verified through comprehensive simulation testing after the circuit design is completed. This method of checking ISO accuracy has technical problems of high time and high modification costs. Specifically, it requires significant resources to be invested in testing late in the design process, extending the overall development cycle and resulting in high time costs. Furthermore, if ISO-related issues are discovered later, large-scale modifications to the circuit design are necessary, increasing development costs and reducing verification efficiency.

[0058] This invention aims to solve the problem of low verification efficiency of signal isolation mechanisms in existing circuit designs. Furthermore, this invention proposes an ISO value comparison and inspection technique based on signal reset operation, which can efficiently and accurately detect and correct potential problems in the ISO mechanism in the early stages of design.

[0059] This invention can be applied to the design and verification ISO value process of IP cores and SOCs (System on Chips). The verification platform is automatically generated via scripts.

[0060] To ensure clarity in the description of the solution, the technical terms involved in the embodiments of the present invention will be explained before formally introducing the technical solution.

[0061] 1. ISO (Isolation) refers to isolating certain circuit modules in low-power mode by cutting off power or setting specific signal states.

[0062] 2. The ISO value refers to a specific value that a signal should maintain when entering a signal isolation state. For example, this specific value can be 0 or 1.

[0063] 3. Reset value: refers to the value set for the signal after the circuit is reset.

[0064] 4. CPF (Common Power Format) is a common file format used to describe the power structure in the early stages of the design process, making it a critical design input in the VLSI (Very Large Scale Integration) design flow.

[0065] 5. UPF (Unified Power Format) defines how power supply networks are used to extend logic specifications. It is a unified and widely adopted low-power implementation standard.

[0066] After a detailed explanation of the technical terms involved in this invention, the inventive points of this invention are summarized below. The key point of this invention lies in using a reset signal as a trigger point to automatically acquire and compare the ISO values ​​of the signals, ensuring that the effectiveness of the ISO mechanism can be detected early in the design process.

[0067] Specifically, this involves the use of automated scripts or tools to generate the various components of the verification platform, which may include a driver, monitor, and checker.

[0068] The driver can be understood as a component in the verification platform that actively applies stimuli to the circuit under test. In this invention, it mainly serves the following two purposes:

[0069] (1) Generate isolation enable signal. The analog power management unit generates a control signal to command the circuit under test to enter or exit the isolation state.

[0070] (2) Generate a reset signal. At a specific time point (such as after power-on stabilization), a reset pulse is generated to trigger the circuit under test to enter the reset state.

[0071] (3) Timing of ISO value acquisition. To ensure the consistency of ISO values, sampling should be performed before power-on and after power-on reset.

[0072] The Monitor is a component in the verification platform that passively observes and acquires the output of the circuit under test. Its main functions are as follows:

[0073] (1) Precise sampling. Before the circuit under test is powered on, and after power-on and the reset operation takes effect, the signal isolation value of the signal under test is collected respectively. For clarity of the scheme description, the signal isolation value collected before power-on can be called the first signal isolation value, and the signal isolation value collected after power-on and the reset operation takes effect can be called the second signal isolation value.

[0074] (2) Data transmission. The collected first signal isolation value and second signal isolation value are transmitted to the Checker for comparison.

[0075] The main function of the checker is to verify whether the expected signal isolation value, the first signal isolation value, and the second signal isolation value corresponding to the signal under test are consistent, thus ensuring the consistency of the three isolation values. The expected signal isolation value is recorded in the design specification data.

[0076] The technical solutions of the embodiments of the present invention will be described in detail below. Figure 1 As shown in the figure, the signal isolation value verification method based on signal reset operation provided by the present invention may include the following steps:

[0077] S110: Obtain the design specification data and power management description file of the circuit under test.

[0078] The design specification data includes the expected signal isolation values ​​corresponding to multiple test signals in the circuit under test.

[0079] In practical applications, the circuit to be tested can be an IP core or a SOC chip, etc. The embodiments of the present invention do not impose specific limitations on the circuit to be tested.

[0080] The design specification data is in the form of a SPEC file, which records the expected signal isolation values ​​for multiple signals to be tested. For example, "When the chip enters sleep mode, the USB_DATA[31:0] bus signals should be isolated and driven to all zeros (32'h0000_0000) to prevent current leakage. Therefore, the expected signal isolation value (which can be called the gold value) recorded in the SPEC file is 32'h0000_0000."

[0081] The power management description file can be either a Uniform Power Format (UPF) or a Common Power Format (CPF).

[0082] The S120, based on a power management description file, generates a verification platform in a simulation environment and identifies multiple signals to be tested.

[0083] Specifically, in the simulation environment, the automated script automatically identifies the signal whose ISO value needs to be verified by parsing the power management description file (such as UPF / CPF), which is the signal to be tested, and generates the components of the verification platform.

[0084] As one implementation of this invention, generating a verification platform in a simulation environment based on a power management description file may include the following steps:

[0085] In the simulation environment, the first, second, and third components of the verification platform are automatically generated based on the power management description file.

[0086] The first component is used to apply isolation enable and reset signals to the circuit under test. This is the driver described in the above embodiment.

[0087] The second component is used to acquire the first signal isolation value corresponding to each test signal under the control of the isolation enable signal, and the second signal isolation value corresponding to each test signal under the control of the reset signal. This is the monitor described in the above embodiment.

[0088] The third component is used to compare whether the expected signal isolation value, the first signal isolation value, and the second signal isolation value corresponding to each signal under test are consistent. This is the checker described in the above embodiment.

[0089] S130, through the verification platform, applies control signals to the circuit under test to make the circuit under test enter the isolation state, and collects the first signal isolation values ​​corresponding to multiple test signals before the circuit under test is powered on.

[0090] After generating the verification platform, the driver component can be used to apply an isolation enable signal to the circuit under test, causing the circuit under test to enter an isolated state. The monitor component can then be used to collect the first signal isolation value corresponding to each test signal under the control of the isolation enable signal.

[0091] S140: After the circuit under test is powered on and stabilized and the reset operation takes effect, the second signal isolation value corresponding to each of the multiple signals under test is collected.

[0092] In this step, the circuit under test is powered on, and after the power-on of the circuit is stable and the reset operation takes effect, the second signal isolation values ​​corresponding to the multiple signals under test are collected.

[0093] S150, compare whether the expected signal isolation value, the first signal isolation value and the second signal isolation value corresponding to each of the multiple test signals are consistent.

[0094] For each of the multiple signals to be tested, a checker is used to compare whether the expected signal isolation value, the first signal isolation value, and the second signal isolation value corresponding to that signal are consistent. Specifically, the expected signal isolation value and the first signal isolation value can be compared to determine whether they are equal, and the first signal isolation value and the second signal isolation value can be compared to determine whether they are equal.

[0095] S160, based on the comparison results, generates the signal isolation value verification result for each signal to be tested.

[0096] Specifically, for each signal to be tested, after comparing the expected signal isolation value, the first signal isolation value and the second signal isolation value corresponding to the signal to be tested, a comparison result can be obtained. The comparison result can be that the expected signal isolation value, the first signal isolation value and the second signal isolation value are consistent, or it can be that the expected signal isolation value, the first signal isolation value and the second signal isolation value are inconsistent.

[0097] This allows the generation of a signal isolation value verification result for the signal to be tested. If the comparison result shows that the expected signal isolation value, the first signal isolation value, and the second signal isolation value are consistent, the signal isolation value verification result can be considered as having passed. If the comparison result shows that the expected signal isolation value, the first signal isolation value, and the second signal isolation value are inconsistent, the signal isolation value verification result can be considered as having not yet passed and requiring further verification.

[0098] The technical solution provided by this invention involves acquiring design specification data and a power management description file for the circuit under test (TBT), wherein the design specification data includes expected signal isolation values ​​corresponding to multiple test signals in the TBT; based on the power management description file, a verification platform is generated in a simulation environment, and multiple test signals are identified; through the verification platform, control signals are applied to the TBT to induce it into an isolated state, and first signal isolation values ​​corresponding to multiple test signals are acquired before the TBT is powered on; after the TBT is powered on and stabilized and the reset operation takes effect, second signal isolation values ​​corresponding to multiple test signals are acquired; the expected signal isolation value, first signal isolation value, and second signal isolation value corresponding to each test signal are compared to see if they are consistent; based on the comparison results, a signal isolation value verification result for each test signal is generated.

[0099] As can be seen, this invention utilizes a reset signal as a trigger point to automatically acquire and compare the ISO values ​​of signals, ensuring that the effectiveness of the ISO mechanism can be detected early in the circuit design process. It completely solves the problems of delayed, inefficient, costly, and high-risk signal isolation verification in traditional circuit design processes. It transforms ISO verification from a passive, late-stage detection activity into a proactive, end-to-end preventative safeguard, significantly improving the first-time success rate of circuit design and having significant value in ensuring the smooth mass production of complex, low-power chips.

[0100] Based on the above embodiments, as one implementation of the present invention, in S160, based on the comparison results, a signal isolation value verification result for each signal to be tested is generated, such as... Figure 2 As shown, it may include the following steps:

[0101] S161, for each of the multiple test signals, if the comparison result shows that the expected signal isolation value, the first signal isolation value, and the second signal isolation value corresponding to the test signal are consistent, it is determined that the signal isolation value of the test signal has passed the verification, and a verification result is generated.

[0102] Specifically, if the expected signal isolation value, the first signal isolation value, and the second signal isolation value of a signal to be tested are consistent, it means that the signal isolation value of the test signal has been verified and a verification result is generated.

[0103] S162, if the comparison result shows that the expected signal isolation value, the first signal isolation value and the second signal isolation value corresponding to the signal to be tested are inconsistent, query the preset exemption list.

[0104] Specifically, if the expected signal isolation value, the first signal isolation value, and the second signal isolation value corresponding to a signal under test are inconsistent, an exemption list can be obtained. This exemption list can be a separate file or exist in the SPEC file. The exemption list is also called the Waiver List. The Waiver List is a predefined file that lists rules or signals that are known to fail, do not need to be checked, or can be ignored.

[0105] The benefits of setting up an exemption list are as follows:

[0106] 1. Automated checking tools are very strict and may report some errors that are incorrect from a purely syntactic point of view but are normal or insignificant from a design and functional point of view. Waive List is used to filter out these "false alarms" to avoid drowning out real errors.

[0107] 2. Improve efficiency. Avoid wasting engineers' time on known and accepted problems, and focus on dealing with new, unknown, and real-world errors.

[0108] 3. Manage known issues. For known issues that cannot be fixed temporarily or do not need to be fixed, they can be added to an exemption list for tracking and management, instead of reporting errors every time verification is performed.

[0109] As one implementation of the present invention, the exemption list includes at least one of the following:

[0110] Signal identifiers that do not require signal isolation checks.

[0111] Rules that allow abnormal signal isolation values ​​under specific operating modes.

[0112] Specifically, the exemption list includes signals that do not require signal isolation checks, allowing for quick identification of which signals do not need to have their signal isolation values ​​verified. Furthermore, it can include rules that permit abnormal signal isolation values ​​under specific operating modes.

[0113] Specific operating modes may include test mode, debug mode, low-power mode, and security mode. The rules governing permissible abnormal signal isolation values ​​in each mode are detailed below.

[0114] In test mode, normal functional logic is intentionally bypassed. For example, the scan chain takes over the internal signals of the chip. At this time, normal isolated signals may be in a non-functional state (such as being forced to a fixed value). This is expected behavior and should not cause an error.

[0115] In debug mode, some power domains may be shut down to focus on the object being debugged, or external probes may be allowed to directly access internal signals. This may violate normal isolation rules, but it is necessary for debugging.

[0116] A certain low-power mode may only require isolation of some signals, while other signals can remain active. For these signals that are not required to be isolated, it is correct that their values ​​do not conform to the "golden value" for isolation, and an exemption is required.

[0117] In safe mode, certain bus or interface signals may be driven to specific values ​​(such as all zeros) to prevent information leakage. This value may differ from the isolation value in normal mode and requires mode exemption.

[0118] S163, if the signal to be tested is in the exemption list, the signal isolation value of the signal to be tested is verified as passed.

[0119] If the signal to be tested is on the exemption list, it means that the signal isolation value of the signal to be tested does not need to be verified. Therefore, it can be directly determined that the signal isolation value verification of the signal to be tested has passed.

[0120] S164. If the signal to be tested is not in the exemption list, generate an error report.

[0121] If the signal to be tested is not on the exemption list, then further verification is required, and therefore an error report is generated.

[0122] As one implementation of this invention, the error report includes identification information for locating the position of the signal under test in the design code.

[0123] At this point, the signal isolation value verification method based on signal reset operation may also include: automatically generating modification suggestions for the design code based on error reports.

[0124] Specifically, to efficiently locate the test signal that failed the signal isolation value verification, the error report can include identification information to pinpoint the location of the test signal within the design code. Furthermore, to improve the efficiency of modifying faulty design code, modification suggestions can be automatically generated based on the error report.

[0125] Based on the above embodiments, as an implementation of the present invention, after automatically generating modification suggestions for the design code based on error reports, the method may further include the following steps:

[0126] Obtain the design code modified based on the suggested modification scheme. For the target test signal that fails the verification, apply a control signal to the circuit under test through the verification platform to put it into an isolated state, and collect the first signal isolation value corresponding to the target test signal before the circuit under test is powered on.

[0127] After the circuit under test is powered on and the reset operation takes effect, the second signal isolation value corresponding to the target test signal is acquired.

[0128] Compare whether the expected signal isolation value, the first signal isolation value, and the second signal isolation value corresponding to the target signal to be tested are consistent.

[0129] If they match, the signal isolation value of the target signal to be tested has been verified.

[0130] If there is a discrepancy, check the default exemption list;

[0131] If the target signal to be tested is on the exemption list, the signal isolation value verification of the target signal to be tested is confirmed to be successful.

[0132] If the target test signal is not in the exemption list, an error report is generated again. Based on the regenerated error report, a modification suggestion scheme for the design code is automatically generated. The modified design code based on the regenerated modification suggestion scheme is obtained and returned to the execution verification platform. A control signal is applied to the circuit under test to put it into the isolation state, and the first signal isolation value corresponding to the target test signal before the circuit under test is powered on is collected. The process continues until the signal isolation value of the target test signal is verified.

[0133] Specifically, after engineers modify the design scheme based on the modification suggestions, they can obtain the modified design code and re-verify the target test signals that failed verification. If there are still target test signals that failed verification, they first check whether the target test signal is on the exemption list. If it is on the exemption list, the signal isolation value of the target test signal is confirmed to have passed verification. If it is not on the exemption list, a new error report is generated, and a modification suggestion scheme for the design code is regenerated based on the new error report. The modified design code based on the regenerated modification suggestion scheme can then be used to re-verify the target test signals that failed verification until the signal isolation value of the target test signal passes verification.

[0134] As can be seen, this invention utilizes a reset signal as a trigger point to automatically acquire and compare the ISO values ​​of signals, ensuring that the effectiveness of the ISO mechanism can be detected early in the circuit design process. It completely solves the problems of delayed, inefficient, costly, and high-risk signal isolation verification in traditional circuit design processes. It transforms ISO verification from a passive, late-stage detection activity into a proactive, end-to-end preventative safeguard, significantly improving the first-time success rate of circuit design and having significant value in ensuring the smooth mass production of complex, low-power chips.

[0135] To ensure clarity, the overall technical solution of this invention will be described in detail below with reference to a specific example. For example... Figure 3 As shown, it may include the following steps:

[0136] 1. Document Preparation. In the early design phase, based on the system functional modules and power management strategy, identify all key signals and reference values ​​requiring ISO verification, and other deliverable documents. These deliverable documents may include the SPEC file, UPF file, and CPF file described in the above embodiments.

[0137] 2. Simulation Environment Preparation. Using the Lowerpower simulation environment, this technology automatically imports the design file containing the marker signal, configures the necessary test signals and simulation parameters (which may include system parameters such as voltage and frequency) according to the Unified Power Format (UPF) or the Common Power Format (CPF), and generates the signal isolation enable and signal isolation value comparison components, which is the first step in the flowchart.

[0138] 3. ISO value pre-acquisition. When the circuit under test is in normal working condition (i.e., based on the existing simulation environment in step 2), the ISO value of the test signal is pre-acquired as the basis data for subsequent comparison, i.e., the second step in the flowchart to obtain the ISO value before power-on.

[0139] 4. Power-on and enable / reset operation of the circuit under test. Wait for the circuit under test to power up and stabilize, and enable the relevant reset signal in the circuit, i.e., steps three and four in the flowchart.

[0140] 5. ISO Value Update Acquisition. Immediately after the reset signal takes effect, acquire the ISO values ​​of all marked signals to obtain the reset value of ISO, which is step 5 in the flowchart.

[0141] 6. ISO Value Comparison and Analysis. The signal ISO value obtained in step 3 is automatically compared with the ISO value after power-on reset. At the same time, the ISO value after power-on reset is compared with the expected signal isolation value in the design specification data. If any mismatch is found, a detailed report is generated immediately.

[0142] 7. Feedback and Correction. For inconsistencies shown in the comparison results, further investigation is conducted to determine whether they fall under the category of parts that need to be ignored, such as ISO signals that do not need to be checked (i.e., the exemption list in the flowchart). In-depth analysis and targeted corrections are then performed.

[0143] 8. Iterative verification. Repeat the above steps throughout the design process until all tagged signals (i.e., signals under test) pass the ISO value check.

[0144] This invention utilizes a reset signal as a trigger point to automatically acquire and compare the ISO values ​​of signals, ensuring the effectiveness of the ISO mechanism can be detected early in the circuit design process. It completely solves the problems of delayed, inefficient, costly, and high-risk signal isolation verification in traditional circuit design flows. It transforms ISO verification from a passive, late-stage detection activity into a proactive, end-to-end preventative safeguard, significantly improving the first-time success rate of circuit design and having significant value in ensuring the smooth mass production of complex, low-power chips.

[0145] Secondly, embodiments of the present invention provide a signal isolation value verification device 40 based on a signal reset operation, such as... Figure 4 As shown, the device includes:

[0146] The file acquisition module 410 is used to acquire the design specification data and power management description file of the circuit under test. The design specification data includes the expected signal isolation values ​​corresponding to multiple test signals in the circuit under test.

[0147] The verification platform generation module 420 is used to generate a verification platform in a simulation environment based on the power management description file and identify multiple signals to be tested.

[0148] The first signal isolation value acquisition module 430 is used to apply a control signal to the circuit under test through the verification platform to make the circuit under test enter the isolation state, and to acquire the first signal isolation values ​​corresponding to the multiple test signals before the circuit under test is powered on.

[0149] The second signal isolation value acquisition module 440 is used to acquire the second signal isolation values ​​corresponding to the plurality of test signals respectively after the circuit under test is powered on and the reset operation takes effect.

[0150] The signal isolation value comparison module 450 is used to compare whether the expected signal isolation value, the first signal isolation value and the second signal isolation value corresponding to each of the plurality of test signals are consistent.

[0151] The verification result generation module 460 is used to generate a signal isolation value verification result for each of the signals to be tested based on the comparison results.

[0152] Thirdly, embodiments of the present invention provide an electronic device 500, such as... Figure 5 As shown, it includes:

[0153] At least one processor 501;

[0154] Memory 502 for storing the at least one processor-executable instruction;

[0155] The at least one processor is configured to execute the instructions to implement the method described in the first aspect.

[0156] Fourthly, embodiments of the present invention provide a computer-readable storage medium that, when instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to perform the method described in the first aspect.

[0157] Fifthly, embodiments of the present invention provide a computer program product, including a computer program that, when executed by a processor, implements the method described in the first aspect.

[0158] The technical solution provided by this invention involves acquiring design specification data and a power management description file for the circuit under test (TBT), wherein the design specification data includes expected signal isolation values ​​corresponding to multiple test signals in the TBT; based on the power management description file, a verification platform is generated in a simulation environment, and multiple test signals are identified; through the verification platform, control signals are applied to the TBT to induce it into an isolated state, and first signal isolation values ​​corresponding to multiple test signals are acquired before the TBT is powered on; after the TBT is powered on and stabilized and the reset operation takes effect, second signal isolation values ​​corresponding to multiple test signals are acquired; the expected signal isolation value, first signal isolation value, and second signal isolation value corresponding to each test signal are compared to see if they are consistent; based on the comparison results, a signal isolation value verification result for each test signal is generated.

[0159] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention without departing from the principles and spirit of the present invention.

Claims

1. A method for verifying signal isolation values ​​based on signal reset operation, characterized in that, The method includes: Obtain the design specification data and power management description file of the circuit under test. The design specification data includes the expected signal isolation values ​​corresponding to multiple test signals in the circuit under test. Based on the power management description file, a verification platform is generated in the simulation environment, and multiple signals to be tested are identified; The verification platform applies control signals to the circuit under test to make the circuit under test enter an isolated state, and collects the first signal isolation values ​​corresponding to the multiple test signals before the circuit under test is powered on. After the circuit under test is powered on and stabilized and the reset operation takes effect, the second signal isolation values ​​corresponding to the multiple test signals are collected respectively. Compare whether the expected signal isolation value, the first signal isolation value, and the second signal isolation value corresponding to each of the plurality of test signals are consistent; Based on the comparison results, a verification result of the signal isolation value for each of the signals to be tested is generated. The step of generating a signal isolation value verification result for each of the signals under test based on the comparison results includes: For each of the plurality of test signals, if the comparison result shows that the expected signal isolation value, the first signal isolation value, and the second signal isolation value corresponding to the test signal are consistent, it is determined that the signal isolation value of the test signal has passed the verification, and a verification result is generated. If the comparison results show that the expected signal isolation value, the first signal isolation value, and the second signal isolation value corresponding to the signal under test are inconsistent, query the preset exemption list; If the signal to be tested is in the exemption list, the signal isolation value verification of the signal to be tested is deemed successful. If the signal to be tested is not in the exemption list, generate an error report; The exemption list includes at least one of the following: Signal markers that do not require signal isolation checks; Rules that allow abnormal signal isolation values ​​under specific operating modes, wherein the specific operating modes include at least one of the following modes: test mode, debug mode, low power mode, and security mode.

2. The method according to claim 1, characterized in that, The error report contains identification information used to locate the position of the signal under test in the design code; The method further includes: automatically generating suggested modification schemes for the design code based on the error report.

3. The method according to claim 2, characterized in that, After automatically generating suggested modifications to the design code based on the error report, the method further includes: Obtain the design code modified based on the modification suggestion scheme. For the target test signal that fails the verification, apply a control signal to the circuit under test through the verification platform to make it enter the isolation state, and collect the first signal isolation value corresponding to the target test signal before the circuit under test is powered on. After the circuit under test is powered on and the reset operation takes effect, the second signal isolation value corresponding to the target test signal is collected. Compare whether the expected signal isolation value, the first signal isolation value, and the second signal isolation value corresponding to the target signal to be tested are consistent; If they match, the signal isolation value of the target signal to be tested has been verified as passed. If there is a discrepancy, check the default exemption list; If the target signal to be tested is in the exemption list, the signal isolation value verification of the target signal to be tested is deemed successful. If the target test signal is not in the exemption list, an error report is generated again. Based on the regenerated error report, a modification suggestion scheme for the design code is automatically generated. The modified design code based on the regenerated modification suggestion scheme is obtained, and the process returns to the steps of applying a control signal to the circuit under test through the verification platform to put it into an isolated state and collecting the first signal isolation value corresponding to the target test signal before the circuit under test is powered on, until the signal isolation value of the target test signal is verified.

4. The method according to any one of claims 1 to 3, characterized in that, Based on the power management description file, a verification platform is generated in the simulation environment, including: In the simulation environment, based on the power management description file, the first component, the second component, and the third component of the verification platform are automatically generated; The first component is used to apply an isolation enable signal and a reset signal to the circuit under test; The second component is used to acquire the first signal isolation value corresponding to each test signal of the circuit under test under the control of the isolation enable signal, and the second signal isolation value corresponding to each test signal of the circuit under test under the control of the reset signal. The third component is used to compare whether the expected signal isolation value, the first signal isolation value, and the second signal isolation value corresponding to each signal to be tested are consistent.

5. A signal isolation value verification device based on signal reset operation, characterized in that, The device includes: The file acquisition module is used to acquire the design specification data and power management description file of the circuit under test. The design specification data includes the expected signal isolation values ​​corresponding to multiple test signals in the circuit under test. The verification platform generation module is used to generate a verification platform in a simulation environment based on the power management description file and identify multiple signals to be tested. The first signal isolation value acquisition module is used to apply a control signal to the circuit under test through the verification platform to make the circuit under test enter the isolation state, and to acquire the first signal isolation values ​​corresponding to the multiple test signals before the circuit under test is powered on. The second signal isolation value acquisition module is used to acquire the second signal isolation values ​​corresponding to the plurality of test signals respectively after the circuit under test is powered on and the reset operation takes effect. The signal isolation value comparison module is used to compare whether the expected signal isolation value, the first signal isolation value and the second signal isolation value corresponding to each of the plurality of signals to be tested are consistent. The verification result generation module is used to generate a signal isolation value verification result for each of the signals to be tested based on the comparison results. The verification result generation module is specifically used for: For each of the plurality of test signals, if the comparison result shows that the expected signal isolation value, the first signal isolation value, and the second signal isolation value corresponding to the test signal are consistent, it is determined that the signal isolation value of the test signal has passed the verification, and a verification result is generated. If the comparison results show that the expected signal isolation value, the first signal isolation value, and the second signal isolation value corresponding to the signal under test are inconsistent, query the preset exemption list; If the signal to be tested is in the exemption list, the signal isolation value verification of the signal to be tested is deemed successful. If the signal to be tested is not in the exemption list, generate an error report; The exemption list includes at least one of the following: Signal markers that do not require signal isolation checks; Rules that allow abnormal signal isolation values ​​under specific operating modes, wherein the specific operating modes include at least one of the following modes: test mode, debug mode, low power mode, and security mode.

6. An electronic device, characterized in that, include: At least one processor; Memory for storing the at least one processor-executable instruction; The at least one processor is configured to execute the instructions to implement the method as described in any one of claims 1-4.

7. A computer-readable storage medium, characterized in that, When the instructions in the computer-readable storage medium are executed by the processor of the electronic device, the electronic device is enabled to perform the method as described in any one of claims 1-4.

8. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the method according to any one of claims 1-4.

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