Method and system for electrical performance optimization of super junction mos devices

Abstract

The application relates to the technical field of semiconductors, and provides an electrical performance optimization method and system for a super-junction MOS device. The method comprises the following steps: arranging multiple trench arrangement regions in the super-junction MOS device; arranging a first trench spacing in a center conduction region, arranging a second trench spacing larger than the first trench spacing in a middle buffer region, and arranging a third trench spacing larger than the second trench spacing in a terminal transition region. The technical problems that when the trenches are uniformly arranged in the super-junction MOS device, the electric field is concentrated in the center region, the breakdown voltage is reduced, and the terminal region has excessive conduction capacity, causing silicon area waste, are solved. The technical effects that the first, second and third trench spacings are arranged in a gradient along the trench arrangement direction, the electric field is smoothly transitioned in the center conduction region-middle buffer region-terminal transition region, the unit area conduction resistance is significantly reduced, and the overall breakdown voltage and device reliability are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to an electrical performance optimization method and system for super junction MOS devices. BACKGROUND

[0002] In the field of medium and high voltage power conversion, server power supply, vehicle OBC / DC-DC, photovoltaic inverter and high frequency LLC resonant converter and other application scenarios put forward comprehensive requirements of lower on-resistance, higher breakdown voltage, smaller charge and stronger reliability on power semiconductor devices. The super junction MOS device based on silicon can significantly reduce the theoretical limit of traditional silicon devices by virtue of the alternating vertical charge compensation structure, and is the most cost-effective mainstream solution in the 600V-900V voltage grade market. However, the existing super junction MOS mostly adopts the uniform trench arrangement design of "single pitch, single width", which forms a significant difference in the electric field environment between the center and the terminal of the chip: the electric field in the center conduction area is relatively uniform, while the electric field in the terminal area is easily affected by the field ring or field plate superposition to form an electric field peak, which in turn triggers local thermal breakdown in reverse recovery or short-circuit transient state. In order to suppress the edge electric field distortion, the traditional method usually increases the epitaxial thickness or arranges multiple field rings, but this not only expands the terminal area and reduces the effective conduction unit, but also narrows the charge compensation design window, which increases the on-resistance and makes the process control more difficult. SUMMARY

[0003] The present application provides an electrical performance optimization method and system for super junction MOS devices, aiming to solve the technical problems of breakdown voltage reduction caused by electric field concentration in the center area and silicon area waste caused by excessive conduction capacity in the terminal area when the trenches are uniformly arranged in the super junction MOS device.

[0004] The first aspect of the present application provides an electrical performance optimization method for a super junction MOS device, the method comprising: arranging a plurality of trench arrangement regions in the super junction MOS device, the plurality of trench arrangement regions comprising a center conduction region, an intermediate buffer region and a terminal transition region; arranging a first trench pitch in the center conduction region, arranging a second trench pitch greater than the first trench pitch in the intermediate buffer region, and arranging a third trench pitch greater than the second trench pitch in the terminal transition region; wherein the first trench pitch, the second trench pitch and the third trench pitch are obtained by a pitch gradient function configuration.

[0005] In another aspect of the present disclosure, an electrical performance optimization system for a super-junction MOS device is provided, which includes: a trench arrangement setting module, configured to set a plurality of trench arrangement regions in the super-junction MOS device, the plurality of trench arrangement regions including a center conduction region, an intermediate buffer region, and a terminal transition region; a trench pitch setting module, configured to set a first trench pitch in the center conduction region, a second trench pitch greater than the first trench pitch in the intermediate buffer region, and a third trench pitch greater than the second trench pitch in the terminal transition region; and wherein the first trench pitch, the second trench pitch, and the third trench pitch are obtained by a pitch gradient function configuration.

[0006] The one or more technical solutions provided in the present disclosure have at least the following technical effects or advantages:

[0007] The above-mentioned electrical performance optimization method for a super-junction MOS device divides the super-junction MOS chip into three sections, i.e., a center conduction region, an intermediate buffer region, and a terminal transition region, along a horizontal direction. The trench pitch in the innermost conduction region is the smallest, the trench pitch increases when transitioning to the buffer region, and the trench pitch is further relaxed when extending to the terminal transition region. The specific values of the pitches of the three sections are obtained by continuous calculation according to a preset pitch gradient function, so that the trench pitch changes with an increasing slope from the center of the chip to the edge, thereby achieving smooth transition of charge compensation and electric field distribution without increasing the chip area.

[0008] The above description is only a summary of the technical solutions of the present disclosure. In order to more clearly understand the technical means of the present disclosure, the specific embodiments of the present disclosure can be implemented according to the content of the description, and in order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the following specific embodiments of the present disclosure are described. BRIEF DESCRIPTION OF DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art without creative labor.

[0010] Figure 1 A flowchart of an embodiment of an electrical performance optimization method for a super-junction MOS device.

[0011] Figure 2 A schematic diagram of an embodiment of a super-junction MOS device.

[0012] Figure 3 A system architecture diagram of an embodiment of an electrical performance optimization system for a super-junction MOS device.

[0013] Explanation of reference signs: super junction MOS device 10, center conduction region 11, intermediate buffer region 12, terminal transition region 13, trench 20, trench arrangement setting module 31, trench spacing setting module 32. DETAILED DESCRIPTION

[0014] The embodiments of the present application provide an electrical performance optimization method and system for a super junction MOS device, and solve the technical problem that when the trenches 20 are arranged uniformly in the super junction MOS device 10, the electric field is concentrated in the center region, which leads to a decrease in the breakdown voltage, and the terminal region has excessive conduction capability, which causes silicon area waste.

[0015] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0016] It should be noted that the terms "comprising" and "having" and any variations thereof are intended to cover not exclusive inclusion, for example, a process, method, system, product or server including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or modules that are not clearly listed or inherent to the process, method, product or device.

[0017] Embodiment one, as shown in the figure, the present application provides an electrical performance optimization method for a super junction MOS device, the method comprises: Figure 1 , Figure 2 The method comprises the following steps:

[0018] A plurality of trench 20 arrangement regions are arranged in the super junction MOS device 10, and the plurality of trench 20 arrangement regions comprise a center conduction region 11, an intermediate buffer region 12 and a terminal transition region 13.

[0019] In the embodiments of the present application, on the super-junction MOS device 10, a plurality of functional areas are annularly divided from the center of the chip outward as a plurality of trench 20 arrangement areas based on the arrangement of the device gate trench 20, including but not limited to a center conduction area 11, an intermediate buffer area 12, and a terminal transition area 13. The area of the center conduction area 11 corresponds to most of the active cells, and the trench 20 is densely arranged at the smallest pitch to ensure that the charge compensation degree is close to balance and the lowest unit area on-resistance is obtained. The intermediate buffer area 12 uses a gradually increasing trench 20 pitch to form an electric field strength transition zone, which not only avoids the physical property mutation of the center area and the terminal area, but also disperses the electric field peak value in advance through the pitch gradient change. The terminal transition area 13 uses the largest trench 20 pitch to effectively alleviate the edge electric field concentration effect by using the sparse trench 20 layout, preventing local breakdown under high voltage conditions. The trench 20 pitch of the above three functional areas can be accurately configured by a pitch gradient function, and the boundary can be adjusted by mathematical modeling to ensure that the best balance between on-resistance and withstand voltage is achieved under specific withstand voltage requirements, ensuring the high current handling capability of the center area, and suppressing the risk of local breakdown under high voltage through the electric field relaxation effect of the terminal area, ensuring the reliability of the device in different circuit applications.

[0020] Further, the present application provides that the plurality of trench 20 arrangement areas further include a center conduction area 11, an inner transition area, an intermediate buffer area 12, an outer transition area, and a terminal transition area 13; wherein the inner transition area is provided with a fourth trench pitch, the fourth trench pitch is greater than or equal to the first trench pitch and less than the second trench pitch, and the outer transition area is provided with a fifth trench pitch, the fifth trench pitch is greater than or equal to the second trench pitch and less than or equal to the third trench pitch.

[0021] Preferably, the super-junction MOS device 10 is arranged with multiple trench 20 arrangement regions extending outward in a ring shape with the geometric center as the origin, in addition to the central conduction region 11, the intermediate buffer region 12 and the terminal transition region 13, the inner transition region and the outer transition region are also included, wherein the inner transition region is provided with a fourth trench spacing, which is greater than or equal to the first trench spacing (belonging to the central conduction region 11) and less than or equal to the second trench spacing (belonging to the intermediate buffer region 12), which can form an electric field gradient transition layer between the central conduction region 11 and the intermediate buffer region 12, and avoid the sudden change of electric field strength through the gradual adjustment of the spacing; the outer transition region is provided with a fifth trench spacing, which is greater than or equal to the second trench spacing (belonging to the intermediate buffer region 12) and less than or equal to the third trench spacing (belonging to the terminal transition region 13), which can form a secondary electric field buffer layer between the intermediate buffer region 12 and the terminal transition region 13, and further disperse the electric field lines extending to the terminal region under high voltage conditions. By dividing the super-junction MOS device 10 into these five trench 20 arrangement regions, the gradient suppression of the electric field strength in the terminal region can be realized while ensuring high current density in the central region, achieving the effect of reducing conduction loss and improving breakdown voltage.

[0022] Further, the present application provides a method for setting multiple trench 20 arrangement regions in a super-junction MOS device 10, which further comprises:

[0023] obtaining connection scene information of the super-junction MOS device 10 in a target circuit system, the connection scene information including the type of components connected to the super-junction MOS device 10, the driving mode, the power voltage and the load characteristics; based on the connection scene, constructing an electric field simulation model containing the super-junction MOS device 10 to obtain the boundary electric field distribution characteristics of the super-junction MOS device 10 in multiple states; based on the boundary electric field distribution characteristics, optimizing and adjusting the region boundaries of the multiple trench 20 arrangement regions.

[0024] Preferably, the design database of the super-junction MOS device 10 is first called and parsed with the circuit schematic diagram, and all element parameters and driving configurations of the target circuit system connected in series and parallel with the super-junction MOS device 10 are extracted, including device type, driving mode, power voltage and load characteristics, wherein the device type is used to identify the elements directly interacting with the super-junction MOS device 10, such as the model of the freewheeling diode, the model of the gate drive IC, and the capacitance value of the filter capacitor; the driving mode is used to quantify the driving signal parameters, such as the rise time, the fall time, the driving voltage, the driving resistance, etc.; the power voltage is used to calibrate the working voltage range, such as the DC bus voltage and the gate drive voltage; and the load characteristics include the specific characteristics of the load connected to the super-junction MOS device 10, such as the load type (resistive / inductive / capacitive), the load current, the switching frequency, etc. By storing these element parameters and driving configurations in a set, the connection scene information is formed. Subsequently, in the existing TCAD platform, the connection scene information is imported, a three-dimensional electric field simulation model containing device geometry, material properties, boundary conditions and connection scene is constructed, and then the electric field distribution of the device in the on state, the off state and other states is simulated by the finite element analysis method. During the simulation process, the boundary electric field gradient change data along the trench 20 arrangement area is focused on, and key parameters such as electric field strength peak, electric field line distribution density and potential gradient are extracted to form the boundary electric field distribution characteristics in each state. Then, when the boundary electric field distribution characteristics show that there is an electric field gradient mutation (such as the gradient change rate exceeding the preset threshold of 5x10 5 V / cm² / μm) in a certain area boundary, it indicates that there is a risk of electric field concentration in this area. At this time, the boundary of the trench 20 arrangement area is optimized according to the position coordinates of the gradient mutation point. The optimization process needs to maintain the nonlinear gradient characteristics of the trench 20 spacing to ensure that the optimized layout still meets the balance requirements of the device voltage withstand level and the on performance. Finally, through multiple iterations of simulation and boundary adjustment, the optimization adjustment of the trench 20 arrangement area is completed, so that the electric field distribution is disturbed to be uniform and the breakdown risk is significantly reduced.

[0025] Further, the application provides the boundary electric field distribution characteristics of the super-junction MOS device 10 in multiple states, wherein the multiple states include the on state, the off state and the reverse recovery state of the super-junction MOS device 10 based on the target circuit system.

[0026] Optionally, when simulating the electric field distribution using the electric field simulation model, three groups of state conditions are loaded in the electric field simulation model in sequence, which are the conduction state of the target circuit system, the off state of the target circuit system and the reverse recovery state of the target circuit system. Among them, the conduction state is to make the super-junction MOS device 10 in the target circuit system in a fully open state, simulate the current transmission path, analyze the electric field intensity distribution at the bottom of the trench 20 in the central conduction region 11, and the state condition of the conduction state can be rated current 30A, drain-source voltage 1.5V, gate voltage 15V (full conduction). The off state is to apply a rated voltage to the device drain, simulate the diffusion path of the electric field line, and verify the electric field intensity, and the state condition of the off state can be gate voltage 0V (off state), drain-source voltage 400V (high voltage blocking). The reverse recovery state is to simulate the transient process of the device from saturation conduction to complete cut-off, capture the voltage overshoot phenomenon caused by parasitic inductance, and the state condition of the reverse recovery state can be current drop rate 5A / ns, drain-source voltage from 0V to 400V. By using the electric field simulation model to simulate the super-junction MOS device 10 in multiple states, the boundary electric field distribution characteristics of each state can be determined, which provides accurate physical field input for subsequent optimization of the trench 20 arrangement region boundary.

[0027] Further, the application provides an optimization adjustment of the region boundary of the plurality of trench 20 arrangement regions based on the boundary electric field distribution characteristics, the method comprising:

[0028] Analyzing the boundary electric field distribution characteristics, extracting boundary electric field gradient change data distributed along the plurality of trench 20 arrangement regions; analyzing the gradient mutation points greater than the preset gradient change rate in the boundary electric field gradient change data; updating the region boundary of the plurality of trench 20 arrangement regions according to the boundary position coordinates where the gradient mutation points are located.

[0029] Optionally, first extract the electric field intensity distribution curve of the device longitudinal direction (from the center conduction region 11 to the terminal transition region 13) from the boundary electric field distribution characteristics corresponding to the above three states. For example, in the off state, the electric field intensity of the terminal transition region 13 surface jumps from 200kV / cm to 320kV / cm, forming a steep electric field gradient. By differentiating these electric field intensity curves, the local electric field gradient change rate is calculated. By summarizing the local electric field gradient change rate corresponding to each state, the boundary electric field gradient change data is formed. Subsequently, according to the breakdown field characteristics of silicon material and process tolerance, a preset gradient change rate is defined, and the data in the boundary electric field gradient change data is traversed, and all data points with a local electric field gradient change rate greater than the preset gradient change rate are selected, and the position corresponding to this data point is taken as the gradient mutation point. Then, the boundary position coordinates corresponding to the gradient mutation point are mapped to the plurality of trench 20 arrangement regions, and the functional area to which each trench 20 arrangement region belongs is updated. In the updating process, for the electric field gradient sudden increase region (such as the terminal area boundary), the outward expansion strategy is adopted, and the boundary of the mutation point region is offset to the outside, while maintaining the nonlinear gradient characteristics of the trench 20 spacing, and the spacing parameters of the associated region are recalculated through the spacing gradient function; for the electric field gradient sudden drop region (such as the center conduction area boundary), the inward shrinkage strategy is adopted, and the boundary is offset to the inside to avoid excessive compression of the effective conduction area. After each boundary adjustment, the electric field simulation model is used for simulation verification to ensure the uniformity of the electric field distribution, so that the electric field smoothly transitions in the center conduction area-middle buffer area-terminal transition area.

[0030] The first trench spacing is arranged in the center conduction region 11, the second trench spacing greater than the first trench spacing is arranged in the middle buffer region 12, and the third trench spacing greater than the second trench spacing is arranged in the terminal transition region 13; wherein the first trench spacing, the second trench spacing and the third trench spacing are obtained through the spacing gradient function configuration.

[0031] In one embodiment, in the trench 20 layout design of the super-junction MOS device 10, the core conduction region at the geometric center of the device is constructed with a high-density array of trenches 20 through a first trench spacing (minimum trench 20 spacing), which is designed to periodically and uniformly distribute the carrier transport path, effectively suppress the current filament effect, and ensure the reduction of on-resistance under large current conditions, while avoiding the risk of thermal runaway caused by local overheating. The intermediate buffer region 12 around the central conduction region is laid out with a nonlinearly increasing second trench spacing (greater than the first trench spacing), which makes the lateral electric field strength smoothly transition from the peak value of the central region to the safe threshold value of the terminal region in a continuously conductive manner, effectively blocking the refraction effect of the electric field lines at the dielectric interface; In the terminal transition region 13 at the outermost edge of the device, a third trench spacing (maximum trench 20 spacing) is used to form a sparse arrangement structure, which is configured to reduce the electric field strength in the terminal region, effectively expand the width of the depletion layer, and increase the breakdown voltage, ensuring that the peak value of the electric field strength is always located within the preset terminal protection region under reverse bias conditions, avoiding the edge breakdown phenomenon caused by interface state charges. The above-mentioned three levels of trench 20 spacing are parameterized designed through a spacing gradient function, thereby forming an electric field strength gradient suppression system from the conduction region to the terminal region, and finally realizing low conduction loss, high breakdown voltage and stable dynamic reliability in the same chip area.

[0032] Further, the present application provides that the first trench width is set in the central conduction region 11, the second trench width greater than the first trench width is set in the intermediate buffer region 12, and the third trench width greater than the second trench width is set in the terminal transition region 13.

[0033] Preferably, in the trench 20 layout design of the super-junction MOS device 10, a high-density trench 20 array is constructed by the first trench width (minimum trench 20 width) in the core conduction region at the device geometric center, which width design makes the carrier transport path periodically and uniformly distributed, effectively suppresses the current filament effect, ensures the reduction of on-resistance under large current working conditions, and at the same time avoids the risk of thermal runaway caused by local overheating. The intermediate buffer region 12 around the central conduction area adopts a nonlinearly increasing second trench width (greater than the first trench width) layout, which makes the lateral electric field intensity smoothly transition from the peak value of the central area to the safety threshold of the terminal area in a continuous and conductive manner, effectively blocking the refraction effect of the electric field line at the dielectric interface. In the terminal transition region 13 at the outermost edge of the device, a sparse arrangement structure is formed by the third trench width (maximum trench 20 width), which width configuration reduces the electric field intensity in the terminal area, effectively expands the width of the depletion layer, and raises the breakdown voltage, ensuring that the peak value of the electric field intensity is always located inside the preset terminal protection area under reverse bias working conditions, avoiding the edge premature breakdown phenomenon caused by interface state charge. The above-mentioned three-level trench 20 width configuration realizes parameterized design through a width gradient function (similar to the interval gradient function), thereby forming an electric field intensity gradient suppression system from the conduction area to the terminal area.

[0034] Further, the present application provides that the central conduction region 11 is provided with a first trench depth, the intermediate buffer region 12 is provided with a second trench depth less than the first trench depth, and the terminal transition region 13 is provided with a third trench depth less than the second trench depth.

[0035] Preferably, in the trench 20 layout design of the super-junction MOS device 10, in the core conduction region at the geometric center of the device, a high-aspect-ratio P / N column array is constructed by a first trench depth (the deepest trench 20 depth), which is designed to make the vertical electric field distribution periodically uniform, effectively suppress the electric field concentration effect, and ensure the breakdown voltage improvement under high voltage working condition, while avoiding the risk of thermal runaway caused by local electric field distortion. In the intermediate buffer region 12 around the center conduction region, a second trench depth (smaller than the first trench depth) is used for layout, which makes the longitudinal electric field strength smoothly transition from the peak value of the center region to the safety threshold of the terminal region in a continuously derivable manner, effectively blocking the refraction effect of the electric field lines at the dielectric interface. In the terminal transition region 13 at the outermost edge of the device, a third trench depth (the shallowest trench 20 depth) is used to form a sparse arrangement structure, which reduces the electric field strength in the terminal region, effectively expands the width of the depletion layer, and improves the breakdown voltage, ensuring that the peak value of the electric field strength is always located inside the preset terminal protection region under reverse bias working condition, avoiding the edge breakdown phenomenon caused by interface state charge. The above-mentioned three-level trench 20 depth configuration realizes parameterized design through a depth gradient function (similar to the pitch gradient function), thereby forming an electric field strength gradient suppression system from the conduction region to the terminal region.

[0036] Further, the pitch gradient function is a nonlinear pitch gradient function, and the nonlinear pitch gradient function is a power function difference function; the power function difference function is gradient adjusted by controlling a gradient adjustment parameter of a nonlinear curvature, and the first trench pitch, the second trench pitch, the third trench pitch, the fourth trench pitch and the fifth trench pitch are set.

[0037] Optionally, in the trench 20 layout design of the super-junction MOS device 10, a pitch gradient function is used to configure the trench 20 pitch of different regions to realize precise control of electrical performance. The pitch gradient function is a nonlinear pitch gradient function, specifically a power function difference function, and the expression is as follows: ; wherein, is the trench 20 pitch at a distance r from the center of the super-junction MOS device 10, is the set minimum trench 20 pitch, located in the center conduction region 11 of the device, is the set maximum trench 20 pitch, located in the terminal transition region 13 of the device, and R is the radius of the super-junction MOS device 10, is a gradient adjustment parameter that controls the nonlinear curvature. Through the pitch gradient function, the trench 20 pitch can be continuously changed from the center to the terminal region. Specifically, in the center conduction region 11 of the device, the minimum trench 20 pitch to ensure high-density trench 20 arrangement, thus optimizing the carrier transport path and reducing the on-resistance. As the distance from the center r increases, the trench 20 spacing gradually increases until it reaches the maximum spacing in the terminal transition region 13 This design allows the electric field strength to smoothly transition from the center to the terminal region, avoiding the phenomenon of electric field concentration. The introduction of the gradient adjustment parameter a allows the rate of change of the trench 20 spacing to be flexibly controlled. When a = 1, the trench 20 spacing increases linearly with r; when a > 1, the curve is steep in the front and steep in the back (convex), which is beneficial for quickly approaching the on region and quickly lifting to in the terminal region, which is suitable for areas that require rapid reduction of electric field strength; when a < 1, the curve is steep in the front and gentle in the back (concave), which is suitable for scenarios where the buffer region gradually transitions and the edge lifts more gently. By adjusting the value of a, the electric field distribution of the device can be optimized, improving the breakdown voltage and reliability of the device. In actual layout, the chip is divided radially into five sections: the center on region, the inner transition region, the intermediate buffer region, the outer transition region, and the terminal transition region. The first trench spacing, the second trench spacing, the third trench spacing, the fourth trench spacing, and the fifth trench spacing are calculated by substituting the typical radii in each section into the spacing gradient function. If the terminal electric field is still high after debugging using these trench 20 spacings, a can be increased or , on the contrary, to reduce the on region resistance, a can be reduced or , thereby finely adjusting the trench 20 arrangement and achieving high-performance design of the super-junction MOS device 10.

[0038] Table 1: Position Sampling Table

[0039]

[0040] As shown in Table 1 above, the table gives the trench 20 spacing values corresponding to the typical radial positions in the center on region, the intermediate buffer region, and the terminal transition region. It can be seen that the trench 20 spacing P(r) monotonically increases with r.

[0041] Table 2: First Calculation Example Table

[0042]

[0043] As shown in Table 2 above, this table is based on the spacing gradient function: (a = 1.0, linear growth) and lists the trench 20 spacing calculation results for five typical radial positions.

[0044] Table 3: Second Calculation Example Table

[0045]

[0046] As above Table 3 is the second calculation example table, this table is based on the pitch gradient function: The trench 20 pitch calculation results of five typical radial positions are listed.

[0047] Table 4: Third calculation example table

[0048]

[0049] As above Table 4 is the third calculation example table, this table is based on the pitch gradient function: The trench 20 pitch calculation results of five typical radial positions are listed.

[0050] Further, the application provides a device withstand voltage interval sample of different super junction MOS devices 10 types; a regulation mapping relationship between the device withstand voltage interval sample and the gradient regulation parameter is established, the device withstand voltage interval of the super junction MOS device 10 is identified, and the gradient regulation parameter matched with the device withstand voltage interval is obtained in the value range according to the regulation mapping relationship; wherein the value range of the gradient regulation parameter is [1.2, 3.0].

[0051] Optionally, in the design process of the super junction MOS device 10, in order to optimize its electrical performance, especially for the needs of different withstand voltage levels, it is necessary to accurately configure the nonlinear gradient regulation parameter a of the trench 20 pitch. First, by identifying the device withstand voltage interval sample of different super junction MOS device 10 types from the super junction MOS device 10 database, for example, some devices can work stably in the voltage range of 400V to 800V, while other devices can work normally at a voltage of 800V to 1200V or even higher. Subsequently, a regulation mapping relationship between the device withstand voltage interval sample and the gradient regulation parameter a is established, so that the device withstand voltage interval sample and the corresponding gradient regulation parameter are one-to-one corresponding, for example, when the device withstand voltage is 400V-800V, the a value should be selected between 1.5-2.0; when the device withstand voltage is increased to 800V-1200V, the a value should be selected between 2.0-2.5; and for high-voltage devices with a withstand voltage exceeding 1200V, the a value should be selected between 2.5-3.0. After determining the specific withstand voltage interval of the device, according to the above regulation mapping relationship, the a value matched with the device withstand voltage interval is selected in the value range [1.2, 3.0] of the gradient regulation parameter a, for example, if it is identified that the withstand voltage interval of a super junction MOS device 10 is 800V-1200V, then according to the mapping relationship, the a value should be selected between 2.0-2.5. In summary, by identifying the device withstand voltage interval and establishing the regulation mapping relationship, the gradient regulation parameter a matched with the device withstand voltage interval can be accurately selected, so as to optimize the electrical performance of the super junction MOS device 10.

[0052] To sum up, the embodiments of the present application have at least the following technical effects:

[0053] The embodiments of the present application arrange multiple trench 20 arrangement areas in the super junction MOS device 10, which include a center conduction area 11, an intermediate buffer area 12, and a terminal transition area 13; a first trench spacing is arranged in the center conduction area 11, a second trench spacing larger than the first trench spacing is arranged in the intermediate buffer area 12, and a third trench spacing larger than the second trench spacing is arranged in the terminal transition area 13; wherein the first trench spacing, the second trench spacing, and the third trench spacing are obtained by a spacing gradient function configuration. These technical effects collectively solve the technical problems of breakdown voltage reduction caused by electric field concentration in the center area and silicon area waste caused by excessive terminal area conduction capability when the trenches 20 are uniformly arranged in the super junction MOS device 10, achieving the technical effects of smooth transition of the electric field in the center conduction area-intermediate buffer area-terminal transition area, significantly reducing the conduction resistance per unit area, and improving the overall breakdown voltage and device reliability by arranging gradientized first, second, and third trench spacings along the trench 20 arrangement direction.

[0054] Embodiment two, based on the same inventive concept as the method for optimizing the electrical performance of the super junction MOS device in the foregoing embodiments, as shown in Figure 3 The present application provides a system for optimizing the electrical performance of a super junction MOS device, which includes: a trench arrangement setting module 31: arranging multiple trench 20 arrangement areas in the super junction MOS device 10, which include a center conduction area 11, an intermediate buffer area 12, and a terminal transition area 13; a trench spacing setting module 32: arranging a first trench spacing in the center conduction area 11, a second trench spacing larger than the first trench spacing in the intermediate buffer area 12, and a third trench spacing larger than the second trench spacing in the terminal transition area 13; wherein the first trench spacing, the second trench spacing, and the third trench spacing are obtained by a spacing gradient function configuration.

[0055] Further, the trench arrangement setting module 31 is further used to perform the following method:

[0056] The multiple trench 20 arrangement areas further include a center conduction area 11, an inner transition area, an intermediate buffer area 12, an outer transition area, and a terminal transition area 13; wherein the inner transition area is arranged with a fourth trench spacing, the fourth trench spacing is greater than or equal to the first trench spacing and less than the second trench spacing, the outer transition area is arranged with a fifth trench spacing, and the fifth trench spacing is greater than or equal to the second trench spacing and less than or equal to the third trench spacing.

[0057] Further, the trench arrangement setting module 31 is further configured to perform the following method:

[0058] Obtaining connection scene information of the super junction MOS device 10 in a target circuit system, the connection scene information including the type of components connected to the super junction MOS device 10, the driving mode, the power supply voltage and the load characteristics; based on the connection scene, constructing an electric field simulation model containing the super junction MOS device 10, obtaining the boundary electric field distribution characteristics of the super junction MOS device 10 in multiple states; based on the boundary electric field distribution characteristics, optimizing and adjusting the region boundaries of the multiple trench 20 arrangement regions.

[0059] Further, the trench arrangement setting module 31 is further configured to perform the following method:

[0060] Obtaining the boundary electric field distribution characteristics of the super junction MOS device 10 in multiple states, wherein the multiple states include the on state, the off state and the reverse recovery state of the super junction MOS device 10 based on the target circuit system.

[0061] Further, the trench arrangement setting module 31 is further configured to perform the following method:

[0062] Analyzing the boundary electric field distribution characteristics, extracting boundary electric field gradient change data distributed along the multiple trench 20 arrangement regions; analyzing the gradient mutation points in the boundary electric field gradient change data which are greater than a preset gradient change rate; updating the region boundaries of the multiple trench 20 arrangement regions according to the boundary position coordinates where the gradient mutation points are located.

[0063] Further, the trench spacing setting module 32 is further configured to perform the following method:

[0064] The interval gradient function is a nonlinear interval gradient function, and the nonlinear interval gradient function is a power function difference function; the power function difference function is gradient adjusted by a gradient adjustment parameter of a nonlinear curvature, and the first trench spacing, the second trench spacing, the third trench spacing, the fourth trench spacing and the fifth trench spacing are set.

[0065] Further, the trench spacing setting module 32 is further configured to perform the following method:

[0066] The device voltage withstand interval sample of the different super-junction MOS device 10 type is obtained; a regulation mapping relationship between the device voltage withstand interval sample and the gradient regulation parameter is established, the device voltage withstand interval of the super-junction MOS device 10 is identified, and the gradient regulation parameter matched with the device voltage withstand interval is obtained in the value range according to the regulation mapping relationship; wherein the value range of the gradient regulation parameter is [1.2, 3.0].

[0067] Further, the trench interval setting module 32 is further used to perform the following method:

[0068] The first trench width is set in the center conduction region 11, the second trench width greater than the first trench width is set in the middle buffer region 12, and the third trench width greater than the second trench width is set in the terminal transition region 13.

[0069] Further, the trench interval setting module 32 is further used to perform the following method:

[0070] The first trench depth is set in the center conduction region 11, the second trench depth less than the first trench depth is set in the middle buffer region 12, and the third trench depth less than the second trench depth is set in the terminal transition region 13.

[0071] It should be noted that the above-mentioned sequence of the embodiments of the present application is only for description, and does not represent the advantages and disadvantages of the embodiments. The above describes a specific embodiment of the present application. The processes depicted in the drawings do not necessarily require the specific order and continuous order shown to achieve the desired results. In some embodiments, multi-task processing and parallel processing are also possible or can be advantageous.

[0072] The above only describes the preferred embodiments of the present application and does not limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0073] The present specification and drawings are only exemplary descriptions of the present application, and are considered to cover any and all modifications, changes, combinations or equivalents within the scope of the present application. Obviously, those skilled in the art can make various modifications and changes to the present application without departing from the scope of the present application. Thus, if these modifications and changes of the present application belong to the scope of the present application and its equivalents, the present application intends to include these modifications and changes.

Claims

1. A method for optimizing the electrical performance of superjunction MOS devices, characterized in that, The method includes: Multiple trench arrangement regions are set in the superjunction MOS device, and the multiple trench arrangement regions include a central conduction region, an intermediate buffer region and a terminal transition region; A first trench spacing is set in the central conductive area, a second trench spacing greater than the first trench spacing is set in the intermediate buffer area, and a third trench spacing greater than the second trench spacing is set in the terminal transition area; wherein, the first trench spacing, the second trench spacing, and the third trench spacing are obtained by configuring a spacing gradient function; The multiple trench arrangement areas also include a central conducting area, an inner transition area, an intermediate buffer area, an outer transition area, and a terminal transition area; The inner transition region is provided with a fourth groove spacing, which is greater than or equal to the first groove spacing and less than the second groove spacing; the outer transition region is provided with a fifth groove spacing, which is greater than or equal to the second groove spacing and less than or equal to the third groove spacing. The spacing gradient function is a non-linear spacing gradient function, which is a power function difference function; The power function difference function performs gradient adjustment by controlling the gradient adjustment parameter of the nonlinear curvature, and sets the first groove spacing, the second groove spacing, the third groove spacing, the fourth groove spacing and the fifth groove spacing; Identify the voltage breakdown range samples of different superjunction MOS device types; Establish an adjustment mapping relationship between the device breakdown voltage range sample and the gradient adjustment parameter, identify the device breakdown voltage range of the superjunction MOS device, and obtain the gradient adjustment parameter matching the device breakdown voltage range within the value range according to the adjustment mapping relationship; The gradient adjustment parameter has a value range of [1.2, 3.0].

2. The method as described in claim 1, characterized in that, The method for setting multiple trench arrangement regions in a superjunction MOS device also includes: Obtain the connection scenario information of the superjunction MOS device in the target circuit system. The connection scenario information includes the type of components connected to the superjunction MOS device, the driving method, the power supply voltage, and the load characteristics. Based on the aforementioned connection scenario, an electric field simulation model containing the superjunction MOS device is constructed to obtain the boundary electric field distribution characteristics of the superjunction MOS device under multiple states. The regional boundaries of the multiple trench arrangement areas are optimized and adjusted based on the boundary electric field distribution characteristics.

3. The method as described in claim 2, characterized in that, Obtain the boundary electric field distribution characteristics of the superjunction MOS device in multiple states, wherein the multiple states include the on state, off state and reverse recovery state of the superjunction MOS device based on the target circuit system.

4. The method as described in claim 2, characterized in that, The method for optimizing and adjusting the regional boundaries of the multiple trench arrangement regions based on the boundary electric field distribution characteristics includes: Analyze the boundary electric field distribution characteristics and extract the boundary electric field gradient variation data distributed along the multiple trench arrangement regions; Analyze the gradient abrupt change points in the boundary electric field gradient change data that are greater than the preset gradient change rate; The region boundaries of the multiple trench layout areas are updated based on the boundary location coordinates of the gradient abrupt change points.

5. The method as described in claim 1, characterized in that, The central conductive area is provided with a first groove width, the intermediate buffer area is provided with a second groove width greater than the first groove width, and the terminal transition area is provided with a third groove width greater than the second groove width.

6. The method as described in claim 1, characterized in that, The central conductive area is provided with a first trench depth, the intermediate buffer area is provided with a second trench depth less than the first trench depth, and the terminal transition area is provided with a third trench depth less than the second trench depth.

7. An electrical performance optimization system for superjunction MOS devices, characterized in that, The system is used to execute the electrical performance optimization method for a superjunction MOS device according to any one of claims 1-6, the system comprising: Trench layout module: Multiple trench layout regions are set in the superjunction MOS device, including a central conduction region, an intermediate buffer region and a terminal transition region; Trench spacing setting module: A first trench spacing is set in the central conductive area, a second trench spacing greater than the first trench spacing is set in the intermediate buffer area, and a third trench spacing greater than the second trench spacing is set in the terminal transition area; wherein, the first trench spacing, the second trench spacing and the third trench spacing are obtained by configuring a spacing gradient function.

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