IC device and method of determining planar arrangement of IC device

Abstract

In one aspect, an IC device is provided, including: a die; a circuit region of the die, the circuit region extending in first and second lateral directions along the die and including a plurality of circuit cells arranged in a plurality of rows extending in parallel in the first direction; wherein the circuit region comprises a first sub-region comprising a first subset of the plurality of rows of circuit cells, a second sub-region comprising a second subset of the plurality of rows of circuit cells, and an intra-die splice sub-region extending across the circuit region in a first direction wherein the first sub-region and the second sub-region are arranged on opposite sides of the intra-die splice sub-region, and wherein the intra-die splice sub-region is formed by a third subset of one or more rows of the plurality of rows of circuit cells, where the circuit cells of the third subset are configured as fill cells having a critical dimension that is greater than the respective critical dimensions of the circuit cells of the first and second subsets. A method for planar arrangement of circuit regions of an IC device is also provided.

Description

Technical Field

[0001] The present invention generally relates to integrated circuit (IC) devices and methods for determining a floorplan of an IC device. Background Art

[0002] The ongoing effort to produce more dense and efficient IC devices has led to significant advances in various areas of IC manufacturing. In particular, photolithography scanners with shorter wavelengths and higher numerical apertures (NA) have been developed.

[0003] Current state-of-the-art high-NA (NA=0.55) extreme ultraviolet lithography (EUVL) scanners use anamorphic projection optics, which reduce the image field on the wafer by a factor of 4 and 8, respectively, perpendicular to and parallel to the plane of incidence of the EUV radiation on the reticle or mask. This results in an image field on the wafer that is two times smaller than that of a 0.33NA EUV scanner (26mm x 16.5mm vs. 26mm x 33mm). This introduces the requirement for intra-die stitching of two image fields from two reticle masks when producing die sizes exceeding the 0.55NA exposure field. Summary of the Invention

[0004] Intra-die stitching at EUVL resolution requires nanometer-level precision technology, optical proximity correction (OPC) correction for spatial image field crosstalk and image field overlay control, as well as stitching-specific design rules.

[0005] It is an object of the present invention to provide a technique that allows alleviating the complexity of at-resolution stitching.

[0006] According to a first aspect of the present invention, there is provided an integrated circuit IC device, comprising:

[0007] grains;

[0008] a circuit region extending in first and second lateral directions along the die and comprising a plurality of circuit cells arranged in a plurality of rows extending in parallel in a first direction;

[0009] The circuit area includes a first sub-area, a second sub-area, and an intra-die stitching sub-area, wherein the first sub-area includes a first subset of the multiple rows of circuit units, the second sub-area includes a second subset of the multiple rows of circuit units, and the intra-die stitching sub-area extends across the circuit area in the first direction.

[0010] wherein the first sub-region and the second sub-region are arranged on opposite sides of the intra-die stitching sub-region, and

[0011] The intra-die stitching sub-region is formed by a third subset of one or more rows of the multiple rows of circuit cells, wherein the circuit cells of the third subset are configured as filling cells having a critical dimension that is greater than the corresponding critical dimensions of the circuit cells of the first subset and the second subset.

[0012] According to a second aspect of the present invention, there is provided a method for planar layout of a circuit region of an IC device, comprising:

[0013] Obtaining a floor plan of the circuit area;

[0014] determining a position of an intra-die stitching boundary of the floorplan, the intra-die stitching boundary extending across the floorplan in a first direction;

[0015] placing one or more rows of fill cells in an intra-die stitching sub-region of the floorplan, wherein the one or more rows of fill cells extend in the first direction and the intra-die stitching sub-region extends along the intra-die stitching boundary, and

[0016] In each of a first sub-region and a second sub-region on opposite sides of the intra-die stitching sub-region of the planar layout, a plurality of rows of circuit units extending in parallel along the first direction are placed,

[0017] The filling unit has a critical dimension greater than a corresponding critical dimension of the circuit units in the first sub-region and the second sub-region.

[0018] The first and second aspects of the present invention are based on the insight that the complexity of resolution stitching can be avoided by introducing an intra-die stitching sub-region of one or more rows of filler cells along an intra-die stitching boundary. Because the filler cells are configured to be associated with a larger (i.e., "relaxed") critical dimension (CD) than the circuit cells of the first and sub-regions on opposite sides of the intra-die stitching region and boundary, the first and second aspects enable IC devices that can be manufactured using intra-die stitching while avoiding resolution stitching. Consequently, the control and alignment accuracy requirements for the stitched image field during manufacturing can be relaxed relative to resolution stitching.

[0019] Adding one or more rows of filler cells can facilitate intra-die stitching with little or negligible loss in area efficiency.

[0020] For example, in some embodiments, the intra-die stitching sub-region may be formed (or composed) of at most 10 rows of circuit cells, at most 5 rows of circuit cells, at most 2 rows of circuit cells, or only 1 row of circuit cells. When the intra-die stitching sub-region is formed by 2 or more rows, the 2 or more rows of the intra-die stitching sub-region are continuous rows of filled cells.

[0021] Another benefit of providing intra-die stitching sub-regions with filled cells is that a certain minimum feature density can also be maintained in the intra-die stitching sub-regions in the levels of the feature pattern including filled cells. This can facilitate the fabrication of these levels and the corresponding levels of the first and second sub-regions compared to if the intra-die stitching sub-regions at these levels were empty. It is worth noting that metal levels that are empty or have low and / or uneven feature density may be more difficult to planarize (e.g., chemical mechanical polishing) compared to the corresponding levels of the first and second sub-regions, and also increase the risk of feature collapse.

[0022] As can be understood from the above discussion, the first and second aspects are particularly useful for technology nodes requiring high NA scanners, such as 0.55NA EUVL scanners, where resolution intra-die stitching would be particularly challenging.

[0023] Thus, the intra-die stitching sub-region and the intra-die stitching boundary may extend along a midline of the die.Furthermore, the first and second sub-regions may have a substantially uniform footprint (ie, as seen in a major plane of the die).

[0024] Unless otherwise stated, various embodiments, examples, and features of circuit regions, sub-regions, circuit cells, and filling cells will be set forth in the following discussion and apply accordingly to each of the first and second aspects.

[0025] The term "circuit cell" is used herein in its normal sense to refer to a unit of circuit area, typically rectangular, comprising a group of related and / or interconnected circuit features. A circuit cell may be "functional" or "non-functional."

[0026] The term "functional unit" is used herein to refer to a circuit unit configured to implement a circuit function. A functional unit may be a logic unit (e.g., a logic gate or a combination of logic gates) configured to implement a logic function, a memory cell, or an I / O cell. A functional unit may be a standard cell, i.e., a circuit unit of a standard cell design selected from a standard cell library. A functional unit may include a semiconductor pattern (i.e., an active area pattern including a source / drain region and a channel region), a gate pattern, and a metal layer pattern.

[0027] The term "non-functional cell" is used herein to refer to a cell that does not implement any circuit function, which circuit functions can be implemented by functional units such as logic cells, memory cells or I / O cells. A non-functional cell can be a dummy cell comprising one or more of a dummy semiconductor pattern, a dummy gate pattern or a dummy metal layer pattern (e.g., a dummy interconnect) that is not electrically and functionally connected to any other (functional) circuit cell. A non-functional cell can also be an interconnect cell, comprising a metal layer pattern configured to interconnect adjacent circuit cells. An interconnect cell can, for example, comprise one or more (horizontal) metal lines, one or more metal contacts and / or one or more metal through-holes. A fill cell configured as an interconnect cell can be particularly used to interconnect two non-fill cells across an intra-grain splicing area, typically via a metal layer pattern of one or more metal levels above the metal layer pattern of the interconnect cell.

[0028] At least a majority of the circuit cells of the first and second subsets are typically functional cells.

[0029] The term "filler cell" herein refers to a circuit cell contained in a tiled sub-region within a die and can be a functional cell or a non-functional cell. In either case, the filler cell is associated with a critical dimension that is greater than the corresponding critical dimensions of the circuit cells of the first and second subsets.

[0030] For simplicity, the term “non-filled cell” may be used hereinafter to refer to any circuit cell of the first and second subsets as a shorthand to distinguish it from the filled cells in the tiled sub-region within the die.

[0031] The term "intra-die stitching sub-region" herein refers to another or "third" sub-region disposed between the first and second sub-regions and defined or formed by (ie, spanned by) one or more rows of fill cells.

[0032] The term "CD" with respect to a fill cell herein refers to the CD of a given type of circuit feature of the fill cell.

[0033] Accordingly, the term "corresponding CD" with respect to a non-filled cell herein refers to the CD of a given type of circuit feature of the non-filled cell.

[0034] In some embodiments, each circuit unit includes one or more feature patterns, wherein each feature pattern is any one of a semiconductor pattern, a gate pattern, or a metal layer pattern.

[0035] In some embodiments, each characteristic pattern is associated with (ie, has) a corresponding CD,

[0036] wherein the critical dimension of the filling cell is a critical dimension associated with any one of one or more feature patterns of the filling cell, and

[0037] The corresponding CDs of the circuit cells of the first and second subsets are CDs associated with corresponding characteristic patterns of the first and second subsets of circuit cells (ie, characteristic patterns corresponding to the above-mentioned characteristic patterns of the filling cells).

[0038] Therefore, in the case where the filling cell includes a semiconductor pattern, the CD of the semiconductor pattern of the filling cell may be greater than the corresponding CD of the corresponding semiconductor pattern of the non-filling cell.

[0039] Therefore, in the case where the filling cell includes a gate pattern, the CD of the gate pattern of the filling cell may be greater than the corresponding CD of the corresponding gate pattern of the non-filling cell.

[0040] Therefore, in the case where the filling cell includes a metal layer pattern, the CD of the metal layer pattern of the filling cell may be greater than the corresponding CD of the corresponding metal layer pattern of the non-filling cell.

[0041] In some embodiments, the CD of the filling cell is a pitch, a critical width dimension, or a spacing of a semiconductor pattern, a gate pattern, or a metal layer pattern of the filling cell.

[0042] Accordingly, when the filling cell includes a semiconductor pattern, a pitch or line width (eg, fin pitch or fin width) of the semiconductor pattern of the filling cell may be greater than a pitch or line width of the semiconductor pattern (eg, fin) of the non-filling cell.

[0043] Accordingly, in the case where the filling cell includes a gate pattern, the pitch of the gate pattern (e.g., contact polysilicon pitch (CPP) or gate contact pitch (GCP)) or gate length (corresponding to the width dimension of the gate) can be greater than the pitch or gate length of the gate pattern of the non-filling cell.

[0044] Accordingly, in the case where the filling cell includes a metal layer pattern, the pitch or width dimension of the metal layer pattern (e.g., metal line pitch, metal line width, metal contact pitch, metal via pitch, or metal via width dimension) may be greater than the pitch or width length of the corresponding metal layer pattern of the non-filling cell group. "Corresponding metal layer pattern" herein refers to the metal layer pattern of the non-filling cell arranged at the same metal level (i.e., interconnect level) as the above-mentioned metal layer pattern of the filling cell.

[0045] In some embodiments, one or more filler cells are configured as dummy cells that are electrically disconnected from the first and second subsets of circuit cells. As described above, by associating the filler cells with a CD that is larger than the corresponding CD of the non-filler cells, the control and alignment accuracy requirements for the stitched image field during the manufacturing process can be relaxed. In addition, configuring one or more filler cells as dummy cells ("dummy filler cells") further reduces the sensitivity of the entire circuit to inaccuracies because the dummy cells themselves are not intended to provide any circuit function. Another benefit of the dummy cells is that the functionality of the non-filler cells may not be affected by the presence of the dummy cells, which can facilitate circuit design, such as floorplanning and wiring.

[0046] The dummy fill cell may include one or more of a dummy semiconductor pattern, a dummy gate pattern, and a dummy metal layer pattern. One or more of the following may apply: the CD of the dummy semiconductor pattern may be greater than the corresponding CD of the semiconductor pattern of the non-fill cell; the CD of the dummy gate pattern may be greater than the corresponding CD of the gate pattern of the non-fill cell; and the CD of the dummy metal layer pattern may be greater than the corresponding CD of the metal layer pattern of the non-fill cell.

[0047] In some embodiments, one or more fill cells are configured as logic cells. Thus, fill cells configured as logic cells ("logic fill cells") can define loose CD functional cells, thereby implementing logic functions and thereby contributing to the overall circuit functionality of the IC device.

[0048] Like functional non-fill cells, logical fill cells may include semiconductor patterns, gate patterns, and metal layer patterns. One or more of the following may apply: the CD of the semiconductor pattern may be greater than the corresponding CD of the semiconductor pattern of the non-fill cells; the CD of the gate pattern may be greater than the corresponding CD of the gate pattern of the non-fill cells; and the CD of the metal layer pattern may be greater than the corresponding CD of the metal layer pattern of the non-fill cells.

[0049] In some embodiments, each logic cell is connected to circuit cells of the first and / or second subsets. Thus, the logic filler cells can be electrically and functionally integrated with the non-filler cells of the first and / or second sub-regions. Where the logic filler cells are connected to the non-filler cells of the first and second sub-regions, the logic filler cells can be used to implement combinational logic functions across the tiled sub-regions within the die. This can be particularly useful where the tiled sub-regions within the die extend across circuit blocks (e.g., macros or IP blocks), as discussed further below.

[0050] In some embodiments, one or more of the filling cells include a metal layer pattern including one or more metal interconnects, such as one or more metal lines, one or more metal contacts, and / or one or more metal vias.

[0051] Thus, a filled cell may include a pattern of one or more metal interconnects having a relaxed CD relative to the corresponding one or more metal interconnects of an unfilled cell.

[0052] Such a metal layer pattern may be included in a fill cell, a functional logic fill cell, or a non-functional fill cell (such as a dummy cell or an interconnect cell).

[0053] In some embodiments, the CD of the filler unit (or CD set) is at least twice the corresponding CD of the circuit units of the first and second subsets (or the corresponding CDs in the corresponding CD sets). Relaxing the CD of the filler unit by a factor of two can significantly relax the control and alignment accuracy requirements for the stitched image field during the manufacturing process.

[0054] In some embodiments, the circuit region includes a set of circuit blocks, wherein each circuit block includes a corresponding set of sub-rows of multiple rows of circuit cells, and

[0055] At least one circuit block in the circuit block set extends from the first sub-region across the intra-die stitching sub-region to the second sub-region, and includes a first sub-row set of first subsets of rows of circuit units, a second sub-row set of second subsets of rows of circuit units, and a third sub-row set of one or more rows of filling units located between the first sub-row set and the second sub-row set.

[0056] This can facilitate designing the circuit area floorplan, as circuit blocks can be more freely placed within the floorplan or circuit area, with less regard for the location of intra-die tile boundaries. To avoid resolution tile, precautions would have to be taken to distribute the circuit blocks so that they do not overlap intra-die tile boundaries. This can be complex and time-consuming, and is sometimes technically infeasible without the concomitant consideration of the overall circuit functionality of the IC device.

[0057] In some embodiments, each circuit block is any one of a macro, an IP block, or a non-IP block. Therefore, the macro, the IP block, and the non-IP block may be supplemented with one or more rows of padding cells.

[0058] In some embodiments of the second aspect, placing the circuit unit includes:

[0059] placing circuit cells in a preliminary distribution on the floor plan;

[0060] identifying a set of timing-critical circuit cells that form part of a timing-critical path located on opposite sides of an intra-die stitching boundary; and

[0061] Circuit units are placed in multiple rows in a first sub-region and a second sub-region, wherein the first sub-region includes a first row closest to the stitching sub-region and the second sub-region includes a second row closest to the stitching sub-region, and wherein the placement prioritizes placing timing critical circuit units in a set of timing critical circuit units in the first row and the second row rather than placing initially distributed non-timing critical circuit units in the first row and the second row.

[0062] Therefore, circuit cells on a timing-critical path that extends across an intra-die stitching boundary can be preferentially placed in rows closest to the intra-die stitching sub-region, rather than non-timing-critical circuit cells. This can also help maintain the timing performance of the IC device by moving non-timing-critical circuit cells farther away from the intra-die stitching sub-region despite the addition of filler cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] These and other aspects of the invention will now be described in more detail with reference to the accompanying drawings.

[0064] Figure 1 Schematic diagram of a die requiring intra-die splicing.

[0065] Figure 2a -b is a schematic diagram of the floor plan of the IC device.

[0066] Figure 3 It is a schematic diagram of the circuit unit.

[0067] Figure 4a -b shows a schematic side-by-side view of a non-filled cell and a filled cell according to an example ( Figure 4a ), and a portion of a circuit region including such non-filled and filled cells ( Figure 4b ).

[0068] Figure 5a -b shows a schematic side-by-side view of a non-filling unit and a filling unit according to yet another example ( Figure 5a ), and a portion of a circuit region including such non-filled and filled cells ( Figure 5b ).

[0069] Figure 6a -b shows a schematic side-by-side view of a non-filling unit and a filling unit according to yet another example ( Figure 6a ), and a portion of a circuit region including such non-filled and filled cells ( Figure 6b ).

[0070] Figure 7a -b shows a schematic side-by-side view of a non-filling unit and a filling unit according to yet another example ( Figure 7a ), and a portion of a circuit region including such non-filled and filled cells ( Figure 7b ).

[0071] Figure 8a -b shows Figure 2a A variation of the floorplan of -b in which the circuit area comprises a collection of circuit blocks.

[0072] Figure 9 is a flow chart of a method for floorplanning a circuit area of ​​an IC device. DETAILED DESCRIPTION

[0073] The accompanying drawings are schematic diagrams only, and the relative sizes of the illustrated elements (such as layers or other structures) may be exaggerated and not drawn to scale. Rather, the dimensions may be adjusted to provide clarity and understanding. When present in the drawings, the indicated axes X and Y point in a first direction and a second direction relative to the die of the IC device. The X and Y directions are transverse to each other. Both the X and Y directions are horizontal, i.e., parallel to the major planes of the die. The X and Y directions may also be referred to as the row or width direction and the height direction, respectively.

[0074] It should also be noted that terms such as "first" and "second" with respect to elements (such as sub-regions, subsets, features, floor plans or other features) or method steps are used herein merely as labels to facilitate distinguishing different elements or steps and do not necessarily mean that these elements or steps are arranged or performed in this particular order, unless otherwise specified.

[0075] Figure 1 Figure 1 is a schematic diagram of a die D that is larger than the image field of the lithography scanner used to pattern the die and therefore requires intra-die stitching. The die D in the example shown is twice the size of the on-wafer image half-field, necessitating stitching of two adjacent images H1 and H2 from two different reticles R1 and R2. The dashed line B represents the intra-die stitching boundary extending across die D in the X direction. A high-NA EUVL scanner provides 4x8 demagnification and uses a reticle size of 104mm x 132mm. This results in an on-wafer image half-field of 26mm x 16.5mm. Therefore, stitching the two images allows exposure of a die area of ​​26mm x 33mm.

[0076] Figure 2a FIG. 1 is a schematic diagram of a planar layout of a circuit region 4 of a die 2 of an integrated circuit device 1 . Figure 2b A representative example portion of the circuit region 4 is shown (eg Figure 2a An enlarged view of the image (shown by the dotted line in FIG).

[0077] The die 2 may be a conventional substrate suitable for semiconductor device processing. The die 2 may be, for example, a Si substrate, a Ge substrate, or a SiGe substrate. Other non-limiting examples include a silicon-on-insulator (SOI) substrate, a GeOI substrate, or a SiGeOI substrate. The die 2 may be, for example, a Si substrate, a Ge substrate, or a SiGe substrate.

[0078] The circuit region 4 extends along the die 2 in first and second directions X, Y and includes a plurality of circuit units 10, 20, 30. The circuit units 10, 20, 30 are arranged in a plurality of rows R1, R2, R3 extending in parallel along the X direction.

[0079] Circuit region 4 includes a first sub-region 41, which includes a first subset of multiple rows of circuit cells R1 (e.g., including rows R11, R12, R13, etc.). In other words, first sub-region 41 includes circuit cells 10 (non-populated cells) arranged in the first row subset R1 of the multiple rows of circuit cells in circuit region 4. Another circuit region 4 includes a second sub-region 42, which includes a second subset of multiple rows of circuit cells R2 (e.g., including rows R21, R22, R23, etc.). In other words, second sub-region 42 includes circuit cells 20 (non-populated cells) arranged in the second row subset R2 of the multiple rows of circuit cells in circuit region 4.

[0080] Figure 2b Only a few rows R11, R12, R13 and R21, R22, R23 of the first and second row subsets R1, R2, respectively, are shown. As shown, the unpopulated circuit cells 10, 20 may generally have a uniform cell height (as viewed along the Y direction), but the cell width (as viewed along the X direction) may vary within and / or between the corresponding rows R11, R12, R13 and R21, R22, R23.

[0081] The unfilled cells 10 , 20 of the first and second sub-regions 41 , 42 may generally be functional cells, for example, configured as logic cells, memory cells or I / O cells, or any other conventional circuit functions.

[0082] The circuit region 4 also includes an intra-die stitching (“third”) sub-region 43 extending across the circuit region 4 in the X direction.

[0083] The first and second sub-regions 41 , 42 are adjacent to (ie, contiguous with) the intra-die stitching sub-region 43 and are arranged on opposite sides of the intra-die stitching sub-region 43 .

[0084] The intra-die stitching sub-region 43 extends along the intra-die stitching boundary B. The boundary B extends in the X direction and, as shown in FIG. 2 , may substantially coincide with the center line of the die 2 .

[0085] Will Figure 2a -b with Figure 1 By comparison, it can be understood that the portions of the die 2 and circuit area 4 located above and below the stitching boundary B can correspond to the first image H1 (exposed using the first mask R1 during the device manufacturing process) and the second image H2 (exposed using the second mask R2 during the device manufacturing process).

[0086] To avoid resolution stitching during device fabrication, the intra-die stitching sub-region 43 is formed by a third subset of one or more rows of circuit cells R3. The circuit cells of the third subset R3 are configured as filling cells 30, and their critical dimensions (CD) are larger than the corresponding CDs of the circuit cells 10, 20 of the first and second subsets R1, R2.

[0087] Providing one or more rows of filler cells 30 with relaxed CDs along the tiling boundary B can facilitate intra-die tiling with little or negligible loss in area efficiency.

[0088] As an illustrative and non-limiting example, assuming that the circuit cell height is 90 nm (corresponding to the cell height in the 14A logic technology node) and the full die height is 33 mm (where “die height” corresponds to the die size along the second direction), the area loss per row of filled cells is approximately 0.00027%.

[0089] In the example shown, the intra-die stitching sub-region 43 is formed by a single row of filler cells R3. While this provides minimal area loss, it is also possible to configure the intra-die stitching sub-region 43 with more rows of filler cells. For example, the intra-die stitching sub-region can be formed by (or composed of) any number of rows of filler cells 30 within a range of 1 to 10 rows.

[0090] The intra-die stitching sub-region 43 can include functional fill cells, non-functional fill cells, and combinations thereof. Various example configurations of fill cells 30 (functional and non-functional) with different types of relaxed CDs are discussed below. However, in general, as will be understood from the following discussion, a circuit cell (non-fill cell 10, 20, or fill cell 30) can include a set of circuit features of corresponding types, each type associated with a corresponding CD. Thus, a fill cell (e.g., any fill cell 30) can be configured to be associated with (i.e., have) a set of CDs (each CD associated with a circuit feature of a corresponding type of the fill cell), wherein each CD in the set of CDs is greater than a corresponding CD in a corresponding set of CDs of a non-fill cell (i.e., the CD of the circuit feature of the corresponding type of the non-fill cell).

[0091] It is contemplated that the CD of a populated cell and the corresponding CD of an unpopulated cell, or as the case may be, a set of CDs of a populated cell and a corresponding set of CDs of an unpopulated cell, can refer to CDs that, if not relaxed for the populated cell, could make resolution stitching challenging for any of the reasons described above. Common examples of such CDs include the pitch of circuit features, the critical width dimension of circuit features, and the spacing of circuit features. Further examples are listed below.

[0092] The amount by which the CD of a filler cell is relaxed relative to the corresponding CD of an unfiller cell can vary. For example, relaxing the CD of a filler cell by a factor of two or more can significantly relax the control and alignment accuracy requirements of the stitched image field during manufacturing. However, in some cases, a smaller relaxation may be sufficient.

[0093] Circuit cells may also include one or more types of circuit features whose CDs have little impact on stitching accuracy. Examples of such CDs include the thickness or width of spacers, such as gate spacers and internal spacers. Where both filled and unfilled cells include such features, the associated CD of the filled cell need not be relaxed relative to the corresponding CD of the unfilled cell.

[0094] In addition, those skilled in the art will appreciate that, during the circuit manufacturing process, the highest resolution lithography and patterning are typically selectively applied to selected levels and a few selected types of circuit features of an IC device. Examples of the types of circuit features and levels to which the highest resolution may be applied include: semiconductor patterns (i.e., active levels), gate patterns (i.e., gate levels), metal layer patterns that form local interconnects (i.e., bottom contact levels, including, for example, source / drain contacts, sometimes referred to as "M0A"), metal layer patterns that form vias to the gates of the local interconnects and gate patterns (i.e., bottommost via levels, sometimes collectively referred to as "VINT," or separately as vias "VINTA" for contacting local interconnects and vias "VINTG" for contacting gates), and metal layer patterns that form horizontal metal lines adjacent to the bottommost via level (i.e., bottommost horizontal metal line level, sometimes referred to as "MINT" or "M0").

[0095] While the highest resolution lithography and patterning can also be applied to higher-level circuit features, such as higher bottom-most via levels (e.g., V0, V1, etc.) and / or higher horizontal metal line levels (e.g., M1, M2, etc.), relaxed pitches and feature widths are typically applied at higher levels where routing congestion is typically lower, and therefore relaxed CD vias and metal lines can be accommodated to reduce the overall resistance of the interconnect structure. Consequently, such relaxed CD level / circuit features (e.g., relaxed pitch and / or relaxed width dimensions) will have substantially no impact on stitching accuracy. Consequently, for levels of IC devices that only include such relaxed CD circuit features, filler cells do not need to include any corresponding circuit features at the corresponding level to avoid resolution stitching. Instead, relaxed CD circuit features for filler cells need only be provided for circuit features and at levels where the non-filler cells of the first and second sub-regions include features that, if not relaxed for the filler cells, might make resolution stitching challenging.

[0096] For simplicity, reference will be made below to the levels of an IC device (i.e., active level, gate level, M0A, VINT, MINT, etc.) using the above-mentioned labels. However, it should be noted that a particular label should not be interpreted as limiting its applicability to implementations using such particular label for device levels. Instead, hereinafter, "active" may refer to a level including a semiconductor pattern (particularly an active pattern or region), "gate" may refer to a level including a gate pattern, "M0A" may refer to a level including a local interconnect, "VINT" may refer to a level including a first / bottommost via, "MINT" may refer to a level including a first / lowest level metal line, "V0" may refer to a level including a second metal via continuous with the MINT level, and "M1" may refer to a level including a second horizontal metal line continuous with the V0 level, and so on. For simplicity, it will be assumed below that circuit features from the active level up to and including the MINT level form at most part of a circuit cell (e.g., non-filled cells 10, 20 and filled cell 30). Circuit features (typically vias and horizontal metal lines) at higher levels (e.g., V0 and M1 and higher) are assumed to be arranged above the circuit cells rather than included within them. Therefore, connections between the non-filled cells (e.g., non-filled cells 10 and 20) of the first and second sub-regions can be implemented using routing resources arranged above the circuit cells. For example, a horizontal metal line at the M1 level or higher can extend across the intra-die stitching region 43, pass over and around the fill cell 30, and connect to the corresponding non-filled cells 10 and 20 through a via at the V0 level.

[0097] Figure 3is a schematic diagram of an example layout of an unfilled cell, which represents the circuit cell 10 of the first sub-region 41 and the circuit cell 20 of the second sub-region 42. It should be noted that the specific layout shown is only a non-limiting example used to introduce various circuit feature patterns that may be included in the circuit cell, and therefore the circuit cells 10, 20 are not limited to this particular layout or implementation.

[0098] The circuit cells 10 , 20 shown include circuit features arranged in a set of feature patterns: a semiconductor pattern 101 , a gate pattern 102 (or “polysilicon”), and a plurality of metal layer patterns 103 , 104 , 105 .

[0099] The semiconductor pattern 101 is formed of a plurality of elongated semiconductor material features (e.g., fin-shaped) extending in parallel in the X-direction. The semiconductor pattern 101 is included in an active layer. Each elongated feature of the semiconductor pattern 101 defines a corresponding active region, which includes a plurality of source / drain regions (adjacent to the gate of the gate pattern 102) and a channel region (overlapping the gate of the gate pattern 102). The S / D region may include a body of semiconductor material, for example, epitaxially grown and doped with n-type or p-type dopants. The channel region may include a channel structure of semiconductor channel material that extends between and connects the semiconductor material bodies of the surrounding S / D regions. The channel structure may be fin-shaped (e.g., to form a finFET transistor) or include a vertical stack of channel layers in the form of nanowires or nanosheets (e.g., to form a gate-all-around transistor).

[0100] Figure 3 Examples of characteristic dimensions of the semiconductor pattern 101 are shown, which may be critical dimensions for intra-die stitching purposes: pitch (eg, active pitch or fin pitch) p a , line width (e.g., active width or fin width) w a and spacing (e.g. active spacing or fin spacing)s a Each of these types of CD is measured along the Y direction.

[0101] The gate pattern 102 includes a group of gates or gate structures extending in parallel in the Y direction and overlapping a channel region of an active region formed by the semiconductor pattern 101. The gate pattern 102 is included in a gate level. Figure 3 The gate 102 is shown schematically and simplified as a single layer, but the gate (i.e., the conductive gate body / gate electrode of each gate structure) can generally include one or more gate metal layers (e.g., work function metal and gate fill metal), and can also have gate spacers disposed along the sidewalls. The gate pattern 102 can also include one or more dummy gates, i.e., gates that are electrically disconnected from the entire circuit.

[0102] Figure 3 An example of a characteristic dimension of the gate pattern 102 is shown, which may be a critical dimension of intra-die stitching, or CPP. For the sake of completeness, other characteristic dimensions of the gate pattern 102 that may be relevant but not specifically shown include gate length (i.e., gate line width) and gate pitch. Each of these types of CD is measured along the Y direction.

[0103] The circuit cells 10, 20 include a pattern of metal contacts forming a local interconnect 103 of the circuit cells 10, 20. The local interconnect 103 is included in the MOA level. The local interconnect 103 may include one or more metal layers, for example (at least) two metal layers: a bottom layer ("active contact" or "trench silicide") and a top layer or "plug" layer (e.g., TiN, Co, Ru and / or W).

[0104] The circuit cells 10, 20 include a pattern of vias 104 contacting the local interconnects 103 and the gate pattern 102. The via pattern 104 is included in the VINT level.

[0105] Circuit cells 10 and 20 include a pattern of horizontal metal lines 105, schematically represented on the left side of circuit cells 10 and 20 by a set of routing tracks extending in parallel in the X direction. Metal lines / routing tracks 105 are contained in the MINT layer. The number of routing tracks determines the track height of circuit cells 10 and 20. Of course, the track height will vary depending on the implementation of circuit cells 10 and 20, and the track height of circuit cells 10 and 20 shown is only an example.

[0106] Figure 3 Examples of characteristic dimensions of each of the metal layer patterns 103 are shown, which may be critical dimensions for intra-die stitching purposes: The CD of the local interconnect 103 includes the line width w M0A (along the X direction). The CD of the via pattern 104 includes the via width dimension w via (along the Y direction) and the through-hole pitch p via (along the Y direction). The CD of the MINT level metal line / routing track 105 includes the track / metal line pitch p MINT , track / line width w MINT and track / line spacing s MINT Each of these types of CD is measured along the Y direction.

[0107] For the sake of completeness, other characteristic dimensions of the local interconnect 103 that may be relevant but are not specifically indicated include the pitch in the X direction (equivalent to the CPP) and the contact pitch in the Y direction (whose specific CD will depend on the pitch p of the MINT level). MINT ).

[0108] The edge tracks of the circuit cells 10, 20 may, as shown and known per se, have double line width (in the Y direction) relative to non-edge tracks and may also be shared with adjacent circuit cells across horizontal cell boundaries. The edge tracks are typically, but not necessarily, used to accommodate power rails (e.g., VDD and VSS).

[0109] exist Figure 3 The lower part of the M0 level further schematically indicates a routing track 106, along which a higher level horizontal metal line extending on the circuit unit 10, 20 can be arranged, usually along the Y direction.

[0110] Figure 4a Shown Figure 2a -b is a schematic side-by-side view of non-filled cells 10, 20 of the first or second sub-region 41, 42, and an example of a filled cell 30-1. Figure 4b Shown Figure 2a -b, the circuit cells 10, 20, 30-1 in the corresponding sub-areas 41, 42, 43 of the circuit area 4.

[0111] The non-filled cells 10, 20 correspond to Figure 3 However, for clarity of illustration, Figure 4a -b omits some feature patterns, and only shows the semiconductor pattern 101, gate pattern 102 and (MINT level) metal line 105 of the non-filled cells 10 and 20. The filled cell 30-1 is depicted as having corresponding feature patterns, namely, semiconductor pattern 301, gate pattern 302 and (MINT level) metal line 305. However, it should be understood that the filled cell 30-1 can include the same features as the non-filled cells 10 and 20. Figure 4a - Additional characteristic patterns corresponding to those discussed in b.

[0112] Filling cell 30-1 is an example of a filling cell having a relaxed CD in the form of a relaxed metal line pitch relative to the corresponding metal line pitch of non-filling cells 10, 20. Figure 4a As shown, the pitch p of the metal line 305 MINT greater than the corresponding pitch p of the metal line pattern 105 MINT (In the example shown, the metal line pattern is a pattern of features of the non-filled cells 10, 20 corresponding to the metal line 305).

[0113] like Figure 4a As shown, the relaxed pitch p of the metal line 305 MINT It can be implied to have a similar relationship with CD, which is represented by the metal line 305 having a line width w MINT and spacing s MINT, each of which may be larger than the corresponding line width w of the metal line 105 MINT and spacing s MINT .

[0114] like Figure 4a As further shown, the filled cell 30-1 may also have a relaxed CD in the form of a relaxed semiconductor pattern pitch relative to the corresponding semiconductor pattern pitch of the non-filled cells 10, 20. Figure 4a As shown, the pitch p of the semiconductor pattern 301 a is greater than the corresponding pitch p of the semiconductor pattern 101 a (In the example shown, it is a feature pattern of the non-filled cells 10 , 20 corresponding to the semiconductor pattern 301 ).

[0115] like Figure 4a As further shown, the relaxed pitch p of the semiconductor pattern 301 a It can mean a similar relationship with CD, which is expressed as the line width w of the semiconductor pattern 301 a and spacing s a , each of which may be larger than the corresponding line width w of the semiconductor pattern 101 (in the example shown, the feature pattern of the non-filled cells 10, 20 corresponding to the semiconductor pattern 301) a and spacing s a .

[0116] In the example shown, the corresponding relaxed CD (p MINT 、w MINT 、s MINT etc.) is approximately twice the corresponding CD of the non-filled cells 10, 20. However, smaller or larger differences are possible. Figure 5a Shown Figure 2a -b is a schematic side-by-side view of non-filling cells 10 , 20 of the first or second sub-region 41 , 42 , and yet another example of a filling cell 30 - 2 . Figure 5b Shown Figure 2a -b, the circuit cells 10, 20, 30-2 in the corresponding sub-areas 41, 42, 43 of the circuit area 4.

[0117] For clarity, Figure 5a -b omits the Figure 4a -b The same characteristic patterns of non-filled cells and filled cells 10, 20, 30-2. Figure 4a The discussion of the non-filled cells 10 and 20 applies accordingly. Figure 5a The non-filled cells 10 and 20.

[0118] Fill cell 30-2 is an example of a fill cell with a relaxed CD in the form of a relaxed gate pitch relative to the corresponding gate pitches of non-fill cells 10, 20. Figure 5a As shown, the pitch CPP of the gate pattern 302 is greater than the corresponding pitch CPP of the gate pattern 102 (in the example shown, the features of the non-filled cells 10 , 20 corresponding to the gate pattern 302 ).

[0119] Although Figure 5a Although not explicitly shown in , the relaxed pitch CPP of the gate pattern may imply a similar relationship with CD, as the gate length and gate spacing of the gate pattern 302 may each be larger than the corresponding gate length and gate spacing of the gate pattern 102 .

[0120] like Figure 5a As shown, the relaxed gate pitch CPP can be aligned with the relaxed pitch p of the metal line 305. MINT and the relaxed pitch p of the semiconductor pattern 301 a Combined.

[0121] Figure 6a Shown Figure 2a -b is a schematic side-by-side view of non-filling cells 10, 20 of the first or second sub-region 41, 42, and a further example of a filling cell 30-3. Figure 6b Shown Figure 2a -b, the circuit cells 10, 20, 30-3 in the corresponding sub-areas 41, 42, 43 of the circuit area 4.

[0122] Apart from Figure 4a In addition to the characteristic patterns shown in 5a-b and 5a-b, Figure 6a -b also shows additional metal layer patterns 303 and 304.

[0123] The metal layer pattern 303 corresponds to the metal layer pattern 103 and thus includes a metal contact pattern that forms a local interconnect 303 filling the cell 30. The local interconnect 303 may be included in the MOA level like the local interconnect 103.

[0124] The metal layer pattern 304 corresponds to the metal layer pattern 104 and thus includes a via pattern 304 contacting the local interconnect 303. Figure 6a Although not shown in FIG. 1-b, the via pattern 304 may further include a via contacting the gate pattern 302. The via pattern 304 may be included in the VINT level like the via pattern 104.

[0125] Filling cell 30-3 is an example of a filling cell having a relaxed CD in the form of a relaxed via pitch relative to the corresponding via pitch of non-filling cells 10, 20. Figure 6a As shown, the pitch p of the through hole pattern 304 via is greater than the corresponding pitch p of the through hole pattern 104 via (In the example shown, it is the pattern of features of the non-filled cells 10, 20 that corresponds to the via pattern 304).

[0126] As further shown, the fill cell 30 - 3 may additionally have a relaxed CD in the form of a relaxed width dimension w of the via pattern 304 relative to the via pattern 104 of the non-fill cells 10 , 20 . via and / or relaxed spacing s via Therefore, if Figure 4a As shown, the width dimension w of the through hole pattern 304 is via Greater than the corresponding width dimension w of the through hole pattern 104 via .

[0127] As further shown, the fill cell 30 - 3 may additionally have a relaxed CD in the form of a relaxed width dimension w of the via pattern 304 relative to the via pattern 104 of the non-fill cells 10 , 20 . via and / or relaxed spacing s via Therefore, if Figure 4a As shown, the width dimension w of the through hole pattern 304 is via Greater than the corresponding width dimension w of the through hole pattern 104 via (In the example shown, it is a feature pattern of the non-filled cells 10 , 20 corresponding to the semiconductor pattern 301 ).

[0128] Although Figure 6a It is not explicitly shown in FIG, but the relaxed pitch p of the through hole pattern 304 via A similar relationship can be combined with the CD of the pitch form of the local interconnect 303 along the Y direction. In addition, the relaxed pitch p of the via pattern 304 via and / or the relaxed pitch of the local interconnect 303 may be aligned with the metal line 305, the semiconductor pattern 301 (eg, Figure 4a ) and / or gate pattern 302 (as shown Figure 5a shown) are combined with the relaxed pitch.

[0129] The above examples of filling cells 30 - 1 , 30 - 2 , and 30 - 3 are all filling cells that can be configured as non-functional dummy cells. The filling cells 30 - 1 , 30 - 2 , and 30 - 3 configured as dummy cells can be electrically disconnected from the non-filling cells 10 and 20 .

[0130] When filling cells 30 - 1 , 30 - 2 , 30 - 3 are configured as dummy cells, the characteristic patterns may be referred to as dummy semiconductor patterns 301 , dummy gate patterns 302 , and dummy metal layer patterns (eg, dummy local interconnects 303 , dummy vias 304 , dummy metal lines 305 ).

[0131] Another example configuration of "non-functional" fill cells 30-1, 30-2, 30-3 is to configure one or more metal layer patterns (such as (MINT level) metal lines 305) as routing resources for providing interconnections between the non-fill cells 10, 20 of the first and second sub-regions 41, 42 across the intra-die stitching sub-region 43. For example, a metal line of the M0 level can extend from the first sub-region 41 into the intra-die stitching sub-region 43 to overlap with the first metal line 305 of the fill cells 30-1, 30-2, 30-3 and connect to it through the first V0 level via. Correspondingly, a metal line of the M0 level can extend from the second sub-region 42 into the intra-die stitching sub-region 43 to overlap with the second metal line 305 of the fill cells 30-1, 30-2, 30-3 and connect to it through the second V0 level via. Such fill cells can be referred to as interconnect cells. Thus, the metal layer pattern of the interconnect cell can be used as a pin for connecting circuit cells across the intra-die stitching sub-region 43. Thus, the interconnect cell can facilitate providing signal routing functionality between the first and second sub-regions 41, 42, but is otherwise considered "non-functional" in that it does not implement any logic functions, memory functions, I / O functions, etc.

[0132] The filler cell 30 may also be configured as a functional unit, thereby providing logic functions, memory functions, I / O functions, and the like.

[0133] Figure 7a Shown Figure 2a -b is a schematic side-by-side view of non-filled cells 10 , 20 of the first or second sub-region 41 , 42 and a further example of a filler cell 30 - 4 configured as a logic cell. Figure 7b Shown Figure 2a -b, the circuit cells 10, 20, 30-3 in the corresponding sub-areas 41, 42, 43 of the circuit area 4.

[0134] The fill cell 30 - 4 is shown configured to implement an inverter. However, this is merely an example, and the fill cell may of course be configured to implement any conventional type of logic function, memory function, I / O function, etc., such as those typically found in standard cell libraries.

[0135] Filling cell 30-4 includes a characteristic pattern corresponding to the characteristic pattern described above with reference to filling cells 30-1, 30-2, and 30-3. Thus, filling cell 30-4 is associated with a set of different CDs, each of which is relaxed relative to a corresponding set of CDs of non-filling cells 10, 20, as shown in FIG. Figure 7a As shown, the relaxed pitch p of the semiconductor pattern 301 a , the relaxed pitch p of the metal wire 305 MINT and the relaxed pitch p of the via pattern 304 via .

[0136] The fill cell 30 - 4 may be connected to the non-fill cells 10 , 20 of the first and / or second sub-regions 41 , 42 , for example, through higher-level routing resources above the fill cell 30 , such as the V0 and M1 levels and above.

[0137] Figure 8a -b shows Figure 2a -b floor plan variants, including those that usually correspond to Figure 2a -b, but the difference is that the circuit area 4 includes a circuit block set 6, which is schematically indicated by a solid line outline. In addition, the intra-die stitching sub-area 43 is formed by, for example, two rows of filling cells 30 of R3.

[0138] The circuit block set 6 is distributed in a non-overlapping manner within the circuit region 4, including first and second sub-regions 41, 42. Therefore, each circuit block 6 includes a corresponding sub-row set (ie, partial row) of the multiple rows of circuit cells R1, R2.

[0139] Each circuit block 6 is any one of a macro, an IP block, or a non-IP block. Non-limiting examples of circuit blocks include processing cores, memories (volatile or non-volatile), digital logic blocks, I / O functions, DACs, wireless and / or wired communication interfaces, etc. A macro itself can be a circuit portion formed by multiple interconnected circuit cells, as is known in the art, and configured to provide circuit functions that are more advanced than a single circuit cell. A macro can implement logic gates, advanced logic functions, arithmetic units, memory controllers, SRAM memories, communication interfaces, etc. Each circuit cell of a macro can be, for example, a standard cell from a standard cell library. An IP (intellectual property) block can be a circuit portion with preconfigured functions. An IP block can form part of a standardized library of IP blocks. An IP block library can be provided by an IP block designer (such as a semiconductor foundry or design company). An IP block is typically a relatively self-contained circuit portion, making it easy to reuse in different implementations of an IC device with little or no need for re-engineering. A non-IP block may define a self-contained and reusable circuit portion with preconfigured functions, just like an IP block, but differs in that it is not included in an IP block library. In contrast, non-IP blocks may be developed by the designer of the IC device.

[0140] The circuit block 6 may be surrounded by additional circuit cells, such as standard cells, to implement other circuit functions that supplement and support the functions of the circuit block 6 .

[0141] As shown, multiple circuit blocks 6, such as circuit block 6', can extend from the first sub-region 41 to the second sub-region 42, spanning the intra-die stitching sub-region 43. Thus, circuit block 6' includes a first sub-row set R1' (e.g., including sub-rows R11', R12', and R13') of the first row subset R1, a second sub-row set R2' (e.g., including sub-rows R21', R22', and R23') of the second row subset R2, and a third sub-row set R3' (e.g., sub-rows R31' and R32') of the rows R3 of filler cells located between the first and second sub-row sets R1' and R2'. Thus, circuit block 6' extends across the intra-die stitching sub-region 43, such that the circuit cells of circuit block 6' are distributed between the first sub-region 41, the second sub-region 42, and the intra-die stitching sub-region 43.

[0142] Since the intra-die stitching sub-region 43 is formed by the fill cells 30 with relaxed CD, intra-die stitching can be provided by circuit blocks such as IP blocks, non-IP blocks, and macros while avoiding resolution stitching.

[0143] The filler cells 30 included in the circuit block 6 ′ may be configured as dummy cells, interconnection cells, or logic cells depending on the function and implementation of the adjacent non-filler blocks 10 , 20 .

[0144] Although the intra-die stitching sub-region 43 in the illustrated example is formed by two rows of filling cells 30 R31 ′ and R32 ′, this is only an example, and the number of rows may vary in different embodiments.

[0145] Figure 9 It is the circuit area used for IC devices (such as Figure 2a 8 -b or 8a - b) is a flowchart of a method 500 for planar layout of a circuit area 4 of an IC device 1.

[0146] The method 500 may be implemented, for example, in an electronic design automation (EDA) tool.

[0147] At S501, a floor plan of the circuit area 4 is obtained. The floor plan may be referred to as an initial floor plan. The initial floor plan may be empty at this stage (ie, without circuit cells).

[0148] At S502 , the location of the intra-die stitching boundary B of the floorplan is determined. The location of stitching boundary B can be determined based on the known size of the die 2 and a priori knowledge of the size of the on-wafer image that the scanner can provide at the highest resolution. Typically, assuming a high-NA scanner, the stitching boundary can be determined as the centerline of the die 2 and the circuit area 4 .

[0149] At S503, one or more rows of filler cells 30 are placed in the intra-die stitching sub-region 43 of the floorplan along the intra-die stitching boundary B. The number of rows of filler cells 30 may be determined based on various parameters, such as the amount of space that can be allocated to filler cells 30 while maintaining the intended functionality of the final IC device, the amount of relaxation in the pitch of the filler cells 30, the specific configuration of the circuit cells 10, 20 that are / will be placed along the intra-die stitching sub-region 43, and the like.

[0150] At S504 , the circuit cells 10 , 20 are placed in multiple rows in each of the first and second sub-regions 41 , 42 of the floorplan, on opposite sides of the intra-die stitching sub-region 43 .

[0151] The placement of the filler cells 30 at S503 and the placement of the circuit cells 10, 20 at S504 can each be fully or partially automated by the EDA tool. For example, the partially automated placement can be based on preliminary placement of the circuit cells 10, 20 and, optionally, the circuit blocks 6, input by the user of the EDA tool. It is also possible that the user of the EDA tool fully manually places the filler cells 30 and / or the circuit cells 10, 20 at S503.

[0152] Although placing the filler cell 30 (at S503) before placing the circuit cells 10, 20 (at S504) may facilitate floorplanning (e.g., because information about the position of the filler cell 30 may be used to guide the placement of the circuit cells 10 and 20), the circuit cells 10, 20 may also be placed before the filler cell 30 is placed in the floorplan.

[0153] For example, after determining the position of the intra-die stitching boundary B, the extent of the intra-die stitching sub-region 43 can be determined. Then, step S504 can be executed to place the circuit units 10 and 20 in the first sub-region 41 and the second sub-region 42. Then, step S503 can be executed to place the filling unit 30 in the intra-die stitching sub-region 43.

[0154] As another example, a floor plan may be provided with a preliminary distribution of the circuit cells 10, 20 and the circuit blocks 6 before or after the location of the intra-die stitching boundary B is determined. The preliminary distribution of the circuit cells 10, 20 and the circuit blocks 6 may be automatically generated (completely or partially) by the EDA tool, or manually generated by a user interacting with the EDA tool. At this stage, the preliminary distribution of the circuit cells 10, 20 may or may not take into account the intra-die stitching boundary B and the intra-die stitching sub-region 43. Thus, the preliminary distribution of the circuit cells 10, 20 may include the circuit cells 10 and 20 placed within the intra-die stitching sub-region. Thereafter, the method may proceed by (at S503) placing one or more rows of fill cells 30 in the intra-die stitching sub-region 43. In the event that the circuit cells 10 and 20 of the preliminary distribution of circuit cells 10 and 20 are included in the intra-die stitching sub-region 43, the method can update the placement of the circuit cells 10 and 20 before placing the filler cells 30 so that no circuit cells 10 and 20 are present in the intra-die stitching sub-region 43. This update of the placement can correspond to step S504, or it can be an intermediate placement step intended only to remove any circuit cells 10 and 20 from the intra-die stitching sub-region 43. In the latter case, the intermediate placement of the circuit cells can be performed after step S503, followed by step S504, to determine the modified placement of the circuit cells 10 and 20 in the first and second sub-regions 41 and 42.

[0155] The floorplan obtained after placing the circuit cells 10 , 20 and the filling cell 30 in their respective sub-areas 41 , 42 , 43 can be further subjected to conventional subsequent steps in floorplanning, such as congestion analysis, clock tree generation, and the like.

[0156] Optionally, at step S504 , placement of circuit cells 10 , 20 may consider whether either circuit cell 10 or 20 is arranged on a timing critical path extending across the intra-die stitching boundary B, and thereby define a timing critical circuit cell.

[0157] Thus, a first sub-step of step S504 may include placing the circuit units 10 , 20 in a preliminary distribution in the floor plan (eg, fully or partially automatically, or manually).

[0158] The second sub-step of S504 may include identifying (i.e., determining) in the preliminary distribution a set of timing-critical circuit cells that form part of a timing-critical path located on opposite sides of the intra-die stitching boundary B. The set of timing-critical circuit cells and the timing-critical path may, for example, be included in a circuit block, such as Figure 8a - Circuit block 6' of B, which extends across the intra-die tile boundary B in the preliminary distribution.

[0159] The third sub-step of S504 may include placing circuit cells in multiple rows in the first and second sub-regions, while prioritizing the placement of the identified timing-critical cells in the first row closest to the intra-die stitching sub-region 43 of the first sub-region 41, and in the second row closest to the intra-die stitching sub-region 43 of the second sub-region 42. In other words, during the fourth sub-step, the circuit cells 10, 20 may be placed in multiple rows in the first and second sub-regions, while prioritizing the placement of timing-critical circuit cells in the first and second rows over the placement of the initially distributed non-timing-critical circuit cells in the first and second rows.

[0160] The second and third sub-steps of S504 may form part of a legalization process of the floor plan. Therefore, the placement of the circuit units 10 , 20 obtained at the third sub-step may correspond to a legal placement of the circuit units 10 and 20 .

[0161] Despite the addition of filler cells 30, prioritizing the placement of timing-critical circuit cells in the rows of the first and second sub-regions closest to (i.e., adjacent to) the intra-die stitching sub-region 43 facilitates maintaining timing performance along the timing-critical path. At the same time, non-critical timing cells can be further away from the intra-die stitching sub-region without negatively impacting timing performance.

[0162] A person skilled in the art realizes that the present invention is by no means limited to the examples described above. On the contrary, many modifications and variations are possible within the scope of the appended claims. For example,

[0163] As can be appreciated from the foregoing discussion, the above-discussed aspects, embodiments, and examples of IC devices and methods for floorplanning are particularly useful for technology nodes requiring high-NA scanners, such as 0.55NA EUVL scanners, where high-resolution intra-die stitching is particularly challenging. However, it is contemplated that the foregoing disclosure may have more general applicability to any IC device implementation and floorplanning method where high-resolution intra-die stitching is desirable during manufacturing. In such cases, the intra-die stitching boundary B does not necessarily need to extend along the centerline of the die 2, nor do the first and second sub-regions 41, 42 necessarily need to have a substantially uniform footprint.

Claims

1. An integrated circuit (IC) device, comprising: grains; a circuit region of the die, the circuit region extending along the die in a first lateral direction and a second lateral direction and comprising a plurality of circuit cells arranged in a plurality of rows extending in parallel in the first direction; The circuit area includes a first sub-area, a second sub-area, and an intra-die stitching sub-area, the first sub-area includes a first subset of the multiple rows of circuit cells, the second sub-area includes a second subset of the multiple rows of circuit cells, and the intra-die stitching sub-area extends across the circuit area in the first direction. wherein the first sub-region and the second sub-region are arranged on opposite sides of the intra-die stitching sub-region, and The intra-die stitching sub-region is formed by a third subset of one or more rows of the multiple rows of circuit cells, wherein the circuit cells of the third subset are configured as filling cells having a critical dimension that is greater than the corresponding critical dimensions of the circuit cells of the first subset and the second subset.

2. The IC device according to claim 1, wherein: Each circuit unit includes one or more feature patterns, wherein each feature pattern is any one of a semiconductor pattern, a gate pattern, or a metal layer pattern.

3. The IC device according to claim 2, wherein: Each feature pattern is associated with a corresponding critical dimension, wherein the critical dimension of the filling cell is a critical dimension associated with any one of one or more feature patterns of the filling cell, and The corresponding critical dimensions of the circuit cells of the first subset and the second subset are critical dimensions associated with corresponding feature patterns of the first subset and the second subset of the circuit cells.

4. The IC device according to claim 3, wherein: The critical dimension of the filling cell is a pitch, a critical width dimension, or a spacing of a semiconductor pattern, a gate pattern, or a metal layer pattern of the filling cell.

5. The IC device according to any one of the preceding claims, characterized in that One or more of the fill cells are configured as dummy cells that are electrically disconnected from the first subset and the second subset of the circuit cells.

6. The IC device according to any one of the preceding claims, characterized in that One or more of the fill cells are configured as a logic cell.

7. The IC device according to claim 6, wherein: Each logic cell is connected to circuit cells of the first subset and / or the second subset.

8. The IC device according to any one of the preceding claims, characterized in that One or more of the filling cells include a metal layer pattern including one or more metal interconnects, such as one or more metal lines, one or more metal contacts, and / or one or more metal vias.

9. The IC device according to claim 8, wherein: Each metal layer pattern of the one or more filling cells is connected to a metal layer pattern included in the first sub-region and / or the second sub-region.

10. The IC device according to any one of the preceding claims, characterized in that The critical dimension of the filler cell is at least twice the corresponding critical dimension of the circuit cells of the first subset and the second subset.

11. The IC device according to any one of the preceding claims, characterized in that The intra-die stitching sub-region is formed by a maximum of 10 rows of circuit units, a maximum of 5 rows of circuit units, a maximum of 2 rows of circuit units, or only 1 row of circuit units.

12. The IC device according to any one of the preceding claims, characterized in that The circuit area includes a set of circuit blocks, wherein each circuit block includes a corresponding set of sub-rows of the plurality of rows of circuit cells, and At least one circuit block in the circuit block set extends from the first sub-region across the intra-die stitching sub-region to the second sub-region, and includes a first sub-row set of first subsets of the rows of circuit units, a second sub-row set of second subsets of the rows of circuit units, and a third sub-row set of the one or more rows of filling units located between the first sub-row set and the second sub-row set.

13. The IC device according to claim 12, wherein: Each circuit block is either a macro, an IP block, or a non-IP block.

14. A computer-implemented method for floorplanning of circuit areas of an IC device, comprising: Obtaining a floor plan of the circuit area; determining a position of an intra-die stitching boundary of the floorplan, the intra-die stitching boundary extending across the floorplan in a first direction; placing one or more rows of fill cells in an intra-die stitching sub-region of the floorplan, wherein the one or more rows of fill cells extend in the first direction and the intra-die stitching sub-region extends along the intra-die stitching boundary, and In each of a first sub-region and a second sub-region on opposite sides of the intra-die stitching sub-region of the planar layout, a plurality of rows of circuit units extending in parallel along the first direction are placed, The filling unit has a critical dimension greater than a corresponding critical dimension of the circuit units in the first sub-region and the second sub-region.

15. The method according to claim 14, characterized in that Placing the circuit unit comprises: placing the circuit units in a preliminary distribution in the floor plan; identifying a set of timing-critical circuit cells that form part of a timing-critical path located on opposite sides of the intra-die stitching boundary; and Circuit units are placed in multiple rows in the first sub-region and the second sub-region, wherein the first sub-region includes a first row closest to the stitching sub-region and the second sub-region includes a second row closest to the stitching sub-region, and wherein the placement prioritizes placing timing critical circuit units in the set of timing critical circuit units in the first row and the second row rather than placing the initially distributed non-timing critical circuit units in the first row and the second row.

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