Device monitoring method and electronic equipment

Abstract

The invention discloses a device monitoring method and electronic equipment, and relates to the technical field of device monitoring, and the method comprises the steps that a logic controller obtains a plurality of state detection signals related to the reset process of an interconnection controller in response to the power-on of an interconnection management device; the logic controller generates a firmware loading mark signal based on the plurality of state detection signals, so that the management controller can read the firmware loading mark signal; in response to the fact that the firmware loading mark signal read by the management controller represents that the loading is effective, the management controller accesses the interconnection controller to monitor the interconnection state after a preset waiting period. According to the device monitoring method, the architecture difference of the interconnection controller can be considered, the access opportunity of the management controller to the interconnection controller is controlled, so that the situation that the management controller accesses the interconnection controller too early is avoided, and the problem that in the related technology, due to the fact that the management controller accesses too early, firmware loading of the interconnection manager is abnormal, and the reliability of the interconnection controller is improved is solved. Therefore, the problem of link training failure is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of device monitoring, and particularly relates to a device monitoring method and an electronic device. BACKGROUND

[0002] In the existing AI server, an interconnection management device is usually arranged to carry a high-speed interconnection link, and the core component thereof is an interconnection controller; in order to ensure the stability of the high-speed interconnection, the interconnection controller needs to be monitored by a management controller. However, due to the differences in the architectures of different interconnection controllers, the management controller cannot accurately determine the firmware loading state of the interconnection controller at the initial power-on stage, which may cause the interconnection controller to be accessed too early, thereby interfering with the firmware loading, causing the link training to fail, and reducing the system running stability; the traditional method generally solves the problem by using a fixed delay, but it cannot be compatible with interconnection controllers of different architectures, and the reliability is poor. SUMMARY

[0003] The present application provides a device monitoring method which can take into account the differences in the architectures of interconnection controllers and control the access timing of the management controller to the interconnection controller, thereby avoiding the early access of the management controller to the interconnection controller, to at least solve the problem that the firmware loading of the interconnection manager is abnormal due to the early access of the management controller in the related art, thereby causing the link training to fail.

[0004] The present application provides a device monitoring method applied to an interconnection management device, the interconnection management device at least comprising a logic controller, an interconnection controller and a management controller, and the method comprises the following steps: In response to the power-on of the interconnection management device, the logic controller acquires a plurality of state detection signals related to the reset process of the interconnection controller; The logic controller generates a firmware loading flag signal based on the plurality of state detection signals, for reading by the management controller; In response to the firmware loading flag signal read by the management controller indicating that the loading is valid, the management controller accesses the interconnection controller to perform interconnection state monitoring after a preset waiting period.

[0005] The present application also provides an electronic device comprising a memory for storing a computer program and a processor for executing the computer program to implement any of the above device monitoring methods.

[0006] Through the application, since the plurality of state detection signals related to the interconnection controller reset process are acquired in the logic controller, and the firmware loading flag signal is generated based on the plurality of state detection signals, the manager can be controlled to delay accessing the interconnection controller, and the management controller can be prevented from accessing the interconnection controller in advance when the firmware has not been completed loading, thus solving the problem that the management controller directly accesses the interconnection controller at the initial power-on time in the prior art, causing firmware loading interference and link training failure, thereby realizing effective protection during firmware loading of the interconnection controller, avoiding difficult-to-troubleshoot failure problems caused by premature access from the source, and improving the success rate of high-speed interconnection link training and the stability of system operation. BRIEF DESCRIPTION OF DRAWINGS

[0007] In order to more clearly illustrate the embodiments of the present application, the drawings required to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0008] Figure 1 A device monitoring method provided by an embodiment of the present application; Figure 2 A device monitoring method provided by an embodiment of the present application; Figure 3 A flip-flop and AND gate circuit structure provided by an embodiment of the present application; Figure 4 An interconnection management device structure provided by an embodiment of the present application; Figure 5 An interconnection management device structure provided by an embodiment of the present application; Figure 6 A device monitoring flowchart provided by an embodiment of the present application; Figure 7 An electronic device schematic diagram provided by an embodiment of the present application. DETAILED DESCRIPTION

[0009] The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0010] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0011] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0012] In one embodiment, Figure 1 As shown, the present application provides a device monitoring method, comprising: Step 101 , in response to the interconnection management device being powered on, the logic controller acquires a plurality of status detection signals related to a reset process of the interconnection controller; Step 102: The logic controller generates a firmware loading flag signal based on multiple status detection signals for the management controller to read; Step 103 : In response to the firmware loading flag signal read by the management controller indicating that loading is valid, the management controller accesses the interconnection controller to monitor the interconnection status after a preset waiting period.

[0013] Specifically, the device monitoring method provided in this embodiment can control the manager to delay access to the interconnection controller by obtaining multiple status detection signals related to the interconnection controller reset process in the logic controller and generating a firmware loading flag signal based on such status detection signals, thereby preventing the management controller from prematurely accessing the interconnection controller when the firmware has not yet been loaded. This solves the problem in the prior art that the management controller directly accesses the interconnection controller at the initial power-on, causing firmware loading interference and link training failure, thereby achieving effective protection during the interconnection controller firmware loading period, avoiding difficult-to-troubleshoot faults caused by premature access from the source, and improving the success rate of high-speed interconnect link training and the stability of system operation.

[0014] It is worth noting that, in one embodiment, a device monitoring method provided by the present application is applied to an interconnection management device, taking a baseboard as an example. After the device is powered on, the CPLD, which serves as a logic controller, receives a power status signal (RT_PWRGD) output by a power chip. The CPLD then sends an interconnection control signal (RT_RESET) to the retimer to control its reset process. It also transparently transmits a link reset signal (RT_PERST) transmitted by an upstream board to the retimer and OAM. Specifically, the substrate is a substrate capable of carrying a GPU module. By carrying a GPU, a complete GPU platform is formed, the GPU acceleration module is directly connected, a channel for high-speed data transmission and exchange is provided, and multi-GPU cooperation is assisted to cope with computationally intensive tasks in the AI field such as image recognition and machine learning. In some embodiments, the substrate can also provide power management, heat dissipation and other support for modules such as GPUs, to ensure stable operation of related modules. In some embodiments, the substrate is a UBB (Universal Baseboard) substrate that can support multiple GPUs (such as 8 OAM modules) working in various wiring and interconnection topologies. Specifically, CPLD (Complex Programmable Logic Device), i.e. complex programmable logic device, UBB board (Universal Base Board), i.e. universal baseboard, is used to carry logic controllers, interconnection controllers, management controllers and accelerators, to realize high-speed interconnection between CPUs and OAMs, OAM (OCP Accelerator Module), i.e. OCP accelerator module, as an open computing project accelerator, is used to perform AI or other high-speed computing tasks, Retimer, i.e. PCIe re-timing chip, as an interconnection controller, is used for signal re-timing and equalization to ensure signal integrity and stability of high-speed interconnection links. During this process, due to the difference in architecture design of different Retimer chips, the Retimer chip may start firmware loading at any time after reset. Unlike the present application, the BMC as a management controller to monitor the Retimer will access the Retimer at the first moment of device power-on to monitor it, but at this time the BMC cannot determine whether the Retimer has completed firmware loading, so it is likely to cause firmware loading exception in the Retimer, and further cause high-speed interconnection link training failure, resulting in OAM card drop and other fault phenomena.

[0015] In one embodiment, as shown in Figure 2 a plurality of state detection signals related to the reset process of the interconnection controller are obtained, including: Step 201, determining the reset process based on the architecture of the interconnection controller, and obtaining the corresponding reset completion time; Step 202, obtaining the timing events associated with the logic controller, and selecting the timing event at the same time as the reset completion time, and taking the corresponding timing event signal as the state detection signal.

[0016] Specifically, in the embodiment, the reset completion time is determined by combining the specific architecture features of the interconnection controller, and a corresponding timing event is selected from multiple timing events of the logic controller as a state detection signal, so that the monitoring point can be flexibly adjusted according to the architecture of different interconnection controllers, the limitations of a single fixed timing determination method are avoided, the determination of the firmware loading state is more accurate, the problem of inconsistent monitoring in the loading process caused by architecture differences is avoided, and the universality and stability of the method are enhanced.

[0017] In one embodiment, a timing event at the same time as the reset completion time is selected, and a corresponding timing event signal is selected as a state detection signal, including: obtaining timing events associated with the logic controller, including at least a power-on event, a link reset event, and an interconnection reset event; determining a power state signal received by the logic controller based on the power-on event; determining a link reset signal received by the logic controller based on the link reset event; determining an interconnection reset control signal output by the logic controller based on the interconnection reset event; one or more of the power state signal, the link reset signal, and the interconnection reset control signal are selected as the state detection signal.

[0018] Specifically, in the embodiment, the power state signal, the link reset signal, and the interconnection reset control signal are obtained by analyzing the power-on event, the link reset event, and the interconnection reset event of the logic controller, and are selected as the state detection signal, so that the reset process can be monitored comprehensively from the power, the link, and the interconnection, the misjudgment caused by relying on a single signal is avoided, and the integrity and reliability of the firmware loading state determination are enhanced.

[0019] In one embodiment, the logic controller includes at least a logic judgment unit, and a firmware loading flag signal is generated based on multiple state detection signals, including: inputting the multiple state detection signals into the logic judgment unit, so that the logic judgment unit compares the input signal values of the multiple state detection signals; in response to the multiple input signal values being consistent with the corresponding preset valid state values, the logic judgment unit outputs the firmware loading flag signal as a valid loading indication; in response to at least one input signal value being inconsistent with the corresponding preset valid state value, the logic judgment unit outputs the firmware loading flag signal as an invalid loading indication.

[0020] Specifically, in the embodiment, the logic decision circuit is introduced in the logic controller, multiple state detection signals are input into the decision circuit for comparison, and the firmware loading flag signal indicating loading valid or loading invalid is output according to whether the input signals are consistent with the preset valid state value. In the embodiment, the decision is completed by the hardware circuit, the delay and burden caused by the software polling are avoided, the firmware loading state is quickly and real-timely decided, and the real-time performance and accuracy of system monitoring are improved.

[0021] In one embodiment, the logic controller comprises an AND gate circuit and a flip-flop, and further comprises the following after taking one or more of the power state signal, the link reset signal and the interconnection reset control signal as the state detection signal: When the logic controller is started, the internal flag bits stored in the logic controller are initialized as invalid state values, and the internal flag bits include the link reset first trigger flag bit and the firmware loading flag bit; The link reset signal and the power state signal are input into the flip-flop; If the input value of the power state signal is the valid state value, the first rising edge of the link reset signal is obtained, and the link reset first trigger flag bit is set as the valid state value; If the input value of the power state signal is the invalid state value, the link reset first trigger flag bit and the firmware loading flag bit are both maintained as the invalid state value; The link reset first trigger flag bit and the interconnection reset control signal are input into the AND gate circuit; If the input value of the interconnection reset control signal and the link reset first trigger flag bit are both the valid state value, the firmware loading flag bit is set as the valid state value, and the firmware loading flag signal indicating loading valid is output; If one or more of the input value of the interconnection reset control signal and the link reset first trigger flag bit is the invalid state value, the firmware loading flag bit is maintained as the invalid state value, and the firmware loading flag signal indicating loading invalid is output.

[0022] Specifically, in the embodiment, the AND gate circuit and the flip-flop are arranged in the logic controller, and the decision is made in combination with the power state signal, the link reset signal and the interconnection reset control signal. Under the premise of stable power supply, only the first rising edge of the link reset signal is captured, the link reset first trigger flag bit is set under the correct timing condition, and then the link reset first trigger flag bit and the interconnection reset control signal are input into the AND gate circuit. It can be ensured that the firmware loading flag bit is set as valid only when the link reset and the interconnection reset are both valid, the misjudgment caused by unstable power supply or signal jitter is avoided, the accuracy and reliability of the firmware loading flag generation are ensured, the link training failure and module card drop caused by abnormal firmware loading are effectively prevented, and the stability of the overall operation of the interconnection management device is improved.

[0023] In one embodiment, as shown in Figure 3 The logic controller includes a flip-flop and a gate circuit, wherein the flip-flop is preferably a D flip-flop, and the flip-flop is provided with multiple inputs, including a storage input, a preset input, a clear input, and a clock input, and the output of the flip-flop is a trigger output for generating a link reset first trigger flag, wherein: When the logic controller is started, the clear input is set to be valid, the link reset first trigger flag of the trigger output is initialized to an invalid state value, and the firmware loading flag is also set to an invalid state value; When the input value of the current state signal is a valid state value, the logic controller inputs the signal to the storage input and sets the preset input to be valid, so that the flip-flop enters an active state and starts waiting for the arrival of the link reset signal; When the link reset signal arrives at the clock input and the first rising edge appears, the trigger output of the flip-flop flips to a valid state value, thereby generating the link reset first trigger flag; The logic controller inputs the link reset first trigger flag and the interconnection reset control signal to the AND gate circuit, and when both are valid state values, the firmware loading flag output by the AND gate circuit is set to a valid state value, and a firmware loading flag signal indicating loading valid is generated, and when either of them is an invalid state value, the firmware loading flag remains an invalid state value, and a firmware loading flag signal indicating loading invalid is output; When the current state signal becomes invalid again, the flip-flop is reset through the clear input, and the link reset first trigger flag and the firmware loading flag both return to an invalid state value, thereby avoiding false positives caused by unstable power supply or link signal jitter.

[0024] Through the above design, the logic controller can rely on the storage input, preset input, clear input, and clock input of the flip-flop to realize joint determination of the power state signal and the link reset signal, and combine the AND gate circuit to logically determine the interconnection reset control signal, thereby generating an accurate firmware loading flag signal. The implementation based on hardware circuit not only ensures the reliability of firmware loading determination, but also can quickly respond and improve the stability of the interconnection controller during operation.

[0025] In one embodiment, after setting the firmware loading flag to a valid state value, it further includes: Continuously monitor the power state signal and the interconnection reset control signal; In response to one or more of the input signal values of the power state signal and the input signal values of the interconnection reset control signal changing, the changed power state signal and / or interconnection reset control signal are re-input to the flip-flop and / or AND gate circuit; In response to the input signal value of the power state signal being the invalid state value, the flip-flop is cleared, and the firmware loading flag bit and the link reset first triggering flag bit are reset to the invalid state value, and the firmware loading flag signal indicating loading invalidity is re-outputted; In response to the input signal value of the interconnection reset control signal being the invalid state value, the original value of the link first triggering flag bit is maintained, and the firmware loading flag bit is updated to the invalid state value.

[0026] Specifically, in the embodiment, by continuing to dynamically monitor the power state signal and the interconnection reset signal after the firmware loading flag is set to be valid, and re-generating a determination result when the signals change, the continuous validity of the firmware loading flag in the running process is ensured, the system rigidity problem caused by the firmware loading flag not being updated once it is outputted is avoided, the system can perceive abnormalities and correct the determination state in time in the running process, and the fault tolerance and running safety of the system are improved.

[0027] In one embodiment, the logic controller further comprises an auxiliary input circuit connected with the interconnection controller, which combines the power state signal, the link reset signal and the interconnection reset control signal to obtain a plurality of state detection signals, and further comprises: An auxiliary signal used to represent the firmware loading completion state of the interconnection controller is obtained through the auxiliary input circuit; An auxiliary flag signal corresponding to the auxiliary signal is generated according to the auxiliary signal, and the auxiliary flag signal is stored in the logic controller; In response to receiving the interconnection controller state query request issued by the management controller, the stored auxiliary flag signal is sent to the management controller to provide auxiliary observation records for the management controller to judge the state change of the interconnection controller.

[0028] Specifically, in the embodiment, the auxiliary input circuit is introduced in the logic controller to obtain the firmware loading completion state of the interconnection controller itself, and generate an auxiliary flag signal for the management controller to call, which can provide a verification mechanism complementary to the logic determination result, so that the management controller can simultaneously use the logic controller determination signal and the interconnection controller itself signal for double verification, avoiding the problem of lacking cross verification by relying on only a single side signal, and further improving the accuracy of state determination and the adaptation ability to various architectures.

[0029] In one embodiment, in response to the firmware loading flag signal read by the management controller indicating loading validity, the management controller accesses the interconnection controller to perform interconnection state monitoring after a preset waiting period, including: Determine the minimum time required for the interconnect controller to complete internal initialization and the maximum time to enter a stable running state based on the architecture of the interconnect controller and historical performance data, and set the lower threshold of the waiting period threshold and the upper threshold of the waiting period threshold, respectively; Determine the waiting period threshold according to the lower threshold of the waiting period threshold and the upper threshold of the waiting period threshold, and select a preset waiting period; Within the preset waiting period, the management controller continuously monitors whether the firmware loading flag signal output by the logic controller changes through the first bus connected to the logic controller; If the preset waiting period ends and the firmware loading flag signal still indicates valid loading, the management controller continuously accesses the interconnect controller through the second bus connected to the interconnect controller; If the firmware loading flag signal changes and indicates invalid loading within the preset waiting period, the management controller resets the preset waiting period in a loop until the firmware loading flag signal indicates valid loading.

[0030] Specifically, in the embodiment, by setting the upper and lower thresholds of the waiting period threshold before the management controller accesses the interconnect controller, combining the architecture of the interconnect controller and historical performance data, and monitoring whether the firmware loading flag changes within the preset waiting period, it is determined whether to access the interconnect controller, which realizes accurate setting of the waiting time, avoids premature access causing firmware loading interference, and avoids unnecessary long waiting affecting efficiency, can guarantee reasonable control of the access timing of the management controller, and takes into account the loading stability and access efficiency, thereby improving the success rate of link training and overall performance.

[0031] In one embodiment, if the preset waiting period ends and the firmware loading flag signal still indicates valid loading, the management controller continuously accesses the interconnect controller through the second bus connected to the interconnect controller, including: Based on the preset monitoring dimension, continuously obtain the running state information of the interconnect controller through the second bus; According to the running state information, perform state monitoring and evaluation on the interconnect controller; During the access process, continuously monitor whether the firmware loading flag signal changes through the first bus; If it is detected that the firmware loading flag signal changes and indicates invalid loading, the current access operation is terminated and an exception handling process is triggered, and if the firmware loading flag signal does not change, the access to the interconnect controller is maintained.

[0032] Specifically, in the embodiment, the synchronization of the running monitoring and the state determination is realized by continuously obtaining the running state register information in the process of the management controller accessing the interconnection controller, simultaneously monitoring the change of the firmware loading flag, and stopping the access and triggering the exception processing procedure as soon as the invalid loading flag is detected, so that the fault can be timely identified and isolated during the running of the interconnection controller, and thus the reliability and maintainability of the system running are significantly improved.

[0033] In an optional embodiment, a plurality of interconnection controllers are arranged in the interconnection management device, and a firmware loading flag signal is generated based on a plurality of state detection signals for the management controller to read, comprising: An independent state detection channel is arranged for each of the plurality of interconnection controllers to store the flag bit, and the flag bit at least includes: a sampling result of the power state signal, a first trigger flag bit of the link reset signal, and a firmware loading flag bit; In response to the device being powered on, the interconnection reset control signal of the corresponding interconnection controller is sequentially released based on the interconnection controller port order, and the link reset signal is synchronously distributed to the corresponding state detection channel, so that the reset processes of the plurality of interconnection controllers are staggered in time, avoiding the congestion of the management side access caused by the simultaneous triggering of each channel in the power-on phase; According to the combination relationship of the power state signal and the link reset signal, the firmware loading flag signals of the plurality of state detection channels are sequentially generated, and the flag bits of the plurality of state detection channels are mapped to a group of continuous register storage units to form a flag bit table and a time stamp record arranged according to the interconnection controller port index, for the management controller to read and determine the access scheduling of the plurality of interconnection controllers according to the firmware loading flag signals of the plurality of state detection channels.

[0034] In an embodiment, the management controller reads and determines the access scheduling of the plurality of interconnection controllers according to the firmware loading flag signals of the plurality of state detection channels, comprising: For the state detection channel with the valid flag, the management controller performs batch access according to the preset waiting period table, wherein after the expiration of the waiting period of the state detection channel in the same batch, the management controller enters the state monitoring process of the corresponding interconnection controller through the interconnection access channel constructed based on the second bus; For the state detection channel with the invalid flag, the management controller does not initiate the access, only records the checking result of the current round and re-evaluates in the next round of scheduling; Further, the management controller limits the maximum number of parallel accesses in each access period, and applies a slight starting offset to the starting access time, so that the access starting points of the plurality of state detection channels in the batch are dispersed in time, so as to reduce the disturbance of the concurrent access to the internal firmware process of each interconnection controller; Further, during the access process, the management controller continuously monitors the change of the logical controller side flag bit table, and when there is any accessed state detection channel in which the flag bit changes from valid to invalid during operation, the management controller immediately terminates the current access to the corresponding state detection channel and moves it to the rollback queue, and resumes the access after the next round of valid flag is regenerated by the logical controller.

[0035] Optionally, in order to quickly locate the exception in the multi-channel scene, the logical controller configures an auxiliary input path for each state detection channel to receive an auxiliary signal from the corresponding interconnection controller, and records the auxiliary flag bit and the last change time in the flag bit table; the management controller dynamically adjusts the access priority when reading the flag bit table: when the state detection channel appears the auxiliary flag indicating that it is in the debugging, rollback or loading incomplete state, even if the basic flag bit is valid, the management controller will lower the priority or prolong the waiting period, so as to reduce the interference to the internal process of the channel.

[0036] Specifically, through the above-mentioned cooperative mechanism, the logical controller is responsible for providing accurate and de-concurrent state judgment and time scheduling under the condition of multiple channels, and the management controller carries out coordinated access of batch, flow control, rollback and recovery accordingly. The two cooperate to realize the orderly supervision of multiple interconnection controllers without changing the single-channel judgment logic, which not only avoids the disturbance of centralized access to firmware loading in the power-on and reset stage, but also improves the overall stability and maintainability of the multi-channel system through continuous monitoring and timely rollback of the flag bit in the running stage.

[0037] In one embodiment, the firmware loading flag signal is generated based on the plurality of state detection signals for the management controller to read, further comprising: The logical controller sets the firmware loading flag signal to be a multi-bit signal including at least two-bit encoding according to the bit width of the first bus; In response to the bit width of the first bus being greater than or equal to twice the number of interconnection controllers, the logical controller sequentially allocates fixed two-bit positions to the plurality of interconnection controllers based on the interconnection controller number sequence, stores the firmware loading state of the corresponding interconnection controller and distributes it to the corresponding channel, so that the management controller can collect all channels in one reading. Optionally, 00 indicates that the firmware is not loaded, 01 indicates that the firmware is being loaded, 10 indicates that the firmware loading fails, and 11 indicates that the firmware loading is completed. In response to the bit width of the first bus being less than twice the number of interconnection controllers, the logical controller sequentially outputs the firmware loading flag signals of the plurality of channels according to a preset frame, and carries a channel index domain and a verification domain in each frame, so that the management controller can construct a complete state view within multiple frame periods.

[0038] Specifically, in this embodiment, by setting a multi-bit encoded firmware loading status signal, the management controller can synchronously or frame-by-frame collect the firmware loading status of multiple interconnected controllers under different bus bit width conditions, thereby realizing the construction of a unified view of multi-channel status and providing a reliable basis for subsequent access scheduling and parallel monitoring. Moreover, compared with the use of a single-bit flag signal, the multi-bit encoding can carry more status information in a single read, such as distinguishing different stages such as loading, loading failure, or loading completion, thereby improving the precision of status collection and monitoring efficiency, while reducing the risk of bus congestion and access conflicts, and improving management flexibility and reliability in scenarios with multiple interconnected controllers.

[0039] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0040] like Figure 4 As shown, the embodiment of the present application further provides an interconnection management device, which is connected to the uplink management device and includes a logic controller, an interconnection controller and a management controller, wherein: The logic controller is connected to the interconnection controller, the accelerator and the management controller respectively, the interconnection controller is connected to the accelerator, and the management controller is connected to the logic controller and the interconnection controller respectively; The logic controller receives the power status signal and the link reset signal, generates an interconnection reset signal and a firmware loading flag signal, wherein the logic controller sends the interconnection reset signal to the interconnection controller, sends the firmware loading flag signal to the management controller, and forwards the link reset signal to the interconnection controller and the accelerator respectively; The interconnection controller performs a reset based on the received interconnection reset signal and triggers the internal firmware loading and link training process when receiving the link reset signal. The interconnection controller is connected to the accelerator and, after completing the firmware loading and link training, provides a stable high-speed interconnection channel for data exchange between the accelerator and the uplink management device. The management controller performs delayed access to the interconnection controller according to the received firmware loading flag signal, that is, continuously accesses the interconnection controller and obtains operation status information after a preset waiting period, so as to realize operation monitoring of the interconnection controller; After receiving the link reset signal and completing the link training with the interconnection controller, the accelerator performs calculation processing and feeds back the calculation results to the interconnection controller through a high-speed channel, which is then forwarded by the interconnection controller to the uplink management device.

[0041] In one embodiment, the uplink management device is connected with the interconnection management device, and the uplink management device at least comprises a central processing unit, a main memory, an uplink interface control module, a system clock and reset module, a power management module, and an optional uplink board-level management controller, wherein, the power management module is configured to supply power to the uplink management device and the interconnection management device, and output a power state signal to the logic controller, so that the logic controller takes the signal as an important input for state detection to generate a firmware loading flag signal and control the reset timing of the interconnection controller; the system clock and reset module is configured to generate a link reset signal when the central processing unit initiates link initialization, and transmit the link reset signal to the logic controller through the uplink interface control module, so that the logic controller distributes the link reset signal to the interconnection controller and the downlink accelerator, and enables the interconnection link to start a training process under a unified reset reference; the central processing unit serves as an initiation unit of uplink data, and establishes a high-speed data channel with the downlink accelerator through the interconnection controller after the interconnection controller completes firmware loading and link training, forms a high-speed channel signal, and forwards the high-speed channel signal to the accelerator after processing and regeneration by the interconnection controller, so as to ensure signal integrity and link stability; at the same time, the calculation result of the accelerator is returned to the interconnection controller through the high-speed channel signal and fed back to the central processing unit, so as to realize end-to-end data exchange; the main memory provides support for task scheduling and data calling of the central processing unit; the uplink board-level management controller interacts with the management controller in the interconnection management device through a low-speed management bus, receives a firmware loading flag signal generated by the logic controller and interconnection controller running state information fed back by the management controller, so as to realize remote monitoring and management of the interconnection link running condition.

[0042] As shown in Figure 5 In one embodiment, the present application further provides another interconnection management device, which is provided with an auxiliary circuit between the logic controller and the interconnection controller in addition to the structure of the above interconnection management device, and the auxiliary circuit is preferably a general-purpose input-output interface GPIO0. Specifically, the logic controller collects additional auxiliary signals from the interconnection controller through the GPIO0 interface, generates an auxiliary flag signal and stores it for subsequent management controller reading and calling.

[0043] Specifically, through the auxiliary circuit, the logic controller can obtain additional information such as the firmware loading completion state or the debugging state of the interconnection controller in addition to the normal power supply state signal, the link reset signal and the interconnection reset control signal, so as to generate a more accurate auxiliary flag signal and feed back to the management controller. At the same time, when the management controller performs interconnection state monitoring, the auxiliary circuit can also provide an additional observation channel, which facilitates quick positioning of the fault link of the interconnection controller when firmware loading abnormity or link training failure occurs, and improves the stability and maintainability of system operation.

[0044] In a specific embodiment, the interconnection management device is in a UBB board structure, and the device comprises a CPLD, a PCIe Retimer chip, a BMC and an OAM, wherein: The CPLD is connected with the PCIe Retimer chip, the OAM and the BMC respectively, the Retimer is connected with the OAM, and the BMC is connected with the CPLD and the PCIe Retimer chip respectively; The CPLD receives a power good signal (RT_PWRGD) and a link reset signal (PERST) output from the uplink board CPU and the power management chip, and generates a Retimer reset control signal (RT_RESET) and a firmware loading flag signal according to the power good signal and the link reset signal, wherein the power good signal is the power supply state signal, the Retimer reset control signal is the interconnection control signal, the RT_RESET signal is sent to the PCIe Retimer chip, and the firmware loading flag signal is sent to the BMC. At the same time, the PERST signal is transmitted by the CPLD to the PCIe Retimer chip and the OAM to ensure that the link is trained under the unified reset reference; The Retimer performs a reset operation after receiving the RT_RESET signal from the CPLD, and starts the firmware loading and link training process when receiving the PERST signal; after completing the firmware loading and training, the Retimer provides re-timing and signal equalization capability for the PCIe X16 high-speed link between the CPU and the OAM, to ensure the stability and signal integrity of the link transmission.

[0045] The BMC performs delayed access on the Retimer according to the firmware loading flag signal output by the CPLD, that is, periodically accesses the Retimer through the I2C interface after a preset waiting period to read the running state and working parameters such as temperature and voltage of the Retimer, to realize the monitoring and management of the Retimer chip; through the delayed access strategy, the firmware loading abnormity caused by early access during the Retimer firmware loading process is avoided, thereby improving the link stability.

[0046] After receiving the PERST signal transmitted by the CPLD and completing the link training with the Retimer, the OAM performs the AI training or inference task; the calculation result of the OAM is returned to the Retimer chip through the PCIeX16 high-speed link, and then forwarded to the CPU by the Retimer, so as to realize the end-to-end high-speed data exchange.

[0047] In a further embodiment, the uplink board includes a CPU, a main memory, a power management chip, a system clock and reset module, and an uplink interface control module: The CPU serves as the initiating unit of the uplink data, sends the PCIeX16 signal to the Retimer through the uplink interface control module, and performs high-speed data interaction with the OAM after the link is established; The power management chip supplies power to the whole board and outputs the RT_PWRGD signal to the CPLD as an important input for the CPLD to determine the firmware loading flag; The system clock and reset module generates the PERST signal, which is transmitted to the CPLD through the uplink interface control module, and then forwarded to the Retimer and the OAM by the CPLD, for unified reset control.

[0048] As shown in Figure 6 In one embodiment, based on the interconnection management device provided in the present application, the execution flow of the device monitoring method of the present application includes: On the logic controller side, first, when the interconnection management device is powered on, the logic controller initializes the internal flag bits, sets the link reset first trigger flag bit and the firmware loading flag bit to the invalid state; then, the logic controller receives the power state signal and judges whether the input value is the valid state value, if not, the power state signal is invalid, then the logic controller keeps the above-mentioned flag bits invalid, and ends the subsequent processing, if yes, the power state signal is valid, then the logic controller releases the interconnection reset control signal to the interconnection controller; then, the logic controller detects the input of the link reset signal, when the first rising edge of the link reset signal is detected, the link reset first trigger flag bit is set to the valid state value, and the interconnection reset control signal is judged together, if both are valid state values, the logic controller sets the firmware loading flag bit to the valid state value, and outputs the firmware loading flag signal indicating that the loading is valid, if at least one of them is invalid state value, the logic controller maintains the firmware loading flag bit to the invalid state value, and outputs the firmware loading flag signal indicating that the loading is invalid; On the management controller side, the management controller executes a corresponding access strategy according to the firmware loading flag signal generated by the logic controller, if the firmware loading flag signal represents invalid loading, the management controller keeps not accessing the interconnection controller, thereby avoiding interference with the firmware loading process due to premature access, if the firmware loading flag signal represents valid loading, the management controller starts to access the interconnection controller after completing a preset waiting period, and continuously acquires running state information during the access process, so as to realize stable monitoring of the interconnection controller; during the access process, if the firmware loading flag bit becomes an invalid state value, the access to the interconnection controller is stopped.

[0049] Specifically, through the cooperative action of the logic controller and the management controller, the embodiment can dynamically identify the actual state of the interconnection controller during the firmware loading process, and reasonably adjust the access timing of the management controller, thereby avoiding the link training failure problem caused by firmware loading abnormity, and guaranteeing the stability and reliability of the interconnection link.

[0050] As shown in Figure 7 The embodiment of the present application also provides an electronic device, which comprises a memory and a processor, the memory stores a computer program, and the processor is arranged to run the computer program to execute the steps in any one of the device monitoring method embodiments.

[0051] The skilled person can further realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be realized in electronic hardware, computer software or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in general terms in the above description. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0052] The above describes in detail the device monitoring method and the electronic device provided by the present application. The principles and implementation modes of the present application are described by applying specific examples. The above description of the examples is only applicable to help understand the method and its core idea of the present application. It should be pointed out that, for the ordinary skilled person in the technical field, without departing from the principles of the present application, the present application can be improved and modified in several ways, and these improvements and modifications also fall within the protection scope of the present application.

Claims

1. A method of monitoring a device, characterized by, The application is applied to an interconnection management device, and the interconnection management device at least comprises a logic controller, an interconnection controller and a management controller, and the method comprises the following steps: In response to power-on of the interconnection management device, the logic controller acquires a plurality of state detection signals related to a reset process of the interconnection controller; The logic controller generates a firmware loading flag signal based on the plurality of state detection signals for the management controller to read; In response to the firmware loading flag signal read by the management controller representing loading valid, the management controller accesses the interconnection controller for interconnection state monitoring after a preset waiting period.

2. The device monitoring method according to claim 1, wherein The acquiring of the plurality of state detection signals related to the reset process of the interconnection controller comprises: Determination of the reset process based on the architecture of the interconnection controller and obtaining of a corresponding reset completion time point; Acquisition of timing events associated with the logic controller and selection of a timing event at the same time point as the reset completion time point, and taking the corresponding timing event signal as the state detection signal.

3. The device monitoring method according to claim 2, wherein The selection of the timing event at the same time point as the reset completion time point and taking the corresponding timing event signal as the state detection signal comprises: Acquisition of timing events associated with the logic controller, at least including a power-on event, a link reset event and an interconnection reset event; Determination of a power state signal received by the logic controller based on the power-on event; Determination of a link reset signal received by the logic controller based on the link reset event; Determination of an interconnection reset control signal output by the logic controller based on the interconnection reset event; Taking one or more of the power state signal, the link reset signal and the interconnection reset control signal as the state detection signal.

4. The device monitoring method according to claim 1, wherein The logic controller at least comprises a logic judgment unit, and the generation of the firmware loading flag signal based on the plurality of state detection signals comprises: Input of the plurality of state detection signals into the logic judgment unit, so that the logic judgment unit compares according to input signal values of the plurality of state detection signals; In response to the fact that the plurality of input signal values are all consistent with corresponding preset valid state values, the logic judgment unit outputs the firmware loading flag signal as representing loading valid; In response to the fact that at least one input signal value is inconsistent with a corresponding preset valid state value, the logic judgment unit outputs the firmware loading flag signal as representing loading invalid.

5. The device monitoring method according to claim 3, wherein The logic controller comprises an AND gate circuit and a flip-flop, and after the taking of one or more of the power state signal, the link reset signal and the interconnection reset control signal as the state detection signal, the method further comprises the following steps: Initialization of internal flag bits stored in the logic controller to invalid state values when the logic controller starts, and the internal flag bits include a link reset first triggering flag bit and a firmware loading flag bit; Input of the link reset signal and the power state signal into the flip-flop; if the input value of the power state signal is a valid state value, obtaining a first rising edge of the link reset signal and setting the link reset first trigger flag to a valid state value; if the input value of the power state signal is an invalid state value, maintaining the link reset first trigger flag and the firmware loading flag to invalid state values; inputting the link reset first trigger flag and the interconnection reset control signal into the AND gate circuit; if the input value of the interconnection reset control signal and the link reset first trigger flag are both valid state values, setting the firmware loading flag to a valid state value and outputting the firmware loading flag signal representing valid loading; if one or more of the input value of the interconnection reset control signal and the link reset first trigger flag is an invalid state value, maintaining the firmware loading flag to an invalid state value and outputting the firmware loading flag signal representing invalid loading.

6. The device monitoring method according to claim 5, wherein After setting the firmware loading flag to a valid state value, further comprising: continuously monitoring the power state signal and the interconnection reset control signal; in response to one or more of the input signal values of the power state signal and the interconnection reset control signal changing, re-inputting the changed power state signal and / or interconnection reset control signal into the flip-flop and / or AND gate circuit; in response to the input signal value of the power state signal being an invalid state value, resetting the flip-flop and resetting the firmware loading flag and the link reset first trigger flag to invalid state values and re-outputting the firmware loading flag signal representing invalid loading; in response to the input signal value of the interconnection reset control signal being an invalid state value, maintaining the original value of the link first trigger flag and updating the firmware loading flag to an invalid state value.

7. The device monitoring method according to claim 3, wherein The logic controller further comprises an auxiliary input circuit connected to the interconnection controller, and after the power state signal, the link reset signal and the interconnection reset control signal are combined to obtain a plurality of state detection signals, further comprising: obtaining an auxiliary signal representing the firmware loading completion state of the interconnection controller through the auxiliary input circuit; generating a corresponding auxiliary flag signal according to the auxiliary signal and storing the auxiliary flag signal in the logic controller; in response to receiving an interconnection controller state query request issued by the management controller, sending the stored auxiliary flag signal to the management controller to provide auxiliary observation records for the management controller to judge the state change of the interconnection controller.

8. The method of claim 1, wherein, In response to the firmware loading flag signal read by the management controller representing valid loading, the management controller accesses the interconnection controller for interconnection state monitoring after a preset waiting period, comprising: Determine, based on the architecture and historical performance data of the interconnection controller, a minimum time required for the interconnection controller to complete internal initialization and a maximum time required to enter a stable operating state, and set a lower threshold value of a waiting period and an upper threshold value of a waiting period respectively; Determine the waiting period threshold value and select the preset waiting period according to the waiting period threshold lower limit and the waiting period threshold upper limit; During the preset waiting period, the management controller continuously monitors, via a first bus connected to the logic controller, whether the firmware loading flag signal output by the logic controller changes; If the firmware loading flag signal changes within the preset waiting period and indicates that loading is invalid, the management controller cyclically resets the preset waiting period until the firmware loading flag signal indicates that loading is valid; If the preset waiting period ends and the firmware loading flag signal still indicates that loading is valid, the management controller continuously obtains the operating status information of the interconnection controller through the second bus based on the preset monitoring dimension; performing status monitoring and evaluation on the interconnection controller according to the operating status information; During the access process, the firmware loading flag signal is continuously monitored through the first bus to determine whether it changes. If a change in the firmware loading flag signal is detected and indicates that the loading is invalid, the current access operation is terminated and an exception handling process is triggered. If the firmware loading flag signal does not change, access to the interconnection controller is maintained.

9. The method of claim 1, wherein, The interconnection management device is provided with a plurality of the interconnection controllers, and the generating of a firmware loading flag signal based on the plurality of status detection signals for the management controller to read includes: Setting independent status detection channels for the plurality of interconnection controllers to store flag bits, the flag bits including at least: a sampling result of a power status signal, a first trigger flag bit of a link reset signal, and a firmware loading flag bit; In response to the device being powered on, the interconnection reset control signals corresponding to the interconnection controllers are released sequentially based on the order of the interconnection controller ports, and the link reset signals are synchronously distributed to the corresponding status detection channels, so that the reset processes of the plurality of interconnection controllers are staggered in time; Based on the combined relationship between the power status signal and the link reset signal, the firmware loading flag signals of the multiple status detection channels are sequentially generated, and the flag bits of the multiple status detection channels are aggregated and mapped to a group of continuous register storage units to form a flag bit table and a timestamp record arranged by interconnection controller port index, so that the management controller can read and determine the access schedule of the multiple interconnection controllers based on the firmware loading flag signals of the multiple status detection channels.

10. An electronic device, comprising: include: Memory for storing computer programs; A processor, configured to implement the device monitoring method according to any one of claims 1 to 9 when executing the computer program.

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