Clock transmission circuit

Abstract

The present disclosure relates to a clock transmission circuit including: a first inverter configured to inversely drive a first transmission node in response to a first clock signal loaded to a first reception node among differential clock signals; a second inverter configured to inversely drive a second transmitting node in response to a second clock signal loaded to a second receiving node among the differential clock signals; a first additional driver configured to additionally drive the first transmitting node in response to a second clock signal loaded to the second receiving node; and a second additional driver configured to additionally drive the second transmitting node in response to a first clock signal loaded to the first receiving node.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2024-0053985, filed on April 23, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present disclosure relate to semiconductor design, and more particularly, to a clock transmission circuit for transmitting a differential clock signal. Background Art

[0004] Electronic devices may include many electronic components, and among electronic devices, computer systems may include many semiconductor devices that can communicate with each other by sending and receiving clock signals and data. As the operating speed of semiconductor devices increases, the frequency of clock signals also increases.

[0005] Semiconductor devices include clock distribution networks, such as clock trees, to distribute clock signals to various internal circuits. The clock tree drives the clock signal to provide the clock signal to the various circuits within the semiconductor device. However, as the clock signal frequency increases and the clock signal pulse width decreases, accurately providing the clock signal becomes increasingly difficult. Furthermore, there are issues such as potential delays in the timing of sending the clock signal or possible duty cycle errors. Summary of the Invention

[0006] Various embodiments of the present disclosure are directed to providing a clock transmission circuit that minimizes the occurrence of duty cycle errors in the process of transmitting a differential clock signal, and a semiconductor device including the clock transmission circuit.

[0007] Furthermore, various embodiments of the present disclosure are directed to providing a clock transmission circuit that minimizes leakage current generated in the process of transmitting a differential clock signal, and a semiconductor device including the clock transmission circuit.

[0008] Problems to be solved by the present disclosure are not limited to the above-mentioned problems, and unmentioned problems will be clearly understood by those skilled in the art from the following description.

[0009] In an embodiment of the present disclosure, a clock sending circuit may include: a first inverter, configured to inversely drive a first sending node in response to a first clock signal loaded to a first receiving node among differential clock signals; a second inverter, configured to inversely drive a second sending node in response to a second clock signal loaded to a second receiving node among differential clock signals; a first additional driver, configured to additionally drive the first sending node in response to the second clock signal loaded to the second receiving node; and a second additional driver, configured to additionally drive the second sending node in response to the first clock signal loaded to the first receiving node.

[0010] In an embodiment of the present disclosure, a clock sending circuit may include: a first sending circuit configured to send a first clock signal among differential clock signals through multiple first inverters connected in a chain form; a second sending circuit configured to send a second clock signal among the differential clock signals through multiple second inverters connected in a chain form and respectively corresponding to the multiple first inverters; at least one first additional driver configured to additionally drive an output node of at least one second selected inverter corresponding to the at least one first selected inverter among the multiple first inverters in response to a signal loaded onto an input node of at least one first selected inverter among the multiple second inverters; and at least one second additional driver configured to additionally drive an output node of at least one first selected inverter in response to a signal loaded onto an input node of the at least one second selected inverter.

[0011] In the present disclosure, by adding a cross-coupled transistor when transmitting a differential clock signal through a plurality of inverters connected in a chain, the angles of the edges of the logic level transitions of the differential clock signal can be aligned relatively high compared to when transmitting the differential clock signal using only inverters. In the cross-coupled transistor, the input node of the inverter is connected to the output node of the inverter. The input node of the inverter transmits the signal on one side of the differential clock signal, and the output node of the inverter transmits the signal on the other side of the differential clock signal. Therefore, the occurrence of duty cycle errors in the process of transmitting the differential clock signal can be minimized.

[0012] Furthermore, according to an embodiment of the present disclosure, by adding cross-coupled transistors to a clock transmission circuit that transmits a differential clock signal, leakage current generated in the cross-coupled transistors having a stacked structure can be minimized. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a diagram for describing a clock transmission circuit according to the first embodiment of the present disclosure.

[0014] Figure 2 is used to describe Figure 1FIG. 2 is a diagram showing another embodiment of the first additional driver and the second additional driver among components of the clock transmission circuit shown in FIG. 1.

[0015] Figure 3 is used to describe Figure 1 FIG. 3 is a diagram showing another embodiment of the first additional driver and the second additional driver among components of the clock transmission circuit shown in FIG. 1.

[0016] Figure 4 is used to describe Figure 1 FIG. 4 is a diagram showing another embodiment of the first additional driver and the second additional driver among components of the clock transmission circuit shown in FIG. 1.

[0017] Figure 5 is used to describe Figure 1 FIG. 5 is a diagram showing another embodiment of the first additional driver and the second additional driver among components of the clock transmission circuit shown in FIG. 1.

[0018] Figure 6 is used to describe Figure 1 FIG. 6 is a diagram showing another embodiment of the first additional driver and the second additional driver among components of the clock transmission circuit shown in FIG. 1.

[0019] Figure 7 is used to describe Figure 1 FIG. 7 is a diagram showing another embodiment of the first additional driver and the second additional driver among components of the clock transmission circuit shown in FIG. 1.

[0020] Figure 8 is a diagram for describing a clock transmission circuit according to a second embodiment of the present disclosure.

[0021] Figure 9 is a diagram for describing a clock transmission circuit according to a third embodiment of the present disclosure.

[0022] Figure 10 is a diagram for describing a clock transmission circuit according to a fourth embodiment of the present disclosure.

[0023] Figure 11 is a diagram for describing a clock transmission circuit according to a fifth embodiment of the present disclosure.

[0024] Figure 12 is a diagram showing a memory system to which a clock transmission circuit according to an embodiment of the present disclosure is applied. DETAILED DESCRIPTION

[0025] Various embodiments of the present disclosure are described below with reference to the accompanying drawings. However, elements and features of the present disclosure can be configured or arranged differently to form other embodiments, which can be variations of any of the disclosed embodiments.

[0026] In the present disclosure, reference to various features (e.g., elements, structures, modules, components, steps, operations, features, etc.) included in “one embodiment,” “an example embodiment,” “an embodiment,” “another embodiment,” “some embodiments,” “various embodiments,” “other embodiments,” “alternative embodiments,” etc. is intended to mean that any such features are included in at least one embodiment of the present disclosure, but can or can not be included in the same embodiment.

[0027] In the present disclosure, the terms “comprise,” “comprising,” “include,” “including,” and “contain” are open-ended. As used in the appended claims, these terms specify the presence of stated elements but do not preclude the presence or addition of one or more other elements. The term in the claims does not exclude additional components (e.g., interface units, circuitry, etc.) from being present in the device.

[0028] In the present disclosure, various units, circuits, or other components can be described or claimed as “configured to” perform one or more tasks. In this context, “configured to” means that the structure (e.g., circuitry) of the block / unit / circuit / component includes one or more structures that perform the task(s) during operation. As such, the task(s) can be performed even if the block / unit / circuit / component is not currently operational (e.g., not currently activated or enabled). The block / unit / circuit / component used in connection with “configured to” language includes hardware-only circuits, such as, for example, circuits implemented in circuitry that does not include a general-purpose processor. The block / unit / circuit / component used in connection with “configured to” language also includes a general-purpose processor, such as, for example, a general-purpose processor that is programmed to perform the task(s). Additionally, the “configured to” can also include a general-purpose processor that is manipulated by software and / or firmware (e.g., an FPGA or general-purpose processor implementing software) to operate in a manner that enables the general-purpose processor to perform the task(s) being discussed. The “configured to” can also include a structure that is made during the manufacturing of the device (e.g., an integrated circuit), to perform the task(s) being discussed.

[0029] As used in this disclosure, the term "circuitry" or "logic" refers to all of the following: (a) hardware-only circuitry such as only analog and / or digital circuitry; and (b) combinations of circuits and software (and / or firmware), such as (as applicable): (i) a combination of processor(s) or (ii) portions of processor(s) / software that include, among other things, hardware, such as a microprocessor or a portion of a microprocessor; and (c) software, such as a microprocessor or a portion of a microprocessor, that is physically on or runs on the hardware. The definition of "circuitry" or "logic" applies to all uses of this term in this application, including in any claims. As a further example, as used in this application, the term "circuitry" or "logic" also covers an implementation that has a sole processor (or multiple processors) or a portion of a processor and its accompanying software and / or firmware. The term "circuitry" or "logic" also encompasses, for example, an integrated circuit for storing devices.

[0030] As used herein, the terms "first," "second," "third," etc. are used as labels for nouns that they precede, and do not necessarily describe an order or sequence in time, space, logic, etc. The terms "first" and "second" are not necessarily used to denote a primary or secondary relationship or to denote a relationship between other terms. Further, the terms "first" and "second" are not necessarily used to denote a primary or secondary relationship or to denote a relationship between other terms. Further, while the terms can be used in this application to identify various elements, the elements are not limited by the terms. The terms are used to distinguish one element from another. For example, a first circuit can be distinguished from a second circuit.

[0031] Further, the term "based on" is used to describe one or more factors to which determination of some element is based. This term is not exclusive, other factors can influence the determination. That is, the determination can be based on those factors alone, or based on those factors at least in part. For example, the phrase "determine A based on B" while in this case B is a factor that affects the determination of A, this phrase does not exclude determinations of A based on C. In other instances, A can be determined based on B alone.

[0032] Herein, an item of data, data item, data entry, or entry of data can be a sequence of bits. For example, a data item can comprise the contents of a file, a portion of a file, a page in a memory, an object in an object-oriented program, a digital message, a digitally scanned image, a portion of a video signal or an audio signal, metadata, or any other entity that can be represented by a sequence of bits. According to an embodiment, a data item can comprise a discrete object. According to another embodiment, a data item can comprise a unit of information within a transmission packet between two different components.

[0033] Figure 1 is a diagram for describing a clock transmitting circuit according to a first embodiment of the present disclosure.

[0034] Referring to Figure 1 The clock transmitting circuit according to the first embodiment of the present disclosure includes a first inverter 11, a second inverter 12, a first additional driver 13, and a second additional driver 14.

[0035] For example, the clock transmitting circuit is a circuit that transmits differential clock signals INCLK1 and INCLK2 to set a frequency switching within a semiconductor device. In this case, the semiconductor device refers to a single integrated circuit (IC) chip that is separated from a semiconductor wafer by a sawing process. That is, the clock transmitting circuit shown in the figure is a circuit that transmits differential clock signals INCLK1 and INCLK2 within, for example, a physically separated one semiconductor chip or semiconductor die.

[0036] In this case, the differential clock signals INCLK1 and INCLK2 include a first clock signal INCLK1 and a second clock signal INCLK2 having opposite phases. The first clock signal INCLK1 and the second clock signal INCLK2 having opposite phases can mean a first clock signal and a second clock signal having opposite logic levels. For example, in a section in which the first clock signal INCLK1 is at a logic "high" level, the second clock signal INCLK2 is at a logic "low" level. For example, in a section in which the first clock signal INCLK1 is at a logic "low" level, the second clock signal INCLK2 is at a logic "high" level.

[0037] Specifically, the clock transmitting circuit transmits the differential clock signals INCLK1 and INCLK2 in a set transmission direction OUTCLK1 and OUTCLK2, for example, a left-to-right direction in the figure.

[0038] Further, for example, the first inverter 11 inverts and drives the first transmission node TND1 in response to the first clock signal INCLK1 among the differential clock signals INCLK1 and INCLK2 loaded onto the first reception node RND1.

[0039] Further, for example, the second inverter 12 inverts and drives the second transmission node TND2 in response to the second clock signal INCLK2 among the differential clock signals INCLK1 and INCLK2 loaded onto the second reception node RND2.

[0040] Further, for example, the first additional driver 13 drives the first transmission node TND1 in response to the second clock signal INCLK2 loaded onto the second reception node RND2.

[0041] Further, for example, the second additional driver 14 drives the second transmission node TND2 in response to the first clock signal INCLK1 loaded onto the first reception node RND1.

[0042] The first clock signal INCLK1 loaded onto the first reception node RND1 drives the first transmission node TND1 through the first inverter 11 in inversion, and at the same time, drives the second transmission node TND2 through the second additional driver 14. Further, the second clock signal INCLK2 loaded onto the second reception node RND2 drives the second transmission node TND2 through the second inverter 12 in inversion, and at the same time, drives the first transmission node TND1 through the first additional driver 13.

[0043] Therefore, for example, at the first transmission node TND1, the first clock signal INCLK1 loaded onto the first reception node RND1 is driven through the first inverter 11 in inversion, and at the same time, the second clock signal INCLK2 loaded onto the second reception node RND2 can be driven through the first additional driver 13. At this time, because the first clock signal INCLK1 and the second clock signal INCLK2 are phase-reversed signals, the logic level of the first clock signal INCLK1 driven through the first inverter 11 in inversion at the first transmission node TND1 has the same logic level as the logic level of the second clock signal INCLK2 driven through the first additional driver 13 at the first transmission node TND1.

[0044] Likewise, for example, at the second transmission node TND2, the second clock signal INCLK2 loaded onto the second reception node RND2 is driven through the second inverter 12 in inversion, and at the same time, the first clock signal INCLK1 loaded onto the first reception node RND1 is driven through the second additional driver 14. At this time, because the first clock signal INCLK1 and the second clock signal INCLK2 are phase-reversed signals, the logic level of the second clock signal INCLK2 driven through the second inverter 12 in inversion at the second transmission node TND2 has the same logic level as the logic level of the first clock signal INCLK1 driven through the second additional driver 14 at the second transmission node TND2.

[0045] For example, when the first clock signal INCLK1 loaded onto the first reception node RND1 is at a logic "high" level, the second clock signal INCLK2 loaded onto the second reception node RND2 is at a logic "low" level. In this case, for example, the signal of the first transmission node TND1 is driven to a logic "low" level through the first inverter 11 and the first additional driver 13, and the signal of the second transmission node TND2 is driven to a logic "high" level through the second inverter 12 and the second additional driver 14.

[0046] In contrast, for example, when the first clock signal INCLK1 loaded on the first receiving node RND1 is at a logic "low" level, the second clock signal INCLK2 loaded on the second receiving node RND2 is at a logic "high" level. In this case, for example, the signal of the first transmitting node TND1 is driven to a logic "high" level through the first inverter 11 and the first additional driver 13, and the signal of the second transmitting node TND2 is driven to a logic "low" level through the second inverter 12 and the second additional driver 14.

[0047] The driving force of the first additional driver 13 can be smaller than the driving force of the first inverter 11. Likewise, the driving force of the second additional driver 14 can be smaller than the driving force of the second inverter 12. In this case, the driving forces of the first inverter 11 and the second inverter 12 can be the same, and the driving forces of the first additional driver 13 and the second additional driver 14 can be the same.

[0048] According to the embodiment, the driving force of each of the first inverter 11 and the second inverter 12 can be set to be multiple times, specifically 4 to 8 times, of the driving force of each of the first additional driver 13 and the second additional driver 14. For example, the driving force of the first inverter 11 and the second inverter 12 can be 4 times the driving force of each of the first additional driver 13 and the second additional driver 14. As another example, the driving force of the first inverter 11 and the second inverter 12 can be 8 times the driving force of each of the first additional driver 13 and the second additional driver 14.

[0049] As described above, the clock transmitting circuit according to the first embodiment of the present disclosure transmits the first clock signal INCLK1 (OUTCLK1) among the differential clock signals INCLK1 and INCLK2 using the first inverter 11 and the first additional driver 13, while transmitting the second clock signal INCLK2 (OUTCLK2) using the second inverter 12 and the second additional driver 14.

[0050] Thus, compared to a case where the clock transmission circuit transmits the differential clock signals INCLK1 and INCLK2 as OUTCLK1 and OUTCLK2 using only the driving forces of the first inverter 11 and the second inverter 12, the clock transmission circuit according to the first embodiment of the present disclosure is able to transmit the differential clock signals INCLK1 and INCLK2 as OUTCLK1 and OUTCLK2 with a driving force that is stronger than the driving forces of the first additional driver 13 and the second additional driver 14. In this case, transmitting the differential clock signals INCLK1 and INCLK2 with a relatively strong driving force can mean that the angle of the edge of the logic level transition of each of the differential clock signals INCLK1 and INCLK2 is aligned relatively high.

[0051] The clock transmission circuit according to the first embodiment of the present disclosure, when transmitting the differential clock signals INCLK1 and INCLK2 as OUTCLK1 and OUTCLK2, uses the driving forces of the first additional driver 13 and the second additional driver 14 and the driving forces of the first inverter 11 and the second inverter 12, and can align the angle of the edge of the logic level transition of each of the differential clock signals INCLK1 and INCLK2 such that the angle becomes relatively high. Thus, it is possible to minimize the occurrence of a duty cycle error in the process of transmitting the differential clock signals INCLK1 and INCLK2.

[0052] Figure 2 is a diagram for describing Figure 1 the first additional driver and the second additional driver among the components of the clock transmission circuit shown in

[0053] As can be seen from the use of the same reference numerals in Figure 1 Figure 2 As can be seen from the use of the same reference numerals in Figure 2 The clock transmission circuit of Figure 1 is implemented in the form of the clock transmission circuit described with reference to

[0054] Specifically, in the embodiment, the first additional driver 13 includes a first NMOS transistor N1 having a gate terminal connected to the second receiving node RND2, a drain terminal connected to the first transmission node TND1, and a source terminal connected to a node of the power supply voltage VDD.

[0055] ​Accordingly, the first additional driver 13 drives the first transmission node TND1 with the supply voltage VDD corresponding to the logic "high" level in response to the second clock signal INCLK2 among the differential clock signals INCLK1 and INCLK2 being loaded on the second reception node RND2 at the logic "high" level corresponding to the supply voltage VDD.

[0056] In this case, the time interval during which the second clock signal INCLK2 among the differential clock signals INCLK1 and INCLK2 is at the logic "high" level corresponding to the supply voltage VDD is the same as the time interval during which the first clock signal INCLK1 is at the logic "low" level corresponding to the ground voltage VSS. Accordingly, the time interval during which the first inverter 11 drives the first transmission node TND1 in an inverted manner with the supply voltage VDD corresponding to the logic "high" level can be the same time interval as the time interval during which the first additional driver 13 drives the first transmission node TND1 with the supply voltage VDD corresponding to the logic "high" level.

[0057] In particular, when the first inverter 11 drives the signal of the first transmission node TND1 from the logic "low" level to the logic "high" level in an inverted manner in response to the first clock signal INCLK1 among the differential clock signals INCLK1 and INCLK2 being at a falling edge at which the first clock signal INCLK1 transitions from the logic "high" level to the logic "low" level, the first additional driver 13 drives the signal of the first transmission node TND1 from the logic "low" level to the logic "high" level in response to a rising edge at which the second clock signal INCLK2 transitions from the logic "low" level to the logic "high" level.

[0058] Accordingly, the signal of the first transmission node TND1 can rise from the logic "low" level to the logic "high" level, for example, in the form of a combination of the driving force of the first inverter 11 and the driving force of the first additional driver 13. Accordingly, the angle of the rising edge at which the signal of the first transmission node TND1 rises from the logic "low" level to the logic "high" level can be aligned higher compared to the existing case, i.e., the case in which only the driving force of the first inverter is used.

[0059] Further, in an embodiment, the second additional driver 14 includes a second NMOS transistor N2 having a gate terminal connected to the first reception node RND1, a drain terminal connected to the second transmission node TND2, and a source terminal connected to the node of the supply voltage VDD.

[0060] Accordingly, the second additional driver 14 drives the second transmission node TND2 with the supply voltage VDD corresponding to the logic "high" level in response to the first clock signal INCLK1 among the differential clock signals INCLK1 and INCLK2 being loaded onto the first reception node RND1 at the logic "high" level corresponding to the supply voltage VDD.

[0061] In this case, the time interval during which the first clock signal INCLK1 among the differential clock signals INCLK1 and INCLK2 is at the logic "high" level corresponding to the supply voltage VDD is the same as the time interval during which the second clock signal INCLK2 is at the logic "low" level corresponding to the ground voltage VSS. Accordingly, the time interval during which the second inverter 12 drives the second transmission node TND2 inversely with the supply voltage VDD corresponding to the logic "high" level and the time interval during which the second additional driver 14 drives the second transmission node TND2 with the supply voltage VDD corresponding to the logic "high" level can be the same time interval.

[0062] In particular, when the second inverter 12 drives the signal of the second transmission node TND2 inversely from the logic "low" level to the logic "high" level in response to the falling edge at which the second clock signal INCLK2 among the differential clock signals INCLK1 and INCLK2 transitions from the logic "high" level to the logic "low" level, the second additional driver 14 drives the signal of the second transmission node TND2 from the logic "low" level to the logic "high" level in response to the rising edge at which the first clock signal INCLK1 transitions from the logic "low" level to the logic "high" level.

[0063] Accordingly, the signal of the second transmission node TND2 can rise from the logic "low" level to the logic "high" level, for example, in the form of the driving force of the second inverter 12 and the driving force of the second additional driver 14 combined. Accordingly, the angle of the rising edge at which the signal of the second transmission node TND2 rises from the logic "low" level to the logic "high" level can be aligned higher compared to the existing case, i.e., the case in which only the driving force of the second inverter is used.

[0064] Figure 3 is a view for describing Figure 1 another embodiment of the first additional driver and the second additional driver among the components of the clock transmission circuit shown in

[0065] As can be seen from the use of the same reference numerals as in Figure 1 in the description of the clock transmission circuit described with reference to Figure 3 in the description of the clock transmission circuit described with reference to Figure 3 the clock transmission circuit of Figure 1 is implemented in the form of the clock transmission circuit described with reference to

[0066] In particular, in the embodiment, the first additional driver 13 comprises a first PMOS transistor P1 having a gate terminal connected to the second receiving node RND2, a source terminal connected to the first transmitting node TND1 and a drain terminal connected to a node of the ground voltage VSS.

[0067] Therefore, the first additional driver 13 drives the first transmitting node TND1 with the ground voltage VSS corresponding to the logic “low” level in response to the second clock signal INCLK2 among the differential clock signals INCLK1 and INCLK2 being loaded on the second receiving node RND2 at the logic “low” level corresponding to the ground voltage VSS.

[0068] In this case, the time interval during which the second clock signal INCLK2 among the differential clock signals INCLK1 and INCLK2 is at the logic “low” level corresponding to the ground voltage VSS is the same as the time interval during which the first clock signal INCLK1 is at the logic “high” level corresponding to the power supply voltage VDD. Therefore, the time interval during which the first inverter 11 drives the first transmitting node TND1 inversely with the ground voltage VSS corresponding to the logic “low” level can be the same time interval as the time interval during which the first additional driver 13 drives the first transmitting node TND1 with the ground voltage VSS corresponding to the logic “low” level.

[0069] In particular, when the first inverter 11 drives the signal of the first transmitting node TND1 inversely from the logic “high” level to the logic “low” level in response to the rising edge at which the first clock signal INCLK1 among the differential clock signals INCLK1 and INCLK2 transitions from the logic “low” level to the logic “high” level, the first additional driver 13 drives the signal of the first transmitting node TND1 from the logic “high” level to the logic “low” level in response to the falling edge at which the second clock signal INCLK2 transitions from the logic “high” level to the logic “low” level.

[0070] Therefore, the signal of the first transmitting node TND1 can fall from the logic “high” level to the logic “low” level, for example, in the form of the driving force of the first inverter 11 combined with the driving force of the first additional driver 13. Therefore, the angle of the falling edge at which the signal of the first transmitting node TND1 falls from the logic “high” level to the logic “low” level can be aligned higher compared to the existing case, i.e., the case in which only the driving force of the first inverter is used.

[0071] Further, in the embodiment, the second additional driver 14 includes a second PMOS transistor P2 having a gate terminal connected to the first receiving node RND1, a source terminal connected to the second transmitting node TND2, and a drain terminal connected to a node of the ground voltage VSS.

[0072] Accordingly, the second additional driver 14 drives the second transmitting node TND2 with the ground voltage VSS corresponding to the logic "low" level in response to the first clock signal INCLK1 among the differential clock signals INCLK1 and INCLK2 being loaded on the first receiving node RND1 at the logic "low" level corresponding to the ground voltage VSS.

[0073] In this case, the time interval during which the first clock signal INCLK1 among the differential clock signals INCLK1 and INCLK2 is at the logic "low" level corresponding to the ground voltage VSS is identical to the time interval during which the second clock signal INCLK2 is at the logic "high" level corresponding to the power supply voltage VDD. Accordingly, the time interval during which the second inverter 12 drives the second transmitting node TND2 inversely with the ground voltage VSS corresponding to the logic "low" level can be identical to the time interval during which the second additional driver 14 drives the second transmitting node TND2 with the ground voltage VSS corresponding to the logic "low" level.

[0074] In particular, when the second inverter 12 drives the signal of the second transmitting node TND2 inversely from the logic "high" level to the logic "low" level in response to a rising edge at which the second clock signal INCLK2 among the differential clock signals INCLK1 and INCLK2 transitions from the logic "low" level to the logic "high" level, the second additional driver 14 drives the second transmitting node TND2 from the logic "high" level to the logic "low" level in response to a falling edge at which the first clock signal INCLK1 transitions from the logic "high" level to the logic "low" level.

[0075] Accordingly, the signal of the second transmitting node TND2 can fall from the logic "high" level to the logic "low" level, for example, in the form of a combination of the driving force of the second inverter 12 and the driving force of the second additional driver 14. Accordingly, the angle of the falling edge at which the signal of the second transmitting node TND2 falls from the logic "high" level to the logic "low" level can be aligned higher compared to the existing case, i.e., the case in which only the driving force of the second inverter is used.

[0076] Figure 4 is a diagram for describing Figure 1 a further embodiment of the first additional driver and the second additional driver among the components of the clock transmitting circuit shown in

[0077] As is apparent from the use of the same reference characters in Figure 1 the drawings, Figure 4 as can be seen, Figure 4 the clock transmission circuit of the first additional driver 13 has a further example of the circuit of the first additional driver 13 and the second additional driver 14 is implemented in the form of the clock transmission circuit described with reference to Figure 1 .

[0078] Specifically, in the embodiment, the first additional driver 13 includes a third NMOS transistor N3 whose gate terminal is connected to the second reception node RND2, whose drain terminal is connected to the first transmission node TND1, and whose source terminal is connected to the first intermediate node MN1, and a fourth NMOS transistor N4 whose gate terminal and source terminal are connected to the node of the power supply voltage VDD, and whose drain terminal is connected to the first intermediate node MN1.

[0079] In this case, the third NMOS transistor N3 included in the first additional driver 13 corresponds to, for example, the first NMOS transistor N1 included in the first additional driver 13 described with reference to Figure 2 . That is, Figure 4 the first additional driver 13 disclosed in the embodiment can be considered to have the form in which the fourth NMOS transistor N4 is further connected between the source terminal of the first NMOS transistor N1 included in the first additional driver 13 described with reference to Figure 2 and the node of the power supply voltage VDD.

[0080] In this case, the fourth NMOS transistor N4 included in the first additional driver 13 has a gate terminal and a source terminal connected to the node of the power supply voltage VDD, and functions as a diode, for example. Therefore, the size of the standby current consumed during the operation of the first additional driver 13 can be minimized.

[0081] Figure 4 The operation of the first additional driver 13 disclosed in the embodiment is substantially the same as the operation of the first additional driver 13 described with reference to Figure 2 . However, compared with the first additional driver 13 described with reference to Figure 2 , Figure 4 the first additional driver 13 disclosed in the embodiment is in a state in which the internal circuit is configured to, for example, minimize the size of the standby current consumed, that is, the size of the current leaked due to the presence of the first additional driver 13, compared with the first additional driver 13 described with reference to Figure 2 .

[0082] Therefore, Figure 4The first additional driver 13 disclosed in the embodiment drives the first transmitting node TND1 with the power supply voltage VDD corresponding to the logic “high” level in response to the second clock signal INCLK2 loaded onto the second receiving node RND2 among the differential clock signals INCLK1 and INCLK2 being at a logic “high” level corresponding to the power supply voltage VDD.

[0083] Therefore, the signal of the first transmission node TND1 can rise from a logic “low” level to a logic “high” level, for example, in the form of a combination of the driving force of the first inverter 11 and the driving force of the first additional driver 13. Therefore, compared with the existing case (i.e., the case of using only the driving force of the first inverter), the angle of the rising edge of the signal of the first transmission node TND1 rising from a logic “low” level to a logic “high” level can be aligned higher.

[0084] Furthermore, in an embodiment, the second additional driver 14 includes a fifth NMOS transistor N5 having a gate terminal connected to the first reception node RND1, a drain terminal connected to the second transmission node TND2, and a source terminal connected to the second intermediate node MN2, and a sixth NMOS transistor N6 having a gate terminal and a source terminal connected to a node of the power supply voltage VDD, and a drain terminal connected to the second intermediate node MN2.

[0085] In this case, the fifth NMOS transistor N5 included in the second additional driver 14 corresponds to, for example, the reference Figure 2 The second additional driver 14 includes a second NMOS transistor N2. That is, Figure 4 The second additional driver 14 disclosed in the embodiment can be considered to have the following form: the sixth NMOS transistor N6 is further connected to the reference Figure 2 Between the source terminal of the second NMOS transistor N2 included in the depicted second additional driver 14 and the node of the power supply voltage VDD.

[0086] In this case, the sixth NMOS transistor N6 included in the second additional driver 14 has a gate terminal and a source terminal connected to a node of the power supply voltage VDD and functions as a diode, for example. Therefore, the amount of standby current consumed during operation of the second additional driver 14 can be minimized.

[0087] Figure 4 The operation of the second additional driver 14 disclosed in Figure 2 The operation of the second additional drive 14 described is essentially the same. However, Figure 4 The second additional driver 14 disclosed in the following state; the internal circuit is constructed as shown in FIG. Figure 2The size of the standby current consumed by the second additional driver 14 described, that is, the size of the current leaked due to the presence of the second additional driver 14, can be minimized.

[0088] Therefore, Figure 4 The second additional driver 14 disclosed in the present embodiment drives the second transmission node TND2 with the power supply voltage VDD corresponding to the logic "high" level in response to the first clock signal INCLK1 among the differential clock signals INCLK1 and INCLK2 being loaded onto the first reception node RND1 being at the logic "high" level corresponding to the power supply voltage VDD.

[0089] Therefore, the signal of the second transmission node TND2 can rise from the logic "low" level to the logic "high" level, for example, in the form of the driving force of the second inverter 12 and the driving force of the second additional driver 14 being combined. Therefore, the rising edge of the signal of the second transmission node TND2 rising from the logic "low" level to the logic "high" level can be aligned higher compared to the existing case, that is, the case where only the driving force of the second inverter is used.

[0090] Figure 2 is a diagram for describing Figure 4 Another embodiment of the first additional driver and the second additional driver among the components of the clock transmission circuit shown in the present embodiment.

[0091] As can be seen from the use of the same reference numerals as in Figure 2 in the present embodiment, Figure 4 As can be seen from the use of the same reference numerals as in Figure 5 the clock transmission circuit of the present embodiment has another example of the circuit of the first additional driver 13 and the second additional driver 14 implemented in the form of the clock transmission circuit described with reference to Figure 1 in the present embodiment.

[0092] Specifically, in the embodiment, the first additional driver 13 includes a third PMOS transistor P3 having a gate terminal connected to the second reception node RND2, a source terminal connected to the first transmission node TND1, and a drain terminal connected to a third intermediate node MN3, and a fourth PMOS transistor P4 having a gate terminal and a drain terminal connected to a node of the ground voltage VSS, and a source terminal connected to the third intermediate node MN3.

[0093] In this case, the third PMOS transistor P3 included in the first additional driver 13 corresponds to, for example, the first PMOS transistor P1 included in the first additional driver 13 described with reference to Figure 1 in the present embodiment. That is, Figure 5The first additional driver 13 disclosed in the embodiment can be considered to have the following form: the fourth PMOS transistor P4 is further connected to the reference Figure 5 Between the drain terminal of the first PMOS transistor P1 included in the described first additional driver 13 and a node of the ground voltage VSS.

[0094] In this case, the fourth PMOS transistor P4 included in the first additional driver 13 has a gate terminal and a drain terminal connected to a node of the ground voltage VSS and functions as a diode, for example. Therefore, the amount of standby current consumed during operation of the first additional driver 13 can be minimized.

[0095] Figure 1 The operation of the first additional driver 13 disclosed in Figure 3 The operation of the first additional driver 13 is essentially the same as described. However, Figure 5 The first additional driver 13 disclosed in the embodiment is in the following state: the internal circuit is constructed as shown in FIG. Figure 3 The magnitude of the standby current consumed by the described first additional driver 13 , ie, the magnitude of the current leaked due to the presence of the first additional driver 13 , can be minimized.

[0096] therefore, Figure 5 The first additional driver 13 disclosed in the embodiment drives the first transmitting node TND1 with the ground voltage VSS corresponding to the logic “low” level in response to the second clock signal INCLK2 loaded on the second receiving node RND2 among the differential clock signals INCLK1 and INCLK2 being at a logic “low” level corresponding to the ground voltage VSS.

[0097] Therefore, the signal of the first transmission node TND1 can fall from a logic “high” level to a logic “low” level, for example, in the form of a combination of the driving force of the first inverter 11 and the driving force of the first additional driver 13. Therefore, compared with the existing case (i.e., the case of using only the driving force of the first inverter), the angle of the falling edge of the signal of the first transmission node TND1 falling from a logic “high” level to a logic “low” level can be aligned higher.

[0098] Furthermore, in an embodiment, the second additional driver 14 includes: a fifth PMOS transistor P5 having a gate terminal connected to the first reception node RND1, a source terminal connected to the second transmission node TND2, and a drain terminal connected to the fourth intermediate node MN4; and a sixth PMOS transistor P6 having a gate terminal and a drain terminal connected to a node of the ground voltage VSS, and a source terminal connected to the fourth intermediate node MN4.

[0099] In this case, the fifth PMOS transistor P5 included in the second additional driver 14 corresponds to, for example, the second PMOS transistor P2 described with reference to Figure 3 the second additional driver 14 described with reference to Figure 5 the second additional driver 14 described with reference to Figure 3 the second additional driver 14 described with reference to

[0100] In this case, the sixth PMOS transistor P6 included in the second additional driver 14 has a gate terminal and a drain terminal connected to a node of the ground voltage VSS, and functions as a diode, for example. Thus, the size of the standby current consumed during the operation of the second additional driver 14 can be minimized.

[0101] Figure 5 the second additional driver 14 described with reference to Figure 3 the second additional driver 14 described with reference to Figure 5 the second additional driver 14 described with reference to Figure 3 the second additional driver 14 described with reference to

[0102] Thus, Figure 5 the second additional driver 14 described with reference to

[0103] Thus, the signal of the second transmission node TND2 can fall from the logic "high" level to the logic "low" level in the form in which the driving force of the second inverter 12 and the driving force of the second additional driver 14 are combined, for example. Thus, the angle of the falling edge in which the second transmission node TND2 falls from the logic "high" level to the logic "low" level can be aligned higher compared to the existing case (i.e., the case in which only the driving force of the second inverter is used).

[0104] Figure 3 is a diagram for describing Figure 5 another embodiment of the first additional driver and the second additional driver among the components of the clock transmission circuit shown in

[0105] As is apparent from the use of the same reference characters, the first additional driver and the second additional driver described with reference toFigure 3 like parts are marked with like reference numerals throughout the various Figure 5 As can be seen in Figure 6 The clock transmission circuit of Fig. 1 1 has a further example of a circuit with a first additional driver 13 and a second additional driver 14 implemented in the form of the clock transmission circuit described with reference to Figure 1 Fig. 1 1.

[0106] In particular, in the embodiment, the first additional driver 13 comprises a seventh NMOS transistor N7 having a gate terminal connected to the second receiving node RND2, a drain terminal connected to the first transmitting node TND1, and a source terminal connected to a node of the supply voltage VDD, and a seventh PMOS transistor P7 having a gate terminal connected to the second receiving node RND2, a source terminal connected to the first transmitting node TND1, and a drain terminal connected to a node of the ground voltage VSS.

[0107] Thus, the first additional driver 13 drives the first transmitting node TND1 with the supply voltage VDD corresponding to a logic "high" level in response to the second clock signal INCLK2 of the differential clock signals INCLK1 and INCLK2 being loaded onto the second receiving node RND2 at the logic "high" level corresponding to the supply voltage VDD. Furthermore, the first additional driver 13 drives the first transmitting node TND1 with the ground voltage VSS corresponding to a logic "low" level in response to the second clock signal INCLK2 of the differential clock signals INCLK1 and INCLK2 being loaded onto the second receiving node RND2 at the logic "low" level corresponding to the ground voltage VSS.

[0108] In this case, the second clock signal INCLK2 among the differential clock signals INCLK1 and INCLK2 is at a time interval of the logic "high" level corresponding to the power supply voltage VDD the same as a time interval of the first clock signal INCLK1 at the logic "low" level corresponding to the ground voltage VSS. Therefore, the time interval in which the first inverter 11 inversely drives the first transmission node TND1 with the power supply voltage VDD corresponding to the logic "high" level can be the same time interval as the time interval in which the first additional driver 13 drives the first transmission node TND1 with the power supply voltage VDD corresponding to the logic "high" level. Further, the second clock signal INCLK2 among the differential clock signals INCLK1 and INCLK2 is at a time interval of the logic "low" level corresponding to the ground voltage VSS the same as a time interval of the first clock signal INCLK1 at the logic "high" level corresponding to the power supply voltage VDD. Therefore, the time interval in which the first inverter 11 inversely drives the first transmission node TND1 with the ground voltage VSS corresponding to the logic "low" level can be the same time interval as the time interval in which the first additional driver 13 drives the first transmission node TND1 with the ground voltage VSS corresponding to the logic "low" level.

[0109] In particular, when the first inverter 11 inversely drives the signal of the first transmission node TND1 from the logic "low" level to the logic "high" level in response to a falling edge at which the first clock signal INCLK1 among the differential clock signals INCLK1 and INCLK2 transitions from the logic "high" level to the logic "low" level, the first additional driver 13 drives the signal of the first transmission node TND1 from the logic "low" level to the logic "high" level in response to a rising edge at which the second clock signal INCLK2 transitions from the logic "low" level to the logic "high" level. Further, when the first inverter 11 inversely drives the signal of the first transmission node TND1 from the logic "high" level to the logic "low" level in response to a rising edge at which the first clock signal INCLK1 among the differential clock signals INCLK1 and INCLK2 transitions from the logic "low" level to the logic "high" level, the first additional driver 13 drives the signal of the first transmission node TND1 from the logic "high" level to the logic "low" level in response to a falling edge at which the second clock signal INCLK2 transitions from the logic "high" level to the logic "low" level.

[0110] Thus, the signal of the first transmission node TND1 can rise from a logic "low" level to a logic "high" level or fall from a logic "high" level to a logic "low" level, for example, in the form of a combination of the drive force of the first inverter 11 and the drive force of the first additional driver 13. Thus, the angle of the rising edge of the first transmission node TND1 rising from a logic "low" level to a logic "high" level and the angle of the falling edge of the first transmission node TND1 falling from a logic "high" level to a logic "low" level can be aligned higher compared to the existing case, i.e. the case of using only the drive force of the first inverter.

[0111] Specifically, in the embodiment, the second additional driver 14 includes an eighth NMOS transistor N8 whose gate terminal is connected to the first reception node RND1, whose drain terminal is connected to the second transmission node TND2, and whose source terminal is connected to a node of the power supply voltage VDD, and an eighth PMOS transistor P8 whose gate terminal is connected to the first reception node RND1, whose source terminal is connected to the second transmission node TND2, and whose drain terminal is connected to a node of the ground voltage VSS.

[0112] Thus, the second additional driver 14 drives the second transmission node TND2 with the power supply voltage VDD corresponding to a logic "high" level in response to the first clock signal INCLK1 among the differential clock signals INCLK1 and INCLK2 being loaded on the first reception node RND1 at the logic "high" level corresponding to the power supply voltage VDD. Further, the second additional driver 14 drives the second transmission node TND2 with the ground voltage VSS corresponding to a logic "low" level in response to the first clock signal INCLK1 among the differential clock signals INCLK1 and INCLK2 being loaded on the first reception node RND1 at the logic "low" level corresponding to the ground voltage VSS.

[0113] In this case, the first clock signal INCLK1 among the differential clock signals INCLK1 and INCLK2 is at a time interval of a logic "high" level corresponding to the power supply voltage VDD the same as a time interval of a logic "low" level corresponding to the ground voltage VSS of the second clock signal INCLK2. Therefore, the time interval in which the second inverter 12 inversely drives the second transmission node TND2 with the power supply voltage VDD corresponding to the logic "high" level can be the same time interval as the time interval in which the second additional driver 14 drives the second transmission node TND2 with the power supply voltage VDD corresponding to the logic "high" level. Also, the first clock signal INCLK1 among the differential clock signals INCLK1 and INCLK2 is at a time interval of a logic "low" level corresponding to the ground voltage VSS the same as a time interval of a logic "high" level corresponding to the power supply voltage VDD of the second clock signal INCLK2. Therefore, the time interval in which the second inverter 12 inversely drives the second transmission node TND2 with the ground voltage VSS corresponding to the logic "low" level can be the same time interval as the time interval in which the second additional driver 14 drives the second transmission node TND2 with the ground voltage VSS corresponding to the logic "low" level.

[0114] In particular, when the second inverter 12 inversely drives a signal of the second transmission node TND2 from a logic "low" level to a logic "high" level in response to a falling edge at which the second clock signal INCLK2 among the differential clock signals INCLK1 and INCLK2 transitions from a logic "high" level to a logic "low" level, the second additional driver 14 drives a signal of the second transmission node TND2 from a logic "low" level to a logic "high" level in response to a rising edge at which the first clock signal INCLK1 transitions from a logic "low" level to a logic "high" level. Also, when the second inverter 12 inversely drives a signal of the second transmission node TND2 from a logic "high" level to a logic "low" level in response to a rising edge at which the second clock signal INCLK2 among the differential clock signals INCLK1 and INCLK2 transitions from a logic "low" level to a logic "high" level, the second additional driver 14 drives a signal of the second transmission node TND2 from a logic "high" level to a logic "low" level in response to a falling edge at which the first clock signal INCLK1 transitions from a logic "high" level to a logic "low" level.

[0115] Thus, the signal of the second transmission node TND2 can rise from a logic "low" level to a logic "high" level or fall from a logic "high" level to a logic "low" level, for example, in the form of a combination of the drive force of the second inverter 12 and the drive force of the second additional driver 14. Thus, the angle of the rising edge of the signal of the second transmission node TND2 rising from a logic "low" level to a logic "high" level and the angle of the falling edge of the signal of the second transmission node TND2 falling from a logic "high" level to a logic "low" level can be aligned higher compared to the existing case, i.e. the case where only the drive force of the second inverter is used.

[0116] Figure 1 is a diagram for describing Figure 6 a further embodiment of the first additional driver and the second additional driver among the components of the clock transmission circuit shown in

[0117] As can be seen from the use of the same reference signs as in Figure 6 , the clock transmission circuit of Figure 1 , the clock transmission circuit of Figure 7 has a further example of the circuit of the first additional driver 13 and the second additional driver 14 implemented in the form of the clock transmission circuit described with reference to Figure 1 .

[0118] In particular, in the embodiment, the first additional driver 13 includes a ninth NMOS transistor N9 whose gate terminal is connected to the second reception node RND2, whose drain terminal is connected to the first transmission node TND1, and whose source terminal is connected to a fifth intermediate node MN5, a tenth NMOS transistor N10 whose gate terminal and source terminal are connected to a node of the power supply voltage VDD, and whose drain terminal is connected to the fifth intermediate node MN5, a ninth PMOS transistor P9 whose gate terminal is connected to the second reception node RND2, whose source terminal is connected to the first transmission node TND1, and whose drain terminal is connected to a sixth intermediate node MN6, and a tenth PMOS transistor P10 whose gate terminal and drain terminal are connected to a node of the ground voltage VSS, and whose source terminal is connected to the sixth intermediate node MN6.

[0119] In this case, the ninth NMOS transistor N9 and the ninth PMOS transistor P9 included in the first additional driver 13 respectively correspond to, for example, the seventh NMOS transistor N7 and the seventh PMOS transistor P7 included in the first additional driver 13 described with reference to Figure 1 . That is, the first additional driver 13 disclosed in Figure 7 may be considered to have the following form: the tenth NMOS transistor N10 is further connected in series to the seventh NMOS transistor N7 described with reference toFigure 7 The node between the source terminal of the seventh NMOS transistor N7 included in the first additional driver 13 and the power supply voltage VDD, and the tenth PMOS transistor P10 is further connected between the node between the drain terminal of the seventh PMOS transistor P7 included in the first additional driver 13 and the ground voltage VSS. Figure 1 The node between the source terminal of the seventh NMOS transistor N7 included in the first additional driver 13 and the power supply voltage VDD, and the tenth PMOS transistor P10 is further connected between the node between the drain terminal of the seventh PMOS transistor P7 included in the first additional driver 13 and the ground voltage VSS.

[0120] In this case, the tenth NMOS transistor N10 included in the first additional driver 13 has a gate terminal and a source terminal connected to a node of the power supply voltage VDD, and functions as a diode, for example. Further, the tenth PMOS transistor P10 included in the first additional driver 13 has a gate terminal and a drain terminal connected to a node of the ground voltage VSS, and functions as a diode, for example. Thus, the size of the standby current consumed during the operation of the first additional driver 13 can be minimized.

[0121] Figure 6 The operation of the first additional driver 13 disclosed in PTL 1 is substantially the same as that of the first additional driver 13 described with reference to Figure 7 The operation of the first additional driver 13 described with reference to PTL 1 is substantially the same as that of the first additional driver 13 described with reference to Figure 6 The first additional driver 13 disclosed in PTL 1 is in a state where the internal circuit is configured to, for example, be substantially the same as that described with reference to PTL 1. Figure 6 The size of the standby current consumed by the first additional driver 13 described with reference to PTL 1, that is, the size of the current leaked due to the presence of the first additional driver 13 can be minimized compared to the first additional driver 13 described with reference to PTL 1.

[0122] Thus, Figure 7 The first additional driver 13 illustrated in FIG. 1 drives the first transmission node TND1 with the power supply voltage VDD corresponding to the logic "high" level in response to the second clock signal INCLK2 loaded on the second reception node RND2 among the differential clock signals INCLK1 and INCLK2 being at the logic "high" level corresponding to the power supply voltage VDD, and drives the first transmission node TND1 with the ground voltage VSS corresponding to the logic "low" level in response to the second clock signal INCLK2 loaded on the second reception node RND2 among the differential clock signals INCLK1 and INCLK2 being at the logic "low" level corresponding to the ground voltage VSS.

[0123] Thus, the signal of the first transmission node TND1 can rise from a logic "low" level to a logic "high" level or fall from a logic "high" level to a logic "low" level, for example, in the form of a combination of the drive force of the first inverter 11 and the drive force of the first additional driver 13. Thus, the angle of the rising edge of the signal of the first transmission node TND1 rising from a logic "low" level to a logic "high" level and the angle of the falling edge of the signal of the first transmission node TND1 falling from a logic "high" level to a logic "low" level can be aligned higher compared to the existing case, i.e., the case where only the drive force of the first inverter is used.

[0124] Further, in the embodiment, the second additional driver 14 includes an eleventh NMOS transistor N11 whose gate terminal is connected to the first reception node RND1, whose drain terminal is connected to the second transmission node TND2, and whose source terminal is connected to the seventh intermediate node MN7, a twelfth NMOS transistor N12 whose gate terminal and source terminal are connected to a node of the power supply voltage VDD, and whose drain terminal is connected to the seventh intermediate node MN7, an eleventh PMOS transistor P11 whose gate terminal is connected to the first reception node RND1, whose source terminal is connected to the second transmission node TND2, and whose drain terminal is connected to the eighth intermediate node MN8, and a twelfth PMOS transistor P12 whose gate terminal and drain terminal are connected to a node of the ground voltage VSS, and whose source terminal is connected to the eighth intermediate node MN8.

[0125] In this case, the eleventh NMOS transistor N11 and the eleventh PMOS transistor P11 included in the second additional driver 14 respectively correspond to, for example, the eighth NMOS transistor N8 and the eighth PMOS transistor P8 included in the second additional driver 14 described with reference to Figure 6 That is, the second additional driver 14 described with reference to Figure 7 may be considered to have the following form: the twelfth NMOS transistor N12 is further connected between the source terminal of the eighth NMOS transistor N8 included in the second additional driver 14 described with reference to Figure 6 and the node of the power supply voltage VDD, and the twelfth PMOS transistor P12 is further connected between the drain terminal of the eighth PMOS transistor P8 included in the second additional driver 14 described with reference to Figure 7 and the node of the ground voltage VSS.

[0126] In this case, the twelfth NMOS transistor N12 included in the second additional driver 14 has a gate terminal and a source terminal connected to a node of the power supply voltage VDD, and functions as a diode, for example. Further, the twelfth PMOS transistor P12 included in the second additional driver 14 has a gate terminal and a drain terminal connected to a node of the ground voltage VSS, and functions as a diode, for example. Thus, the size of the standby current consumed during the operation of the second additional driver 14 can be minimized.

[0127] Figure 6 The operation of the second additional driver 14 disclosed in the second embodiment is substantially the same as the operation of the second additional driver 14 described with reference to Figure 7 However, in the second additional driver 14 disclosed in the second embodiment, Figure 6 the size of the standby current consumed, i.e., the size of the current leaked due to the presence of the second additional driver 14, can be minimized compared to the second additional driver 14 described with reference to Figure 6

[0128] Thus, in the second additional driver 14 illustrated in FIG. 6, Figure 7 the first clock signal INCLK1 among the differential clock signals INCLK1 and INCLK2 loaded on the first reception node RND1 is at a logic “high” level corresponding to the power supply voltage VDD, the first transmission node TND2 is driven with the power supply voltage VDD corresponding to the logic “high” level, and the first clock signal INCLK1 among the differential clock signals INCLK1 and INCLK2 loaded on the first reception node RND1 is at a logic “low” level corresponding to the ground voltage VSS, the first transmission node TND2 is driven with the ground voltage VSS corresponding to the logic “low” level.

[0129] Thus, the signal of the second transmission node TND2 can rise from the logic “low” level to the logic “high” level or fall from the logic “high” level to the logic “low” level in a form in which the driving force of the first inverter 11 and the driving force of the second additional driver 14 are combined. Thus, the angle of the rising edge at which the signal of the second transmission node TND2 rises from the logic “low” level to the logic “high” level and the angle of the falling edge at which the signal of the second transmission node TND2 falls from the logic “high” level to the logic “low” level can be aligned higher compared to the existing case, i.e., the case in which only the driving force of the second inverter is used.

[0130] Figure 6 is a diagram for describing a clock transmission circuit according to a second embodiment of the present disclosure.

[0131] Referring to Figure 7 ​The clock transmission circuit according to the second embodiment of the present disclosure includes a first transmission circuit T1, a second transmission circuit T2, N first additional drivers 83<1:2>, and N second additional drivers 84<1:2>. In this case, N can be a natural number equal to or greater than 1.

[0132] In this case, for example, as described with reference to Figure 6 The clock transmission circuit is a circuit that transmits the differential clock signals INCLK1 and INCLK2 within the semiconductor device to set the frequency switching.

[0133] Therefore, the differential clock signals INCLK1 and INCLK2 include the first clock signal INCLK1 and the second clock signal INCLK2 having opposite phases.

[0134] Further, the first transmission circuit T1 transmits the first clock signal INCLK1 among the differential clock signals INCLK1 and INCLK2 by the plurality of first inverters 81<1:4> connected in a chain form, that is, in series. That is, the first transmission circuit T1 transmits the first clock signal INCLK1 in a case where the first clock signal INCLK1 is repeatedly inverted and driven a plurality of times by the plurality of first inverters 81<1:4> connected in a chain form. In this case, the plurality of first inverters 81<1:4> include input nodes I1<1:4> and output nodes O1<1:4>, respectively. Signals transmitted to the input nodes I1<1:2> are inverted and driven to the output nodes O1<1:2>, respectively.

[0135] Further, the second transmission circuit T2 transmits the second clock signal INCLK2 among the differential clock signals INCLK1 and INCLK2 by the plurality of second inverters 82<1:4> connected in a chain form and corresponding to the plurality of first inverters 81<1:4>, respectively. That is, the second transmission circuit T2 transmits the second clock signal INCLK2 in a case where the second clock signal INCLK2 is repeatedly inverted and driven a plurality of times by the plurality of second inverters 82<1:4> connected in a chain form. In this case, the plurality of second inverters 82<1:4> include input nodes I2<1:4> and output nodes O2<1:4>, respectively. Signals transmitted to the input nodes I2<1:2> are inverted and driven to the output nodes O2<1:2>, respectively.

[0136] Further, the plurality of first inverters 81<1:4> included in the first transmission circuit T1 and the plurality of second inverters 82<1:4> included in the second transmission circuit T2 can be disposed in a form in which the plurality of first inverters 81<1:4> and the plurality of second inverters 82<1:4> correspond to each other.

[0137] For example, asFigure 7 As shown, if the first transmission circuit T1 includes four first inverters 81<1:4> connected in a chain, the second transmission circuit T2 can include four second inverters 82<1:4> connected in a chain and corresponding to the four first inverters 81<1:4>, respectively.

[0138] That is, the first inverter 81<1> among the plurality of first inverters 81<1:4> and the first inverter 82<1> among the plurality of second inverters 82<1:4> can be considered to be disposed in a mutually corresponding manner. Likewise, the second inverter 81<2> among the plurality of first inverters 81<1:4> and the second inverter 82<2> among the plurality of second inverters 82<1:4> can be considered to be disposed in a mutually corresponding manner. Further, the third inverter 81<3> among the plurality of first inverters 81<1:4> and the third inverter 82<3> among the plurality of second inverters 82<1:4> can be considered to be disposed in a mutually corresponding manner. Further, the fourth inverter 81<4> among the plurality of first inverters 81<1:4> and the fourth inverter 82<4> among the plurality of second inverters 82<1:4> can be considered to be disposed in a mutually corresponding manner.

[0139] For reference, unlike in the figure, for example, the first transmission circuit T1 includes first inverters 81<1:4> in a number greater than or less than 4, and the second transmission circuit T2 also includes second inverters 82<1:4> in a number greater than or less than 4 in a form in which the second inverters 82<1:4> correspond to the first inverters 81<1:4>. In the subsequent description, the first transmission circuit T1 includes four first inverters 81<1:4>, and the second transmission circuit T2 includes four second inverters 82<1:4> in a form in which the second inverters 82<1:4> correspond to the first inverters 81<1:4>.

[0140] Further, for example, N first additional drivers 83<1:2> drive output nodes O1<1:2> of N second selected inverters 81<1:2> among the plurality of first inverters 81<1:4> corresponding to the N first selected inverters 82<1:2> among the plurality of second inverters 82<1:4>, respectively, in response to signals loaded on different input nodes I2<1:2> of the N first selected inverters 82<1:2>.

[0141] Further, N second additional drivers 84<1:2> drive output nodes O2<1:2> of the N first selected inverters 82<1:2>, respectively, in response to signals loaded on different input nodes I1<1:2> of the N second selected inverters 81<1:2>, for example.

[0142] In this case, for example, the N first additional drivers 83<1:2> and the second additional drivers 84<1:2> are provided in a form in which the N first additional drivers 83<1:2> and the second additional drivers 84<1:2> correspond to only the N first selected inverters 82<1:2> and the second selected inverters 81<1:2>, respectively, that is, to some of the plurality of first inverters 81<1:4> and the second inverters 82<1:4>.

[0143] According to an embodiment, only each of the first and second inverters 82<1:2> among the plurality of second inverters 82<1:4> can be divided (that is, determined) as one of the N first selected inverters 82<1:2>, and the remaining third and fourth selected inverters 82<3:4> can not be divided as a "first selected inverter". Likewise, only each of the first and second inverters 81<1:2> among the plurality of first inverters 81<1:4> can be divided as one of the N second selected inverters 81<1:2>, and the remaining third and fourth selected inverters 81<3:4> can not be divided as a "second selected inverter".

[0144] More specifically, for example, among the plurality of first inverters 81<1:4> and the second inverters 82<1:4>, when the driving force of one of the first inverters 81<1:3> and the second inverters 82<2:4> that is later in order is greater than the driving force of one of the first inverters 81<1:3> and the second inverters 82<1:3> that is earlier in order, one of the first inverter 81<1:3> and the second inverter 82<1:3> that is earlier in order is divided as one of the N second selected inverters and the first selected inverters.

[0145] Further, for example, among the plurality of first inverters 81<1:4> and the second inverters 82<1:4>, when the driving force of one of the first inverters 81<1:3> and the second inverters 82<2:4> that is later in order is greater than the driving force of one of the first inverters 81<1:3> and the second inverters 82<1:3> that is earlier in order, one of the first inverters 81<2:4> and the second inverters 82<2:4> that is later in order is divided as one of the N second selected inverters and the first selected inverters.

[0146] Although the driving force of one of the first inverters 81 <1:3> and the second inverters 82 <2:4> that are later in order is greater than the driving force of one of the first inverters 81 <1:3> and the second inverters 82 <1:3> that are earlier in order, only some of the first inverters 81 <1:3> and the second inverters 82 <1:3> that are earlier in order can be divided into the "second selected inverter and the first selected inverter", and the rest can not be divided into the "second selected inverter and the first selected inverter". Likewise, only some of the first inverters 81 <2:4> and the second inverters 82 <2:4> that are later in order can be divided into the "second selected inverter and the first selected inverter", and the rest can not be divided into the "second selected inverter and the first selected inverter". That is, which of the plurality of first inverters 81 <1:4> and the second inverters 82 <1:4> is divided into the "second selected inverter and the first selected inverter" can differ according to the choice of design.

[0147] According to an embodiment, when the driving force of the 2nd first inverter 81 <2> and the 2nd second inverter 82 <2> among the plurality of first inverters 81 <1:4> and the second inverters 82 <1:4> is greater than the driving force of the 1st first inverter 81 <1> and the 1st second inverter 82 <1>, the 1st first inverter 81 <1> can be divided into the 1st second selected inverter 81 <1>, and the 1st second inverter 82 <1> can be divided into the 1st first selected inverter 82 <1>. For example, the driving force of the 1st first inverter 81 <1> and the 1st second inverter 82 <1> is 2 / 3 of the driving force of the 2nd first inverter 81 <2> and the 2nd second inverter 82 <2>.

[0148] According to another embodiment, when the driving force of the 3rd first inverter 81 <3> and the 3rd second inverter 82 <3> among the plurality of first inverters 81 <1:4> and the second inverters 82 <1:4> is greater than the driving force of the 2nd first inverter 81 <2> and the 2nd second inverter 82 <2>, the 2nd first inverter 81 <2> can be divided into the 2nd second selected inverter 81 <2>, and the 2nd second inverter 82 <2> can be divided into the 2nd first selected inverter 82 <1>. For example, the driving force of the 2nd first inverter 81 <2> and the 2nd second inverter 82 <2> is 2 / 3 of the driving force of the 3rd first inverter 81 <3> and the 3rd second inverter 82 <3>, respectively.

[0149] Further, the clock transmission circuit according to the second embodiment of the present disclosure further includes the third inverter 85 and the fourth inverter 86 under a certain condition in addition to the first transmission circuit T1, the second transmission circuit T2, the N first additional drivers 83<1:2>, and the N second additional drivers 84<1:2>. Further, for example, the clock transmission circuit according to the second embodiment of the present disclosure includes only the first transmission circuit T1, the second transmission circuit T2, the N first additional drivers 83<1:2>, and the N second additional drivers 84<1:2> without including the third inverter 85 and the fourth inverter 86 when the certain condition is not satisfied. Further, for example, the clock transmission circuit according to the second embodiment of the present disclosure further includes the third inverter 85 and the fourth inverter 86, and the first transmission circuit T1, the second transmission circuit T2, the N first additional drivers 83<1:2>, and the N second additional drivers 84<1:2> regardless of whether the certain condition is satisfied. That is, whether the third inverter 85 and the fourth inverter 86 are included in addition to the first transmission circuit T1, the second transmission circuit T2, the N first additional drivers 83<1:2>, and the N second additional drivers 84<1:2> can be different according to the choice of design.

[0150] In this case, the certain condition is a case where the driving force of one of the first inverter 81<1:3> and the second inverter 82<1:3> that is in the front in order among the plurality of first inverters 81<1:4> and the plurality of second inverters 82<1:4> is the same as the driving force of one of the first inverter 81<2:4> and the second inverter 82<2:4> that is in the rear in order among the plurality of first inverters 81<1:4> and the plurality of second inverters 82<1:4>. Under this certain condition, the third inverter 85 inverts and drives the output node O2<1:3> of the second inverter 82<1:3> that is in the front in order in response to a signal loaded on the output node O1<1:3> of the first inverter 81<1:3> that is in the front in order. Likewise, under the certain condition, the fourth inverter 86 inverts and drives the output node O1<1:3> of the first inverter 81<1:3> that is in the front in order in response to a signal loaded on the output node O2<1:3> of the second inverter 82<1:3> that is in the front in order.

[0151] According to an embodiment, the driving force of the 3rd first inverter 81<3> and the 3rd second inverter 82<3> among the plurality of first inverters 81<1:4> and the plurality of second inverters 82<1:4> is the same as the driving force of the 4th first inverter 81<4> and the 4th second inverter 82<4> among the plurality of first inverters 81<1:4> and the plurality of second inverters 82<1:4>. Therefore, the clock transmitting circuit according to the second embodiment of the present disclosure further comprises: a 3rd inverter 85, inverting driving the output node O2<3> of the 3rd second inverter 82<3> in response to the signal loaded on the output node O1<3> of the 3rd first inverter 81<3>; and a 4th inverter 86, inverting driving the output node O1<3> of the 3rd first inverter 81<3> in response to the signal loaded on the output node O2<3> of the 3rd second inverter 82<3>.

[0152] As a reference, N can be set as a natural number greater than or equal to 1. In the subsequent description, N is 2 as shown in the figure.

[0153] Specifically, for example, the 1st first additional driver 83<1> among the two first additional drivers 83<1:2> drives the output node O1<1> of the 1st second selected inverter 81<1> among the two second selected inverters 81<1:2> in response to the signal loaded on the input node I2<1> of the 1st first selected inverter 82<1> among the two first selected inverters 82<1:2>.

[0154] In addition, for example, the 1st second additional driver 84<1> among the two second additional drivers 84<1:2> drives the output node O2<1> of the 1st first selected inverter 82<1> among the two first selected inverters 82<1:2> in response to the signal loaded on the input node I1<1> of the 1st second selected inverter 81<1> among the two second selected inverters 81<1:2>.

[0155] In addition, for example, the 2nd first additional driver 83<2> among the two first additional drivers 83<1:2> drives the output node O1<2> of the 2nd second selected inverter 81<2> among the two second selected inverters 81<1:2> in response to the signal loaded on the input node I2<2> of the 2nd first selected inverter 82<2> among the two first selected inverters 82<1:2>.

[0156] Further, for example, the 2nd second additional driver 84<2> among the two second additional drivers 84<1:2> drives the output node O2<2> of the 2nd first selected inverter 82<2> among the two first selected inverters 82<1:2> in response to a signal loaded on the input node I1<2> of the 2nd second selected inverter 81<2> among the two second selected inverters 81<1:2>.

[0157] In this case, for example, the 1st first additional driver 83<1> among the two first additional drivers 83<1:2> and the 1st second additional driver 84<1> among the two second additional drivers 84<1:2> respectively correspond to the 1st first additional driver 13 and the 1st second additional driver 14 described with reference to Figure 8 the first additional driver 13 and the second additional driver 14 described with reference to Figure 8 the first inverter 11 and the second inverter 12 described with reference to

[0158] Therefore, embodiments of the detailed circuit regarding each of the 1st first additional driver 83<1> among the two first additional drivers 83<1:2> and the 1st second additional driver 84<1> among the two second additional drivers 84<1:2> can refer to embodiments described with reference to any one of Figure 1

[0159] Further, for example, the 2nd first additional driver 83<2> among the two first additional drivers 83<1:2> and the 2nd second additional driver 84<2> among the two second additional drivers 84<1:2> respectively correspond to the 2nd first additional driver 13 and the 2nd second additional driver 14 described with reference to Figure 1 the first additional driver 13 and the second additional driver 14 described with reference to Figure 1 the first inverter 11 and the second inverter 12 described with reference to

[0160] Therefore, embodiments of the detailed circuit regarding each of the 2nd first additional driver 83<2> among the two first additional drivers 83<1:2> and the 2nd second additional driver 84<2> among the two second additional drivers 84<1:2> can refer to embodiments described with reference to any one of Figure 2 to Figure 7

[0161] According to embodiments, the first additional driver 13 and the second additional driver 14 described with reference to Figure 1 and Figure 1 ​​, the two first additional drivers 83<1:2> comprise two first NMOS transistors N1 having their gate terminals connected to the input nodes I2<1:2> of the two first selected inverters 82<1:2>, their drain terminals connected to the output nodes O2<1:2> of the two second selected inverters 81<1:2>, and their source terminals connected to a node of the power supply voltage VDD. Further, the two second additional drivers 84<1:2> comprise two second NMOS transistors N2 having their gate terminals connected to the input nodes I1<1:2> of the two second selected inverters 81<1:2>, their drain terminals connected to the output nodes O1<1:2> of the two first selected inverters 82<1:2>, and their source terminals connected to a node of the power supply voltage VDD. For reference, the specific operation of each of the two first additional drivers 83<1:2> and each of the two second additional drivers 84<1:2> can refer to Figure 2 to Figure 7 and the specific operation will not be specifically described.

[0162] According to embodiments, referring to Figure 8 and Figure 2 , the two first additional drivers 83<1:2> comprise two first PMOS transistors P1 having their gate terminals connected to the input nodes I2<1:2> of the two first selected inverters 82<1:2>, their source terminals connected to the output nodes O1<1:2> of the two second selected inverters 81<1:2>, and their drain terminals connected to a node of the ground voltage VSS. Further, the two second additional drivers 84<1:2> comprise two second PMOS transistors P2 having their gate terminals connected to the input nodes I1<1:2> of the two second selected inverters 81<1:2>, their source terminals connected to the output nodes O2<1:2> of the two first selected inverters 82<1:2>, and their drain terminals connected to a node of the ground voltage VSS. For reference, the specific operation of each of the two first additional drivers 83<1:2> and each of the two second additional drivers 84<1:2> can refer to Figure 2 and the specific operation will not be specifically described.

[0163] According to embodiments, referring to Figure 8 and Figure 3The two first additional drivers 83<1:2> comprise two third NMOS transistors N3 having their gate terminals connected to the input nodes I2<1:2> of the two first selected inverters 82<1:2>, their drain terminals connected to the output nodes O1<1:2> of the two second selected inverters 81<1:2>, and their source terminals connected to two first intermediate nodes MN1, respectively, and two fourth NMOS transistors N4 having their gate and source terminals connected to a node of the power supply voltage VDD, and their drain terminals connected to the two first intermediate nodes MN1, respectively. Further, the two second additional drivers 84<1:2> comprise two fifth NMOS transistors N5 having their gate terminals connected to the input nodes I1<1:2> of the two second selected inverters 81<1:2>, their drain terminals connected to the output nodes O2<1:2> of the two first selected inverters 82<1:2>, and their source terminals connected to two second intermediate nodes MN2, respectively, and two sixth NMOS transistors N6 having their gate and source terminals connected to a node of the power supply voltage VDD, and their drain terminals connected to the two second intermediate nodes MN2, respectively. For reference, the specific operation of each of the two first additional drivers 83<1:2> and each of the two second additional drivers 84<1:2> can refer to Figure 3 and the specific operation will not be described in detail.

[0164] According to embodiments, reference is made to Figure 8 and Figure 4The two first additional drivers 83<1:2> comprise two third PMOS transistors P3 having their gate terminals connected to the input nodes I2<1:2> of the two first selected inverters 82<1:2>, their source terminals connected to the output nodes O1<1:2> of the two second selected inverters 81<1:2>, and their drain terminals connected to two third intermediate nodes MN3, respectively, and two fourth PMOS transistors P4 having their gate and drain terminals connected to a node of ground voltage VSS, and their source terminals connected to the two third intermediate nodes MN3, respectively. Further, the two second additional drivers 84<1:2> comprise two fifth PMOS transistors P5 having their gate terminals connected to the input nodes I1<1:2> of the two second selected inverters 81<1:2>, their source terminals connected to the output nodes O2<1:2> of the two first selected inverters 82<1:2>, and their drain terminals connected to two fourth intermediate nodes MN4, respectively, and two sixth PMOS transistors P6 having their gate and drain terminals connected to a node of ground voltage VSS, and their source terminals connected to the two fourth intermediate nodes MN4, respectively. For reference, the specific operation of each of the two first additional drivers 83<1:2> and each of the two second additional drivers 84<1:2> can refer to Figure 4 and the specific operation will not be described in detail.

[0165] According to embodiments, reference is made to Figure 8 and Figure 5The two first additional drivers 83<1:2> comprise two seventh NMOS transistors N7 having their gate terminals connected to the input nodes I2<1:2> of the two first selected inverters 82<1:2>, their drain terminals connected to the output nodes O1<1:2> of the two second selected inverters 81<1:2>, and their source terminals connected to a node of the power supply voltage VDD, and two seventh PMOS transistors P7 having their gate terminals connected to the input nodes I2<1:2> of the two first selected inverters 82<1:2>, their source terminals connected to the output nodes O1<1:2> of the two second selected inverters 81<1:2>, and their drain terminals connected to a node of the ground voltage VSS. Further, the two second additional drivers 84<1:2> comprise two eighth NMOS transistors N8 having their gate terminals connected to the input nodes I1<1:2> of the two second selected inverters 81<1:2>, their drain terminals connected to the output nodes O2<1:2> of the two first selected inverters 82<1:2>, and their source terminals connected to a node of the power supply voltage VDD, and two eighth PMOS transistors P8 having their gate terminals connected to the input nodes I1<1:2> of the two second selected inverters 81<1:2>, their source terminals connected to the output nodes O2<1:2> of the two first selected inverters 82<1:2>, and their drain terminals connected to a node of the ground voltage VSS. For reference, the specific operation of each of the two first additional drivers 83<1:2> and each of the two second additional drivers 84<1:2> can refer to Figure 5 and the specific operation will not be described in detail.

[0166] According to embodiments, reference is made to Figure 8 and Figure 6The two first additional drivers 83<1:2> comprise two ninth NMOS transistors N9 having their gate terminals connected to the input nodes I2<1:2> of the two first selected inverters 82<1:2>, their drain terminals connected to the output nodes O1<1:2> of the two second selected inverters 81<1:2>, and their source terminals connected to two fifth intermediate nodes MN5, respectively; two tenth NMOS transistors N10 having their gate and source terminals connected to a node of the power supply voltage VDD, and their drain terminals connected to the two fifth intermediate nodes MN5, respectively; two ninth PMOS transistors P9 having their gate terminals connected to the input nodes I2<1:2> of the two first selected inverters 82<1:2>, their source terminals connected to the output nodes O1<1:2> of the two second selected inverters 81<1:2>, and their drain terminals connected to two sixth intermediate nodes MN6, respectively; and two tenth PMOS transistors P10 having their gate and drain terminals connected to a node of the ground voltage VSS, and their source terminals connected to the two sixth intermediate nodes MN6. Further, the two second additional drivers 84<1:2> comprise two eleventh NMOS transistors N11 having their gate terminals connected to the input nodes I1<1:2> of the two second selected inverters 81<1:2>, their drain terminals connected to the output nodes O2<1:2> of the two first selected inverters 82<1:2>, and their source terminals connected to two seventh intermediate nodes MN7, respectively; two twelfth NMOS transistors N12 having their gate and source terminals connected to a node of the power supply voltage VDD, and their drain terminals connected to the two seventh intermediate nodes MN7, respectively; two eleventh PMOS transistors P11 having their gate terminals connected to the input nodes I1<1:2> of the two second selected inverters 81<1:2>, their source terminals connected to the output nodes O2<1:2> of the two first selected inverters 82<1:2>, and their drain terminals connected to two eighth intermediate nodes MN8, respectively; and two twelfth PMOS transistors P12 having their gate and drain terminals connected to a node of the ground voltage VSS, and their source terminals connected to the two eighth intermediate nodes MN8, respectively. For reference, the specific operations of each of the two first additional drivers 83<1:2> and each of the two second additional drivers 84<1:2> can refer to those of the additional driver 83 of FIG. 6, and the specific operations will not be specifically described. Figure 6

[0167] ​Figure 8 is a diagram for describing a clock transmitting circuit according to a third embodiment of the present disclosure.

[0168] Referring to Figure 7 , the clock transmitting circuit according to the third embodiment of the present disclosure includes a first transmitting circuit T1, a second transmitting circuit T2, N first additional drivers 93, and N second additional drivers 94. In this case, N can be a natural number equal to or greater than 1.

[0169] Specifically, the first transmitting circuit T1 transmits a first clock signal INCLK1 among differential clock signals INCLK1 and INCLK2 by a plurality of first inverters 91<1:4> connected in a chain form.

[0170] Further, the second transmitting circuit T2 transmits a second clock signal INCLK2 among the differential clock signals INCLK1 and INCLK2 by a plurality of second inverters 92<1:4> connected in a chain form and respectively corresponding to the plurality of first inverters 91<1:4>.

[0171] Further, each of the N first additional drivers 93 drives an output node O1<4> of each of N second selected inverters 91<4> respectively corresponding to N first selected inverters 92<4> among the plurality of first inverters 91<1:4> in response to a signal loaded on an input node I2<4> of each of the N first selected inverters 92<4> among the plurality of second inverters 92<1:4>.

[0172] Further, each of the N second additional drivers 94 drives an output node O2<4> of each of the N first selected inverters 92<4> in response to a signal loaded on an input node I1<4> of each of the N second selected inverters 91<4>.

[0173] It can be seen that the first transmitting circuit T1 and the second transmitting circuit T2 included in the clock transmitting circuit according to the third embodiment of the present disclosure respectively correspond to the first transmitting circuit T1 and the second transmitting circuit T2 included in the clock transmitting circuit according to the second embodiment described with reference to Figure 7 . Accordingly, the detailed structure and operation of the first transmitting circuit T1 and the second transmitting circuit T2 can be described with reference to Figure 9 .

[0174] Further, the clock transmitting circuit according to the third embodiment of the present disclosure corresponds to the clock transmitting circuit according to the first embodiment described with reference to Figure 9The difference of the clock transmission circuit of the second embodiment described includes that when N is 1, only one first selected inverter 92<4> among the plurality of second inverters 92<1:4> and one second selected inverter 91<4> among the plurality of first inverters 91<1:4> are divided, thus only one second additional driver 93 and one second additional driver 94 are included, and the third inverter 85 and the fourth inverter 86 are not included.

[0175] According to the embodiment, only the fourth inverter 92<4> among the plurality of second inverters 92<1:4> is divided as the first selected inverter 92<4>, and the rest of the first to third inverters 92<1:3> are not divided as the "first selected inverters". Likewise, only the fourth inverter 91<4> among the plurality of first inverters 91<1:4> is divided as the second selected inverter 91<4>, and the rest of the first to third inverters 91<1:3> are not divided as the "second selected inverters".

[0176] According to the embodiment, the first additional driver 93 drives the output node O1<4> of the second selected inverter 91<4> in response to the signal loaded on the input node I2<4> of the first selected inverter 92<4>.

[0177] Further, each of the N second additional drivers 94 drives the output node O2<4> of the first selected inverter 92<4> in response to the signal loaded on the input node I1<4> of the second selected inverter 91<4>.

[0178] In this case, the first additional driver 93 and the second additional driver 94 respectively correspond to, for example, the first additional driver 13 and the second additional driver 14 described with reference to Figure 8 the first embodiment. Further, the first selected inverter 92<4> and the second selected inverter 91<4> respectively correspond to, for example, the first inverter 9 and the second inverter 12 described with reference to Figure 8 the first embodiment.

[0179] Therefore, the embodiment of the detailed circuit of each of the first additional driver 93 and the second additional driver 94 can refer to the embodiment described in any one of Figure 8 the first embodiment.

[0180] In the clock transmission circuit according to the third embodiment of the present disclosure, because only the fourth inverters 91<4> and 92<4> among the plurality of first inverters 91<1:4> and the plurality of second inverters 92<1:4> are divided as the first selected inverter 92<4> and the second selected inverter 91<4>, the driving force of the fourth inverters 91<4> and 92<4> is relatively larger than the driving force of the third inverters 91<3> and 92<3>.

[0181] Figure 1 is a diagram for describing a clock transmitting circuit according to the fourth embodiment of the present disclosure.

[0182] Referring to Figure 1 , the clock transmitting circuit according to the fourth embodiment of the present disclosure includes a first transmitting circuit T1, a second transmitting circuit T2, N first additional drivers 103, and N second additional drivers 104. In this case, N can be a natural number equal to or greater than 1.

[0183] Specifically, the first transmitting circuit T1 transmits a first clock signal INCLK1 among differential clock signals INCLK1 and INCLK2 by a plurality of first inverters 101<1:4> connected in a chain form.

[0184] Further, the second transmitting circuit T2 transmits a second clock signal INCLK2 among the differential clock signals INCLK1 and INCLK2 by a plurality of second inverters 102<1:4> connected in a chain form and respectively corresponding to the plurality of first inverters 101<1:4>.

[0185] Further, each of the N first additional drivers 103 drives an output node O1<1> of each of N second selected inverters 101<1> respectively corresponding to N first selected inverters 102<1> among the plurality of first inverters 101<1:4> in response to a signal loaded on an input node I2<1> of each of the N first selected inverters 102<1> among the plurality of second inverters 102<1:4>.

[0186] Further, each of the N second additional drivers 104 drives an output node O2<1> of each of the N first selected inverters 102<1> in response to a signal loaded on an input node I1<1> of each of the N second selected inverters 101<1>.

[0187] It can be seen that the first transmitting circuit T1 and the second transmitting circuit T2 included in the clock transmitting circuit according to the fourth embodiment of the present disclosure respectively correspond to the first transmitting circuit T1 and the second transmitting circuit T2 included in the clock transmitting circuit according to the second embodiment described with reference to Figure 2 to Figure 7 . Accordingly, the detailed structure and operation of the first transmitting circuit T1 and the second transmitting circuit T2 can be described with reference to Figure 10 .

[0188] Further, the clock transmitting circuit according to the fourth embodiment of the present disclosure corresponds to the clock transmitting circuit according to the third embodiment described with reference to Figure 10The difference of the clock transmission circuit of the second embodiment described includes that when N is 1, only one first selected inverter 102<4> among the plurality of second inverters 102<1:4> and one second selected inverter 101<4> among the plurality of first inverters 101<1:4> are divided, thus only one second additional driver 103 and one second additional driver 104 are included, and a third inverter 85 and a fourth inverter 86 are not included.

[0189] According to the embodiment, only the first inverter 102<1> among the plurality of second inverters 102<1:4> is divided as the first selected inverter 102<1>, and the rest of the second to fourth inverters 102<2:4> are not divided as the "first selected inverters". Likewise, only the first inverter 101<1> among the plurality of first inverters 101<1:4> is divided as the second selected inverter 101<1>, and the rest of the second to third inverters 101<2:4> are not divided as the "second selected inverters".

[0190] According to the embodiment, the first additional driver 103 drives the output node O1<1> of the second selected inverter 101<1> in response to the signal loaded on the input node I2<1> of the first selected inverter 102<1>.

[0191] Further, the second additional driver 104 drives the output node O2<1> of the first selected inverter 102<1> in response to the signal loaded on the input node I1<1> of the second selected inverter 101<1>.

[0192] In this case, the first additional driver 103 and the second additional driver 104 respectively correspond to, for example, the first additional driver 13 and the second additional driver 14 described with reference to Figure 8 the first embodiment described with reference to Figure 8 the first inverter 10 and the second inverter 12 described with reference to

[0193] Therefore, the embodiment of the detailed circuit of each of the first additional driver 103 and the second additional driver 104 can refer to the embodiment described with reference to any one of Figure 8 the first embodiment described with reference to

[0194] In the clock transmission circuit according to the fourth embodiment of the present disclosure, because only the first inverters 101<1> and 102<1> among the plurality of first inverters 101<1:4> and the plurality of second inverters 102<1:4> are divided as the first selected inverter 102<1> and the second selected inverter 101<1>, the driving force of the second inverters 101<2> and 102<2> is relatively larger than the driving force of the first inverters 101<1> and 102<1>.

[0195] Figure 1 is a diagram for describing a clock transmitting circuit according to the fifth embodiment of the present disclosure.

[0196] Referring to Figure 1 , the clock transmitting circuit according to the fifth embodiment of the present disclosure includes a first transmitting circuit T1, a second transmitting circuit T2, N first additional drivers 113, and N second additional drivers 114. In this case, N can be a natural number equal to or greater than 1.

[0197] Specifically, the first transmitting circuit T1 transmits a first clock signal INCLK1 among differential clock signals INCLK1 and INCLK2 by a plurality of first inverters 111<1:4> connected in a chain form.

[0198] Further, the second transmitting circuit T2 transmits a second clock signal INCLK2 among the differential clock signals INCLK1 and INCLK2 by a plurality of second inverters 112<1:4> connected in a chain form and respectively corresponding to the plurality of first inverters 111<1:4>.

[0199] Further, each of the N first additional drivers 113 drives an output node O1<1, 4> of each of N second selected inverters 111<1, 4> respectively corresponding to N first selected inverters 112<1, 4> among the plurality of first inverters 111<1:4> in response to a signal loaded on an input node I2<1, 4> of each of the N first selected inverters 112<1, 4> among the plurality of second inverters 112<1:4>.

[0200] Further, each of the N second additional drivers 114 drives an output node O2<1, 4> of each of the N first selected inverters 112<1, 4> in response to a signal loaded on an input node I1<1, 4> of each of the N second selected inverters 111<1, 4>.

[0201] It can be seen that the first transmitting circuit T1 and the second transmitting circuit T2 included in the clock transmitting circuit according to the fifth embodiment of the present disclosure correspond to the first transmitting circuit T1 and the second transmitting circuit T2 included in the clock transmitting circuit according to the second embodiment described with reference to Figure 2 to Figure 7 . Therefore, the detailed structure and operation of the first transmitting circuit T1 and the second transmitting circuit T2 can be described with reference to Figure 11 .

[0202] Further, it can be seen that the clock transmitting circuit according to the fifth embodiment of the present disclosure corresponds to the clock transmitting circuit according to the first embodiment described with reference to Figure 11The clock transmission circuit according to the second embodiment described is the same in that when N is 2, two first selected inverters 112<1, 4> among the plurality of second inverters 112<1:4> and two second selected inverters 111<1, 4> among the plurality of first inverters 111<1:4> are included, two first additional drivers 113<1, 4> and two second additional drivers 114<1, 4> are included, and a third inverter 115 and a fourth inverter 116 are included. The clock transmission circuit according to the fifth embodiment of the present disclosure is the same as the clock transmission circuit according to the second embodiment described with reference to FIG. 6, except for the following. Figure 8 The clock transmission circuit according to the second embodiment described is different in that the positions at which the two first selected inverters 112<1, 4> and the two second selected inverters 111<1, 4> among the plurality of first inverters 111<1:4> and the second inverters 112<1:4> are provided are different, and the positions at which the third inverter 115 and the fourth inverter 116 are provided are different.

[0203] According to the embodiment, the first inverter 112<1> and the fourth inverter 112<4> among the plurality of second inverters 112<1:4> are classified as the first selected inverters 112<1>, while the remaining second and third inverters 112<2:3> are not classified as the “first selected inverters”. Likewise, the first inverter 111<1> and the fourth inverter 111<4> among the plurality of first inverters 111<1:4> are classified as the second selected inverters 111<1>, while the remaining second and third inverters 111<2:3> are not classified as the “second selected inverters”.

[0204] According to the embodiment, the 1st first additional driver 113<1> among the two first additional drivers 113<1, 4> drives the output node O1<1> of the 1st second selected inverter 111<1> among the two second selected inverters 111<1, 4> in response to a signal loaded on the input node I2<1> of the 1st first selected inverter 112<1> among the two first selected inverters 112<1, 4>.

[0205] Further, the 1st second additional driver 114<1> among the two second additional drivers 114<1, 4> drives the output node O2<1> of the 1st first selected inverter 112<1> among the two first selected inverters 112<1, 4> in response to a signal loaded on the input node I1<1> of the 1st second selected inverter 111<1> among the two second selected inverters 111<1, 4>.

[0206] Further, a 2nd first additional driver 113<4> among the two first additional drivers 113<1, 4> drives an output node 02<4> of a 2nd first selected inverter 112<4> among the two first selected inverters 112<1, 4> in response to a signal loaded on an input node 12<4> of the 2nd first selected inverter 112<4> among the two first selected inverters 112<1, 4>.

[0207] Further, a 2nd second additional driver 114<4> among the two second additional drivers 114<1, 4> drives an output node 02<4> of a 2nd first selected inverter 112<4> among the two first selected inverters 112<1, 4> in response to a signal loaded on an input node 12<4> of the 2nd first selected inverter 112<4> among the two first selected inverters 112<1, 4>.

[0208] In this case, a 1st first additional driver 113<1> among the two first additional drivers 113<1, 4> and a 1st second additional driver 114<1> among the two second additional drivers 114<1, 4> respectively correspond to, for example, the first additional driver 13 and the second additional driver 14 described with reference to Figure 8 In this case, a 1st first additional driver 113<1> among the two first additional drivers 113<1, 4> and a 1st second additional driver 114<1> among the two second additional drivers 114<1, 4> respectively correspond to, for example, the first additional driver 13 and the second additional driver 14 described with reference to Figure 8 In this case, a 1st first additional driver 113<1> among the two first additional drivers 113<1, 4> and a 1st second additional driver 114<1> among the two second additional drivers 114<1, 4> respectively correspond to, for example, the first additional driver 13 and the second additional driver 14 described with reference to

[0209] Therefore, embodiments of the detailed circuit regarding each of the 1st first additional driver 113<1> among the two first additional drivers 113<1, 4> and the 1st second additional driver 114<1> among the two second additional drivers 114<1, 4> can refer to the embodiments described with reference to any one of Figure 8 In this case, a 1st first additional driver 113<1> among the two first additional drivers 113<1, 4> and a 1st second additional driver 114<1> among the two second additional drivers 114<1, 4> respectively correspond to, for example, the first additional driver 13 and the second additional driver 14 described with reference to

[0210] In this case, a 1st first additional driver 113<1> among the two first additional drivers 113<1, 4> and a 1st second additional driver 114<1> among the two second additional drivers 114<1, 4> respectively correspond to, for example, the first additional driver 13 and the second additional driver 14 described with reference to Figure 1 In this case, a 1st first additional driver 113<1> among the two first additional drivers 113<1, 4> and a 1st second additional driver 114<1> among the two second additional drivers 114<1, 4> respectively correspond to, for example, the first additional driver 13 and the second additional driver 14 described with reference to Figure 1The first inverter 11 and the second inverter 12 described in the above.

[0211] Therefore, the embodiment of the detailed circuit of each of the 2nd first additional driver 113<4> among the two first additional drivers 113<1, 4> and the 2nd second additional driver 114<4> among the two second additional drivers 114<1, 4> can refer to the embodiment described in any one of Figure 2 to Figure 7

[0212] According to an embodiment, the clock transmission circuit of the fifth embodiment according to the present disclosure includes: a third inverter 115 that inverts and drives an output node O2<2> of a 2nd second inverter 112<2> in response to a signal loaded on an output node O1<2> of a 2nd first inverter 111<2>; and a fourth inverter 116 that inverts and drives the output node O1<2> of the 2nd first inverter 111<2> in response to a signal loaded on the output node O2<2> of the 2nd second inverter 112<2>.

[0213] In the clock transmission circuit of the fifth embodiment according to the present disclosure, because the first inverters 111<1, 4> and the fourth inverters 112<1, 4> among the plurality of first inverters 111<1:4> and the second inverters 112<1:4> are divided into the first selected inverters 112<1, 4> and the second selected inverters 111<1, 4>, the driving force of the second inverters 111<2> and 112<2> is relatively larger than that of the first inverters 111<1> and 112<1>, and the driving force of the fourth inverters 111<4> and 112<4> is relatively larger than that of the third inverters 111<3> and 112<3>.

[0214] Further, in the clock transmission circuit of the fifth embodiment according to the present disclosure, because the third inverter 115 and the fourth inverter 116 are provided between the output node O1<2> of the 2nd first inverter 111<2> and the output node O2<2> of the 2nd second inverter 112<2> among the plurality of first inverters 111<1:4> and the second inverters 112<1:4>, the driving force of the 2nd first inverter 111<2> and the 2nd second inverter 112<2> is the same as that of the 3rd first inverter 111<3> and the 3rd second inverter 112<3>.

[0215] Figure 1 is a diagram showing a memory system applying the clock transmission circuit according to an embodiment of the present disclosure.

[0216] Referring to Figure 1 ​In an embodiment, a memory system includes a memory controller 121 and a memory device 122 as a semiconductor device. In this case, the memory device 122 includes, for example, a clock transmission circuit 123 that receives, transmits, and buffers a data strobe signal DQS / DQSB.

[0217] The memory controller 121 transmits a command and an address CMD / ADDR to control the memory device 122. Further, the memory controller 121 receives data DATA read from the memory device 122 or transmits data DATA to be written to the memory device 122.

[0218] The data strobe signal DQS / DQSB is a signal for strobing data DATA transmitted between the memory controller 121 and the memory device 122. According to an embodiment, the memory controller 121 transmits the data strobe signal DQS / DQSB to the memory device 122 together with data DATA to be written. Further, the memory device 122 transmits the data strobe signal DQS / DQSB to the memory controller 121 together with data DATA read from the memory device 122.

[0219] The data strobe signal DQS / DQSB is, for example, a differential clock signal that is switched at a set frequency. That is, the data strobe signal DQS / DQSB is transmitted in the form of a differential signal between the memory controller 121 and the memory device 122.

[0220] According to an embodiment, the data strobe signal DQS / DQSB is Figure 2 to Figure 7 Figure 12 Figure 12 Figure 1 to Figure 11 the differential clock signals INCLK1 and INCLK2 as illustrated. Further, for example, a main signal DQS among the data strobe signals DQS / DQSB is a first clock signal INCLK1 among the differential clock signals INCLK1 and INCLK2. For example, a sub signal DQSB among the data strobe signals DQS / DQSB is a second clock signal INCLK2 among the differential clock signals INCLK1 and INCLK2. Conversely, for example, a main signal DQS among the data strobe signals DQS / DQSB is a second clock signal INCLK2 among the differential clock signals INCLK1 and INCLK2. For example, a sub signal DQSB among the data strobe signals DQS / DQSB is a first clock signal INCLK1 among the differential clock signals INCLK1 and INCLK2.

[0221] For reference, the memory device 122 can be any memory device among a volatile memory device and a non-volatile memory device. In this case, the volatile memory device is a memory device in which data stored in the memory device is lost when power supply of the memory device is blocked. The volatile memory device includes, for example, a static RAM (SRAM), a dynamic RAM (DRAM), and a synchronous DRAM (SDRAM). Also, the non-volatile memory device is a memory device that retains data stored in the memory device even when power supply of the memory device is blocked. The non-volatile memory device includes, for example, a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory device, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), and a ferroelectric RAM (FRAM).

[0222] It is obvious to those skilled in the art to which the present disclosure pertains that the above-described embodiments of the present disclosure are not limited by the above-described embodiments and drawings, and the embodiments of the present disclosure can be replaced, modified, and changed in various ways without departing from the technical spirit of the present disclosure.

[0223] For example, the positions and types of the logic gates and the transistors shown in the above-described embodiments must be differently implemented according to the polarity of an input signal. Also, the embodiments can be combined to form additional embodiments.

Claims

1. A clock transmitting circuit comprising: a first inverter inverting driving a first transmitting node in response to a first clock signal among differential clock signals loaded to a first receiving node; a second inverter inverting driving a second transmitting node in response to a second clock signal among the differential clock signals loaded to a second receiving node; a first additional driver additionally driving the first transmitting node in response to the second clock signal loaded to the second receiving node; and a second additional driver additionally driving the second transmitting node in response to the first clock signal loaded to the first receiving node.

2. The clock transmitting circuit according to claim 1, wherein the first additional driver includes a first NMOS transistor whose gate terminal is connected to the second receiving node, whose drain terminal is connected to the first transmitting node, and whose source terminal is connected to a node of a power supply voltage; and the second additional driver includes a second NMOS transistor whose gate terminal is connected to the first receiving node, whose drain terminal is connected to the second transmitting node, and whose source terminal is connected to the node of the power supply voltage.

3. The clock transmitting circuit according to claim 1, wherein the first additional driver includes a first PMOS transistor whose gate terminal is connected to the second receiving node, whose source terminal is connected to the first transmitting node, and whose drain terminal is connected to a node of a ground voltage; and the second additional driver includes a second PMOS transistor whose gate terminal is connected to the first receiving node, whose source terminal is connected to the second transmitting node, and whose drain terminal is connected to the node of the ground voltage.

4. The clock transmitting circuit according to claim 1, wherein the first additional driver includes: a third NMOS transistor whose gate terminal is connected to the second receiving node, whose drain terminal is connected to the first transmitting node, and whose source terminal is connected to a first intermediate node; and a fourth NMOS transistor whose gate terminal and source terminal are connected to a node of a power supply voltage, and whose drain terminal is connected to the first intermediate node; and the second additional driver includes: a fifth NMOS transistor whose gate terminal is connected to the first receiving node, whose drain terminal is connected to the second transmitting node, and whose source terminal is connected to a second intermediate node; and a sixth NMOS transistor whose gate terminal and source terminal are connected to the node of the power supply voltage, and whose drain terminal is connected to the second intermediate node.

5. The clock transmitting circuit according to claim 1, wherein the first additional driver includes: a third PMOS transistor whose gate terminal is connected to the second receiving node, whose source terminal is connected to the first transmitting node, and whose drain terminal is connected to a third intermediate node, and the second additional driver includes: a fourth PMOS transistor whose gate terminal is connected to the first receiving node, whose source terminal is connected to the second transmitting node, and whose drain terminal is connected to a fourth intermediate node. a fourth PMOS transistor having a gate terminal and a drain terminal connected to a node of the ground voltage, and a source terminal connected to the third intermediate node; and the second additional driver includes: a fifth PMOS transistor having a gate terminal connected to the first receiving node, a source terminal connected to the second transmitting node, and a drain terminal connected to a fourth intermediate node, and a sixth PMOS transistor having a gate terminal and a drain terminal connected to a node of the ground voltage, and a source terminal connected to the fourth intermediate node.

6. The clock transmitting circuit according to claim 1, wherein the first additional driver includes: a seventh NMOS transistor having a gate terminal connected to the second receiving node, a drain terminal connected to the first transmitting node, and a source terminal connected to a node of the power supply voltage; and a seventh PMOS transistor having a gate terminal connected to the second receiving node, a source terminal connected to the first transmitting node, and a drain terminal connected to a node of the ground voltage; and the second additional driver includes: an eighth NMOS transistor having a gate terminal connected to the first receiving node, a drain terminal connected to the second transmitting node, and a source terminal connected to the node of the power supply voltage; and an eighth PMOS transistor having a gate terminal connected to the first receiving node, a source terminal connected to the second transmitting node, and a drain terminal connected to the node of the ground voltage.

7. The clock transmitting circuit according to claim 1, wherein the first additional driver includes: a ninth NMOS transistor having a gate terminal connected to the second receiving node, a drain terminal connected to the first transmitting node, and a source terminal connected to a fifth intermediate node; a tenth NMOS transistor having a gate terminal and a source terminal connected to a node of the power supply voltage, and a drain terminal connected to the fifth intermediate node; a ninth PMOS transistor having a gate terminal connected to the second receiving node, a source terminal connected to the first transmitting node, and a drain terminal connected to a sixth intermediate node; and a tenth PMOS transistor having a gate terminal and a drain terminal connected to a node of the ground voltage, and a source terminal connected to the sixth intermediate node; and the second additional driver includes: an eleventh NMOS transistor having a gate terminal connected to the first receiving node, a drain terminal connected to the second transmitting node, and a source terminal connected to a seventh intermediate node; a twelfth NMOS transistor having a gate terminal and a source terminal connected to the node of the power supply voltage, and a drain terminal connected to the seventh intermediate node; a thirteenth NMOS transistor having a gate terminal connected to the second receiving node, a drain terminal connected to the first transmitting node, and a source terminal connected to the node of the power supply voltage; and a thirteenth PMOS transistor having a gate terminal connected to the second receiving node, a source terminal connected to the first transmitting node, and a drain terminal connected to the node of the ground voltage; and the second additional driver includes: a fourteenth NMOS transistor having a gate terminal connected to the first receiving node, a drain terminal connected to the second transmitting node, and a source terminal connected to the node of the power supply voltage; and a fourteenth PMOS transistor having a gate terminal connected to the first receiving node, a source terminal connected to the second transmitting node, and a drain terminal connected to the node of the ground voltage. a twelfth PMOS transistor whose gate terminal and drain terminal are connected to a node of the ground voltage, and whose source terminal is connected to the eighth intermediate node. a twelfth PMOS transistor whose gate terminal and drain terminal are connected to a node of the ground voltage, and whose source terminal is connected to the eighth intermediate node.

8. The clock transmission circuit according to claim 1, wherein a driving force of the first additional driver is smaller than a driving force of the first inverter; and a driving force of the second additional driver is smaller than a driving force of the second inverter.

9. The clock transmitting circuit of claim 1, wherein, phases of the first clock signal and the second clock signal are opposite to each other.

10. A clock transmission circuit, comprising: a first transmission circuit that transmits a first clock signal among differential clock signals through a plurality of first inverters connected in a chain form; a second transmission circuit that transmits a second clock signal among the differential clock signals through a plurality of second inverters connected in a chain form and corresponding to the plurality of first inverters, respectively; at least one first additional driver that additionally drives an output node of at least one second selected inverter among the plurality of first inverters in response to a signal loaded on an input node of at least one first selected inverter among the plurality of second inverters; and at least one second additional driver that additionally drives an output node of the at least one first selected inverter in response to a signal loaded on an input node of the at least one second selected inverter.

11. The clock transmission circuit according to claim 10, wherein the at least one first additional driver includes at least one first NMOS transistor whose gate terminal is connected to the input node of the at least one first selected inverter, whose drain terminal is connected to the output node of the at least one second selected inverter, and whose source terminal is connected to a node of a power supply voltage; and the at least one second additional driver includes at least one second NMOS transistor whose gate terminal is connected to the input node of the at least one second selected inverter, whose drain terminal is connected to the output node of the at least one first selected inverter, and whose source terminal is connected to the node of the power supply voltage.

12. The clock transmission circuit according to claim 10, wherein the at least one first additional driver includes at least one first PMOS transistor whose gate terminal is connected to the input node of the at least one first selected inverter, whose source terminal is connected to the output node of the at least one second selected inverter, and whose drain terminal is connected to a node of a ground voltage; and the at least one second additional driver includes at least one second PMOS transistor whose gate terminal is connected to the input node of the at least one second selected inverter, whose source terminal is connected to the output node of the at least one first selected inverter, and whose drain terminal is connected to the node of the ground voltage. The at least one second additional driver comprises at least one second PMOS transistor having a gate terminal connected to an input node of the at least one second selected inverter, a source terminal connected to an output node of the at least one first selected inverter, and a drain terminal connected to a node of the ground voltage.

13. The clock transmission circuit according to claim 10, wherein The at least one first additional driver comprises: at least one third NMOS transistor having a gate terminal connected to an input node of the at least one first selected inverter, a drain terminal connected to an output node of the at least one second selected inverter, and a source terminal connected to at least one first intermediate node; and at least one fourth NMOS transistor having a gate terminal and a source terminal connected to a node of the supply voltage, and a drain terminal connected to the at least one first intermediate node; and The at least one second additional driver comprises: at least one fifth NMOS transistor having a gate terminal connected to an input node of the at least one second selected inverter, a drain terminal connected to an output node of the at least one first selected inverter, and a source terminal connected to at least one second intermediate node; and at least one sixth NMOS transistor having a gate terminal and a source terminal connected to the node of the supply voltage, and a drain terminal connected to the at least one second intermediate node.

14. The clock transmission circuit according to claim 10, wherein The at least one first additional driver comprises: at least one third PMOS transistor having a gate terminal connected to an input node of the at least one first selected inverter, a source terminal connected to an output node of the at least one second selected inverter, and a drain terminal connected to at least one third intermediate node; and at least one fourth PMOS transistor having a gate terminal and a drain terminal connected to a node of the ground voltage, and a source terminal connected to the at least one third intermediate node; and The at least one second additional driver comprises: at least one fifth PMOS transistor having a gate terminal connected to an input node of the at least one second selected inverter, a source terminal connected to an output node of the at least one first selected inverter, and a drain terminal connected to at least one fourth intermediate node; and at least one sixth PMOS transistor having a gate terminal and a drain terminal connected to the node of the ground voltage, and a source terminal connected to the at least one fourth intermediate node.

15. The clock transmission circuit according to claim 10, wherein The at least one first additional driver comprises: at least one seventh NMOS transistor having a gate terminal connected to an input node of the at least one first selected inverter, a drain terminal connected to an output node of the at least one second selected inverter, and a source terminal connected to a node of a supply voltage; and at least one seventh PMOS transistor having a gate terminal connected to an input node of the at least one first selected inverter, a source terminal connected to an output node of the at least one second selected inverter, and a drain terminal connected to a node of a ground voltage; and the N second additional drivers comprise: at least one eighth NMOS transistor having a gate terminal connected to an input node of the at least one second selected inverter, a drain terminal connected to an output node of the at least one first selected inverter, and a source terminal connected to the node of the supply voltage; and at least one eighth PMOS transistor having a gate terminal connected to an input node of the at least one second selected inverter, a source terminal connected to an output node of the at least one first selected inverter, and a drain terminal connected to the node of the ground voltage.

16. The clock transmission circuit of claim 10, wherein the at least one first additional driver comprises: at least one ninth NMOS transistor having a gate terminal connected to an input node of the at least one first selected inverter, a drain terminal connected to an output node of the at least one second selected inverter, and a source terminal connected to at least one fifth intermediate node; at least one tenth NMOS transistor having a gate terminal and a source terminal connected to a node of a supply voltage, and a drain terminal connected to the at least one fifth intermediate node; at least one ninth PMOS transistor having a gate terminal connected to an input node of the at least one first selected inverter, a source terminal connected to an output node of the at least one second selected inverter, and a drain terminal connected to at least one sixth intermediate node; and at least one tenth PMOS transistor having a gate terminal and a drain terminal connected to a node of a ground voltage, and a source terminal connected to the at least one sixth intermediate node; and the at least one second additional driver comprises: at least one eleventh NMOS transistor having a gate terminal connected to an input node of the at least one second selected inverter, a drain terminal connected to an output node of the at least one first selected inverter, and a source terminal connected to at least one seventh intermediate node; at least one twelfth NMOS transistor having a gate terminal and a source terminal connected to a node of a supply voltage, and a drain terminal connected to the at least one seventh intermediate node; and at least one eleventh PMOS transistor having a gate terminal connected to an input node of the at least one second selected inverter, a source terminal connected to an output node of the at least one first selected inverter, and a drain terminal connected to at least one eighth intermediate node; and at least one twelfth PMOS transistor having a gate terminal and a drain terminal connected to a node of a ground voltage, and a source terminal connected to the at least one eighth intermediate node. at least one twelfth NMOS transistor, a gate terminal and a source terminal of which are connected to a node of the power supply voltage, and a drain terminal of which is connected to the at least one seventh intermediate node; at least one eleventh PMOS transistor, a gate terminal of which is connected to an input node of the at least one second selected inverter, a source terminal of which is connected to an output node of the at least one first selected inverter, and a drain terminal of which is connected to at least one eighth intermediate node; and at least one twelfth PMOS transistor, a gate terminal and a drain terminal of which are connected to a node of the ground voltage, and a source terminal of which is connected to the at least one eighth intermediate node.

17. The clock transmission circuit according to claim 10, wherein a driving force of each first additional driver is smaller than a driving force of each second selected inverter; and a driving force of each second additional driver is smaller than a driving force of each first selected inverter.

18. The clock transmitting circuit of claim 10, wherein, phases of the first clock signal and the second clock signal are opposite to each other.

19. The clock transmitting circuit of claim 10, wherein, when a driving force of a first inverter and a second inverter, which are sequentially later among the plurality of first inverters and second inverters, is larger than a driving force of a first inverter and a second inverter, which are sequentially earlier, the first inverter and the second inverter, which are sequentially earlier, are determined as the at least one second selected inverter and the at least one first selected inverter, or the first inverter and the second inverter, which are sequentially later, are determined as the at least one second selected inverter and the at least one first selected inverter.

20. The clock transmitting circuit of claim 19, further comprising: third inverter and fourth inverter, when a driving force of the first inverter and the second inverter, which are sequentially earlier among the plurality of first inverters and second inverters, and a driving force of the first inverter and the second inverter, which are sequentially later, are equal to each other, in response to a signal loaded on an output node of the first inverter and the second inverter, which are sequentially earlier, respectively inverting an output node of the second inverter and the first inverter.

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