High-side driving chip architecture with multiple protection mechanisms

Abstract

The invention relates to a high-side driving chip architecture with multiple protection mechanisms, and aims to solve the technical problems of low reliability of a high-side driving circuit and low safety of a whole vehicle in the prior art. The invention provides a high-side driving chip architecture with multiple protection mechanisms, which comprises a high-side driving module, a main control module, a power management module, a first protection unit arranged between the main control module and the high-side driving module, and a second protection unit arranged between the main control module and a system load to be driven, the third protection unit is arranged between the power management module and the high-side driving module; the first protection unit is used for turning off abnormal to-be-driven system loads, the second protection unit is used for turning off similar abnormal to-be-driven system loads at the same time, and the third protection unit is used for turning off all to-be-driven system loads when the main control module is abnormal.

Description

TECHNICAL FIELD

[0001] The present application relates to a high-side driver chip architecture, in particular to a high-side driver chip architecture with multiple protection mechanisms. BACKGROUND

[0002] High-side driver chips are widely used in the automotive field and are commonly used to drive various loads of vehicles. With the increasing intelligence of vehicles, the number of loads related to intelligence also increases, thus increasing the demand for high-side driver chips.

[0003] With the development of semiconductor technology, high-side driver chips have become more intelligent, not only having complex diagnostic capabilities, but also being able to support advanced dynamic control strategies. In addition, compared with traditional mechanical relays, high-side driver chips have a longer service life and higher reliability, can work stably in extremely harsh environments, and have a design life far exceeding the service life of vehicles. At the same time, the power consumption of high-side driver technology is much lower than that of traditional mechanical relays, and for new energy vehicles, it can effectively utilize limited electrical energy and improve the vehicle's endurance.

[0004] The Chinese patent document with publication number CN117811558A discloses a high-side driver circuit, a control method thereof, and a vehicle. The high-side driver circuit includes at least one pre-driver unit and at least one switching unit. Upon receiving a load operation instruction, the pre-driver unit controls the first end of the switching unit and the second end of the switching unit to be conductive, and controls the pulse modulation PWM frequency of the switching unit. The pre-driver unit and the switching unit are used to replace the high-side chip to realize high-side driving, which can effectively reduce the cost and have more advantages. Moreover, with the pre-driver unit and the switching unit, the purpose of controlling the load and the speed regulation circuit can be achieved.

[0005] The Chinese patent document with publication number CN116683407A discloses a PMOS high-side driver circuit with a diagnostic retention function, which includes an MCU control circuit including a driving transistor, the driving transistor being a PMOS transistor; the MCU control circuit is configured to control the switching of the PMOS transistor and output a control signal for controlling the load; an overcurrent sampling circuit electrically connected to the MCU control circuit and configured to detect the current state of the PMOS transistor; an overvoltage sampling circuit electrically connected to the MCU control circuit and configured to detect the voltage state of the PMOS transistor; a diagnostic retention circuit electrically connected to the overcurrent sampling circuit and the overvoltage sampling circuit and configured to maintain the sampling results of the overcurrent sampling circuit and the overvoltage sampling circuit; a control circuit electrically connected to the MCU control circuit and configured to control the switching of the PMOS transistor according to the sampling results of the overcurrent sampling circuit and the overvoltage sampling circuit.

[0006] However, the high-side drive circuit disclosed in the above two patent documents lacks sufficient hardware circuit protection mechanisms, and thus has low reliability and safety. SUMMARY

[0007] The present application aims to solve the technical problem of low reliability and safety of the existing high-side drive circuit, and provides a high-side drive chip architecture with multiple protection mechanisms.

[0008] To achieve the above-mentioned purpose, the technical solution provided by the present application is as follows:

[0009] A high-side drive chip architecture with multiple protection mechanisms comprises a high-side drive module, a main control module, and a power management module, and is characterized in that it further comprises a drive unit; the drive unit comprises the high-side drive module, a first protection unit arranged between the main control module and the high-side drive module, and a third protection unit arranged between the power management module and the high-side drive module.

[0010] The input end of the first protection unit is connected with the first output unit of the main control module, and the output end is connected with the input end of the high-side drive module; the second output end of the high-side drive module is connected with the first input end of the main control module; the first protection unit is used to control the high-side drive module to shut down an abnormal to-be-driven system load when the main control module detects that the second output end of the high-side drive module feeds back an abnormal to-be-driven system load.

[0011] The input end of the third protection unit is connected with the output unit of the power management module, and the output end is connected with the input end of the high-side drive module; the main control module and the power management module are bidirectionally connected; the third protection unit is used to control the high-side drive module to shut down the to-be-driven system load when the main control module is abnormal.

[0012] Further, the first protection unit comprises a logic AND gate; the first output unit of the main control module comprises a first output end and a second output end; the first output end of the main control module is connected with the first input end of the logic AND gate, and is used to output a first control signal; the second output end of the main control module is connected with the second input end of the logic AND gate, and is used to output a second control signal; the output end of the logic AND gate is connected with the input end of the high-side drive module, and is used to output a third control signal; and the first output end of the high-side drive module is connected with one end of the to-be-driven system load.

[0013] The first control signal is a driving system load signal, the second control signal is set to high level when the to-be-driven system load is normal, the third control signal outputs the same driving signal as the first control signal, and the first output end of the high-side driving module is controlled to drive the to-be-driven system load to work; when the main control module detects an abnormal to-be-driven system load fed back by the second output end of the high-side driving module, the second control signal is set to low level, the third control signal outputs low level, and the high-side driving module is controlled to shut down the abnormal to-be-driven system load.

[0014] Further, the third protection unit includes a PNP transistor and a first NPN transistor, the output unit of the power management module includes a first output end and a second output end, the first output end of the power management module is connected with the base of the PNP transistor and is used for outputting a sixth control signal, the second output end of the power management module is connected with the emitter of the PNP transistor and is used for outputting a seventh control signal, the collector of the PNP transistor is connected with the base of the first NPN transistor, the collector of the first NPN transistor is connected with the input end of the high-side driving module and is used for outputting an eighth control signal, and the emitter of the first NPN transistor is grounded.

[0015] The sixth control signal and the seventh control signal are high level when the main control module is normal, the sixth control signal is set to low level when the main control module is abnormal, the PNP transistor is turned on, the first NPN transistor is turned on in turn, and the eighth control signal is set to low level, thereby controlling the high-side driving module to shut down all to-be-driven system loads.

[0016] Further, the output end of the logic AND gate is further connected with the third input end of the main control module through a first current-limiting resistor, and is used for feeding back the third control signal to the main control module to monitor whether it is valid output;

[0017] The first output end of the high-side driving module is further connected with the second input end of the main control module through a second current-limiting resistor, and is used for feeding back the driving signal output by the high-side driving module to the main control module to monitor whether it is valid output;

[0018] The second output end of the high-side driving module is connected with the first input end of the main control module through a third current-limiting resistor, and the second output end of the high-side driving module is further provided with a pull-down resistor, which is used for converting the current value output by the second output end into a voltage value, judging the state of the current to-be-driven system load according to the voltage value, and feeding back the state of the current to-be-driven system load to the main control module through the third current-limiting resistor.

[0019] Furthermore, the first output end of the high-side driver module is also connected to a system power supply, and a pull-up resistor is arranged between the first output end of the high-side driver module and the system power supply. The pull-up resistor is used to pull up the first output end of the high-side driver module to the system power supply by the pull-up resistor when the load of the system to be driven is open, so that the first output end outputs a high level. After the high level output by the first output end enters the main control module, the main control module detects that the load of the system to be driven is abnormally open.

[0020] At the same time, the present invention also provides a high-side driver chip architecture with multiple protection mechanisms, including a main control module and a power management module. The special feature is that it also includes N of the above-mentioned drive units, each for driving N system loads to be driven. The N system loads to be driven are divided into M groups of similar system loads to be driven according to load type;

[0021] It also includes M second protection units respectively arranged between the main control module and M groups of similar system loads to be driven, M < N;

[0022] The input ends of the M second protection units are respectively connected to the M second output units of the main control module, and the output ends are respectively connected to the other ends of the N system loads to be driven, and the second output ends of the N high-side driver modules are respectively connected to the N first input ends of the main control module, and are used to shut down a corresponding group of similar abnormal system loads to be driven when the main control module detects similar abnormal system loads to be driven fed back by the second output ends of the high-side driver modules;

[0023] The input ends of the N first protection units are respectively connected to the N first output units of the main control module, and the output ends are respectively connected to the input ends of the N high-side driver modules. The first protection unit is used to shut down the abnormal to-be-driven system load when the main control module detects the abnormal to-be-driven system load fed back by the second output end of the high-side driver module;

[0024] The input ends of the N third protection units are respectively connected to the output ends of the power management module, and the output ends are respectively connected to the input ends of the N high-side driver modules. The main control module and the power management module are bidirectionally connected. The third protection unit is used to simultaneously shut down all system loads to be driven when an abnormality occurs in the main control module.

[0025] Further, the M second protection units each comprise an NMOS tube and a second NPN transistor, the M second output units of the master control module each comprise a third output end and a fourth output end, the third output end of the master control module is connected with the gate of the NMOS tube, for outputting a fourth control signal, the fourth output end of the master control module is connected with the base of the second NPN transistor, for outputting a fifth control signal; the emitter of the second NPN transistor and the source of the NMOS tube are grounded, the drain of the NMOS tube is connected with the other end of the to-be-driven system load, for providing a complete loop for the to-be-driven system load, the collector of the second NPN transistor is connected with the gate of the NMOS tube, for controlling the on-off of the NMOS tube;

[0026] The fourth control signal is a high level, the fifth control signal is a low level when the to-be-driven system load is normal, the NMOS tube is opened, and a complete loop is provided for the to-be-driven system load, when the master control module detects the same type of abnormal to-be-driven system load fed back by the second output end of the high-side drive module, the fifth control signal is set to a high level, the second NPN transistor is turned on, thereby pulling down the gate of the NMOS tube, the NMOS tube is turned off, and the connection between the corresponding group of the same type of to-be-driven system load and the ground is cut off, thereby shutting down the same type of abnormal to-be-driven system load.

[0027] Further, the first protection unit comprises a logic AND gate, each first output unit of the master control module comprises a first output end and a second output end, the first output end of each first output unit is connected with the first input end of the corresponding logic AND gate, for outputting a first control signal, the second output end is connected with the second input end of the corresponding logic AND gate, for outputting a second control signal, the output ends of the N logic AND gates are respectively connected with the input ends of the N high-side drive modules, for outputting a third control signal; the first output ends of the N high-side drive modules are respectively connected with one ends of the N to-be-driven system loads;

[0028] The first control signal is a drive system load signal, the second control signal is set to a high level when the to-be-driven system load is normal, the corresponding third control signal outputs the same drive signal as the first control signal, for controlling the first output end of the corresponding high-side drive module to drive the to-be-driven system load to work; when the master control module detects an abnormal to-be-driven system load fed back by the second output end of the high-side drive module, the corresponding second control signal is set to a low level, the third control signal outputs a low level, for controlling the high-side drive module to shut down the abnormal to-be-driven system load;

[0029] The third protection unit comprises a PNP triode and a first NPN triode, the output unit end of the power management module comprises a first output end and a second output end, the first output end of the power management module is connected with the base of the PNP triode and is used for outputting a sixth control signal, the second output end of the power management module is connected with the emitter of the PNP triode and is used for outputting a seventh control signal, the collector of the PNP triode is connected with the base of the first NPN triode, the emitter of the first NPN triode is grounded, and the collector is used for outputting an eighth control signal, and the collectors of the N first NPN triodes are respectively connected with the input ends of the N high-side drive modules.

[0030] The sixth control signal and the seventh control signal are high levels when the master control module is normal, the sixth control signal is low when the master control module is abnormal, each PNP triode is turned on, then each first NPN triode is turned on, and each eighth control signal is low, thereby controlling the high-side drive module to turn off all to-be-driven system loads.

[0031] Further, the output ends of the N logic AND gates are respectively connected with the N third input ends of the master control module through first current-limiting resistors, and are used for feeding back each third control signal to the master control module to monitor whether the third control signal is valid output; the first output ends of the N high-side drive modules are respectively connected with the N second input ends of the master control module through second current-limiting resistors, and are used for feeding back the driving signals output by the high-side drive modules to the master control module to monitor whether the driving signals are valid output.

[0032] The second output ends of the N high-side drive modules are respectively connected with the N first input ends of the master control module through third current-limiting resistors, and the second output ends of the N high-side drive modules are respectively provided with pull-down resistors, which are used for converting the current values output by the corresponding second output ends into voltage values, judging the states of the to-be-driven system loads according to the voltage values, and feeding back the states of the to-be-driven system loads to the master control module through the third current-limiting resistors.

[0033] Further, the first output ends of the N high-side drive modules are respectively connected with system power supplies, and the first output ends of the N high-side drive modules are respectively provided with pull-up resistors between the first output ends and the system power supplies, the pull-up resistors are used for pulling up the first output ends of the high-side drive modules to the system power supplies when the corresponding to-be-driven system loads are open circuits, so that the first output ends output high levels, and the high levels output by the first output ends enter the master control module, and the master control module detects that the to-be-driven system loads are open circuit abnormities.

[0034] The present application has the following advantages:

[0035] 1. The present invention has a high-side driver chip architecture with multiple protection mechanisms. Multiple hardware circuit protection mechanisms are set up around the high-side driver circuit, significantly improving the reliability of the high-side driver chip, thereby improving the functional safety level of the entire vehicle system;

[0036] 2. The present invention has a high-side driver chip architecture with multiple protection mechanisms. The design of the high-side driver chip architecture is more intelligent and has a higher degree of integration, which effectively reduces the power consumption and cost of the entire controller, and can provide more complex diagnostic logic and support more advanced dynamic control strategies. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 This is a circuit architecture diagram of an embodiment of a high-side driver chip architecture with multiple protection mechanisms according to the present invention (taking a single system load as an example);

[0038] Figure 2 FIG. 1 is a circuit diagram of an embodiment of a high-side driver chip architecture with multiple protection mechanisms according to the present invention (taking multiple system loads as an example). DETAILED DESCRIPTION

[0039] The present invention will be further described below with reference to the accompanying drawings and examples.

[0040] This embodiment provides a high-side driver chip architecture with multiple protection mechanisms, such as Figure 1 As shown, it includes a main control module, a power management module and a driving unit, the driving unit includes a high-side driving module, a first protection unit arranged between the main control module and the high-side driving module, and a third protection unit arranged between the power management module and the high-side driving module, the second output end of the high-side driving module is connected to the first input end of the main control module, and the first output end of the high-side driving module is connected to one end of the belt drive system load;

[0041] The first protection unit includes a logic AND gate, a first output end of the main control module is connected to a first input end of the logic AND gate, for outputting a first control signal; a second output end of the main control module is connected to a second input end of the logic AND gate, for outputting a second control signal; an output end of the logic AND gate is connected to an input end of the high-side driver module, for outputting a third control signal;

[0042] The first control signal is a driving load signal, and the second control signal is high when the system load to be driven is normal, and under the action of the logic AND gate, the third control signal is set as the same driving signal as the first control signal and is transmitted to the high-side driving module, and after receiving the third control signal, the high-side driving module sends a driving signal to the system load to be driven through the first output end of the high-side driving module to drive the system load to work; the second control signal is also used to set the third control signal to low when the main control module detects abnormal system load to be driven fed back by the second output end of the high-side driving module, and under the action of the logic AND gate, the third control signal is set to low and is transmitted to the high-side driving module, and after receiving the third control signal, the high-side driving module turns off the single abnormal system load to be driven to avoid the influence of the abnormal system load to be driven on other system loads to be driven.

[0043] The third protection unit includes a PNP transistor T1 and a first NPN transistor T2, the first output end of the power management module is connected with the base of the PNP transistor T1 for outputting a sixth control signal, the second output end of the power management module is connected with the emitter of the PNP transistor T1 for outputting a seventh control signal, the collector of the PNP transistor T1 is connected with the base of the first NPN transistor T2, the collector of the first NPN transistor T2 is connected with the input end of the high-side driving module for outputting an eighth control signal, and the emitter of the first NPN transistor T2 is grounded.

[0044] The sixth control signal and the seventh control signal are high when the main control module is normal, which is used to ensure that the PNP transistor T1 and the first NPN transistor T2 are in a non-conductive state, so that the main control module works normally; the sixth control signal is also used to send a state conversion request to the main control module when the main control module is abnormal, and after the main control module performs state conversion on the power management module, the power management module sets the sixth control signal to low, so that the PNP transistor T1 is turned on, and then the first NPN transistor T2 is turned on, so that the eighth control signal is set to low, and all system loads to be driven are turned off.

[0045] The output end of the logic AND gate is also connected with the third input end of the main control module through a resistor R1, the resistor R1 plays a current limiting role, and is used to feed back the third control signal to the main control module to monitor whether it is a valid output; and the first output end of the high-side driving module is connected with the second input end of the main control module through a resistor R2, the resistor R2 plays a current limiting role, and is used to feed back the driving signal output by the high-side driving module to the main control module to monitor whether it is a valid output.

[0046] There are multiple fault diagnosis mechanisms in the high-side drive chip, which are realized through the second output end of the high-side drive module. The second output end of the high-side drive module and the first input end of the main control module are connected through a resistor R3, which plays a current limiting role. The realization of abnormal diagnosis is through detecting the current size of the to-be-driven system load. However, the monitoring of the current size is relatively difficult to realize. Therefore, the second output end of the high-side drive module is further provided with a pull-down resistor R5, which converts the current signal into a voltage signal, and then feeds back to the main control module through the current limiting resistor R3. The main control module judges the state of the to-be-driven system load according to the size of the voltage and the truth table diagnosed by the high-side drive module.

[0047] The first output end of the high-side drive module is connected with a system power supply through a resistor R4. The high-side drive module can judge multiple fault types, wherein the fault judgment conditions in the to-be-driven system load driving and non-driving states are inconsistent. The resistor R4 is set to facilitate open circuit fault diagnosis. The resistance value of the to-be-driven system load is far less than that of the resistor R4. When the to-be-driven system load is open, the first output end of the high-side drive module is pulled up to the system power supply through the resistor R4, so the level of the first output end is high. The main control module will detect the open circuit fault. When the to-be-driven system load is not open, the first output end is low.

[0048] In the embodiment, whether the third control signal is valid depends on the first control signal and the second control signal. The first control signal can be a PWM signal output or a high-low level output. Its truth table is shown in Table 1. Whether the to-be-driven system load can be grounded and thus can smoothly drive the system load depends on the fourth control signal and the fifth control signal. Its truth table is shown in Table 2. Only when the two conditions are met at the same time, the system load can be successfully driven.

[0049] Table 1

[0050] First control signal Second control signal Third control signal No output Low level Invalid No output High level Invalid No output Low level Invalid No output High level Valid

[0051] Table 2

[0052]

[0053]

[0054] As shown in Table 1 and Table 2, only when the signal output by the first control signal is valid and the second control signal is high, the third control signal is valid, and only when the fourth control signal is high and the fifth control signal is low, the system load to be driven can be successfully grounded. When the second control signal is low, no matter whether the first control signal is output or not, the system load will not be driven, and when the fifth control signal is high, no matter what state the fourth control signal is, the system load to be driven will not be driven, thereby ensuring the safety of the high-side drive module. When the above two conditions are met, the system load to be driven can be successfully driven.

[0055] The embodiment provides a high-side drive chip architecture with a multiple protection mechanism, as shown in the figure. Figure 2 As shown in the figure, taking three drive units described above as an example, the number of drive units can be further expanded, including a master control module, a power management module, a high-side drive module 1, a high-side drive module 2, a high-side drive module 3, the high-side drive module 1 being used for driving a system load 1, the high-side drive module 2 being used for driving a system load 2, and the high-side drive module 3 being used for driving a system load 3; the system load 1 and the system load 2 are the same type of system load to be driven.

[0056] A first protection unit is arranged between the master control module and the high-side drive module 1, a second protection unit is arranged between the master control module and the high-side drive module 2, and a third protection unit is arranged between the master control module and the high-side drive module 3; since the system load 1 to be driven and the system load 2 to be driven are the same type of load, a first second protection unit is arranged between the master control module and the system load 1 to be driven and the system load 2 to be driven, and a second second protection unit is arranged between the master control module and the system load 3 to be driven; a first third protection unit, a second third protection unit and a third third protection unit are arranged between the power management module and the high-side drive module 1, the high-side drive module 2 and the high-side drive module 3 respectively.

[0057] The first protection unit includes a logic AND gate, the second protection unit includes an NMOS tube and a second NPN transistor, and the third protection unit includes a PNP transistor and a first NPN transistor.

[0058] The three first output ends of the master control module are connected with the first input ends of the first logical AND gate, the second logical AND gate and the third logical AND gate respectively, for outputting the first control signal, the ninth control signal and the eleventh control signal; the three second output ends of the master control module are connected with the second input ends of the first logical AND gate, the second logical AND gate and the third logical AND gate respectively, for outputting the second control signal, the tenth control signal and the twelfth control signal; the first output ends of the high-side drive module 1, the high-side drive module 2 and the high-side drive module 3 are connected with one ends of the to-be-driven system load 1, the to-be-driven system load 2 and the to-be-driven system load 3 respectively;

[0059] The first control signal, the ninth control signal and the eleventh control signal are all drive system load signals; the second control signal, the tenth control signal and the twelfth control signal are high level when the to-be-driven system load is normal, and the corresponding output third control signal is set as the same drive signal as the first control signal, the ninth control signal and the eleventh control signal, for controlling the first output ends of the high-side drive module 1, the high-side drive module 2 and the high-side drive module 3 to drive the to-be-driven system load to work; when the master control module detects the abnormal to-be-driven system load fed back by the second output ends of the high-side drive module, the second control signal, the tenth control signal and the twelfth control signal are set as low level, and the corresponding third control signal is set as low level under the action of the logical AND gate, for controlling the high-side drive module to shut off the abnormal to-be-driven system load.

[0060] The third output end of the master control module is connected with the gate of the NMOS tube Q1, for outputting the fourth control signal; the fourth output end of the master control module is connected with the base of the second NPN transistor T3, for outputting the fifth control signal; the emitter of the second NPN transistor T3 and the source of the NMOS tube Q1 are grounded; the drain of the NMOS tube Q1 is connected with the other ends of the to-be-driven system load 1 and the to-be-driven system load 2 respectively, for providing a complete loop for the to-be-driven system load 1 and the to-be-driven system load 2; the collector of the second NPN transistor T3 is connected with the gate of the NMOS tube Q1, for controlling the on-off of the NMOS tube Q1;

[0061] The fifth output end of the second output unit of the master control module is connected with the gate of the NMOS tube Q2, for outputting the thirteenth control signal; the sixth output end of the master control module is connected with the base of the NPN transistor T8, for outputting the fourteenth control signal; the emitter of the NPN transistor T8 and the source of the NMOS tube Q2 are grounded; the drain of the NMOS tube Q2 is connected with the other end of the to-be-driven system load 3, for providing a complete loop for the to-be-driven system load 3; the collector of the NPN transistor T8 is connected with the gate of the NMOS tube Q2, for controlling the on-off of the NMOS tube Q2;

[0062] The fourth control signal is high level, the fifth control signal is low level when the system load to be driven is normal, the NMOS tube Q1 is opened, and a complete loop is provided for the system load to be driven, and when the main control module detects the same abnormal system load to be driven from the second output end of the high-side drive module, the second control signal is high level, the NPN transistor T3 is turned on, the gate of the NMOS tube Q1 is pulled down, the NMOS tube Q1 is turned off, and the connection between the same abnormal system load to be driven and the ground is cut off, so that the same abnormal system load to be driven is turned off.

[0063] The output unit of the power management module includes a first output end and a second output end, the first output end of the power management module is connected with the bases of the PNP transistors T1, T4 and T6 respectively, and is used for outputting a sixth control signal, the second output end of the power management module is connected with the emitters of the PNP transistors T1, T4 and T6 respectively, and is used for outputting a seventh control signal, the collectors of the PNP transistors T1, T4 and T6 are connected with the bases of the NPN transistors T2, T5 and T7 respectively, the collectors of the NPN transistors T2, T5 and T7 are connected with the input ends of the high-side drive modules 1, 2 and 3 respectively, and are used for outputting an eighth control signal, and the emitters of the NPN transistors T2, T5 and T7 are grounded;

[0064] The sixth control signal and the seventh control signal are high level when the main control module is normal, and the sixth control signal is low level when the main control module is abnormal, so that all the PNP transistors are turned on, and then all the NPN transistors are turned on, so that the eighth control signal is low level, and all the system loads to be driven are turned off.

[0065] One single system load to be driven can be turned off by the first protection unit to avoid the influence on other system loads to be driven when it is abnormal, in the embodiment, when the system load to be driven 1 is abnormal, the main control module sets the second control signal to be low level, the first control signal and the second control signal are low level under the action of the logic AND gate, so that the third control signal output is low level, and the system load to be driven 1 is turned off, and the system load to be driven 2 is controlled by the ninth control signal and the tenth control signal, and the system load to be driven 3 is controlled by the eleventh control signal and the twelfth control signal, so that the system load to be driven 2 and the system load to be driven 3 can be avoided to be influenced.

[0066] When there are several to-be-driven system load types, they can use the same NMOS tube to realize grounding, so the second protection unit can be used to simultaneously turn off the several to-be-driven system loads, in the embodiment, the to-be-driven system load 1 and the to-be-driven system load 2 are the same type of system load, and are controlled by the NMOS tube Q1 and the NPN transistor T3, when the to-be-driven system load 1 and the to-be-driven system load 2 are abnormal, the main control module sets the fifth control signal to high level, so as to turn off the NMOS tube Q1, at this time, the to-be-driven system load 1 and the to-be-driven system load 2 are simultaneously turned off, and the to-be-driven system load 3 is controlled by the NMOS tube Q2 and the NPN transistor T8, and the input signals are the thirteenth control signal and the fourteenth control signal, so that the to-be-driven system load 1 and the to-be-driven system load 2 can be avoided.

[0067] When the main control module is abnormal, the third protection unit can be used as a total switch to turn off all to-be-driven system loads, the PNP transistor T1, the PNP transistor T4 and the PNP transistor T6 are controlled by the sixth control signal, the NPN transistor T2, the NPN transistor T5 and the NPN transistor T7 are controlled by the seventh control signal, when the main control module is abnormal, the power management module sets the sixth control signal to low level, so that the PNP transistor is turned on, and then the NPN transistor is turned on, so that the eighth control signal is set to low level, and all to-be-driven system loads are turned off. The three protection mechanisms of the application gradually improve the protection level and gradually expand the turn-off range to minimize the impact on the entire controller.

[0068] The output end of the first logic AND gate and the first input end of the main control module are connected through the resistor R1, the output end of the second logic AND gate and the second input end of the main control module are connected through the resistor R6, and the output end of the third logic AND gate and the third input end of the main control module are connected through the resistor R11, the resistor R1, the resistor R6 and the resistor R11 play a current limiting role, and are respectively used to feed back the outputs of the first logic AND gate, the second logic AND gate and the third logic AND gate to the main control module to monitor whether they are valid outputs.

[0069] The first output end of the high-side drive module 1 and the third input end of the main control module are connected through the resistor R2, the first output end of the high-side drive module 2 and the fourth input end of the main control module are connected through the resistor R7, and the first output end of the high-side drive module 3 and the fifth input end of the main control module are connected through the resistor R12, the resistor R2, the resistor R7 and the resistor R12 play a current limiting role, and are respectively used to feed back the drive signals output by the high-side drive module 1, the high-side drive module 2 and the high-side drive module 3 to the main control module to monitor whether they are valid outputs.

[0070] The high-side drive chip has multiple fault diagnosis mechanisms, which are realized through the second output end of the high-side drive module, the second output end of the high-side drive module 1 is connected with the seventh input end of the master control module through a resistor R3, the second output end of the high-side drive module 1 is further provided with a pull-down resistor R5, the second output end of the high-side drive module 2 is connected with the eighth input end of the master control module through a resistor R8, the second output end of the high-side drive module 2 is further provided with a pull-down resistor R10, the second output end of the high-side drive module 3 is connected with the ninth input end of the master control module through a resistor R13, the second output end of the high-side drive module 3 is further provided with a pull-down resistor R15, the resistors R5, R10 and R15 all have the function of converting a current signal into a voltage signal, and then feeding back to the master control module through the current-limiting resistors R3, R8 and R13 respectively, and the master control module judges the state of the current to-be-driven system load according to the voltage and the truth table diagnosed by the high-side drive module.

[0071] The first output end of the high-side drive module 1 is connected with a system power supply 1 through a resistor R4, the first output end of the high-side drive module 2 is connected with a system power supply 2 through a resistor R9, and the first output end of the high-side drive module 3 is connected with a system power supply 3 through a resistor R14, the high-side drive module can judge multiple fault types, wherein the fault judgment conditions are inconsistent in the to-be-driven system load driving and non-driving states, the resistors R4, R9 and R14 are provided for facilitating open-circuit fault diagnosis, when the to-be-driven system load 1, the to-be-driven system load 2 and the to-be-driven system load 3 are open circuits, the first output end of the high-side drive module 1 is pulled up to the system power supply 1 through the resistor R4, the first output end of the high-side drive module 2 is pulled up to the system power supply 2 through the resistor R9, the first output end of the high-side drive module 3 is pulled up to the system power supply 3 through the resistor R14, so the level of the first output end is high, and the master control module detects the open-circuit fault, when the to-be-driven system load is not an open circuit, the second output end is low.

[0072] The contents not described in detail in the specification of the present application belong to the prior art known to those skilled in the art. The above examples are provided only for the purpose of describing the present application, and are not intended to limit the scope of the present application. The scope of the present application is defined by the appended claims. Various equivalent replacements and modifications made without departing from the spirit and principles of the present application should be covered within the scope of the present application.

Claims

1. A high-side driver chip architecture with multiple protection mechanisms, comprising a master control module and a power management module, characterized in that: further comprising a driving unit, the driving unit comprising a high-side driver module, a first protection unit arranged between the master control module and the high-side driver module, and a third protection unit arranged between the power management module and the high-side driver module; the input end of the first protection unit is connected with the first output unit of the master control module, and the output end is connected with the input end of the high-side driver module; the second output end of the high-side driver module is connected with the first input end of the master control module; the first protection unit is used to control the high-side driver module to shut down the abnormal to-be-driven system load when the master control module detects the abnormal to-be-driven system load fed back by the second output end of the high-side driver module; the input end of the third protection unit is connected with the output unit of the power management module, and the output end is connected with the input end of the high-side driver module; the master control module and the power management module are bidirectionally connected; the third protection unit is used to control the high-side driver module to shut down the to-be-driven system load when the master control module is abnormal. 2.The high-side driver chip architecture with multiple protection mechanisms according to claim 1, characterized in that: the first protection unit comprises a logic AND gate; the first output unit of the master control module comprises a first output end and a second output end; the first output end of the master control module is connected with the first input end of the logic AND gate, and is used to output a first control signal; the second output end of the master control module is connected with the second input end of the logic AND gate, and is used to output a second control signal; the output end of the logic AND gate is connected with the input end of the high-side driver module, and is used to output a third control signal; and the first output end of the high-side driver module is connected with one end of the to-be-driven system load. The first control signal is a driving system load signal; the second control signal is set to high level when the to-be-driven system load is normal; the third control signal outputs the same driving signal as the first control signal, and controls the first output end of the high-side driver module to drive the to-be-driven system load to work; when the master control module detects the abnormal to-be-driven system load fed back by the second output end of the high-side driver module, the second control signal is set to low level, and the third control signal outputs low level, thereby controlling the high-side driver module to shut down the abnormal to-be-driven system load. 3.The high-side driver chip architecture with multiple protection mechanisms according to claim 1, characterized in that: the third protection unit comprises a PNP transistor and a first NPN transistor; the output unit of the power management module comprises a first output end and a second output end; the first output end of the power management module is connected with the base of the PNP transistor, and is used to output a sixth control signal; the second output end of the power management module is connected with the emitter of the PNP transistor, and is used to output a seventh control signal; the collector of the PNP transistor is connected with the base of the first NPN transistor; the collector of the first NPN transistor is connected with the input end of the high-side driver module, and is used to output an eighth control signal; and the emitter of the first NPN transistor is grounded. ​ ​ ​ ​ ​ The sixth control signal and the seventh control signal are high level when the master control module is normal, and the sixth control signal is low level when the master control module is abnormal, so that the PNP triode is turned on, the first NPN triode is turned on, and the eighth control signal is low level, thereby controlling the high side drive module to turn off the load to be driven.

4. The high side drive chip architecture with multiple protection mechanisms according to claim 1, characterized in that: The output end of the logical AND gate is further connected with the third input end of the master control module through a first current limiting resistor, for feeding back the third control signal to the master control module to monitor whether it is valid output; The first output end of the high side drive module is further connected with the second input end of the master control module through a second current limiting resistor, for feeding back the driving signal output by the high side drive module to the master control module to monitor whether it is valid output; The second output end of the high side drive module is connected with the first input end of the master control module through a third current limiting resistor, and the second output end of the high side drive module is further provided with a pull-down resistor, for converting the current value output by the second output end into a voltage value, judging the state of the load to be driven according to the voltage value, and feeding back the state of the load to be driven to the master control module through the third current limiting resistor.

5. The high side drive chip architecture with multiple protection mechanisms according to claim 1, characterized in that: The first output end of the high side drive module is further connected with a system power supply, and a pull-up resistor is arranged between the first output end of the high side drive module and the system power supply, for pulling up the first output end of the high side drive module to the system power supply when the load to be driven is open circuit, so that the first output end outputs high level, and the master control module detects that the load to be driven is open circuit abnormality after the high level output by the first output end enters the master control module.

6. A high side drive chip architecture with multiple protection mechanisms, comprising a master control module and a power management module, characterized in that: N driving units according to claim 1 are further included, for driving N loads to be driven respectively, and the N loads to be driven are divided into M groups of same type loads to be driven according to the type of load; M second protection units are further included, arranged between the master control module and the M groups of same type loads to be driven respectively, and M The input ends of the M second protection units are connected with M second output units of the master control module respectively, the output ends are connected with the other ends of the N loads to be driven respectively, the second output ends of the N high side drive modules are connected with N first input ends of the master control module respectively, for turning off the corresponding group of same type loads to be driven when the master control module detects the same type abnormal load to be driven fed back by the second output end of the high side drive module; The input ends of the N first protection units are connected with N first output units of the master control module respectively, and the output ends are connected with the input ends of the N high side drive modules respectively, for turning off the abnormal load to be driven when the master control module detects the abnormal load to be driven fed back by the second output end of the high side drive module. The input end of the N third protection units is connected with the output end of the power management module, and the output end is connected with the input end of the N high-side drive modules; the master control module is bidirectionally connected with the power management module; the third protection unit is used for simultaneously shutting down all to-be-driven system loads when the master control module is abnormal.

7. The high-side drive chip architecture with multiple protection mechanisms according to claim 6, characterized in that: The M second protection units each comprise an NMOS tube and a second NPN transistor; the M second output units of the master control module each comprise a third output end and a fourth output end; the third output end of the master control module is connected with the gate of the NMOS tube, and is used for outputting a fourth control signal; the fourth output end of the master control module is connected with the base of the second NPN transistor, and is used for outputting a fifth control signal; the emitter of the second NPN transistor is grounded, the source of the NMOS tube is grounded, the drain of the NMOS tube is connected with the other end of the to-be-driven system load, and is used for providing a complete loop for the to-be-driven system load; the collector of the second NPN transistor is connected with the gate of the NMOS tube, and is used for controlling the on-off of the NMOS tube; The fourth control signal is a high level, the fifth control signal is a low level when the to-be-driven system load is normal, the NMOS tube is opened, a complete loop is provided for the to-be-driven system load, when the master control module detects the same type of abnormal to-be-driven system load fed back by the second output end of the high-side drive module, the fifth control signal is set to a high level, the second NPN transistor is turned on, the gate of the NMOS tube is pulled down, the NMOS tube is shut down, the connection between the corresponding group of the same type of to-be-driven system load and the ground is cut off, and the same type of abnormal to-be-driven system load is shut down.

8. The high-side drive chip architecture with multiple protection mechanisms according to claim 6, characterized in that: The first protection unit comprises a logic AND gate; each first output unit of the master control module comprises a first output end and a second output end; the first output end of each first output unit is connected with the first input end of the corresponding logic AND gate, and is used for outputting a first control signal; the second output end is connected with the second input end of the corresponding logic AND gate, and is used for outputting a second control signal; the output ends of the N logic AND gates are respectively connected with the input ends of the N high-side drive modules, and are used for outputting a third control signal; and the first output ends of the N high-side drive modules are respectively connected with one end of the N to-be-driven system loads. The first control signal is a to-be-driven system load signal; when the to-be-driven system load is normal, the second control signal is set to a high level, the corresponding third control signal outputs the same driving signal as the first control signal, and controls the first output end of the corresponding high-side drive module to drive the to-be-driven system load to work; when the master control module detects an abnormal to-be-driven system load fed back by the second output end of the high-side drive module, the corresponding second control signal is set to a low level, the third control signal outputs a low level, and the high-side drive module is controlled to shut down the abnormal to-be-driven system load. The third protection unit includes a PNP triode and a first NPN triode, the output unit end of the power management module includes a first output end and a second output end, the first output end of the power management module is connected with the base of the PNP triode, and the first output end is used for outputting a sixth control signal; the second output end of the power management module is connected with the emitter of the PNP triode, and the second output end is used for outputting a seventh control signal; the collector of the PNP triode is connected with the base of the first NPN triode, the emitter of the first NPN triode is grounded, and the collector is used for outputting an eighth control signal; the collectors of the N first NPN triodes are respectively connected with the input ends of the N high-side drive modules. The sixth control signal and the seventh control signal are high levels when the master control module is normal, the sixth control signal is low when the master control module is abnormal, each PNP triode is turned on, then each first NPN triode is turned on, and each eighth control signal is low, so that the high-side drive module is controlled to turn off all system loads to be driven.

9. The high-side drive chip architecture with multiple protection mechanisms according to claim 6, characterized in that: the output ends of the N logical AND gates are respectively connected with the N third input ends of the master control module through first current-limiting resistors, and are used for feeding back each third control signal to the master control module to monitor whether the third control signal is valid; the first output ends of the N high-side drive modules are respectively connected with the N second input ends of the master control module through second current-limiting resistors, and are used for feeding back the drive signals output by the high-side drive modules to the master control module to monitor whether the drive signals are valid; the second output ends of the N high-side drive modules are respectively connected with the N first input ends of the master control module through third current-limiting resistors, and the second output ends of the N high-side drive modules are respectively provided with pull-down resistors, which are used for converting the current values output by the corresponding second output ends into voltage values, judging the states of the system loads to be driven according to the voltage values, and feeding back the states of the system loads to be driven to the master control module through the third current-limiting resistors.

10. The high-side drive chip architecture with multiple protection mechanisms according to claim 6, characterized in that: the first output ends of the N high-side drive modules are respectively connected with system power supplies, and the first output ends of the N high-side drive modules are respectively provided with pull-up resistors between the first output ends and the system power supplies, the pull-up resistors are used for pulling up the first output ends of the high-side drive modules to the system power supplies when the corresponding system loads to be driven are open circuits, so that the first output ends output high levels, and the high levels output by the first output ends enter the master control module, and the master control module detects that the system loads to be driven are open circuit abnormalities.

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