Direct wire reveal package

Abstract

The invention relates to a direct wire reveal package. An electronic package and an out-of-package package-on-package structure are described. In an embodiment, an electronic package includes a plurality of stepped dies encapsulated by a molding layer and a plurality of vertical wire bonds, where the plurality of vertical wire bonds protrude from a top surface of the molding layer such that the vertical wire bonds uprightly protrude over the top surface of the molding layer.

Description

TECHNICAL FIELD

[0001] Embodiments described herein relate to semiconductor packages. More specifically, embodiments relate to stacking of memory dies. BACKGROUND

[0002] Current market demands for portable and mobile electronic devices such as mobile phones, personal digital assistants (PDAs), digital cameras, portable players, gaming devices, and other mobile devices require more performance and features to be integrated into smaller and smaller spaces. Accordingly, various multi-die packaging solutions, such as system-in-a-package (SiP) and package-on-package (PoP) have become more popular to meet the demand for higher die / component density devices. In one implementation, memory dies or packages such as dynamic random access memory (DRAM), which is generally considered as volatile memory, and / or non-volatile memory dies or packages such as flash memory (e.g., NAND) are stacked on top of logic dies or packages (e.g., application specific integrated circuits (ASICs)) or system-on-a-chip (SoC). As the portable and mobile electronic device market progresses, there is a need for memory dies or packages to have greater memory capabilities. In one implementation, multiple memory dies are vertically stacked to increase the memory in the memory die package. SUMMARY

[0003] Electronic packages and package-on-package ("PoP") structures are described. In embodiments, an electronic package includes a plurality of stacked dies, a plurality of vertical wire bonds, and a molding layer encapsulating the plurality of stacked dies and the plurality of vertical wire bonds, where the wire bonds extend vertically from contact pads of the plurality of stacked dies and protrude from the molding layer to stand proud above a top surface of the molding layer. In embodiments, an electronic package includes a plurality of stacked dies, a plurality of vertical interconnect bars, and a molding layer encapsulating the plurality of stacked dies and the plurality of vertical interconnect bars. In embodiments, a package-on-package structure includes at least a first electronic package, a second electronic package, a support structure, a vertical interconnect array bar, and a molding layer encapsulating the first electronic package, the second electronic package, the support structure, and the vertical interconnect array bar, where the vertical interconnect array bar extends from a top surface of the first electronic package to a top surface of the second electronic package. BRIEF DESCRIPTION OF DRAWINGS

[0004] FIG. 1A is a schematic cross-sectional side view illustration of an electronic package with stand proud vertical wire bonds according to embodiments.

[0005] FIG. 1Bis a schematic cross-sectional side view illustration of an electronic package having upright protruding vertical wire bonds and solder bumps according to an embodiment.

[0006] FIG. 1C is a schematic cross-sectional side view illustration of an electronic package having vertical wire bonds and a package routing layer according to an embodiment.

[0007] FIG. 1D is a schematic top view illustration of an electronic package having upright protruding vertical wire bonds according to an embodiment.

[0008] FIG. 2 is a flowchart illustrating a method for forming an electronic package having upright protruding vertical wire bonds according to an embodiment.

[0009] FIGS. 3A-3D is a schematic cross-sectional side view illustration of a method for forming an electronic package having upright protruding vertical wire bonds according to an embodiment.

[0010] FIG. 4A is a schematic cross-sectional side view illustration of an electronic package having vertical interconnect bars according to an embodiment.

[0011] FIG. 4B is a schematic cross-sectional side view illustration of an electronic package having vertical interconnect bars according to an embodiment.

[0012] FIG. 5 is a flowchart illustrating a method for forming an electronic package having vertical interconnect bars according to an embodiment.

[0013] FIGS. 6A-6E is a schematic cross-sectional side view illustration of a method for forming an electronic package having vertical interconnect bars according to an embodiment.

[0014] FIGS. 7A-7D is a schematic cross-sectional side view illustration of an off-package stacked package structure according to an embodiment.

[0015] FIGS. 8A-8D is a schematic cross-sectional side view illustration of an off-package stacked package structure adjacent to an electronic package according to an embodiment.

[0016] FIGS. 9A-9C is a schematic cross-sectional side view illustration of a stepped die adjacent to an electronic package according to an embodiment.

[0017] FIGS. 10A-10C is a schematic cross-sectional side view illustration of a stepped die adjacent to an electronic package according to an embodiment. DETAILED DESCRIPTION

[0018] Embodiments describe electronic packages and package-on-package ("PoP") structures that include multiple dies (e.g., memory dies) that can be vertically stacked in a stepped manner (e.g., stepped, etc.). In one aspect, it has been observed that testing of stacked memory packages typically occurs at the wafer level prior to package singulation and after a package routing layer (e.g., redistribution layer) has been formed over a reconstituted wafer that includes the stacked memory dies. This can be attributed, for example, to the wafer-level processes used to form the package routing layer. However, it has been observed that testing such packages at the wafer level can be problematic because the probe cards used to test such packages have a rectangular array of probes that can better suit testing of rectangular panels rather than circular wafers. In embodiments, an electronic package includes multiple stepped dies encapsulated in a molding layer and multiple vertical wire bonds that extend from contact pads of the multiple stepped dies and protrude from a top surface of the molding layer such that the vertical wire bonds stand proud above the top surface of the molding layer. Thus, the memory dies can be stacked onto a panel rather than a wafer because there is no need to form a redistribution layer prior to testing. Thus, the protruding wire bonds can be tested at the panel level rather than the wafer level, where the vertical wire bonds can then undergo further fabrication for subsequent packaging processes (e.g., flip chip, integrated fan-out, etc.). Such a fabrication sequence can increase the throughput of testing and potentially reduce manufacturing costs by moving the packaging sequence to a panel-level facility rather than a wafer-level facility, and potentially completely remove the necessity of a package routing layer (e.g., redistribution layer) depending on the product. In embodiments, a similar structure can be fabricated with vertical interconnect bars (e.g., through-silicon via bars, through-glass via bars, etc.) rather than vertical wire bonds, which can allow for a more fine pitch design. In embodiments, a package-on-package structure can be assembled through modular scaling of the described electronic packages, where the electronic packages themselves can be stepped and supported by one or more support structures.

[0019] In various embodiments, descriptions are made with reference to the accompanying drawings. Certain embodiments, however, can be practiced without one or more of these specific details, or in combination with other known methods and configurations. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the embodiments. In other instances, well-known semiconductor processes and manufacturing techniques have not been described in particular detail in order not to unnecessarily obscure embodiments. Reference throughout this specification to "an embodiment" means that a particular feature, structure, configuration, or characteristic described in connection with an embodiment is included in at least one embodiment. Thus, the appearance of the phrase "in one embodiment" in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, configurations, or characteristics can be combined in any suitable manner in one or more embodiments.

[0020] As used herein, the terms "over," "on," "to," "between," "across," and "on" can refer to a relative position of one layer with respect to other layers. One layer can be "over," "on," "across," or "on" or bonded "to" or in "contact" with another layer either directly or with one or more intervening layers. One layer can be "between" multiple layers either directly or with one or more intervening layers.

[0021] Referring now to FIG. 1A , a cross-sectional side view illustration of an electronic package having multiple vertical wire bonds with upstanding protrusions in accordance with embodiments is provided. The package 100 can include multiple stepped dies 110 and multiple vertical wire bonds 120 encapsulated by a molding layer 130. The multiple stepped dies 110 can include various types of digital, analog, or mixed-signal integrated circuits. In embodiments, the multiple stepped dies are memory dies or chips (e.g., DRAM, NOT-AND ("NAND"), etc.). Additionally, an adhesive layer (e.g., die attach film, etc.) can be applied to the backside of the dies to attach the dies to an underlying die or substrate (e.g., carrier substrate, etc.). In FIG. 1A the example, the multiple stepped dies 110 include dies 110A, 110B, 110C, 110D vertically stacked in a "stepped" manner so as to create contact flanges 114A, 114B, and 114C, respectively, in which the dies can be attached to one another by an adhesive layer 105. Further, due to the stepping of the dies, the contact flanges become the only exposed areas in which back end of line ("BEOL") build-up structures can be exposed. Thus, the die wiring / contact layers of the multiple dies can be designed to extend to these exposed areas at the edges of the dies. For example, in FIG. 1AIn particular embodiments, the plurality of stepped dies 110 includes a die contact pad 112A on a contact ledge 114A, a die contact pad 112B on a contact ledge 114B, a die contact pad 112C on a contact ledge 114C, and a die contact pad 112D, where these die contact pads can connect the dies to other locations within the package.

[0022] Further reference is made to FIG. 1A , the plurality of vertical wire bonds 120 extend vertically through a thickness of the molding layer 130 and protrude through a top surface 131 of the molding layer 130, such that the plurality of vertical wire bonds 120 stand proud above the top surface 131. Further, a height by which the plurality of vertical wire bonds 120 protrude above the top surface 131 can vary based on factors related to memory die testing (e.g., instrument type, pitch design, etc.). In FIG. 1A an example, the plurality of vertical wire bonds 120 protrude a height h above the top surface 131 of the molding layer 130, where h can be in a range of 5 microns to 10 microns, although other heights are contemplated. In this way, the vertical wire bonds that protrude / stand proud above the top surface of the molding layer can be contacted by test probes to enable testing at a package level (rather than a wafer level), such that the package can be shipped as a known good package. In some embodiments, such as when the package 100 and another package (e.g., a system on a chip, etc.) can be encapsulated together in another molding layer, the vertically wire bonds that stand proud can remain intact above the top surface of the molding layer. In other embodiments, the vertically wire bonds that stand proud can undergo further fabrication for subsequent packaging processes (e.g., flip chip, integrated fan-out, etc.). For example, a grinding operation can remove the protruding vertical wire bonds, where optional solder bumps (e.g., solder bumps 125) can then be placed such as FIG. 1B an example, or an optional package routing layer 140 can be formed on the top surface 131, such as FIG. 1C an example, where the optional package routing layer 140 can include a dielectric layer 141, one or more metal redistribution lines, and plated vias (e.g., plated vias 145). Further reference is made to FIG. 1C , the plated vias can connect to the plurality of vertical wire bonds 120, where the plated vias can then be bumped with solder bumps (e.g., solder bumps 125).

[0023] Reference is now made to FIG. 1D , a schematic top view illustration of an electronic package having vertically wire bonds that stand proud, in accordance with an embodiment, is provided. In FIG. 1DIn an example, the plurality of stepped dies 110 include a die 110B above a die 110A, a die 110C above a die 110B, and a die 110D above a die 110C. The plurality of stepped dies 110 expose contact flanges 114A, 114B, and 114C, where the plurality of vertical wire bonds 120 can be bonded. Further, the plurality of vertical wire bonds 120 can include direct access regions 121A, 121B and an array region 122. The direct access regions 121A, 121B can include vertical wire bonds having a larger or coarser pitch size and / or a wider diameter than the wire bonds located in the array region 122. In one embodiment, the direct access regions 121A, 121B include vertical wire bonds having a 90 micron pitch. In this way, the described embodiments eliminate the need for specialized instruments or probes for testing memory dies, allowing standardized instruments and probes to directly contact the coarser pitch and / or larger diameter vertical wire bonds located in the direct access areas 121A, 121B, so that testing of the memory dies can be accomplished at the bar level.

[0024] Now refer to FIG. 2 as well as FIGS. 3A-3D , FIG. 2 is a flow chart illustrating a method for forming an electronic package having upstanding protruding vertical wire bonds according to an embodiment; FIGS. 3A-3D is a schematic cross-sectional side view illustration of a method for forming an electronic package having upright raised vertical wire bonds according to an embodiment. FIGS. 3A-3D Simultaneous discussion FIG. 2 The method flow. FIG. 3A As shown, at operation 2010, a plurality of dies may be stacked in a stepped manner to form a plurality of stepped dies 110 on a carrier substrate 102, which may be a suitable substrate such as a semiconductor wafer, glass, a metal plate, or the like. More specifically, the carrier substrate 102 may be panel-shaped so that the packaging sequence can be performed outside of a wafer facility. In particular, a first die 110A may be attached to the carrier substrate 102 using an adhesive layer 105, followed by stepping of a second die 110B, a third die 110C, and a fourth die 110D, wherein the adhesive layer 105 is applied between these stepped dies. Furthermore, the stepping of the dies exposes die contact pads 112A on contact flange 114A, die contact pads 112B on contact flange 114B, die contact pads 112C on contact flange 114C, and die contact pads 112D.

[0025] like FIG. 3BAs shown, at operation 2020, a plurality of vertical wire bonds 120 are bonded to the plurality of stepped dies 110. In particular, the plurality of vertical wire bonds 120 are bonded to the die contact pads 112A, 112B, 112C, and 112D and pulled vertically apart. In an embodiment, the plurality of vertical wire bonds 120 are gold wires. In an alternative embodiment, copper wires may be utilized, wherein the protrusion height of the copper wires is controlled (see FIG. FIG. 3D ) to prevent oxidation (e.g., organic solderability preservative ("OSP"), electroless gold plating ("electroless ENEPIG"), etc.). Further, the plurality of vertical wire bonds 120 may include wires having different diameters and / or attached at different pitches. Return to Reference FIG. 1C The vertical wire bonds located in the direct access regions 121A, 121B may have a larger diameter and / or a larger pitch (e.g., 90 micron pitch) than the vertical wire bonds located in the array region 122 to create a larger surface for memory die test equipment (e.g., probes) to contact the vertical wire bonds during testing. At operation 2030, FIG. 3C The encapsulation of the plurality of stepped dies 110 and the plurality of vertical wire bonds 120 is shown, where the encapsulation may be completed with a mold layer (such as mold layer 130) or other suitable insulator gap fill material (such as oxide, nitride, etc.). This may be followed by a gradual grinding of the mold layer 130 and the plurality of vertical wire bonds 120 at operation 2040, where the plurality of vertical wire bonds 120 may become flush with (or even recessed from) the top surface 132 of the mold layer 130. In such a case, the plurality of vertical wire bonds may not be sufficiently exposed to enable electrical contact with memory die test equipment, which may result in unreliable testing or inability to perform the test at all.

[0026] like FIG. 3D As shown, at operation 2050, the mold layer can be recessed to expose the plurality of vertical wire bonds such that the plurality of vertical wire bonds can protrude upright above the top surface of the mold layer. For example, the mold layer can be recessed by a dry plasma etching process or other suitable process for removing the mold layer 130 so that a memory die test instrument can directly contact the plurality of vertical wire bonds 120 located in the direct access areas 121A, 121B. In one embodiment, the mold layer 130 is dry plasma etched so that the height h of the plurality of vertical wire bonds above the top surface 131 of the mold layer 130 is approximately 5 microns to 10 microns. After recessing the mold layer 130, memory die testing can be performed to determine a known good package, followed by further manufacturing processes such that the package 100 can be mounted on a module substrate (e.g., a printed circuit board, etc.). In some embodiments, after the grinding operation, optional solder bumps (e.g., FIG. 1BThe solder bumps 125 shown in FIG are placed on the package 100, followed by removal and singulation of the carrier substrate 102. In other embodiments, after the grinding operation, an optional package wiring layer, such as a PCB, may be formed over the package 100 before removing the carrier substrate 102. FIG. 1C In this case, the package wiring layer 140 may include one or more dielectric layers 141 that may be formed by standard deposition techniques (e.g., spin coating, spray coating, physical vapor deposition, chemical vapor deposition, etc.), one or more optional metal redistribution lines formed of copper or other suitable materials, and plated vias 145 formed of copper or other suitable materials connected to the plurality of vertical wire bonds, wherein these plated vias may be raised with solder bumps 125, as shown. FIG. 1C shown.

[0027] Now refer to FIGS. 4A-4B , a cross-sectional side view illustration of an electronic package having vertical interconnect strips is provided according to an embodiment. FIG. 1A The example is different in FIGS. 4A-4B In the example of , the package 100 does not include vertical wire bonds, but rather includes a plurality of vertical interconnect strips 150. FIGS. 4A-4B In the example of , the plurality of stepped dies 110 include vertically stacked dies 110A, 110B, 110C, and 110D to produce contact flanges 114A, 114B, and 114C, respectively, wherein the dies are attached to each other by an adhesive layer 105. In addition, the plurality of stepped dies 110 and the plurality of vertical interconnects 150 may be encapsulated by a mold layer 130. Further, the plurality of vertical interconnects 150 may be formed of a suitable material (e.g., silicon, glass, etc.), and may include vias (e.g., via 152) plated with copper or other suitable materials to form through-silicon vias, through-glass vias, etc., wherein the vertical interconnects may be structured such that the pitch of the vertical interconnects is the same as the pitch of the memory dies. In some embodiments, the plurality of vertical interconnects 150 may extend vertically from the contact flanges through the thickness of the mold layer to a top surface of the mold layer, which may include an optional package wiring layer. For example, in FIG. 4A In the embodiment, a plurality of vertical interconnect strips 150 are connected to the die contact pads 112A on the contact flange 114A, the die contact pads 112B on the contact flange 114B, and the die contact pads 112C on the contact flange 114C, wherein the plurality of vertical interconnect strips 150 may be bonded to the die contact pads at contact flanges (e.g., solder bumps, anisotropic conductive film, etc.). FIG. 4AIn the example of FIG. 1, the plurality of vertical interconnect bars 150 are connected to the die contact pads by solder bumps 125 and extend through the thickness of the molding layer 130 to the package routing layer 140. In this case, the height of the vertical interconnect bars can vary, for example, based on the distance between the die contact pads and the package routing layer, and the width of the vertical interconnect bars can be less than the width of the contact pads on which the vertical interconnect bars are adhered. For the die contact pad 112D, a plated via (e.g., plated via 145) can be formed in the molding layer 130 instead of a vertical interconnect bar to provide a connection between the die contact pad 112D and a subsequent layer (e.g., package routing layer 140, etc.) formed on the top surface 131 of the molding layer 130. In one example, the package routing layer 140 can be formed over the molding layer 130 and include one or more dielectric layers 141, one or more optional metal redistribution lines (not shown), and plated vias 145, which can be bumped with solder bumps 125. Further reference is made to FIG. 2. FIG. 4A A number of plated vias, such as plated via 145 located above the die contact pad 112D, can be stacked, where a lower plated via can be located in the molding layer 130 and an upper plated via can be located in the package routing layer 140.

[0028] Reference is made to FIG. 2, which illustrates a cross-sectional view of the package 100 along the line 2-2 of FIG. 1. In this example, the plurality of vertical interconnect bars 150 are connected to the die contact pads by solder bumps 125 and extend through the thickness of the molding layer 130 to the package routing layer 140. In this case, the height of the vertical interconnect bars can vary, for example, based on the distance between the die contact pads and the package routing layer, and the width of the vertical interconnect bars can be less than the width of the contact pads on which the vertical interconnect bars are adhered. For the die contact pad 112D, a plated via (e.g., plated via 145) can be formed in the molding layer 130 instead of a vertical interconnect bar to provide a connection between the die contact pad 112D and a subsequent layer (e.g., package routing layer 140, etc.) formed on the top surface 131 of the molding layer 130. In one example, the package routing layer 140 can be formed over the molding layer 130 and include one or more dielectric layers 141, one or more optional metal redistribution lines (not shown), and plated vias 145, which can be bumped with solder bumps 125. Further reference is made to FIG. 2. FIG. 4B In other embodiments, the vertical interconnect bars themselves can be stepped, where the height of the vertical interconnect bars can be approximately the same as the height of the adjacent dies, and the width of the vertical interconnect bars can span multiple contact pads. For example, in the example of FIG. 1, the vertical interconnect bar adjacent to the die 110C (vertical interconnect bar 150C) spans the contact pads 114B and 114A, and the vertical interconnect bar adjacent to the die 110D (vertical interconnect bar 150D) spans the contact pads 114C, 114B, and 114A. In addition, since the height of the vertical interconnect bars can be approximately the same as the height of the adjacent dies, the vertical interconnect bars do not extend to the top surface 131 of the molding layer 130. As such, in addition to the plated vias 145 located above the die contact pads 112 in the molding layer 130, the package 100 also includes plated vias 145 located above the vertical interconnect bar 150D in the molding layer 130, as shown in FIG. 2. FIG. 4B In other embodiments, the vertical interconnect bars themselves can be stepped, where the height of the vertical interconnect bars can be approximately the same as the height of the adjacent dies, and the width of the vertical interconnect bars can span multiple contact pads. For example, in the example of FIG. 1, the vertical interconnect bar adjacent to the die 110C (vertical interconnect bar 150C) spans the contact pads 114B and 114A, and the vertical interconnect bar adjacent to the die 110D (vertical interconnect bar 150D) spans the contact pads 114C, 114B, and 114A. In addition, since the height of the vertical interconnect bars can be approximately the same as the height of the adjacent dies, the vertical interconnect bars do not extend to the top surface 131 of the molding layer 130. As such, in addition to the plated vias 145 located above the die contact pads 112 in the molding layer 130, the package 100 also includes plated vias 145 located above the vertical interconnect bar 150D in the molding layer 130, as shown in FIG. 2. FIG. 4B In other embodiments, the vertical interconnect bars themselves can be stepped, where the height of the vertical interconnect bars can be approximately the same as the height of the adjacent dies, and the width of the vertical interconnect bars can span multiple contact pads. For example, in the example of FIG. 1, the vertical interconnect bar adjacent to the die 110C (vertical interconnect bar 150C) spans the contact pads 114B and 114A, and the vertical interconnect bar adjacent to the die 110D (vertical interconnect bar 150D) spans the contact pads 114C, 114B, and 114A. In addition, since the height of the vertical interconnect bars can be approximately the same as the height of the adjacent dies, the vertical interconnect bars do not extend to the top surface 131 of the molding layer 130. As such, in addition to the plated vias 145 located above the die contact pads 112 in the molding layer 130, the package 100 also includes plated vias 145 located above the vertical interconnect bar 150D in the molding layer 130, as shown in FIG. 2. FIG. 4B, some plated vias may be stacked, such as via 145 located above the die contact pad 112D and above the vertical interconnect bar 150D, where the lower plated via may be located in the mold layer 130 and the upper plated via may be located in the package wiring layer 140 .

[0029] Now refer to FIG. 5 as well as FIGS. 6A-3D , FIG. 5 is a flow chart illustrating a method for forming an electronic package having vertical interconnect strips according to an embodiment; FIGS. 6A-6D is a schematic cross-sectional side view illustration of a method for forming an electronic package having vertical interconnect strips according to an embodiment. FIGS. 6A-6D Simultaneous discussion FIG. 5 The method flow. FIG. 6A As shown, at operation 5010, a plurality of dies may be stacked in a stepped manner to form a plurality of stepped dies 110 on a carrier substrate 102, which may be a suitable substrate such as a semiconductor wafer, glass, a metal plate, etc. Specifically, a first die 110A is attached to the carrier substrate 102 using an adhesive layer 105, followed by stepping of a second die 110B, a third die 110C, and a fourth die 110D, wherein the adhesive layer 105 is applied between the stepped dies. Furthermore, the stepping of the dies exposes die contact pads 112A on contact flange 114A, die contact pads 112B on contact flange 114B, die contact pads 112C on contact flange 114C, and die contact pads 112D.

[0030] like FIG. 6B As shown, at operation 5020, a plurality of vertical interconnect bars 150 are bonded to the plurality of stepped dies 110. The plurality of vertical interconnect bars 150 may be through-silicon via bars, through-glass via bars, etc. Further, the plurality of vertical interconnect bars 150 may be bonded to the die contact pads of the plurality of stacked dies by thermocompression bonding, compression bonding, bulk reflow, anisotropic conductive film, or any other suitable bonding technology. FIG. 6B In the example of FIG, a plurality of vertical interconnect strips 150 are connected to the die contact pads 112A, 112B, and 112C via solder bumps 125. At operation 2030, FIG. 6C The plurality of stepped dies 110 and the plurality of vertical interconnect strips 150 are shown encapsulated to form a top surface 132, wherein the encapsulation may be accomplished with a mold layer (such as mold layer 130) or other suitable insulator gap fill material (such as oxide, nitride, etc.). At operation 2040, FIG. 6Dshowing gradual grinding of the molding layer 130 and the plurality of vertical interconnect bars 150 from the top surface 132 to a desired package height, such as the top surface 131, which can expose the vias 152 of the plurality of vertical interconnect bars 150. Further, plated vias 145 can be formed in the molding layer 130 over the die contact pads 112D, where the plated vias 145 can be formed of copper or other suitable material and connected to the die contact pads 112D. In other embodiments where the height of the vertical interconnect bars 150 is substantially the same as the height of an adjacent die, such as the vertical interconnect bars 150D in FIG. 4B At operation 5050, FIG. 6E showing formation of a package wiring layer 140 over the top surface 131 of the molding layer 130, followed by removal of the carrier substrate 102. In this case, the package wiring layer 140 can include one or more dielectric layers 141 formed by standard deposition techniques (e.g., spin coating, spray coating, physical vapor deposition, chemical vapor deposition, etc.), one or more optional metal redistribution lines (not shown) formed of copper or other suitable material, and plated vias 145, where the plated vias can be formed over the vias 152 of the plurality of vertical interconnect bars 150 and the plated vias 145 located in the molding layer 130 (where the vias 145 can be stacked over the die contact pads 112D). Such plated vias 145 in the package wiring layer 140 can then be bumped with solder bumps 125.

[0031] Referring now to FIGS. 7A-7D , a schematic cross-sectional side view illustration of a package-on-package structure is provided in accordance with an embodiment. Electronic packages can be stacked to form a package-on-package structure to increase the number of memory dies in a single package. For example, in FIG. 7AIn some embodiments, package 200 includes packages 100A and 100B encapsulated by molding layer 230, support structure 260, and vertical interconnect array strip 250. Package 100A (upper package) and package 100B (lower package) can be vertically stacked in a stepped manner, with support structure 260 can be located adjacent to the lower package (e.g., package 100B) and below the upper package (e.g., package 100A) in order to provide support for the upper package, with adhesive layer 240 (e.g., die attach film) can be applied between the packages. Further, the stepping of packages 100A and 100B can create contact ledge 214, with vertical interconnect array strip 250 (e.g., through silicon via array strip, through glass via array strip, etc.) can extend from contact ledge 214 through the thickness of molding layer 230 to top surface 201 of package 200. In this case, the plurality of vertical interconnects 120 of package 100B (lower package) can include solder bumps 125 (similar to the example of FIG. 1B ) to bond the plurality of vertical interconnects 120 of package 100B to vias 252 of vertical interconnect array strip 250. Further, the plurality of vertical interconnects 120 of package 100A (upper package) can be upstanding proud above top surface 201 of package 200, such that memory die testing can be performed, after which the plurality of vertical interconnects 120 of package 100A can undergo further manufacturing processes. For example, after testing, a grinding operation can remove the protruding vertical interconnects, with optional solder bumps (e.g., solder bumps 125) can then be placed on top surface 201 of package 200, similar to the example shown in FIG. 1B , or optional package wiring layers (e.g., package wiring layers 140) can be formed over top surface 201 of package 200, similar to the example shown in FIG. 1C .

[0032] Further reference is made to FIGS. 7B-7D , which provides a schematic cross-sectional side view illustration of a variant of the package out stacked package structure described in FIG. 7A . For example, in FIG. 7B , package 200 includes packages 100A and 100B, with packages 100A and 100B including a plurality of vertical interconnects 120 and package wiring layers 140, similar to package 100 described in FIG. 1C . In FIG. 7C , package 200 includes packages 100A and 100B, with packages 100A and 100B including a plurality of vertical interconnect strips 150 (rather than a plurality of vertical interconnects 120), similar to package 100 described in FIG. 4AIn such an embodiment, the height of the plurality of vertical interconnect bars 150 extends vertically from the die contact pads of the stacked die through the thickness of the molding layer 130 and to the package wiring layer 140. FIG. 7D , package 200 includes packages 100A and 100B, wherein packages 100A and 100B include a plurality of vertical interconnect strips 150 (rather than a plurality of vertical wirebonds 120), similar to FIG. 4B In such an embodiment, the height of the plurality of vertical interconnect bars 150 is substantially the same as the height of the adjacent die, wherein the vertical interconnect bars may span across the plurality of contact flanges of the die. FIGS. 7B-7D In the example of FIG, vertical interconnect array bar 250 may extend from contact flange 214 through the thickness of mold layer 230 and to top surface 201 of package 200. In this case, solder bumps 125 placed on package wiring layer 140 of package 100B (lower package) may bond vertical interconnect array bar 250 to package 100B.

[0033] Now refer to FIGS. 8A-8D , provides a schematic cross-sectional side view illustration of adjacent stacked electronic packages according to an embodiment. FIGS. 8A-8D The example described in FIGS. 7A-7D A variation of the example described in FIGS. 7A-7D A group of stepped packages in a can be positioned "face to face" with adjacent stepped packages facing each other to form a "V" shaped arrangement of memory dies. For example, in FIG. 8AIn some embodiments, package 300 includes packages 100A, 100B, 100C, and 100D encapsulated by molding layer 330, support structure 360, and vertical interconnect array bar 350. Packages 100A and 100B can be vertically stacked in a stepped manner and can face packages 100C and 100D that are also vertically stacked in a stepped manner, with memory dies forming a "V" shaped arrangement within package 300. Further, package 300 can include support structure 360 that can be located adjacent to lower packages (e.g., packages 100B and 100D) and below upper packages (e.g., packages 100A and 100C) in order to provide support for the upper packages, with adhesive layer 240 (e.g., die attach film) that can be applied between the packages. Further, the face-to-face positioning of packages 100A and 100B with packages 100C and 100D can result in contact flanges 314, with vertical interconnect array bar 350 (e.g., through silicon via bar, through glass via bar, etc.) that can extend from contact flanges 314 through the thickness of molding layer 330 to top surface 301 of package 300. In this case, the plurality of vertical wire bonds 120 of the lower packages (packages 100B and 100D) can include solder bumps 125 (similar to the example of FIG. 1B ) to bond the plurality of vertical wire bonds 120 of packages 100B and 100D to vias 352 of vertical interconnect array bar 350. Further, the plurality of vertical wire bonds 120 of the upper packages (packages 100A and 100C) can stand proud above top surface 201 of package 200, such that memory die testing can be performed, after which the plurality of vertical wire bonds 120 of packages 100A and 100C can undergo further manufacturing processes. For example, after testing, a grinding operation can remove the protruding vertical wire bonds, with optional solder bumps (e.g., solder bumps 125) that can then be placed on top surface 301 of package 300, similar to the example shown in FIG. 1B , or optional package wiring layers (e.g., package wiring layers 140) can be formed over top surface 301 of package 300, similar to the example shown in FIG. 1C .

[0034] Further reference is made to FIGS. 8B-8D , which provides a schematic cross-sectional side view illustration of a variation of the adjacent stacked electronic packages described in FIG. 8A . For example, in FIG. 8B , package 300 includes packages 100A, 100B, 100C, and 100D that include a plurality of vertical wire bonds 120 and package wiring layers 140, similar to packages 100 described in FIG. 1C . In FIG. 8CIn some embodiments, the package 300 includes packages 100A, 100B, 100C, and 100D that include a plurality of vertical interconnect bars 150 (rather than a plurality of vertical wirebonds 120), similar to the package 100 described in FIG. 4A In some embodiments, the package 300 includes packages 100A, 100B, 100C, and 100D that include a plurality of vertical interconnect bars 150 (rather than a plurality of vertical wirebonds 120), similar to the package 100 described in FIG. 8D In some embodiments, the package 300 includes packages 100A, 100B, 100C, and 100D that include a plurality of vertical interconnect bars 150 (rather than a plurality of vertical wirebonds 120), similar to the package 100 described in FIG. 4B In some embodiments, the package 300 includes packages 100A, 100B, 100C, and 100D that include a plurality of vertical interconnect bars 150 (rather than a plurality of vertical wirebonds 120), similar to the package 100 described in FIGS. 8B-8D In some embodiments, the vertical interconnect array bar 350 can span a lower package (such as packages 100B and 100D) and extend from the contact ledge 314 through the thickness of the molding layer 330 and to the top surface 301 of the package 300. In particular, the solder bumps 125 placed on the package routing layer 140 of the lower packages (packages 100B and 100D) can bond the vertical interconnect array bar 350 to the packages 100B and 100D.

[0035] Referring now to FIGS. 9A-9C , a schematic cross-sectional side view illustration of adjacent stepped dies is provided in accordance with an embodiment. For example, FIGS. 9A-9C In some embodiments, the example described in FIG. 1A includes a plurality of stepped dies stacked in two-high rather than four-high as described in FIG. 9A In some embodiments, the package 400 includes a plurality of stepped dies 110 and a plurality of vertical wirebonds 120 encapsulated by a molding layer 130. The plurality of stepped dies 110 includes dies 110A, 110B, 110C, and 110D that include die contact pads 112A, 112B, 112C, and 112D, respectively. In addition, an upper die, such as die 110B, can be stepped on top of a lower die, such as die 110A, where the dies 110A and 110B can be attached by an adhesive layer 105. Further, an upper die, such as die 110D, can be stepped on top of a lower die, such as die 110C, where the dies 110C and 110D can be attached by an adhesive layer 105. In FIG. 9AIn the example of FIG4 , the 110A / 110B stack can be arranged or positioned face-to-face with the 110C / 110D stack to form a "V" shaped arrangement of memory dies, wherein the plurality of vertical wire bonds can be grouped toward a center position of the package 400. In particular, the plurality of vertical wire bonds 120 can be bonded to the die contact pad 112A of die 110A, the die contact pad 112B of die 110B, the die contact pad 112C of die 110C, and the die contact pad 112D of die 110D, wherein the plurality of vertical wire bonds are located at the center position 407. Further, similar to FIG4 , the plurality of vertical wire bonds 120 can be bonded to the die contact pad 112A of die 110A, the die contact pad 112B of die 110B, the die contact pad 112C of die 110C, and the die contact pad 112D of die 110D. FIG. 1A In the embodiment described in the foregoing, the plurality of vertical wire bonds 120 protrude upright above the top surface 131 of the mold layer 130, so that memory die testing can be performed, after which the plurality of vertical wire bonds 120 of the package 400 can undergo further manufacturing processes. For example, after testing, a grinding operation can be performed, wherein solder bumps (e.g., solder bumps 125) can then be placed on the package 400, similar to FIG. 1B , or an optional package wiring layer (eg, package wiring layer 140 ) may be formed over package 400 , as shown in FIG. FIG. 9B In this case, the package wiring layer 140 may include one or more dielectric layers 141, one or more optional metal redistribution lines (not shown), and plated vias 145 connected to the plurality of vertical wire bonds 120, wherein the solder bumps 125 may then be placed on the plated vias 145. FIG. 9C Shown FIG. 9A A variation of the present invention, in which, for example, a plurality of vertical interconnect strips 150 may be used instead of a plurality of vertical wire bonds, similar to FIG. 4A In this case, vertical interconnect bar 150 spans the lower die (e.g., 110A and 110C) and extends through the thickness of mold layer 130 and to top surface 131 of mold layer 130. In particular, solder bumps 125 can be placed on the die contact pads of the lower die (such as die contact pad 112A of die 110A and die contact pad 112C of die 110C) to bond the vertical interconnect bar to the lower die.

[0036] Now refer to FIGS. 10A-10C , provides a schematic cross-sectional side view illustration of adjacent stepped dies according to an embodiment. FIGS. 10A-10C The example described in is similar to FIGS. 9A-9C The example described in , where multiple dies are stacked two high instead of four high. However, FIGS. 10A-10C The examples described in FIGS. 9A-9C The example described in the example differs in that FIGS. 10A-10CThe stepped dies can be positioned or arranged "back to back" with each other so that the vertical connections reside at the edge of the package, which is similar to FIGS. 9A-9C The opposite is true for the face-to-face embodiment in which the vertical connections are grouped in the middle of the package. For example, FIG. 10A , package 500 includes a plurality of stepped dies 110 and a plurality of vertical wire bonds 120 encapsulated by a mold layer 130. The plurality of stepped dies 110 may include dies 110A, 110B, 110C, and 110D, which include die contact pads 112A, 112B, 112C, and 112D, respectively. Additionally, die 110B may be stepped on top of die 110A, wherein dies 110A and 110B may be attached by adhesive layer 105. Further, die 110D may be stepped on top of die 110C, wherein die 110C and die 110D may be attached by adhesive layer 105. In FIG. 10A In the example of FIG, the 110A / 110B stack is back-to-back with the 110C / 110D stack so that the plurality of vertical wire bonds 120 can be located toward the edge of the package 500. In particular, the plurality of vertical wire bonds 120 can be bonded to the die contact pad 112A of the die 110A, the die contact pad 112B of the die 110B, the die contact pad 112C of the die 110C, and the die contact pad 112D of the die 110D. Further, for example, similar to FIG. 1A In the embodiment described in the foregoing, the plurality of vertical wire bonds 120 may be raised upright above the top surface 131 of the mold layer 130 so that a memory die test may be performed, after which the plurality of vertical wire bonds 120 of the package 500 may undergo further manufacturing processes. For example, after testing, a grinding operation may be performed, wherein solder bumps (e.g., solder bumps 125) may then be placed on the package 500, similar to the embodiment described in the foregoing. FIG. 1B , or an optional package wiring layer (eg, package wiring layer 140) may be formed over the package 500, as shown in FIG. FIG. 10B In this case, the package wiring layer 140 may include one or more dielectric layers 141, one or more optional metal redistribution lines (not shown), and plated vias 145 connected to the plurality of vertical wire bonds 120, wherein the solder bumps 125 may then be placed on the plated vias 145. FIG. 10C Shown FIG. 10A A variation of the present invention, in which, for example, a plurality of vertical interconnect strips 150 may be used instead of a plurality of vertical wire bonds, similar to FIG. 4AIn this case, the plurality of vertical interconnect bars 150 can extend through the thickness of the molding layer 130 to the top surface 131 of the molding layer 130. In particular, the solder bumps 125 can be placed on the die contact pads of the lower dies, such as the die contact pads 112A of the die 110A and the die contact pads 112C of the die 110C, to bond the plurality of vertical interconnect bars to the lower dies.

[0037] It will become apparent to those skilled in the art utilizing the various aspects of the embodiments that combinations or variations of the above-described embodiments are possible for stacked memory packages and their package-outside stacked package structures. While the embodiments have been described in language specific to structural features and / or methodological acts, it is to be understood that the appended claims are not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as illustrative forms of implementing the claims.

Claims

1. An electronic package comprising: a plurality of stepped dies including a plurality of contact flanges; a plurality of vertical wire bonds bonded to the plurality of contact flanges; and a molding layer encapsulating the plurality of stepped dies and the plurality of vertical wire bonds, wherein the plurality of vertical wire bonds extend beyond a top surface and stand proud above the molding layer.

2. The electronic package of claim 1, wherein the plurality of stepped dies are memory dies.

3. The electronic package of claim 1, wherein the plurality of vertical wire bonds include a first region having a first pitch size and a second region having a second pitch size, the first pitch size being greater than the second pitch size.

4. The electronic package of claim 1, wherein the plurality of stepped dies include a first set of dies including a first upper die attached to a first lower die and a second set of dies including a second upper die and a second lower die, the first set of dies and the second set of dies positioned such that the plurality of vertical wire bonds are located at a center location on the electronic package.

5. The electronic package of claim 1, wherein the plurality of stepped dies include a first set of dies including a first upper die attached to a first lower die and a second set of dies including a second upper die and a second lower die, the first set of dies and the second set of dies positioned such that the plurality of vertical wire bonds are located at first and second edges on the electronic package.

6. An electronic package comprising: a plurality of stepped dies including a plurality of contact flanges; a plurality of vertical interconnect bars bonded to the plurality of contact flanges; and a molding layer encapsulating the plurality of stepped dies and the plurality of vertical interconnect bars.

7. The electronic package of claim 6, wherein the plurality of stepped dies are memory dies.

8. The electronic package of claim 6, wherein a height of the plurality of vertical interconnect bars extends from the plurality of contact flanges to a top surface of the molding layer and a width of the plurality of vertical interconnect bars is less than a width of the plurality of contact flanges.

9. The electronic package of claim 6, wherein a height of the plurality of vertical interconnect bars is less than a height of an adjacent die and a width of the plurality of vertical interconnect bars spans one or more of the plurality of contact flanges.

10. The electronic package of claim 6, wherein the plurality of stepped dies include a first set of dies including a first upper die attached to a first lower die and a second set of dies including a second upper die and a second lower die, the first set of dies and the second set of dies positioned such that the plurality of vertical interconnect bars are located at a center location on the electronic package. ​ ​ 11. The electronic package of claim 6, wherein the plurality of stepped dies includes a first set of dies including a first upper die attached to a first lower die and a second set of dies including a second upper die and a second lower die, the first set of dies and the second set of dies positioned such that the plurality of vertical interconnect bars are located at a first edge and a second edge on the electronic package.

12. A package-on-package structure, the package-on-package structure comprising: a plurality of stepped electronic packages including at least a first set of electronic packages including a first upper electronic package and a first lower electronic package; one or more support structures including at least a first support structure located adjacent to the first lower electronic package and below the first upper electronic package; an array of vertical interconnect bars; and a molding layer encapsulating the plurality of stepped electronic packages, the one or more support structures, and the array of vertical interconnect bars.

13. The package-on-package structure of claim 12, wherein the plurality of stepped electronic packages each include a plurality of stepped dies, the plurality of stepped dies being memory dies.

14. The package-on-package structure of claim 12, wherein the first upper electronic package and the first lower electronic package each include: a plurality of stepped dies including a plurality of contact flanges; a plurality of vertical wire bonds bonded to the plurality of contact flanges; and a molding layer encapsulating the plurality of stepped dies and the plurality of vertical wire bonds, wherein the plurality of vertical wire bonds extend beyond a top surface and stand proud above the molding layer.

15. The package-on-package structure of claim 14, further comprising a second set of electronic packages including a second upper electronic package and a second lower electronic package, the second upper electronic package and the second lower electronic package including: a plurality of stepped dies including a plurality of contact flanges; a plurality of vertical wire bonds bonded to the plurality of contact flanges; and a molding layer encapsulating the plurality of stepped dies and the plurality of vertical wire bonds, wherein the plurality of vertical wire bonds extend beyond a top surface and stand proud above the molding layer.

16. The package-on-package structure of claim 15, wherein the first set of electronic packages and the second set of electronic packages are positioned face-to-face such that a top surface of the first lower electronic package and a top surface of the second lower electronic package form a package contact flange, wherein the array of vertical interconnect bars spans the package contact flange. ​ ​ ​ 17. The package-on-package structure of claim 12, wherein the first upper electronic package and the first lower electronic package each comprise: a plurality of stepped dies comprising a plurality of contact flanges; a plurality of vertical interconnect bars bonded to the plurality of contact flanges; and a molding layer encapsulating the plurality of stepped dies and the plurality of vertical interconnect bars.

18. The package-on-package structure of claim 17, further comprising a second set of electronic packages comprising a second upper electronic package and a second lower electronic package, the second upper electronic package and the second lower electronic package comprising: a plurality of stepped dies comprising a plurality of contact flanges; a plurality of vertical interconnect bars bonded to the plurality of contact flanges; and a molding layer encapsulating the plurality of stepped dies and the plurality of vertical interconnect bars.

19. The package-on-package structure of claim 18, wherein the first set of electronic packages and the second set of electronic packages are positioned face-to-face such that a top surface of the first lower electronic package and a top surface of the second lower electronic package form a package contact flange, wherein the array of vertical interconnect bars spans the package contact flange.

20. The package-on-package structure of claim 12, further comprising a plurality of package wiring layers formed over each of the plurality of stepped electronic packages. ​ ​

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